Non-aligned BCH codeword syndrome calculation implementation method
By improving the adjoint computation method, the problem of insufficient hardware resources for parallel data processing of unaligned BCH codewords in optical fiber communication is solved, realizing parallel data processing with lower clock frequency and less resource consumption, and supporting pipelined real-time computation of unaligned codewords.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TIANJIN JADE BIRD COMMUNICATION TECHNOLOGY CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-17
AI Technical Summary
In fiber optic communication, parallel data processing of unaligned BCH codewords leads to insufficient hardware resources. Traditional methods require increasing clock frequency or computing resources, making it impossible to process data streams in a timely manner.
By improving the adjoint computation method, iterative calculation is performed based on the unaligned position of the received codeword, avoiding data shifting and realizing real-time pipelined processing of parallel data.
It reduces processing clock frequency and hardware logic resource consumption, supports parallel computing of unaligned codewords, reduces decoding latency, and improves data processing capabilities and design flexibility.
Smart Images
Figure CN121887353A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, specifically to a method for implementing the synodal computation of unaligned BCH codewords. Background Technology
[0002] In fields such as communications, forward error correction (FEC) technology is often used to ensure the correctness of data transmission. At the transmitting end, the data is encoded, and the encoded codewords are sent into the channel for transmission. At the receiving end, the codewords, which may contain errors, are decoded to correct them. FEC has various encoding methods, such as RS code, BCH code, and LDPC code. BCH code is one of the commonly used encoding methods and has been adopted by many communication protocols.
[0003] The calculation of the synod is required in the processes of BCH code receiver locking, code pattern adaptive judgment, and decoding. For a received codeword without errors, its synod is equal to 0. For a received codeword with errors, its synod is generally not 0 (unless a channel error happens to cause a received codeword to become another valid codeword by mistake, but this situation often corresponds to a large number of errors, exceeding the error correction capability, and thus making it impossible to correct the codeword). The calculation of the synod is the first step in the error correction process, and the subsequent steps of the error correction process depend on the calculated synod result.
[0004] In optical fiber communication applications, especially in backbone channels such as core networks, the communication bandwidth is very large, and optical communication equipment is required to process FEC error correction of data in the optical fiber in real time. This requires the implementation of high-bandwidth parallel data processing. Therefore, hardware chips such as FPGA / ASIC are usually used in optical communication equipment to realize real-time parallel FEC decoding processing of optical communication data.
[0005] In hardware chip circuit implementations (such as FPGA chips), parallel data processing (rather than serial computation) is often used to improve data throughput bandwidth. This means that more than one bit of received codeword data is input and processed in each clock cycle, the specific parallelism depending on the chosen implementation. For example, a parallelism of 64 means 64 bits of data are input each clock cycle, and the corresponding synod calculation for 64 bits of data is completed in parallel within one clock cycle. However, considering that the codeword length may not be an integer multiple of the parallelism, or that the frame format used in the transmission protocol may cause the codeword position to not be aligned with the start of the parallelism, implementations often encounter misaligned BCH codeword reception, meaning the first and last bits of the codeword are not aligned with the highest and lowest bits of the parallel data. Mathematically, each synod in BCH should correspond to a specific codeword, and the calculation of a synod should begin with the first bit of the codeword and end with the last bit. Traditional implementations often use a shifting method to align the data before performing calculations and processing. That is, the received parallel data is first shifted to align the first bit of the codeword to the highest (or lowest) bit of the parallel data, and then subsequent calculations and processing are performed.
[0006] The disadvantage of the above method is that the data must be shifted and aligned each time. When the length of the codeword is not an integer multiple of the parallelism, a non-divisible remainder will be generated in the clock cycle at the end of the codeword. The next codeword will be aligned and processed again in the next clock cycle. Therefore, when transmitting codewords back to back (the first bit of each codeword in the transmitted data immediately follows the last bit of the previous codeword), there is not enough free interval between codewords. As a result, using only one set of computing resources cannot process the data stream in real time at the receiving data frequency. It is necessary to increase the clock frequency or instantiate more processing computing resources. However, the above methods have an adverse impact on the implementation of hardware resources. Summary of the Invention
[0007] The purpose of this invention is to provide a method for implementing synodal computation of unaligned BCH codewords, which improves the synodal computation method to achieve parallel synodal computation processing of unaligned BCH codewords without shifting data.
[0008] To achieve the above objectives, the first aspect of the present invention provides a technical solution:
[0009] A method for implementing unaligned BCH codeword syntactic computation includes:
[0010] S1, the transmitting end uses BCH code to encode the data and sends the encoded codeword to the channel for transmission;
[0011] S2, The receiving end receives the encoded codeword from the channel;
[0012] S3, the receiving end performs syntactic calculation on the received codeword to determine whether a bit error has occurred. The receiving end makes this determination based on the beginning and end positions of the unaligned codewords within the received codeword.
[0013] If the first bit of the current codeword is in the aligned position, then the received codeword is calculated using an iterative method based on the alignment position; if the first bit of the received codeword is not aligned, then step S4 is executed.
[0014] S4, if the first position of the received codeword is unaligned, then an iterative calculation method with an improved computational syndrome is applied to the received codeword. The iterative calculation process of the improved computational syndrome includes:
[0015] First, the intermediate process value Synd_t of the improved adjoint iteration is calculated as follows:
[0016] Synd_t = d[0]*a_0+d[1]*a_1+…+d[i]*a_i+d[c-1]*a_(c-1)
[0017] Where Synd_t is the intermediate value of the improved adjoint iteration of parallel computation in the current clock cycle; d[i] is the i-th bit of the parallel input data in the current clock cycle; a_i is a fixed parameter of the adjoint computation determined according to the corresponding BCH code; i=0,1,...c-1;
[0018] When c is unaligned, it represents the number of bits in the parallel data input during the current clock cycle that start a new codeword, where c = 1, 2, ..., p-1; p is the degree of parallelism, i.e., the bit width of the parallel data processed in each clock cycle.
[0019] Then, based on the intermediate process value Synd_t obtained from the calculation, the iteration of the adjoint equation is updated, and the final output result Synd_reg of the codeword calculated using the improved adjoint equation is obtained as follows:
[0020] Synd_reg = Synd_reg* a_(pc)+ Synd_t.
[0021] Furthermore, in S3, if the first bit of the current codeword is the highest bit of the parallel data, then it is determined that the first bit of the current codeword is in the alignment position.
[0022] Furthermore, in S3, if the first bit of the current codeword is located at the alignment position, the iterative calculation method using the adjoint expression of the alignment position includes:
[0023] First, the intermediate process value Synd_t of the adjoint iteration is calculated as follows:
[0024] Synd_t = d[0]*a_0+d[1]*a_1+…+d[p-1]*a_(p-1)
[0025] Then, based on the intermediate process value Synd_t obtained from the calculation, the iterative process of the adjoint is updated to obtain the final output result Synd_reg of the codeword calculated using the adjoint iterative process:
[0026] Synd_reg = Synd_reg* a_p + Synd_t.
[0027] Furthermore, in S4, when c=1, it means that the lowest bit of the p bits of parallel data input in the current clock cycle is the first bit of a new codeword, at which time Synd_t = d[0]*a_0.
[0028] Furthermore, when the input parallel data of the clock cycle includes both the end of the previous codeword and the beginning of the next codeword, the following two actions are performed simultaneously: output the calculation result of the previous codeword and start the initial calculation of the new codeword.
[0029] The two actions are processed in parallel within the current clock cycle to achieve back-to-back, seamless data computation.
[0030] Furthermore, the back-to-back, gapless data format means that there is no gap between adjacent codewords.
[0031] Furthermore, the value of a_i is specified by the communication protocol used by the channel.
[0032] Furthermore, after S4, the method also includes: the receiving end determines whether there are any errors in the received codewords based on the final output result Synd_reg, and corrects the received codewords that have errors; the corrected codewords are decoded to restore the original data.
[0033] The second aspect of the present invention provides a technical solution:
[0034] An electronic device includes: a processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, it implements the unaligned BCH codeword adjoint computation method as described above.
[0035] The third aspect of the present invention provides a technical solution:
[0036] A computer-readable storage medium storing a program or instructions that, when executed by a processor, implements the unaligned BCH codeword adjoint computation method as described above.
[0037] Compared with the prior art, the beneficial effects of the present invention are:
[0038] 1. The method for implementing the synodal computation of unaligned BCH codewords of the present invention eliminates the need for shifting the original received data during the synodal computation of unaligned BCH codewords. Instead, it improves the synodal computation method to achieve pipelined real-time computation of the synodal computation of unaligned BCH codewords in parallel data. The present invention improves the synodal iterative computation method to match the case of unaligned data.
[0039] 2. The unaligned BCH codeword adjoint computation method of the present invention supports the following multiple cases:
[0040] (1) Supports cases where the codeword length and parallelism are not integer divisible;
[0041] (2) Supports cases where the beginning and end positions of the codeword are not aligned with the received parallel data;
[0042] (3) Supports back-to-back situations where codewords in the data have small or even no gaps.
[0043] 3. The unaligned BCH codeword adjoint computation implementation method of the present invention has the following technical effects on hardware logic resources.
[0044] (1) Lower processing clock frequency is beneficial for timing constraints and reducing power consumption;
[0045] (2) Less hardware logic resource consumption is beneficial for achieving greater processing power and reducing costs with limited logic resources.
[0046] (3) More flexible choice of parallelism is conducive to more flexible and free choice of clock frequency and logic resource trade-off in design;
[0047] (4) It is conducive to realizing real-time pipelined processing of data streams and reducing data decoding latency.
[0048] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0049] Figure 1 This is a flowchart of the method for implementing unaligned BCH codeword syntactic computation according to the present invention. Detailed Implementation
[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0051] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0052] The proposed method for implementing the synodal computation of unaligned BCH codewords in this invention does not employ a shift-based data reception method for synodal computation of unaligned BCH codewords. Instead, it improves the synodal computation method to achieve pipelined real-time computation of the synodal computation of unaligned BCH codewords in parallel data.
[0053] Reference Figure 1 As shown, this disclosure provides a method for implementing unaligned BCH codeword adjoint computation, including:
[0054] S1, the transmitting end uses BCH code to encode the data and sends the encoded codeword to the channel for transmission.
[0055] S2, the receiving end receives the encoded codeword from the channel.
[0056] S3, the receiving end performs syntactic calculation on the received codeword to determine whether a bit error has occurred.
[0057] The receiving end determines the alignment based on the beginning and end positions of the unaligned codewords in the received codeword:
[0058] If the first bit of the current codeword is in the alignment position, then the received codeword is calculated using an iterative method based on the alignment position. Specifically, if the first bit of the current codeword is the highest bit of the parallel data, then the first bit of the current codeword is determined to be in the alignment position.
[0059] In this invention, if the first bit of the current codeword is located at the alignment position, the iterative calculation method using the adjoint expression of the alignment position includes:
[0060] First, the intermediate process value Synd_t of the adjoint iteration is calculated as follows:
[0061] Synd_t = d[0]*a_0+d[1]*a_1+…+d[p-1]*a_(p-1) (1)
[0062] Where Synd_t is the intermediate value of the adjoint iteration in the current clock cycle, d[i] is the i-th bit of the input parallel data in the current clock cycle, i=0,1,...p-1, where p is the degree of parallelism, i.e., the bit width of the parallel data processed in each clock cycle. a_i is a fixed parameter determined by the adjoint calculation based on the corresponding BCH code.
[0063] It should be noted that the multiplication and addition operations mentioned above are the multiplication and addition operations in the Galois field of the binary finite field in the mathematical principle of BCH codes, and the subsequent calculation formulas related to the adjoint are all the same.
[0064] Regarding the value of a_i, taking the ITU standard T-REC-G.975.1 as an example (an FEC error correction method using BCH code in the OTN protocol of optical fiber communication), the row codeword of I.7 in T-REC-G.975.1 uses BCH code, and its primitive polynomial is x^10 + x^3 + 1. Therefore, its corresponding value of a_i is (MSBfirst):
[0065] a_0=0000000001
[0066] a_1 = 0000000010
[0067] a_2 = 0000000100
[0068] …
[0069] a_9 = 1000000000
[0070] a_10=0000001001
[0071] …
[0072] The specific derivation of a_i is based on the fundamental mathematical knowledge of Galois fields in the basic mathematical principles of BCH codes. This is only an example and will not be elaborated further.
[0073] Then, based on the intermediate process value Synd_t obtained from the calculation, the iterative process of the adjoint is updated to obtain the final output result Synd_reg of the codeword calculated using the adjoint iterative process:
[0074] Synd_reg = Synd_reg* a_p+ Synd_t (2)
[0075] Synd_reg is the iterative calculation value of the synodal computation. When the calculation ends at the codeword, Synd_reg is the final output of the synodal computation for that codeword.
[0076] The following example illustrates the alignment of codewords: For instance, if the beginning of a received codeword is 101011001001…, and assuming an implementation with a parallelism of 8, the 8-bit width of the parallel data at the beginning of the received codeword is 10101100, which is the first 8 bits of the received codeword.
[0077] Assuming the received codewords are unaligned, for example, with the same parallelism of 8, let's say the end of the previous received codeword is ... 001110110011, and the beginning of the next received codeword is 101011001001... If the codewords in the received data are transmitted back-to-back (i.e., one codeword follows the previous one without any interval), the unaligned case could be that the highest bit is the last bit of the previous received codeword and the lower 7 bits are the first 7 bits of the next received codeword, meaning the current parallel data width of 8 bits is 11010110. Similarly, the unaligned case could also be that the highest 2 bits are the last 2 bits of the previous received codeword and the lower 6 bits are the first 6 bits of the next received codeword, meaning the current parallel data width of 8 bits is 01101011, and other similar unaligned cases.
[0078] The above embodiment uses an iterative calculation of the alignment position of the received codeword. If the first position of the received codeword is not aligned, then step S4 is executed.
[0079] S4, if the first position of the received codeword is not aligned, then an iterative calculation method based on the improved synod is used for the received codeword. The iterative calculation process of the improved synod includes:
[0080] First, the intermediate process value Synd_t of the improved adjoint iteration is calculated as follows:
[0081] Synd_t = d[0]*a_0+d[1]*a_1+…+d[i]*a_i+d[c-1]*a_(c-1) (3)
[0082] Where Synd_t is the intermediate value of the improved adjoint iteration in parallel computation during the current clock cycle; d[i] is the i-th bit of the parallel input data during the current clock cycle; a_i is a fixed parameter of the adjoint computation determined according to the corresponding BCH code; i = 0, 1, ... c-1. The value of a_i is specified by the communication protocol used by the channel.
[0083] When c is unaligned, it refers to the number of bits in the parallel data input during the current clock cycle that form the starting bit of a new codeword, where c = 1, 2, ..., p-1; p is the degree of parallelism, i.e., the bit width of the parallel data processed per clock cycle.
[0084] For example, when c=1, it means that the lowest bit of the p bits of parallel data input in the current clock cycle is the first bit of a new codeword, and at this time Synd_t = d[0]*a_0.
[0085] When c=3, it means that the lowest 3 bits of the p bits of parallel data input in the current clock cycle are the first 3 bits of the new codeword. At this time, Synd_t = d[0]*a_0+d[1]*a_1+d[2]*a_2.
[0086] Then, based on the intermediate process value Synd_t obtained from the calculation, the iteration of the adjoint equation is updated, and the final output result Synd_reg of the codeword calculated using the improved adjoint equation is obtained as follows:
[0087] Synd_reg = Synd_reg* a_(pc)+ Synd_t (4)
[0088] As can be seen from the above, by improving the adjoint iterative calculation process, no shifting is performed on the original received data d. Similarly, the Synd_reg at the end of the reception of any codeword is the final output result of the adjoint iterative calculation of that codeword.
[0089] In this invention, when the input parallel data of a certain clock cycle simultaneously includes the end of the previous codeword and the beginning of the next codeword, the following two actions are performed simultaneously: outputting the calculation result of the previous codeword and simultaneously initiating the initial calculation of the new codeword. These two actions are processed in parallel within the current clock cycle to achieve back-to-back, gapless data calculation. Back-to-back, gapless data refers to adjacent codewords without any gap between them.
[0090] For example, for an implementation with a parallelism of 8, assuming an unaligned case where the highest bit is the last bit of the previous received codeword and the lower 7 bits are the first 7 bits of the next received codeword, then the current clock cycle contains both the end of the previous codeword (1 bit) and the beginning of the next codeword (7 bits). Therefore, this parallel implementation with a parallelism of 8 should simultaneously output the value of the current iteration's updated syndrome, i.e., the current value of Synd_reg, within the current clock cycle. At the same time, since the current data also contains the beginning of the next received codeword, the current clock cycle should calculate the initial iteration of Synd_t corresponding to the 7 bits of data of the beginning of the next received codeword. Obviously, in this case, c=7, i.e., Synd_t = d[0]*a_0+d[1]*a_1+…+d[6]*a_(6).
[0091] Following S4, the following steps are also included: the receiving end determines whether there are any errors in the received codewords based on the final output result Synd_reg, and corrects the errors in the received codewords; the corrected codewords are decoded to restore the original data.
[0092] The present invention also proposes an electronic device, comprising: a memory and one or more processors. The memory stores one or more application programs adapted to be executed by the one or more processors to implement any of the unaligned BCH codeword adjoint computation implementation methods described in the above embodiments.
[0093] The present invention also proposes a computer-readable storage medium storing computer program instructions; when executed by a processor, these computer program instructions implement any of the unaligned BCH codeword adjoint computation methods described in the above embodiments. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.
[0094] In summary, the unaligned BCH codeword synodal computation method of this invention addresses the data processing difficulties encountered in traditional BCH decoding when parallel data and received codewords are misaligned, leading to the need for data shifting for alignment before computation. This invention proposes an improved parallel synodal computation method for unaligned codewords without shifting. This invention improves the synodal parallel iterative computation process by modifying the iterative computation formula according to the position of the unaligned data to adapt to the current parallel data. Synodal computation of unaligned BCH codewords can be achieved without shifting the parallel data, enabling data processing even when codewords are transmitted back-to-back without gaps.
[0095] In the description of this invention, it should be understood that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0096] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0097] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A method for implementing the synodal computation of unaligned BCH codewords, characterized in that, include: S1, the transmitting end uses BCH code to encode the data and sends the encoded codeword to the channel for transmission; S2, The receiving end receives the encoded codeword from the channel; S3, the receiving end performs syntactic calculation on the received codeword to determine whether a bit error has occurred. The receiving end makes this determination based on the beginning and end positions of the unaligned codewords within the received codeword. If the first bit of the current codeword is in the aligned position, then the received codeword is calculated using an iterative method based on the alignment position; if the first bit of the received codeword is not aligned, then step S4 is executed. S4, if the first position of the received codeword is unaligned, then an iterative calculation method with an improved computational syndrome is applied to the received codeword. The iterative calculation process of the improved computational syndrome includes: First, the intermediate process value Synd_t of the improved adjoint iteration is calculated as follows: Synd_t = d[0]*a_0+d[1]*a_1+…+d[i]*a_i+d[c-1]*a_(c-1) Where Synd_t is the intermediate value of the improved adjoint iteration of parallel computation in the current clock cycle; d[i] is the i-th bit of the parallel input data in the current clock cycle; a_i is a fixed parameter of the adjoint computation determined according to the corresponding BCH code; i=0,1,...c-1; When c is unaligned, it represents the number of bits in the parallel data input during the current clock cycle that start a new codeword, where c = 1, 2, ..., p-1; p is the degree of parallelism, i.e., the bit width of the parallel data processed in each clock cycle. Then, based on the intermediate process value Synd_t obtained from the calculation, the iteration of the adjoint equation is updated, and the final output result Synd_reg of the codeword calculated using the improved adjoint equation is obtained as follows: Synd_reg = Synd_reg* a_(pc)+ Synd_t.
2. The method for implementing unaligned BCH codeword adjoint computation according to claim 1, characterized in that, In S3, if the first bit of the current codeword is the highest bit of the parallel data, then it is determined that the first bit of the current codeword is in the alignment position.
3. The method for implementing unaligned BCH codeword adjoint computation according to claim 1, characterized in that, In S3, if the first bit of the current codeword is located at the alignment position, the iterative calculation method using the alignment position's adjoint expression includes: First, the intermediate process value Synd_t of the adjoint iteration is calculated as follows: Synd_t = d[0]*a_0+d[1]*a_1+…+d[p-1]*a_(p-1) Then, based on the intermediate process value Synd_t obtained from the calculation, the iterative process of the adjoint is updated to obtain the final output result Synd_reg of the codeword calculated using the adjoint iterative process: Synd_reg = Synd_reg* a_p + Synd_t.
4. The method for implementing unaligned BCH codeword adjoint computation according to claim 1, characterized in that, In S4, when c=1, it means that the lowest bit of the p bits of parallel data input in the current clock cycle is the first bit of a new codeword. At this time, Synd_t = d[0]*a_0.
5. The method for implementing unaligned BCH codeword adjoint computation according to claim 1, characterized in that, When the input parallel data of the clock cycle includes both the end of the previous codeword and the beginning of the next codeword, the following two actions are performed simultaneously: output the calculation result of the previous codeword and start the initial calculation of the new codeword. The two actions are processed in parallel within the current clock cycle to achieve back-to-back, seamless data computation.
6. The method for implementing unaligned BCH codeword adjoint computation according to claim 5, characterized in that, The back-to-back, gapless data format means that there is no gap between adjacent codewords.
7. The method for implementing unaligned BCH codeword adjoint computation according to claim 1, characterized in that, The value of a_i is specified by the communication protocol used by the channel.
8. The method for implementing unaligned BCH codeword adjoint computation according to claim 1, characterized in that, Following S4, the process also includes: the receiving end determining whether the received codeword has errors based on the final output result Synd_reg, and correcting the received codeword with errors; decoding the corrected codeword to restore the original data.
9. An electronic device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the method for unaligned BCH codeword adjoint computation as described in any one of claims 1 to 8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a processor, implement the unaligned BCH codeword adjoint computation method as described in any one of claims 1 to 8.