Multi-type network node interconnection architecture

Abstract

The invention discloses a multi-type network node interconnection architecture, belongs to the field of embedded computers, and aims to design an Ethernet switching circuit by taking an Ethernet switch as a core, so that high-speed interconnection of multi-type network nodes is realized. Meanwhile, an MCU configuration management circuit is designed to provide configuration management of link initialization of multiple types of network nodes. According to the interconnection architecture and method, the problem that multiple types of network nodes cannot be compatibly used in a network switch is solved, the high-performance data exchange requirement of a product integrating the multiple types of network nodes is met, an embedded computer debugging network bus architecture is enriched, and the debugging efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the technical field of embedded computers, and particularly relates to a multi-type network node interconnection architecture. Background Technology

[0002] The development of embedded computer architecture is becoming increasingly diversified, with multiple types of main processing devices containing different types of interfaces in the same network. At the same time, the demand for data exchange is increasing. How to satisfy the data exchange needs of multiple types of network nodes in the same network, while also simplifying the embedded hardware, is an improvement on the performance of traditional embedded computers and an increase in the efficiency of embedded computer use.

[0003] In view of this, the present invention is hereby proposed. Summary of the Invention

[0004] The multi-type network node interconnection architecture provided by this invention solves the technical problem of high energy consumption in existing airborne heating devices. The technical solution of this invention has many beneficial effects, as described below: A multi-type network node interconnection architecture is disclosed, suitable for Ethernet switches to achieve interconnection and communication of multiple types of network nodes. It includes Ethernet switching circuits, multiple types of network nodes, and an MCU configuration management circuit. The multiple types of network nodes include CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes. The Ethernet switching circuit, with the Ethernet switch as its core, is used for high-speed interconnection between the various types of network nodes. The MCU configuration management circuit is used for configuring the type of Ethernet switching network ports and initializing the port types of the Ethernet switch. The CPU node is used as a MAC controller to provide an RGMII interface to the outside world, and the RGMII interface is converted into an SGMII interface through a PHY chip; Using the aforementioned intelligent SOC node as a MAC controller, it can provide an external XGMII interface; The cascaded nodes of the network switch are configured as either MAC controllers or PHY controllers via the software registers of the Ethernet switch. The external device network node is used to convert the digital signals transmitted by the Ethernet switching circuit into electrical signals and output them to external electronic devices.

[0005] Network nodes supporting SGMII / XGE interfaces include CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes. (Note: Ethernet switches support a maximum of 16 network ports.) The Ethernet switching circuit is designed with the JEM5396 Ethernet switch as its core to enable high-speed interconnection between various types of network nodes.

[0006] The MCU configuration management circuit utilizes the MCU to configure the port types of the Ethernet switching network, and is used to initialize the port types of the Ethernet switch.

[0007] Preferably, the JEM5396 Ethernet switch channel is configured with multiple types of network nodes, namely CPU nodes, intelligent SOC nodes, network switch cascading nodes, and external device network nodes. a) The CPU node is a MAC controller that provides an RGMII interface to the outside world, which is converted to an SGMII interface through a PHY; b) The SOC node is a MAC controller that provides an XGE interface to the outside world; c) Cascade nodes of network switches (corresponding Ethernet switch ports) can be configured as MAC controllers or PHYs via software registers; d) External device network nodes are electrical signals. The PHY converts the electrical signals into digital signals. It should be noted that the network communication protocol does not support MAC to MAC communication, but it supports MAC and PHY communication. The port mode register of JEM5396 can be configured through the MCU's SPI bus to dynamically adjust the corresponding port to PHY mode.

[0008] Preferably, the MCU configuration management circuit uses the SPI bus to exchange data with the JEM5396 Ethernet switch, configuring the MCU as the master device and the Ethernet switch as the slave device.

[0009] Preferably, the MCU modifies the port configuration register of the JEM5396 Ethernet switch via the SPI bus to switch the port mode. The Ethernet switch port defaults to MAC mode, and the ports corresponding to the cascaded SOC network nodes and Ethernet switches need to be changed to PHY mode. The specific steps include the following: Step 1: The MCU writes 8 bytes of data into the JEM5396 Ethernet switch's Override register 0x000x6? via the SPI bus, as shown in the following SPI instruction: wspi0x000x6?0x8B; Step 2: The MCU writes 0x01:0xf0 to the SGMII Master 0x1? 0x20 register of the JEM5396 Ethernet switch via the SPI bus, as shown in the following SPI instruction: wspi 0x1? 0x20 0x01:0xf0; Step 3: The MCU writes 0x13:0x40 to the MII control register 0x1? 0x00 of the JEM5396 Ethernet switch via the SPI bus to restart the auto-negotiation register, as follows: wspi0x1? 0x000x13:0x40.

[0010] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: The design incorporates an Ethernet switch as the core of the Ethernet switching circuit, enabling high-speed interconnection of multiple types of network nodes. Simultaneously, an MCU configuration management circuit is designed to provide configuration management for link initialization of multiple network node types, resolving incompatibility issues between different network node types within the network switch. This meets the high-performance data exchange requirements of products integrating multiple network node types, enriches the embedded computer debugging network bus architecture, improves debugging efficiency, and increases the diversity of network switching architecture within the product. It supports data communication between multiple network node types in network switching and can dynamically support the access of multiple network node types to the network switch. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the topology of the present invention; Figure 2 This is a schematic diagram of multiple types of network nodes. Detailed Implementation

[0013] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0014] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this invention, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0015] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0016] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that aspects can be practiced without these specific details. To enable those skilled in the art to better understand the invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise stated, "a plurality of" means two or more.

[0017] like Figures 1 to 2 The multi-type network node interconnection architecture shown is suitable for Ethernet switches to achieve interconnection and communication of multiple types of network nodes. It includes Ethernet switching circuits, multiple types of network nodes, and an MCU configuration management circuit. The multiple types of network nodes include CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes. The purpose is to leverage the high-speed switching characteristics of Ethernet switches to enhance the data switching capabilities of embedded computers to meet the real-time transmission requirements of large amounts of data. Simultaneously, the MCU configuration management circuit is designed to configure the port types of the Ethernet switching network. Ethernet switching circuits, with Ethernet switches as the core, are used for high-speed interconnection between various types of network nodes; The MCU configuration management circuit is used for configuring the type of Ethernet switching network ports and initializing the port types of the Ethernet switch. The CPU node is used as the MAC controller to provide the RGMII interface to the outside world. The PHY chip converts the RGMII interface to the SGMII interface. Using intelligent SOC nodes as MAC controllers, it can provide an external XGMII interface; Cascaded nodes of network switches are configured as either MAC controllers or PHY controllers via the software registers of the Ethernet switches. External device network nodes are used to convert digital signals transmitted by Ethernet switching circuits into electrical signals and output them to external electronic devices.

[0018] This node interconnection architecture is designed for diverse embedded computer scenarios. It can integrate Ethernet switching networks of multiple types of network nodes, fully develop the high-speed switching of Ethernet switches (for example, the JEM5396 model is preferred), improve the data switching capabilities of embedded computers, meet the real-time transmission requirements of large amounts of data, and can accommodate multiple types of Ethernet interfaces to perform highly identifiable data interaction in the same switching network. In one embodiment, multiple network nodes with SGMII interface types are designated as CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes, enabling a configuration that supports a multi-functional structure. The network nodes supporting SGMII / XGMII interface types are designated as CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes. (Note: Ethernet switches support a maximum of 16 network ports). The MCU configuration management circuit uses an SPI bus to exchange data with the Ethernet switch. Configure the MCU microcontroller in the MCU configuration management circuit as the master device and the Ethernet switch as the slave device. Specifically... The MCU (Microcontroller Unit) modifies the port configuration registers of the Ethernet switch via the SPI bus; Set the Ethernet switch ports to MAC mode by default, and change the ports corresponding to the intelligent SOC network nodes and the cascaded Ethernet switches to PHY controller mode to ensure normal communication between multiple types of nodes. Specifically, follow these steps: Step 1: The MCU microcontroller uses the SPI bus to write the port number to be configured from address 0x00 and address 0x6 of the Ethernet switch's Override register to a specific value 8B. This specific value 8B is a standard 8-bit binary data, represented in hexadecimal. For example, the following SPI instruction: wspi 0x000x6 ? 0x8B, port number to be configured, from switch port 0 to switch port F (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F represent 16 ports). Step 2: The MCU microcontroller changes the mode by writing the specific value "0x01:0xf0" to the registers at address 0x1 (the port number to be configured) and address 0x20 of the SGMII Master interface of the Ethernet switch via the SPI bus. For example, the following SPI instruction is used: wspi0x1?0x200x01:0xf0; Step 3: The MCU microcontroller writes the specific value 0x13:0x40 to address 0x1 (the port number to be configured) and address 0x00 of the MII control register of the Ethernet switch via the SPI bus. The specific value 0x13:0x40 is used to restart the auto-negotiation register of the Ethernet switch, as shown in the following SPI instruction: wspi0x1? 0x00 0x13:0x40.

[0019] For example, using a JEM5396 Ethernet switch, this design employs two FT2000 / 4 CPU nodes (ports 0 and 1), one Ascend 310P intelligent SOC node (port 2), one JEM5396 network switch cascade node (port 3), and one external device network node (port 4), along with an HWD32F103MLQFP64 MCU and an SPI bus for interconnection. The MCU is configured with the JEM5396 Ethernet switch port modes: ports 0, 1, and 4 are in default MAC mode, while ports 2 and 3 are set to PHY mode. The specific steps are as follows: Step 1: The MCU writes 8 bytes of data to the Override register 0x000x6? of the JEM5396 Ethernet switch via the SPI bus, as shown in the following SPI instruction: wspi0x000x62 0x8B; Step 2: The MCU writes 0x01:0xf0 to the SGMII Master 0x12 0x20 register of the JEM5396 Ethernet switch via the SPI bus, as shown in the following SPI instruction: wspi 0x12 0x20 0x01:0xf0; Step 3: The MCU writes 0x13:0x40 to the MII control register 0x12 0x00 of the JEM5396 Ethernet switch via the SPI bus to restart the auto-negotiation register, as follows: wspi 0x12 0x00 0x13:0x40.

[0020] Step 4: The MCU writes 8B into the Override register 0x000x63 of the JEM5396 Ethernet switch via the SPI bus, as shown in the following SPI instruction: wspi0x000x630x8B, to change the communication mode; Step 5: The MCU writes 0x01:0xf0 to the SGMII Master 0x130x20 register of the JEM5396 Ethernet switch via the SPI bus, as shown in the following SPI instruction: wspi 0x130x20 0x01:0xf0; Step 6: The MCU writes 0x13:0x40 to the MII control register 0x13 0x00 of the JEM5396 Ethernet switch via the SPI bus to restart the auto-negotiation register, as shown in the following SPI instruction: wspi 0x13 0x00 0x13:0x40, which is used to change the corresponding mode.

[0021] Steps 1 to 3 configure port 2, and steps 4 to 6 configure port 3.

[0022] Ethernet is a commonly used debug bus network in embedded systems. Debug buses are generally used for external software online debugging, operating system and software firmware installation, etc. Ethernet switches are communication devices used to realize Ethernet data exchange between multiple nodes, providing high-speed, stable, full-duplex, high-bandwidth data transmission between multiple nodes. Therefore, the reasonable and effective introduction of Ethernet switches into embedded computer products can not only enrich the types of data exchange buses in the product, but also support remote debugging. Design concept: An Ethernet switching circuit is designed with the JEM5396 Ethernet switch as the core, realizing high-speed interconnection of multiple types of network nodes. At the same time, an MCU configuration management circuit is designed to provide configuration management for the link initialization of multiple types of network nodes. This can solve the incompatibility between multiple types of network nodes in the network switch, meet the high-performance data exchange requirements of products integrating multiple types of network nodes, enrich the embedded computer debug network bus architecture, and improve debugging efficiency. See [link to relevant documentation]. Figure 2 In the network transmission process from A to B, it must go from the top layer of A to the bottom layer of A, then to the bottom layer of B, and finally to the top layer of B. Therefore, this interconnection architecture pattern ensures the communication path between A and B.

[0023] The product provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the invention claims.

Claims

1. A multi-type network node interconnection architecture, suitable for Ethernet switches to realize interconnection and communication of multiple types of network nodes, characterized in that, It includes Ethernet switching circuits, multiple types of network nodes, and MCU configuration management circuits. The multiple types of network nodes include CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes. The Ethernet switching circuit, with the Ethernet switch as its core, is used for high-speed interconnection between the various types of network nodes. The MCU configuration management circuit is used for configuring the type of Ethernet switching network ports and initializing the port types of the Ethernet switch. The CPU node is used as a MAC controller to provide an RGMII interface to the outside world, and the RGMII interface is converted into an SGMII interface through a PHY chip; Using the aforementioned intelligent SOC node as a MAC controller, it can provide an external XGMII interface; The cascaded nodes of the network switch are configured as either MAC controllers or PHY controllers via the software registers of the Ethernet switch. The external device network node is used to convert the digital signals transmitted by the Ethernet switching circuit into electrical signals and output them to external electronic devices.

2. The multi-type network node interconnection architecture according to claim 1, characterized in that, The network nodes of the SGMII interface type are CPU nodes, intelligent SOC nodes, network switch cascade nodes, and external device network nodes.

3. The multi-type network node interconnection architecture according to claim 1, characterized in that, The MCU configuration management circuit uses an SPI bus to exchange data with an Ethernet switch, wherein... Configure the MCU microcontroller in the MCU configuration management circuit as the master device and the Ethernet switch as the slave device.

4. The multi-type network node interconnection architecture according to claim 3, characterized in that, Configure the MCU microcontroller in the MCU configuration management circuit as the master device and the Ethernet switch as the slave device. The MCU microcontroller modifies the port configuration register of the Ethernet switch via the SPI bus; The Ethernet switch ports are set to MAC mode by default, and the ports corresponding to the cascaded intelligent SOC network nodes and Ethernet switches are modified to the PHY controller mode.

5. The multi-type network node interconnection architecture according to claim 4, characterized in that, Modifying the ports corresponding to the cascaded intelligent SOC network nodes and Ethernet switches to the PHY controller mode includes... Step 1: The MCU microcontroller writes the port number to be configured from address 0x00 and address 0x6 of the Ethernet switch's Override register to a specific value of 8 bytes via the SPI bus; Step 2: The MCU microcontroller writes the specific value 0x01:0xf0 to the registers at address 0x1 (the port number to be configured) and address 0x20 of the SGMII Master interface of the Ethernet switch via the SPI bus. Step 3: The MCU microcontroller writes specific values ​​0x13 to 0x40 to address 0x1 (the port number to be configured) and address 0x00 of the MII control register of the Ethernet switch via the SPI bus. The specific values ​​0x13 to 0x40 are used to restart the auto-negotiation register of the Ethernet switch.

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