Low-orbit constellation high-speed switching method based on FPGA

Abstract

The invention belongs to the technical field of satellite communication and network switching, particularly relates to a low-orbit constellation high-speed switching method based on an FPGA (Field Programmable Gate Array), and aims to solve the problems of low cache utilization rate, difficulty in scheduling time sequence convergence and single event upset dead lock of spaceborne switching equipment in a resource limited and intense radiation environment. The method is applied to a switching system constructed by an FPGA (Field Programmable Gate Array), the switching system comprises an input module, an output module and a switching core, and the switching core adopts a data and control separation architecture of a local shared data pool and a virtual output queue. After the data frame is subjected to verification and fixed-length slicing, dynamic multiplexing of storage resources is realized through address pointer circulation; an availability mask is introduced into an exchange core, and cycle-by-cycle continuous output of a scheduling decision is realized through a three-stage assembly line; and the self-healing controller triggers hierarchical reset through state verification, so that deadlock is avoided. The method does not need to depend on external storage, on-chip resource consumption is reduced, line-speed forwarding is achieved, logic soft errors can be automatically repaired, the throughput performance, scheduling timeliness and on-orbit survivability of a low-orbit satellite network are remarkably improved, and the method adapts to satellite-borne environment harsh constraints.

Description

Technical Field

[0001] This invention belongs to the field of satellite communication and network switching technology, specifically relating to a high-speed switching method for low-Earth orbit constellations based on FPGA implementation. Background Technology

[0002] With the rapid evolution of low-Earth orbit (LEO) satellite internet and large-scale constellation networking technologies, high-concurrency services such as multi-source remote sensing data aggregation, high-speed inter-satellite routing, and broadband user access continue to grow. The bidirectional aggregation bandwidth demand of onboard switching systems has exceeded 100 Gbps, and their performance directly determines the communication service quality of LEO constellations. At the same time, the onboard environment imposes strict constraints on the size, weight, power consumption (SWaP), and radiation resistance reliability of equipment. Developing high-speed switching technologies adapted to this scenario has become a core prerequisite for promoting the large-scale application of LEO satellite networks.

[0003] Existing spaceborne switching systems mostly use aerospace-grade FPGAs to replace ground-based dedicated switching chips (ASICs) to adapt to the strong radiation environment in space. To compensate for the insufficient on-chip cache of FPGAs, some solutions attempt to expand storage capacity by adding external DDR3 / DDR4 SDRAM. In terms of switching architecture, a design combining Crossbar and Virtual Output Queue (VOQ) is often adopted to alleviate the impact of head-of-line (HOL) blocking on transmission efficiency.

[0004] However, existing technologies are insufficient to meet the actual needs of low-Earth orbit constellations: FPGA on-chip block RAM resources are limited, the operating frequency and bandwidth of external DDR are limited by process technology, and the overhead of small packet read / write switching is large, making it impossible to achieve line-rate forwarding; the number of queues in the VOQ architecture increases quadratically with the number of input / output modules, leading to a surge in logic resource consumption and difficulty in scheduling timing convergence; the static queue partitioning mode cannot adapt to the burstiness of satellite services and the differences in message length, resulting in low cache utilization and easy storage fragmentation; in addition, single-event upsets (SEUs) caused by space radiation can easily lead to system state mismatch, which in turn can cause deadlock, seriously threatening operational reliability. Existing solutions lack an effective technical path that can solve the above problems simultaneously. Summary of the Invention

[0005] To address the problems existing in the background technology, this invention provides a high-speed switching method for low-orbit constellations based on FPGA implementation. The method is applied to a switching system built on FPGA, which includes N input modules, M output modules, and a switching core located therebetween. The switching core includes multiple parallel storage queuing units and a three-stage pipeline scheduler. Each storage queuing unit contains a locally shared data pool, a free address list, and virtual output queues corresponding to the M output modules. The method includes:

[0006] S1: Receive data frames through each input module and perform integrity verification on them; use the stream feature identifier of the data frame as the lookup key value, and match it in the local forwarding table to obtain the target output module and service priority of the data frame;

[0007] S2: The received data frame is split into multiple fixed-length internal information cells, and internal exchange header information is generated according to the target output module, service priority, and length of the data frame; wherein, each local shared data pool includes multiple physical pages of the same size, each physical page corresponds to an address, and the size of each internal information cell is the same as the size of the physical page in the local shared data pool;

[0008] S3: Store the internal information cell into the free physical page of the local shared data pool according to the corresponding free address list, and store the internal exchange header information and the address corresponding to the physical page into the corresponding virtual output queue, and update the corresponding free address list.

[0009] S4: The three-level pipeline scheduler generates a scheduling strategy based on the non-empty request status of each virtual output queue, the flow control status of each output module, and the ready status of each storage queuing unit.

[0010] S5: Read internal information cells from physical pages in the local shared data pool according to the scheduling policy and each virtual output queue, and update the corresponding free address linked list;

[0011] S6: The read internal information cells are reassembled into data frames by each output module and then transmitted.

[0012] The present invention has at least the following beneficial effects

[0013] This solution utilizes an FPGA to construct a switching system comprising input modules, output modules, and a switching core (including a storage queuing unit and a three-stage pipeline scheduler). The core process—data frame verification and slicing—local shared data pool + virtual output queue storage—three-stage pipeline scheduling—cell reassembly and transmission—effectively solves the problems of low buffer utilization, difficult scheduling timing convergence, single-event upset leading to deadlock, and resource constraints faced by spaceborne switching equipment in the background technology. It achieves dynamic reuse and linear expansion of storage resources, reduces on-chip storage resource consumption, achieves line-speed forwarding, and improves the determinism and timeliness of scheduling decisions. This significantly enhances the throughput, radiation resistance reliability, and on-orbit survivability of low-Earth orbit satellite networks, fully adapting to the size, weight, and power consumption constraints of the spaceborne environment. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the system architecture of the present invention;

[0015] Figure 2 This is a schematic diagram of the architecture of the storage queuing unit of the present invention;

[0016] Figure 3 This is a schematic diagram of the three-level pipeline scheduling logic architecture of the present invention;

[0017] Figure 4 This is a flowchart of the status monitoring and recovery logic of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figures 1-4 This invention provides a high-speed switching method for low-orbit constellations based on FPGA implementation. The method is applied to a switching system built on FPGA, the switching system comprising N input modules, M output modules, and a switching core located therebetween; the switching core includes multiple parallel storage queuing units and a three-stage pipeline scheduler; each storage queuing unit includes a locally shared data pool, a free address list, and virtual output queues corresponding to the M output modules. The method includes:

[0020] S1: Receive data frames through each input module and perform integrity verification on them; use the stream feature identifier of the data frame as the lookup key value, and match it in the local forwarding table to obtain the target output module and service priority of the data frame;

[0021] Preferably, the integrity verification of the data frame includes: using a Frame Check Sequence (FCS) to verify the integrity of the data frame, and comparing the FCS recalculated from the valid data of the data frame with the reserved FCS field at the end of the data frame to ensure that the data has not been tampered with or has errors.

[0022] Preferably, the flow feature identifier of the data frame includes: destination MAC address, destination IP address, and flow label; the local lookup table contains mapping entries from flow feature identifier to forwarding control information, and the forwarding control information includes: target output module and service priority; the target output module and service priority corresponding to the data frame are obtained by mapping the flow feature identifier of the data frame in the local lookup table.

[0023] S2: The received data frame is split into multiple fixed-length internal information cells, and internal exchange header information is generated according to the target output module, service priority, and length of the data frame; wherein, each local shared data pool includes multiple physical pages of the same size, each physical page corresponds to an address, and the size of each internal information cell is the same as the size of the physical page in the local shared data pool;

[0024] Preferably, the internal exchange header information includes: the target output module of the data frame, the service priority, and the length of the data frame; the internal exchange header information is stored in the virtual output queue before the first internal cell of the data frame; wherein, the identifier SOP is added to the physical page storage address of the first internal cell of the data frame, and the identifier EOP is added to the physical page storage address of the last internal cell of the data frame.

[0025] S3: Store the internal information cell into the free physical page of the local shared data pool according to the corresponding free address list, and store the internal exchange header information and the address corresponding to the physical page into the corresponding virtual output queue, and update the corresponding free address list.

[0026] Preferably, each storage queuing unit is provided with an input management state machine and an output scheduling state machine; wherein, the input management state machine is used to store internal information cells into the idle physical pages of the local shared data pool according to the corresponding idle address linked list, and to store the internal exchange header information and the address corresponding to the physical page into the corresponding virtual output queue; the output scheduling state machine is used to read internal information cells from the physical pages of the local shared data pool according to the scheduling policy and the addresses recorded in each virtual output queue.

[0027] S4: The three-level pipeline scheduler generates a scheduling strategy based on the non-empty request status of each virtual output queue, the flow control status of each output module, and the ready status of each storage queuing unit.

[0028] Preferably, the generation scheduling strategy includes:

[0029] S41: Collect internal exchange header information from each virtual output queue to construct the original N×N request bitmap matrix. , , , Indicates the first The first input module and the first There are requests in the virtual output queue of each output module; Indicates the first The first input module and the first There are no requests in the virtual output queue of each output module;

[0030] S42: Construct the output flow control vector , , , Indicates output module idle; This indicates that the output module is in use;

[0031] S43: Construct the input ready vector , , , Indicates output module The corresponding output scheduling state machine for the input buffer swapping is idle; Indicates input module The output scheduling state machine of the corresponding storage queuing unit is occupied;

[0032] S44: Construct an availability mask matrix , , among which, element The calculation formula is:

[0033]

[0034] in, This represents the logical AND operation; Indicates the first The input module to the first Availability requests for each output module; Indicates the first The input module to the first Requests for each output module are available. Indicates the first The input module to the first The request for the output module is unavailable;

[0035] S45: Read the current... The input module is for the first Virtual output queues for each output module Transmission license quota The length of the head data frame of the virtual output queue. and each virtual output queue Preset bandwidth weight increment and quota saturation limit ;

[0036] Identify the output module Furthermore, a non-empty virtual output queue is cached to form the output module. active queue set ; judge Are all virtual output queues in a state of insufficient quota? If so, then trigger the quota replenishment operation of the virtual output queue, and update the formula as follows:

[0037]

[0038] Based on the updated transmission allowance quota of the virtual output queue and the length of the head data frame of the virtual output queue. ; Calculate the qualified request identifier:

[0039]

[0040] in, Indicates a qualified request identifier, indicating the first The input module to the first The request from each output module is valid;

[0041] In the output module Among all qualified requests, the qualified request with the highest business priority is selected as the candidate scheduling strategy for this output module;

[0042] S46: Determine if multiple output modules exist. The same input module was selected at the same time. If a request is eligible, then compare the business priorities of the conflicting requests and retain the request with the highest priority; if the priorities are the same, then select one of the eligible requests as the final scheduling strategy based on the round-robin pointer.

[0043] For the virtual output queue corresponding to the final scheduling policy, perform a transmission license quota update operation. The update formula is as follows:

[0044]

[0045] in, For the current scheduling period of the virtual output queue, the transmission license quota, For the next cycle of transmission license quota, The length of the scheduled data frame. The initial transmission license quota.

[0046] S5: Read internal information cells from physical pages in the local shared data pool according to the scheduling policy and each virtual output queue, and update the corresponding free address linked list;

[0047] S6: The read internal information cells are reassembled into data frames by each output module and then transmitted.

[0048] Preferably, for each virtual output queue, three variables are monitored in real time: , and ; It represents the logical mirror depth, incrementing by 1 with the enqueue signal and decrementing by 1 with the dequeue signal; Indicates the actual storage depth of the virtual output queue; This represents the cumulative ECC failure count, which is incremented by 1 each time an uncorrectable ECC error occurs from a physical page in the local shared data pool; the balance equation is checked every clock cycle. ,like Furthermore, after a specific clock cycle, if a logic error caused by a single-event upset occurs, a first-level micro-reset is performed on the virtual output queue: suspending read / write operations on the virtual output queue, resetting the address FIFO of the virtual output queue, and resetting... and Simultaneously, the exchange system maintains the global failure accumulation value. ,in, Represents the k-th virtual output queue; sets the tolerance threshold. When the conditions are met When the system determines that the available physical page resources have been exhausted due to accumulated errors, a second-level global reset is triggered: system-level reset initialization is performed on the local shared data pool and the corresponding free address list for all input modules.

[0049] Preferably, the tolerance threshold includes:

[0050]

[0051] in: The total number of physical pages configured for the local shared data pool; The minimum burst buffer space reserved by the switching system to meet specific packet loss rate requirements; A preset safety redundancy margin value to prevent counter overflow.

[0052] Preferably, when reading an internal cell from the local shared data pool, if an ECC check error is detected in the internal cell, an error flag is set in the data stream passed to the corresponding output module. During the data frame reassembly process, the output module detects any internal information cell... If effective, immediately truncate the transmission of the current data frame and insert an incorrect Frame Check Sequence (FCS), forcing downstream devices to discard the data frame.

[0053] In this embodiment, to overcome the problems of low buffering efficiency, difficulty in scheduling timing convergence, and system deadlock caused by single-event upsets in existing spaceborne switching technologies under resource-constrained and high-radiation environments, a high-speed switching method for low-Earth orbit constellations based on FPGA is provided. This invention adopts an integrated architecture of "cell slicing + local sharing + three-stage pipeline scheduler + multi-dimensional state comparison," realizing high-speed switching and highly reliable autonomous recovery of N modules on a single FPGA device.

[0054] In this embodiment, the Ingress module (input module) receives variable-length Ethernet data frames, performs CRC checks and extracts flow feature identifiers; it searches the local forwarding table based on the extracted flow feature identifiers to obtain the local forwarding table; then it performs a fixed-length logical segmentation operation to cut the variable-length data frame into multiple fixed-length internal cells, pads the last insufficient internal cell to make its length a fixed value, and generates an internal switching header containing routing information.

[0055] In this embodiment, a local shared memory architecture with separate data plane and control plane is used to construct the switching system: In the data plane, the internal cells after cell segmentation are written sequentially into the local shared data pool constructed by the on-chip block memory of the FPGA, and the physical storage address pointer of the cell in the local shared data pool is obtained. The local shared data pool enables hard core error checking and correction (ECC); in the control plane, according to the target output module of the data frame, the physical storage address pointer is... Push in input module The corresponding virtual output queue address is in the FIFO; each input module Configure M logically independent address FIFOs as virtual output queues, each pointing to one of the M output modules; the three-level pipeline scheduler recalculates the execution strategy in each clock cycle and schedules according to the execution strategy.

[0056] In this embodiment, the hardware parameters such as the number of input modules, the number of output modules, the storage depth, the bit width, and the clock frequency all have parameterizable configuration characteristics. Those skilled in the art can adjust these parameters according to the resource scale and business requirements of the target FPGA chip in practical applications. Such parameterized variations based on the concept of this invention should be included within the protection scope of this invention.

[0057] This embodiment is built on a Field-Programmable Gate Array (FPGA) platform. Thanks to the linear optimization design of on-chip resources in this invention, this architecture can be adapted to radiation-hardened FPGA chips with different resource levels. For example... Figure 1As shown, the system is logically divided into a data plane and a control plane. The data plane is responsible for carrying high-bandwidth service traffic, including N Ingress preprocessing modules (input modules), N storage queuing units, and N Egress reassembly modules; the control plane is responsible for core scheduling and state management, including a three-level pipeline scheduler, an audit and self-healing controller, and the control plane for each storage queuing unit; the system adopts a global synchronous clock domain design to ensure the timing convergence of the pipeline logic.

[0058] In this embodiment, the Ingress module (input module) mainly includes three stages in its data frame processing flow: physical layer adaptation, forwarding information parsing, and cell slicing.

[0059] In the first phase, the ngress interface receives data frames from the link layer via the internal bus. The verification logic first calculates and compares the Frame Check Sequence (FCS) at the end of the data frame. If the verification fails, the state machine discards the frame at the entry point without triggering subsequent operations; if the verification passes, the data frame is written into the first-level FIFO for buffering and processing.

[0060] In the second stage, the parsing logic extracts the flow feature identifier from the data frame header as a lookup key. Depending on the application scenario, the flow feature identifier can be the destination MAC address, destination IP address, or flow tag, etc. This key is then sent to the local forwarding table for matching, obtaining the following two key control pieces of information: the target output module vector; used to indicate which output module(s) the frame should be forwarded to; in this embodiment, unicast is used as an example, i.e., obtaining a unique target module index, denoted as . Service Priority (Class of Service): Used to map internal service quality levels, denoted as... .

[0061] In the third stage, to adapt to the physical page management mechanism of the subsequent local shared storage pool, the slicing logic divides the variable-length Ethernet frame into several fixed-length internal cells; the length of the internal cell is set to L bytes. If the data frame length is not an integer multiple of L, padding is added to the end of the last cell, and the number of valid bytes is recorded. An internal header is encapsulated before the first cell. This header encapsulates the target output module number j, priority p, and data frame length obtained in the previous steps, and is used to carry control information transmitted across modules.

[0062] Please see Figure 2This embodiment aims to address the challenge of cache resources growing quadratically with the number of modules in traditional crossbar switch architectures. The invention proposes a two-dimensional decoupled architecture combining physically centralized storage and logical virtual queuing. At the hardware level, this architecture consists of an input management state machine, a local shared data pool, an output scheduling state machine, a free address linked list, and multi-virtual output queue address management. The specific implementation process is as follows:

[0063] Step 1: Instantiate a dual-module block RAM on the FPGA to construct a locally shared data pool. This data pool is logically divided into... A fixed-length physical page, each physical page size strictly matching the internal cell length L; establish a depth of... The free address linked list is essentially a first-in-first-out queue; after the system is powered on and reset, the input management state machine executes the initialization sequence, which sets the address pointers of all physical pages in the shared data pool ( to The data is sequentially written to the Free List. At this point, the Free List is full, indicating that all physical resources are available for allocation. When the Ingress module outputs a sliced ​​fixed-length cell, the input management FSM performs the following atomic operation: The FSM attempts to pop a free physical address pointer from the head of the Free List. If the Free List is empty, it indicates that physical storage resources are exhausted. The FSM immediately pulls a backpressure signal high to the front-end Ingress module, suspending cell reception until a new address is released. Then, the input management FSM writes the information data (Data Payload) into the local shared data pool. The physical address unit is pointed to; at this time, the ECC logic of the RAM hard core works synchronously, generating a checksum based on the written data and storing it in the redundant bit width to complete the radiation hardening of the data. In order to eliminate head-of-line blocking (HOL blocking), this invention maintains a set of logically independent address FIFOs for each input module; assuming that the target output module of the current cell is j; the FSM will allocate the physical address pointer The information cell attribute bits (such as SOP / EOP identifiers) are encapsulated into a short control word; the FSM only writes this control word to a specific address FIFO (virtual output queue) belonging to module j, without moving heavy-load data in the data pool; through the above mechanism, this embodiment realizes dynamic statistical multiplexing of storage resources: the physical data pool is no longer mechanically divided among various output modules, and the total amount of on-chip BRAM resources required by the system depends only on the total throughput and the expected burst tolerance, and is linearly related to the number of modules N. .

[0064] Please see Figure 3 In this embodiment, to overcome the uncertainty in the iteration convergence time of traditional iterative scheduling algorithms (such as iSLIP), this invention designs a fully parallel, deterministic three-stage pipelined scheduling architecture. This architecture utilizes the parallel logic resources of the FPGA to decompose the complex bipartite graph matching problem into three atomic-level pipeline stages: state masking, parallel arbitration, and conflict resolution, ensuring completion within a single clock cycle. The specific implementation process for large-scale scheduling decisions is as follows:

[0065] First-stage pipeline: The main task of this stage is pre-screening, that is, eliminating invalid requests and invalid contention before arbitration occurs; the scheduler collects request signals (internal exchange header information) from each virtual output queue; and constructs the original... Request bitmap matrix Real-time acquisition of backpressure status from downstream Egress modules (output modules) and read module status from the shared storage pool; the mask logic module performs bitwise AND operations to generate an availability mask matrix. If an output module j is in a congested state, or the output scheduling state machine corresponding to an input module i is already occupied, then the corresponding request bit... Forced to be zeroed; this mechanism ensures that all requests entering the next level of arbitration are physically executable at the current moment, effectively avoiding the associated effects of head-of-line blocking (HOL);

[0066] Second-stage pipeline: In this stage, the system leverages the parallel computing capabilities of the FPGA to execute policy generation independently and in parallel within the scheduling logic modules corresponding to the M output modules. Each scheduling logic module maintains a set of status registers for that output module, including the current transmission license quota. Preset bandwidth weight increment and quota saturation limit The specific logic flow is as follows: To avoid the network being impacted by subsequent bursts of traffic due to the continuous issuance of quotas to idle queues in traditional algorithms, this embodiment introduces an active queue set. The concept is as follows: The hardware logic first scans all virtual output queues currently pointing to output module j, identifies input modules with non-empty caches as active members, and forms a set. Subsequently, the parallel comparator detects... Current quota for each queue Is it less than the length of the data frame at the head of the queue? If and only if the active set When all queues are in a quota-insufficient state (i.e., unable to send the current head packet), the hardware triggers a quota replenishment operation. The replenishment operation is based on the formula...

[0067]

[0068] The module updates the quotas of all active queues in parallel. This mechanism ensures that quotas are only replenished when truly needed and no one can send packets, thus precisely controlling traffic shaping while maintaining job continuity. After the quota status is updated (or when no update is needed), the logic module combines the availability mask matrix generated by the first-level pipeline. Calculate the final qualified request identifier. The calculation logic is as follows:

[0069]

[0070] In other words, for a request to be deemed valid, two conditions must be met simultaneously: the physical link and flow control status must be available. And the current quota is sufficient to cover the length of the head-of-line packet. Finally, in the generated qualified request vector, the scheduler performs absolute priority arbitration. The system scans all... The request is directly locked by using the preamble 1 detection logic as the candidate scheduling strategy for the output module. This design ensures that high-priority services can preempt the transmission channel with zero waiting time when the quota is sufficient, while low-priority services obtain weighted fair bandwidth under the constraint of the quota mechanism.

[0071] The third-level pipeline: This is the final stage of the pipeline, primarily responsible for handling resource contention among input modules and completing the final execution of the scheduling results and state write-back. The specific implementation logic is as follows:

[0072] The second-level pipeline generates M candidate scheduling strategies, which may result in multiple output modules simultaneously selecting the same input module i. In this case, the global arbitration matrix will perform parallel detection on all requests received by each input module i. The arbitration logic adopts a two-layer decision-making mechanism: Layer 1: First, compare the business priority information p carried in all conflicting requests. The arbitrator directly retains the request with the highest priority, which ensures that critical business flows have the highest preemption right across the entire system. Layer 2: If there are multiple conflicting requests with the same highest priority, the Round-Robin arbitrator is activated. Based on the current RR pointer position maintained by the input module, one of the output modules is fairly selected as the final winner, and the RR pointer is updated to point to the next position to prevent starvation between services of the same priority. Once the conflict is resolved, the system generates the final scheduling matrix. The input / output pairs are locked. At this point, the hardware logic triggers a critical credit consumption operation to form a closed-loop control. The update logic is as follows: For each virtual queue that has obtained final scheduling authorization, the actual length of its head data frame is read, and the corresponding value is deducted from its current transmission license quota. The update formula is:

[0073]

[0074] in, For the current scheduling period of the virtual output queue, the transmission license quota, For the next cycle of transmission license quota, The length of the scheduled data frame. The initial transmission license quota.

[0075] This deduction mechanism based on actual packet length (rather than simply decrementing the packet count) achieves precise byte-level bandwidth metering, ensuring that the actual bandwidth occupied by each service flow strictly conforms to the preset weight ratio in variable-length message exchange scenarios. Finally, the scheduler issues a dequeue command to the virtual output queue, initiating the transmission of data from the shared buffer pool to the Egress module.

[0076] Please see Figure 4 In this embodiment, to address the issue of logic pointer drift caused by single-event upsets (SEUs) in the high-radiation environment of low Earth orbit, this invention constructs a bypass-style hardware audit plane outside the conventional data exchange path. This plane, through real-time auditing and a tiered response mechanism, automatically repairs logic deadlocks within milliseconds, ensuring the device possesses long-term on-orbit self-healing capabilities. The specific implementation process is as follows:

[0077] Constructing a 3D state mirror

[0078] The audit controller periodically takes snapshots of each virtual output queue within the system, obtaining status count values ​​in three dimensions:

[0079] Logical expected value : Represents the logical mirror depth, incremented by 1 with the enqueue signal and decremented by 1 with the dequeue signal; it originates from the logical counter of the virtual output queue manager and represents the number of cells that the software logic believes should exist in the current queue.

[0080] Physical Real Value : Indicates the actual storage depth of the virtual output queue, which is derived from the difference between the physical read and write pointers of the shared RAM controller, representing the number of physical pages actually occupied by this queue in the hardware storage pool.

[0081] Failure accumulation value : Represents the cumulative number of ECC failures. This value is incremented by 1 when an uncorrectable ECC error occurs from a physical page in the local shared data pool. It is an error counter derived from the ECC check logic and represents the number of cells that have been automatically discarded by the hardware due to uncorrectable bit errors.

[0082] Perform a real-time balance audit:

[0083] During each audit cycle, the controller uses a hardware adder to perform a balance equation check on the three variables mentioned above:

[0084]

[0085] In an ideal, error-free state, the total number of logically recorded cells should be strictly equal to the sum of the physically existing number of cells and the known loss (ECC packet loss), i.e. It is always equal to 0.

[0086] like This indicates a silent logic fault has occurred in the system. This is usually due to the SEU hitting the state machine's state register or address pointer, causing the logical pointer to become out of sync with the physical memory. Such faults cannot be detected by ECC and will lead to a "false full" deadlock if left unattended.

[0087] Level 1 self-healing: Precise repair based on micro-reset; when a single queue is detected to meet the requirements... When the fault occurs, a first-level self-healing process is triggered: only the specific virtual output queue that has failed and its corresponding address FIFO are locked; the read and write pointers of the virtual output queue are forcibly reset to zero, and all physical addresses it occupies are released back to the Free List; this operation only takes a few clock cycles and only affects a single traffic category of a single module, while the normal forwarding services of the other N-1 modules are completely unaffected, thus achieving fault repair.

[0088] Level 2 Self-Healing: A threshold-based system-level reset. After prolonged system operation, if the number of failed physical pages (zombie pages) due to multiple ECC errors accumulates excessively, threatening the overall availability of the system, the Level 2 self-healing process is triggered. The controller continuously calculates the total failure value of all queues across the entire system in real time. Set tolerance threshold When the conditions are met When the system determines that the available physical page resources have been exhausted due to accumulated errors, a secondary global reset is triggered: a system-level reset initialization is performed on the local shared data pools and corresponding free address lists of all input modules. To achieve a balance between ensuring service continuity and avoiding congestion deadlock, the threshold... Set according to the following formula:

[0089]

[0090] in: The total number of physical pages configured for the local shared data pool; The minimum burst buffer space reserved by the switching system to meet specific packet loss rate requirements; A preset safety redundancy margin is used to prevent the counter from overflowing. This calculation logic ensures that as long as the number of failed pages has not been reached... The remaining available physical resources are always sufficient to support the system's maximum designed burst traffic, thus avoiding business interruptions caused by blind resets.

[0091] In this embodiment, the Egress module (output module), as the output terminal of the switching architecture, is mainly responsible for the protocol restoration from cells to data frames and the final integrity verification. The Egress module has built-in M independent reassembly contexts corresponding to the number of output modules. The state machine concurrently restores discrete fixed-length cells from the local shared memory pool into variable-length Ethernet frames based on the SOP / EOP identifier and sequence number carried in the cell header. To prevent error propagation, when a cell with an uncorrectable ECC mark is received from upstream, the reassembly logic does not immediately interrupt; instead, it forcibly generates an invalid frame check sequence (Invalid FCS) at the end of the currently reassembling data frame and truncates the transmission. This mechanism utilizes the physical layer verification rules of the Ethernet protocol standard to ensure that downstream devices can automatically identify and discard the damaged frame.

[0092] In summary, this invention achieves dynamic reuse and linear expansion of storage resources through a separation architecture of "local shared data pool + virtual output queue," significantly reducing on-chip storage consumption and avoiding storage fragmentation. Utilizing an end-to-end availability mask and a non-iterative three-stage pipeline scheduling, it achieves cycle-by-cycle continuous scheduling while ensuring timing convergence, effectively solving the head-of-queue blocking problem. Through the three-dimensional state verification and hierarchical reset mechanism of the self-healing controller, it autonomously repairs logic errors caused by single-event flips, avoiding system deadlock. Simultaneously, without relying on external storage, it achieves line-rate forwarding while meeting the constraints of volume, weight, and power consumption (SWaP) in the spaceborne environment, filtering ECC error frames, and significantly improving the throughput, bandwidth utilization, and on-orbit survivability of low-Earth orbit satellite networks, fully adapting to high-concurrency, high-radiation spaceborne application scenarios.

[0093] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-speed switching method for low-orbit constellations based on FPGA implementation, characterized in that, The method is applied to a switching system built on an FPGA, the switching system including N input modules, M output modules, and a switching core located therebetween; the switching core includes multiple parallel storage queuing units and a three-stage pipeline scheduler; Each storage queuing unit includes a locally shared data pool, a free address list, and a virtual output queue corresponding to M output modules. The method includes: S1: Receive data frames through each input module and perform integrity verification on them; use the stream feature identifier of the data frame as the lookup key value, and match it in the local forwarding table to obtain the target output module and service priority of the data frame; S2: The received data frame is split into multiple fixed-length internal information cells, and internal exchange header information is generated according to the target output module, service priority, and length of the data frame; wherein, each local shared data pool includes multiple physical pages of the same size, each physical page corresponds to an address, and the size of each internal information cell is the same as the size of the physical page in the local shared data pool; S3: Store the internal information cell into the free physical page of the local shared data pool according to the corresponding free address list, and store the internal exchange header information and the address corresponding to the physical page into the corresponding virtual output queue, and update the corresponding free address list. S4: The three-level pipeline scheduler generates a scheduling strategy based on the non-empty request status of each virtual output queue, the flow control status of each output module, and the ready status of each storage queuing unit. S5: Read internal information cells from physical pages in the local shared data pool according to the scheduling policy and each virtual output queue, and update the corresponding free address linked list; S6: The read internal information cells are reassembled into data frames by each output module and then transmitted.

2. The low-orbit constellation high-speed switching method based on FPGA according to claim 1, characterized in that, Integrity verification of data frames includes: using Frame Check Sequence (FCS) to verify the integrity of data frames, and comparing the FCS recalculated from the valid data of the data frame with the reserved FCS field at the end of the data frame to ensure that the data has not been tampered with or corrupted.

3. The low-orbit constellation high-speed switching method based on FPGA implementation according to claim 1, characterized in that, The flow feature identifier of the data frame includes: destination MAC address, destination IP address, and flow label; the local lookup table contains mapping entries from flow feature identifiers to forwarding control information, which includes: target output module and service priority; the target output module and service priority corresponding to the data frame are obtained by mapping the flow feature identifier of the data frame in the local lookup table.

4. The low-orbit constellation high-speed switching method based on FPGA according to claim 1, characterized in that, The internal exchange header information includes: the target output module of the data frame, the service priority, and the length of the data frame; the internal exchange header information is stored in the virtual output queue before the first internal cell of the data frame; wherein, the identifier SOP is added to the physical page storage address of the first internal cell of the data frame, and the identifier EOP is added to the physical page storage address of the last internal cell of the data frame.

5. The low-orbit constellation high-speed switching method based on FPGA according to claim 4, characterized in that, Each storage queuing unit is equipped with an input management state machine and an output scheduling state machine. The input management state machine is used to store internal information cells into the idle physical pages of the local shared data pool according to the corresponding idle address list, and to store the internal exchange header information and the address corresponding to the physical page into the corresponding virtual output queue. The output scheduling state machine is used to read internal information cells from the physical pages of the local shared data pool according to the scheduling policy and the addresses recorded in each virtual output queue.

6. The low-orbit constellation high-speed switching method based on FPGA according to claim 5, characterized in that, The generation scheduling strategy includes: S41: Collect internal exchange header information from each virtual output queue to construct the original N×N request bitmap matrix. , , , Indicates the first The first input module and the first There are requests in the virtual output queue of each output module; Indicates the first The first input module and the first There are no requests in the virtual output queue of each output module; S42: Construct the output flow control vector , , , Indicates output module idle; This indicates that the output module is in use; S43: Construct the input ready vector , , , Indicates output module The corresponding output scheduling state machine for the input buffer swapping is idle; Indicates input module The output scheduling state machine of the corresponding storage queuing unit is occupied; S44: Construct an availability mask matrix , , among which, element The calculation formula is: in, This represents the logical AND operation; Indicates the first The input module to the first Availability requests for each output module; Indicates the first The input module to the first Requests for each output module are available. Indicates the first The input module to the first The request for the output module is unavailable; S45: Read the current... The input module is for the first Virtual output queues for each output module Transmission license quota The length of the head data frame of the virtual output queue. and each virtual output queue Preset bandwidth weight increment and quota saturation limit ; Identify the output module Furthermore, a non-empty virtual output queue is cached to form the output module. active queue set ;judge Are all virtual output queues in a state of insufficient quota? If so, then trigger the quota replenishment operation of the virtual output queue, and update the formula as follows: Based on the updated transmission allowance quota of the virtual output queue and the length of the head data frame of the virtual output queue. ; Calculate the qualified request identifier: in, Indicates a qualified request identifier, indicating the first The input module to the first The request from each output module is valid; In the output module Among all qualified requests, the qualified request with the highest business priority is selected as the candidate scheduling strategy for this output module; S46: Determine if multiple output modules exist. The same input module was selected at the same time. If a request is eligible, then compare the business priorities of the conflicting requests and retain the request with the highest priority; if the priorities are the same, then select one of the eligible requests as the final scheduling strategy based on the round-robin pointer. For the virtual output queue corresponding to the final scheduling policy, perform a transmission license quota update operation. The update formula is as follows: in, For the current scheduling period of the virtual output queue, the transmission license quota, For the next cycle of transmission license quota, The length of the scheduled data frame. The initial transmission license quota.

7. The low-orbit constellation high-speed switching method based on FPGA according to claim 5, characterized in that, For each virtual output queue, three variables are monitored in real time: , and ; It represents the logical mirror depth, incrementing by 1 with the enqueue signal and decrementing by 1 with the dequeue signal; Indicates the actual storage depth of the virtual output queue; This represents the cumulative ECC failure count, which is incremented by 1 each time an uncorrectable ECC error occurs from a physical page in the local shared data pool; the balance equation is checked every clock cycle. ,like Furthermore, after a specific clock cycle, if a logic error caused by a single-event upset occurs, a first-level micro-reset is performed on the virtual output queue: suspending read / write operations on the virtual output queue, resetting the address FIFO of the virtual output queue, and resetting... and Simultaneously, the exchange system maintains the global failure accumulation value. ,in, Represents the k-th virtual output queue; sets the tolerance threshold. When the conditions are met When the system determines that the available physical page resources have been exhausted due to accumulated errors, a second-level global reset is triggered: system-level reset initialization is performed on the local shared data pool and the corresponding free address list for all input modules.

8. The low-orbit constellation high-speed switching method based on FPGA according to claim 7, characterized in that, The tolerance threshold includes: in: The total number of physical pages configured for the local shared data pool; The minimum burst buffer space reserved by the switching system to meet specific packet loss rate requirements; A preset safety redundancy margin value to prevent counter overflow.

9. A high-speed switching method for low-orbit constellations based on FPGA implementation according to claim 5, characterized in that, When reading internal cells from the local shared data pool, if an ECC check error is detected in the internal cell, an error flag is set in the data stream passed to the corresponding output module. ; During the data frame reassembly process, the output module detects any internal information cell... If effective, immediately truncate the transmission of the current data frame and insert an incorrect Frame Check Sequence (FCS), forcing downstream devices to discard the data frame.

Images