Switching element

Abstract

The switching element includes a semiconductor substrate provided with a trench, a gate insulating film, and a gate electrode. The semiconductor substrate has a source region, a body region, a drift region, a first electric field relaxation region, and a connection region. The drift region is in contact with the gate insulating film on a side surface of the trench on the lower side of the body region and a bottom surface of the trench. The first electric field relaxation region is disposed inside the drift region, is disposed at a lower portion of the trench at a distance from a bottom surface of the trench, and extends along the bottom surface of the trench. The connection region protrudes downward from the body region so as to reach the first electric field relaxation region, and extends lengthwise in a direction intersecting the trench when viewed from above. When [epsilon] (F / cm) is the dielectric constant of the connection region, Ec (V / cm) is the critical electric field intensity of the connection region, e (C) is the element charge, and Q (cm-2) is the surface density of the p-type impurity in a plan view of the connection region located below the trench from above, Qgt is satisfied. Ec / e.

Description

[0001] This application is a divisional application of the original application filed on November 22, 2019, with application number 201980102398.0 and invention title "Switching Element". Technical Field

[0002] The technology disclosed in this specification relates to a switching element. Background Technology

[0003] The switching element disclosed in Japanese Patent Publication No. 2009-158681 includes a semiconductor substrate and a gate electrode. A trench is formed on the upper surface of the semiconductor substrate. A gate electrode is disposed within the trench. The gate electrode is insulated from the semiconductor substrate by a gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, and an electric field mitigation region (bottom region). The source region is an n-type region that is in contact with the gate insulating film on the side of the trench. The body region is a p-type region that is in contact with the gate insulating film on the side of the trench below the source region. The drift region is an n-type region disposed below the body region and in contact with the gate insulating film on the side and bottom surface of the trench below the body region. The electric field mitigation region is a p-type region disposed inside the drift region and spaced apart from the bottom surface of the trench at the lower part of the trench. Summary of the Invention

[0004] The problem the invention aims to solve In the switching element of Patent Document 1, in the event of avalanche breakdown, a portion of the holes generated near the electric field mitigation region are injected into the gate insulating film as they flow from the drift region to the bulk region. This causes problems such as changes in the characteristics of the gate insulating film and variations in the gate threshold. This specification proposes a technique that can suppress changes in the characteristics of the gate insulating film in the event of avalanche breakdown.

[0005] Solution for solving the problem The switching element disclosed in this specification comprises: a semiconductor substrate having a trench formed on its upper surface; a gate insulating film covering the inner surface of the trench; and a gate electrode disposed within the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, a first electric field mitigation region, and a connection region. The source region is an n-type region connected to the gate insulating film on a side of the trench. The body region is a p-type region connected to the gate insulating film on a side below the source region. The drift region is an n-type region disposed below the body region, connected to the gate insulating film on a side below the body region, and connected to the gate insulating film on the bottom surface of the trench. The first electric field mitigation region is a p-type region disposed inside the drift region, spaced apart from the bottom surface of the trench, and extending along the bottom surface of the trench. The connecting region is a p-type region that protrudes downward from the body region in a manner reaching the first electric field mitigation region and extends relatively long in the direction intersecting the trench when viewed from above. Let the dielectric constant of the connecting region be ε (F / cm), the critical electric field strength of the connecting region be Ec (V / cm), the elementary charge be e (C), and the areal density of the p-type impurities in the connecting region located at the lower part of the trench when viewed from above be Q (cm³). -2 When ), Q>ε·Ec / e is satisfied.

[0006] When the switching element is turned off, the electric field tends to concentrate in the portion where the connection region connects to the first electric field mitigation region. Therefore, in this switching element, avalanche breakdown occurs near the portion where the connection region connects to the first electric field mitigation region. Holes generated by avalanche breakdown flow through the connection region to the bulk region. Furthermore, in this switching element, the areal density Q satisfies the above equation, so the depletion layer extending within the connection region does not reach the lower end of the trench. That is, a non-depletion region (the area where the depletion layer has not extended) remains in the connection region around the lower end of the trench. The non-depletion region suppresses the injection of holes flowing in the connection region (holes generated by avalanche breakdown) into the gate insulating film. Therefore, in the above-described switching element, even in the event of avalanche breakdown, changes in the characteristics of the gate insulating film can be suppressed. Attached Figure Description

[0007] Figure 1 This is a three-dimensional cross-sectional view of the MOSFET in Example 1.

[0008] Figure 2 yes Figure 1 A cross-sectional view on plane II.

[0009] Figure 3 yes Figure 1 A cross-sectional view on plane III.

[0010] Figure 4 yes Figure 1 A cross-sectional view on plane IV.

[0011] Figure 5 yes Figure 1 A cross-sectional view on plane V.

[0012] Figure 6 The MOSFET corresponding to Example 2 Figure 3 Cross-sectional view.

[0013] Figure 7 The MOSFET corresponding to Example 2 Figure 4 Cross-sectional view.

[0014] Figure 8 This is a plan view of the MOSFET in Example 2. Detailed Implementation

[0015] The following lists the technical elements disclosed in this specification. Furthermore, each of the following technical elements is useful independently.

[0016] In one example of the structure disclosed in this specification, the semiconductor substrate may also be made of silicon carbide, satisfying Q > 1.49 × 10⁻⁶. 13 .

[0017] In one example of the structure disclosed in this specification, the structure may also be such that: a plurality of trenches are provided on the upper surface of the semiconductor substrate, a plurality of connection regions are provided, a plurality of first electric field mitigation regions are provided, and a plurality of p-type second electric field mitigation regions are also provided. Each first electric field mitigation region is disposed at the lower part of the corresponding trench, each connection region extends in a manner that intersects with the plurality of trenches, and each second electric field mitigation region is disposed at the lower part of the corresponding connection region, connected to the corresponding connection region, and extends in a manner that intersects with the plurality of first electric field mitigation regions.

[0018] In this structure, the electric field concentration near the lower end of the connection region is suppressed when the switching element is off. Furthermore, the first and second electric field mitigation regions are configured in a lattice pattern when viewed from above. Therefore, when the switching element is off, the depletion layer rapidly extends from the first and second electric field mitigation regions to the drift region surrounded by them. This rapid expansion of the depletion layer within the drift region reduces the drain-source capacitance of the switching element.

[0019] In one example of the structure disclosed in this specification, the p-type impurity concentration in the connection region may also be higher than the p-type impurity concentration in the first electric field mitigation region.

[0020] In this structure, the electric field is more likely to concentrate near the part where the connecting region connects to the first electric field easing region. Therefore, avalanche breakdown can occur near the part where the connecting region connects to the first electric field easing region.

[0021] (Example 1) Figures 1-5 The MOSFET (metal-oxide-semiconductor field-effect transistor) 10 is shown as an embodiment. The MOSFET 10 has a semiconductor substrate 12. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 will be referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction will be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction. Figures 2-5 As shown, electrodes, insulating films, etc., are disposed on the upper surface 12a of the semiconductor substrate 12. Furthermore, in Figure 1 For illustrative purposes, the diagram of the structure on the upper surface 12a of the semiconductor substrate 12 is omitted.

[0022] The semiconductor substrate 12 is made of silicon carbide (SiC). Multiple trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12. For example... Figure 1 As shown, a plurality of trenches 22 extend parallel to each other on the upper surface 12a. The plurality of trenches 22 extend relatively long in a straight line along the y-direction. The plurality of trenches 22 are arranged at intervals in the x-direction. A gate insulating film 24 and a gate electrode 26 are disposed inside each trench 22.

[0023] The gate insulating film 24 covers the inner surface of the trench 22. The gate insulating film 24 has a side insulating film 24a covering the sides of the trench 22 and a bottom insulating film 24b covering the bottom surface of the trench 22. The gate insulating film 24 is made of silicon oxide, for example.

[0024] Gate electrode 26 is disposed within trench 22. Gate electrode 26 is insulated from semiconductor substrate 12 by gate insulating film 24. Figure 2 , Figure 3 as well as Figure 5 As shown, the upper surface of the gate electrode 26 is covered by an interlayer insulating film 28.

[0025] A source electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The source electrode 70 covers the upper surface 12a and the interlayer insulating film 28. The portion of the source electrode 70 without the interlayer insulating film 28 is in contact with the upper surface 12a of the semiconductor substrate 12. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A drain electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The drain electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

[0026] like Figure 1 As shown, multiple source regions 30, body regions 32, drift regions 34, drain regions 35, multiple first electric field relaxation regions 36, and multiple connection regions 38 are disposed inside the semiconductor substrate 12.

[0027] Each source pole region 30 is an n-type region. For example... Figure 1 and Figure 2 As shown, multiple source regions 30 are arranged in each semiconductor region (hereinafter referred to as the inter-trench region) sandwiched by adjacent trenches 22. Figure 1 and Figure 4 As shown, in each trench region, multiple source regions 30 are arranged at intervals along the y-direction. Figure 2 and Figure 4 As shown, each source region 30 is disposed on the upper surface 12a facing the semiconductor substrate 12 and makes ohmic contact with the source electrode 70. Each source region 30 is connected to two trenches 22 located on both sides of the trench region. Each source region 30 is connected to the side insulating film 24a at the upper end of the trench 22.

[0028] Body region 32 is a p-type region. Body region 32 has multiple contact regions 32a and main body regions 32b.

[0029] Each contact region 32a is a p-type region with a high concentration of p-type impurities. For example... Figure 1 and Figure 3 As shown, each contact region 32a is disposed in the inter-trench region. Each contact region 32a is disposed in the area facing the upper surface 12a of the semiconductor substrate 12. Multiple contact regions 32a are disposed in each inter-trench region. Figure 1 and Figure 4 As shown, in each trench region, the source region 30 and the contact region 32a are alternately arranged in the y-direction. Therefore, the contact region 32a is positioned between the two source regions 30. Each contact region 32a makes ohmic contact with the source electrode 70.

[0030] The main region 32b is a p-type region where the concentration of p-type impurities is lower than that of each contact region 32a. For example... Figures 1-4 As shown, the main body region 32b is disposed below each source region 30 and each contact region 32a. The main body region 32b is connected to each source region 30 and each contact region 32a from below. The main body region 32b is distributed over the entire area below each source region 30 and each contact region 32a. Figure 2 and Figure 3 As shown, the main body region 32b is connected to the side insulating film 24a on the lower side of the source region 30. The lower end of the main body region 32b is positioned above the lower end of the gate electrode 26.

[0031] like Figure 3 and Figure 4 As shown, a plurality of connecting areas 38 extending downward from the main body area 32b are provided at the lower part of the contact area 32a. Each connecting area 38 extends to a position lower than the lower end of the trench 22. Figure 2 and Figure 4 As shown, no connection region 38 is provided in the lower part of the source region 30. Figure 3 As shown, the connecting area 38 extends along the direction (x direction) intersecting the groove 22. As... Figure 1 and Figure 4 As shown, similar to contact region 32a, multiple connection regions 38 are arranged at intervals in the y-direction. The p-type impurity concentration of each connection region 38 is higher than that of the main body region 32b.

[0032] Drift region 34 is an n-type region with low n-type impurity concentration. For example... Figures 1-4 As shown, the drift region 34 is disposed below the body region 32 (more specifically, the main body region 32b) and the connecting region 38. The drift region 34 is connected to the main body region 32b and the connecting region 38 from below. Additionally, as... Figure 4 As shown, the drift region 34 is also distributed in the area sandwiched between two adjacent connecting regions 38 in the y-direction. That is, in Figure 4 In the cross-section shown, the drift region 34 and the connection region 38 are connected laterally. The drift region 34 is separated from each source region 30 through the main body region 32b. Figure 1 and Figure 2 As shown, the drift region 34 extends from the inter-groove area to a region lower than each groove 22. Figure 2 As shown, the drift region 34 is in contact with the side insulating film 24a on the lower side of the main body region 32b. Additionally, the drift region 34 is in contact with the bottom insulating film 24b in the area where the connection region 38 is not present. Positioned slightly lower than the lower end of the connection region 38, the drift region 34 is distributed over approximately the entire area of ​​the semiconductor substrate 12 in both the x and y directions.

[0033] Drain region 35 is an n-type region where the n-type impurity concentration is higher than that of drift region 34. For example... Figures 1-5 As shown, the drain region 35 is disposed below the drift region 34. The drain region 35 is connected to the drift region 34 from below. The drain region 35 is disposed in the area facing the lower surface 12b of the semiconductor substrate 12 and makes ohmic contact with the drain electrode 72.

[0034] Each first electric field mitigation region 36 is a p-type region. The p-type impurity concentration in each first electric field mitigation region 36 is lower than the p-type impurity concentration in the connection region 38. Each first electric field mitigation region 36 is disposed within the drift region 34. Figures 1-3 As shown, each first electric field mitigation region 36 is disposed at intervals from the bottom surface of the corresponding trench 22 in the lower part of the trench 22. Figure 1 and Figure 5 As shown, each first electric field mitigation region 36 extends relatively long in the y-direction along the bottom surface of the corresponding trench 22. Figure 2 and Figure 5 As shown, in the area where the connection region 38 is absent, the first electric field mitigation region 36 is surrounded by a drift region 34. Therefore, the drift region 34 is positioned at the interval between the bottom surface of the trench 22 and the first electric field mitigation region 36. Figure 2 In the cross-section shown, the first electric field mitigation region 36 is in contact with the drift region 34 on its upper, side, and lower surfaces. For example... Figure 3 As shown, at the lower part of the connection region 38, the first electric field mitigation region 36 is connected to the lower end of the connection region 38. That is, each connection region 38 protrudes downward from the main body region 32b in such a way that it reaches each first electric field mitigation region 36. The lower end of each first electric field mitigation region 36 is positioned lower than the lower end of each connection region 38. As described above, the upper end of the connection region 38 is connected to the main body region 32b. Therefore, the first electric field mitigation region 36 is connected to the main body region 32b via the connection region 38. Therefore, the first electric field mitigation region 36 is connected to the source electrode 70 via the connection region 38, the main body region 32b, and the contact region 32a. Therefore, the potential of the first electric field mitigation region 36 is approximately equal to the potential of the source electrode 70.

[0035] In this embodiment, the MOSFET 10 is configured to satisfy the relationship Q > ε·Ec / e. Furthermore, the symbol ε represents the dielectric constant (F / cm) of the connection region 38. The symbol Ec represents the critical electric field strength (V / cm) of the connection region 38. The symbol e represents the elementary charge (C). The symbol Q represents the areal density Q (cm²) of the p-type impurities in the connection region 38 located in the lower part of the trench 22 (i.e., the portion of the connection region 38 located between the first electric field mitigation region 36 and the bottom surface of the trench 22) when viewed from above. -2 The areal density Q is equal to the concentration of p-type impurities (cm³) in the connecting region 38 located in the lower part of the trench 22. -3 The value obtained by integrating in the z-direction. In this embodiment, the semiconductor substrate 12 is made of silicon carbide, therefore ε = 8.55 × 10⁻⁶. -13 (F / cm), Ec=2.8×10 6 (V / cm). Additionally, e = 1.6 × 10⁻⁶ -19 (C). Therefore, to satisfy Q>1.49×10 13 The areal density Q of the connecting region 38 was adjusted in this way.

[0036] When using MOSFET 10, the drain electrode 72 is applied with a higher potential than the source electrode 70. When a voltage above the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32b in contact with the gate insulating film 24, and the switching element 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears, and MOSFET 10 is turned off.

[0037] When MOSFET 10 is off, the potential of the drain electrode 72 is much higher than the potential of the source electrode 70. In this state, the drift region 34 has a potential close to that of the drain electrode 72. Furthermore, as described above, the first field mitigation region 36 has a potential approximately equal to that of the source electrode 70. Therefore, a high reverse voltage is applied to the pn junction at the interface between the drift region 34 and the first field mitigation region 36. Consequently, the depletion layer extends extensively from the first field mitigation region 36 to the drift region 34. This ensures the breakdown voltage of MOSFET 10.

[0038] When MOSFET 10 is turned off, drift region 34 is depleted, and depletion layer 80 (dotted shaded area) continues to extend within the p-type region (i.e., first electric field mitigation region 36, connection region 38, body region 32). In areas where connection region 38 is not provided, such as... Figure 2 As shown, the depletion layer 80 extends over almost the entire region of the first electric field mitigation region 36, and extends from the drift region 34 to a portion of the main body region 32b. Figure 4 As shown, the depletion layer 80 extends into the interior of the p-type region along the interface between the p-type region (connection region 38 and main body region 32b) and the drift region 34.

[0039] In the MOSFET 10 of this embodiment, the p-type impurity concentration in the connection region 38 is higher than that in the first field mitigation region 36. Therefore, the connection region 38 is less likely to be depleted compared to the first field mitigation region 36. Furthermore, the high p-type impurity concentration in the connection region 38 makes the first field mitigation region 36 adjacent to the connection region 38 less likely to be depleted compared to other areas of the first field mitigation region 36. Therefore, within the area containing both the first field mitigation region 36 and the connection region 38, such as... Figure 3 and Figure 5As shown, the depletion layer 80 is curved. That is, a non-depleted region remains in the first electric field mitigation region 36 located in the lower part of the connection region 38. As a result, in the lower part of the connection region 38, the equipotential lines are curved, and the spacing between the equipotential lines becomes narrower. Thus, in the MOSFET 10 of this embodiment, the electric field is concentrated near the portion where the connection region 38 is connected to the first electric field mitigation region 36. Therefore, avalanche breakdown is prone to occur near the portion where the connection region 38 is connected to the first electric field mitigation region 36. Holes generated due to avalanche breakdown flow to the source electrode 70 via the connection region 38 and the body region 32. Here, if the areal density Q of the connection region 38 satisfies the above-described relationship, the depletion layer 80 extending in the connection region 38 will not reach the lower end of the trench 22. That is, even if an electric field of critical electric field strength is applied to the connection region 38, the depletion layer 80 will not reach the lower end of the trench 22. Therefore, a non-depletion region remains in the connection region 38 around the lower end of trench 22. In the non-depletion region, the hole movement speed is slower compared to the depletion region. Therefore, holes flowing in the connection region 38 (holes generated near the connection region 38 due to avalanche breakdown) suppressed by the non-depletion region are injected into the gate insulating film 24, and most of the holes flow to the source electrode 70. Thus, in this MOSFET 10, even in the event of avalanche breakdown, changes in the characteristics of the gate insulating film 24 can be suppressed.

[0040] (Example 2) Figures 6-8 This refers to MOSFET 100 in Example 2. Figure 6 This indicates the corresponding embodiment 1. Figure 3 The cross section, Figure 7 This indicates the corresponding embodiment 1. Figure 4 The cross-section. Additionally... Figure 8 This diagram shows a top view of the semiconductor substrate 12. Hereinafter, the same reference numerals are used for the same structural elements as in Embodiment 1, and their descriptions are omitted. In the MOSFET 10 of Embodiment 2, based on the structure of Embodiment 1, a plurality of second electric field mitigation regions 37 are provided inside the semiconductor substrate 12. Furthermore, in… Figure 8 In the diagram, the first electric field easing region 36 and the second electric field easing region 37 are represented by shaded areas.

[0041] like Figure 7 As shown, each second electric field mitigation region 37 is disposed at the lower part of the corresponding connection region 38. Each second electric field mitigation region 37 is connected to the corresponding connection region 38. The upper end of each second electric field mitigation region 37 is connected to the lower end of the corresponding connection region 38. Figure 6 As shown, each second electric field mitigation region 37 is positioned at approximately the same depth as each first electric field mitigation region 36. Figure 6 and Figure 8As shown, each second electric field mitigation region 37 extends in a manner that intersects with a plurality of first electric field mitigation regions 36. That is, each second electric field mitigation region 37 extends in the x-direction along the lower end of the corresponding connecting region 38. Each second electric field mitigation region 37 connects the plurality of first electric field mitigation regions 36 to each other. That is, as... Figure 8 As shown, each first electric field mitigation region 36 and each second electric field mitigation region 37 are configured in a lattice pattern when viewed from above. Each second electric field mitigation region 37 has approximately the same p-type impurity concentration as each first electric field mitigation region 36.

[0042] In this embodiment, a second electric field mitigation region 37 with a lower p-type impurity concentration than the connection region 38 is disposed at the lower part of the connection region 38. Therefore, when the MOSFET 100 is off, the second electric field mitigation region 37 is depleted, and the electric field applied to the connection region 38 is mitigated. Furthermore, the first electric field mitigation region 36 and the second electric field mitigation region 37 are configured in a lattice pattern when viewed from above. Therefore, the depletion layer rapidly extends from the first electric field mitigation region 36 and the second electric field mitigation region 37 to the drift region 34, which is surrounded by the first electric field mitigation region 36 and the second electric field mitigation region 37, and to the drift region 34 of the trench region above it. In this way, the depletion layer rapidly expands within the drift region 34, thereby reducing the drain-source capacitance of the MOSFET 100. As a result, the output capacitance of the MOSFET 100 is reduced, and the losses generated in the MOSFET 100 can be reduced. For example, when the MOSFET 100 is operated as a diode, recovery losses can be reduced.

[0043] In the embodiments described above, the connection region 38 is disposed at the lower part of the contact region 32a. However, the connection region 38 may not be disposed at the lower part of the contact region 32a, for example, it may be disposed at the lower part of the source region 30.

[0044] Furthermore, in the embodiments described above, the semiconductor substrate 12 is made of silicon carbide. However, the semiconductor substrate 12 may also be made of other semiconductor materials such as silicon (Si) or gallium nitride (GaN). In this case, the surface density Q can be appropriately set based on the dielectric constant and critical electric field strength of the material used.

[0045] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples described above. The technical elements illustrated in this specification or figures exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or figures achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A switching element, characterized in that, have: A semiconductor substrate with trenches formed on its upper surface; A gate insulating film covering the inner surface of the trench; and A gate electrode is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has: The n-type source region is in contact with the gate insulating film on the side of the trench; The p-type body region is in contact with the gate insulating film on the side below the source region; An n-type drift region is disposed on the lower side of the body region, the side surface of the lower side of the body region is in contact with the gate insulating film, and the bottom surface of the trench is in contact with the gate insulating film. A p-type first electric field mitigation region is disposed inside the drift region, spaced apart from the bottom surface of the trench, and extends along the bottom surface of the trench. as well as The p-shaped connection region protrudes downward from the body region in a manner that reaches the first electric field mitigation region, and extends in the direction intersecting the groove when viewed from above. The switching element further includes a source electrode disposed on the upper surface of the semiconductor substrate. The body region has a p-type contact region that makes ohmic contact with the source electrode. The p-type connection area is located below the p-type contact area.

2. The switching element according to claim 1, characterized in that, The body region also has a main body region with a lower concentration of p-type impurities than the p-type contact region. The main body region is connected to the source region and the p-type contact region from the bottom, and is in contact with the gate insulating film on the bottom side of the source region. The connecting area protrudes downward from the main body area. The concentration of p-type impurities in the connection region is higher than that in the main body region.

3. The switching element according to claim 1, characterized in that, The n-type drift region is located below the n-type source region. The n-type impurity concentration in the n-type drift region is lower than the n-type impurity concentration in the n-type source region.

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