Capacitor with electrically inactive metal layer

Abstract

The invention relates to a capacitor with an electrically inactive metal layer. The disclosed subject matter relates generally to semiconductor devices and structures in integrated circuit (IC) chips. More specifically, the present disclosure relates to a metal-dielectric-metal capacitor having an electrically inactive metal layer arranged in one interconnect level below another interconnect level comprising two sets of metal lines interdigitated with each other.

Description

Technical Field

[0001] This disclosure generally relates to structures in semiconductor devices and integrated circuit (IC) chips. More specifically, this disclosure relates to a metal-dielectric-metal capacitor having an electrically inactive metal layer disposed in an interconnect layer beneath another interconnect layer comprising two sets of intersecting metal lines. Background Technology

[0002] Rapid advancements in electronic technology and semiconductor manufacturing processes, driven by substantial customer demand, have led to the global adoption of electronic devices. Simultaneously, manufacturing processes continue to achieve smaller dimensions. One component in integrated circuit chips is the capacitor. Improvements in capacitor manufacturing technology allow for the production of capacitors with accurate and consistent capacitance values ​​while manufacturing dimensions continue to shrink. As manufacturing dimensions shrink, the spacing between adjacent metals formed during back-to-office (BEOL) processes also decreases, and, for example, in high-voltage applications, this reduced spacing can increase the likelihood of dielectric breakdown between adjacent metals.

[0003] One way to prevent breakdown between adjacent metals is to create dielectric material regions beneath and above the metal of the capacitor. However, to comply with minimum density design rules in semiconductor manufacturing, the area of ​​the individual parameterized cells (P-cells) containing the capacitor needs to be limited, thus reducing design flexibility. Furthermore, the spacing rules between adjacent P-cells must be kept above a minimum, which can result in a larger circuit footprint and wasted board space between adjacent P-cells. Summary of the Invention

[0004] In one aspect disclosed herein, a structure is provided in a semiconductor device having: a first interconnect level located above a substrate; a first plurality of metal layers located within the first interconnect level, wherein the metal layers in the first plurality of metal layers are electrically inactive; a second interconnect level located above the first interconnect level; and a second plurality of metal layers located within the second interconnect level, wherein the second plurality of metal layers includes a first set of metal lines intersecting with a second set of metal lines. Each of the first plurality of metal layers is vertically aligned only below each of the first set of metal lines in the second plurality of metal layers.

[0005] In another aspect of this disclosure, a structure is provided in a semiconductor device having: a first interconnect level located above a substrate; a first plurality of metal layers located within the first interconnect level, wherein the metal layers in the first plurality of metal layers are electrically inactive; a second interconnect level located above the first interconnect level; and a second plurality of metal layers located within the second interconnect level. Each of the first plurality of metal layers is positioned equidistant from two adjacent metal layers in the second plurality of metal layers. Attached Figure Description

[0006] This disclosure can be understood by referring to the following description in conjunction with the accompanying drawings.

[0007] For the sake of simplicity and clarity, the accompanying drawings illustrate a general manner of construction, and certain descriptions and details of features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the embodiments of this disclosure. Furthermore, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to aid in understanding the embodiments of this disclosure. The same reference numerals in different drawings denote the same elements, and similar reference numerals may, but do not necessarily, denote similar elements.

[0008] Figure 1 This is a cross-sectional view of an example structure in a semiconductor device.

[0009] Figure 2 This is a cross-sectional view of another example structure in a semiconductor device.

[0010] Figure 3 This is a cross-sectional view of another example structure in a semiconductor device.

[0011] Figure 4 This is a cross-sectional view of another example structure in a semiconductor device.

[0012] Figure 5AA , Figure 5B , Figure 5C It is shown Figure 1 and Figure 2 A top view of an example layout of the metal layers in the example structure shown.

[0013] Figure 5AB , Figure 5B , Figure 5C It is shown Figure 3 and Figure 4 A top view of an example layout of the metal layers in the example structure shown.

[0014] Figure 5D It is shown Figure 1 and Figure 4A top view of an example layout of multiple metal layers in the interconnect hierarchy of the example structure shown.

[0015] Figure 6A , Figure 6B and Figure 6C It is shown Figure 1 , Figure 2 , Figure 3 and Figure 4 An enlarged cross-sectional view of the metal layer in the interconnect hierarchy of the example structure.

[0016] Figure 7 yes Figure 1 The partial cross-sectional view of the example structure shown illustrates an exemplary arrangement of metal layers in each interconnect level.

[0017] Figure 8 yes Figure 2 The partial cross-sectional view of the example structure shown illustrates an exemplary arrangement of metal layers in each interconnect level.

[0018] Figure 9 yes Figure 3 The partial cross-sectional view of the example structure shown illustrates an exemplary arrangement of metal layers in each interconnect level.

[0019] Figure 10 yes Figure 4 The partial cross-sectional view of the example structure shown illustrates an exemplary arrangement of metal layers in each interconnect level.

[0020] Figure 11 It is shown Figure 9 and Figure 10 A partial cross-sectional view of an example variation of the exemplary arrangement of metal layers in the various interconnect layers shown. Detailed Implementation

[0021] Various illustrative embodiments of this disclosure are described below. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limited to this disclosure.

[0022] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4Examples of structure 100 in a semiconductor device may include a first interconnect level 130 above a substrate 102, a first plurality of metal layers 136 in the first interconnect level 130, a second interconnect level 140 above the first interconnect level 130, and a second plurality of metal layers 146a, 146b, 146c, 146d in the second interconnect level 140. Other interconnect levels and contact levels may also be formed in structure 100. As used herein, the term “interconnect level” may refer to a level located in the back-end process (BEOL) region of an integrated circuit (IC) chip or in a semiconductor device containing interconnect structures formed in one or more inter-metal dielectric (IMD) layers.

[0023] Each interconnect level disclosed herein may include a metallization level and a via level. The term "metallization level" may refer to a level within the BEOL region of an IC chip that contains one or more layers of conductive material configured to provide electrical signal routing between components or features of the IC chip. A metallization level may have an uppermost and lowermost boundary that is substantially coplanar with the respective top and bottom surfaces of one or more layers of conductive material. In some implementations, one or more layers of conductive material in each metallization level may be labeled as "Mx" lines, where the letter "x" in the term "Mx" is an integer representing the metallization level in which one or more layers of conductive material reside. The term "via level" may refer to a level within the BEOL region of an IC chip that contains one or more interconnect vias configured to provide electrical connections between different metallization levels. A via level may have an uppermost and lowermost boundary that is substantially coplanar with the respective top and bottom surfaces of one or more interconnect vias. In some implementations, one or more interconnect vias in each via level can be labeled as "Vx" vias, where the letter "x" in the term "Vx" is an integer representing the via level in which the one or more interconnect vias reside.

[0024] Structure 100 may include many interconnection levels. For example, "n" interconnection levels may be formed in structure 100. Figure 1 and Figure 3 In the example shown, structure 100 may include four interconnect layers 120, 130, 140, and 150 (where the number "n" is 4) and a contact layer 110. Figure 2 and Figure 4 In the example shown, structure 100 may include five interconnect levels 120, 130, 140, 150, and 160 (where the number "n" is 5) and a contact level 110. Other numbers of interconnect levels are also possible, and Figure 1 , Figure 2 , Figure 3 and Figure 4The structure 100 shown is not limited to the number of interconnect layers shown in these corresponding figures. The number of interconnect layers formed in structure 100 may depend, for example, on design requirements or the process involved. The interconnect layers described herein may be arranged to be stacked on top of each other in the vertical direction.

[0025] exist Figure 1 , Figure 2 , Figure 3 and Figure 4 In the example shown, structure 100 may include a contact level 110 located on substrate 102. Contact level 110 may include a dielectric region 114 and various interconnect structures (not shown) for connection to transistors (not shown) formed on substrate 102. In some implementations, contact level 110 may be referred to as a “mid-stage process” region, which provides electrical connection between features in the BEOL and front-end process (FEOL) regions. Structure 100 may also include an interconnect level 120 located below a first interconnect level 130. Interconnect level 120 may be vertically located between the first interconnect level 130 and contact level 110. Interconnect level 120 may include wires 126 formed in an intermetallic dielectric 124. Although not shown in the figures, wires 126 may be directly or indirectly connected to the interconnect structures in contact level 110.

[0026] Structure 100 may further include an interconnect layer located above the second interconnect layer 140. Figure 1 and Figure 3 In the example shown, a third interconnect layer 150 may be formed above a second interconnect layer 140, and a fourth interconnect layer 160 may be formed above a third interconnect layer 150. A third plurality of metal layers 156a, 156b, 156c, and 156d may be formed in the third interconnect layer 150. A fourth plurality of metal layers 166a, 166b, and 166c may be formed in the fourth interconnect layer 160. Although not shown, alternative embodiments are contemplated in this disclosure, wherein... Figure 1 and Figure 3 The example shown is modified to remove the intermediate interconnect layer 150 (and the plurality of metal layers 156 formed therein) between the second interconnect layer 140 and the fourth interconnect layer 160. In other words, in the contemplated alternative embodiment, the fourth interconnect layer 160 may be located directly above the second interconnect layer 140.

[0027] exist Figure 2 and Figure 4In the example shown, a third interconnect layer 150 may be formed above a second interconnect layer 140, a fourth interconnect layer 160 may be formed above a third interconnect layer 150, and a fifth interconnect layer 170 may be formed above a fourth interconnect layer 160. A plurality of third metal layers 156a, 156b, 156c, and 156d may be formed in the third interconnect layer 150. A plurality of fourth metal layers 166a, 166b, and 166c may be formed in the fourth interconnect layer 160. The fifth interconnect layer 170 may include a conductor 176, an intermetallic dielectric 174, and a dielectric layer 172. Although not shown, alternative embodiments are contemplated in this disclosure, wherein... Figure 2 and Figure 4 The example shown has been modified to remove the intermediate interconnect layer 150 (and the plurality of metal layers 156 formed therein) between the second interconnect layer 140 and the fourth interconnect layer 160. In other words, the fourth interconnect layer 160 may be located directly above the second interconnect layer 140.

[0028] Each of interconnect layers 120, 130, 140, 150, 160, and 170 may contain one or more dielectric materials. Examples of dielectric materials in the interconnect layers described herein may include, but are not limited to, silicon dioxide, tetraethyl orthosilicate (TEOS), and materials with a chemical composition of SiC. x O y H z Materials (where x, y, and z are stoichiometric ratios), silicon oxynitride (SiON), silicon nitride, nitrogen-doped silicon carbide (SiCN), SiC x H z or SiN w C x H z(Where each of w, x, y, and z individually has a value greater than 0 and less than 0.75). Each of interconnect levels 130, 140, 150, and 160 may further include one or more dielectric layers. For example, interconnect level 130 may include dielectric layers 132 and 134, interconnect level 140 may include dielectric layers 142 and 144, interconnect level 150 may include dielectric layers 152 and 154, and interconnect level 160 may include dielectric layers 162 and 164. The dielectric layers in each interconnect level may be formed using deposition techniques such as spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source atomized chemical deposition (LSMCD), and atomic layer deposition (ALD). In some embodiments, within the same interconnect level, dielectric layer 132 in interconnect level 130 may have a different dielectric material than dielectric layer 134 in interconnect level 130. In other embodiments, between different interconnect layers, the dielectric layer 134 in interconnect layer 130 may have a different dielectric material than the dielectric layer 142 in interconnect layer 140.

[0029] Multiple metal layers 136, 146, 156, 166 and wires 126, 176 may comprise metals such as tantalum (Ta), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), nickel (Ni), platinum (Pt), aluminum (Al), or alloys thereof. Other suitable types of metals, alloys, or conductive materials may also be used. The metal layers 136, 146, 156, 166 and wires 126, 176 may be formed, for example, using a damascene process (e.g., single damascene or double damascene) in the dielectric material of the respective interconnect layers. Other processing steps may be used, such as reactive ion etching (RIE), chemical mechanical polishing (CMP), electroplating, and deposition techniques (e.g., sputtering, CVD, PVD, MBD, PLD, LSMCD, ALD).

[0030] exist Figure 1 , Figure 2 , Figure 3 and Figure 4In the example shown, the second interconnect layer 140 may be formed directly above the first interconnect layer 130. The term "directly above" may refer to the absence of any intermediate interconnect layers between the first interconnect layer 130 and the second interconnect layer 140 in the vertical direction. For example, in an embodiment where the second interconnect layer 140 is directly above the first interconnect layer 130, the first interconnect layer 130 may include a first dielectric layer 134, the second interconnect layer may include a second dielectric layer 142, and the second dielectric layer 142 in the second interconnect layer 140 may be directly above the first dielectric layer 134 in the first interconnect layer 130. Similarly, a third interconnect layer 150 may be formed directly above the second interconnect layer 140, and a fourth interconnect layer 160 may be formed directly above the third interconnect layer 150. Figure 2 and Figure 4 In the example shown, the fifth interconnect layer 170 can be formed directly above the fourth interconnect layer 160.

[0031] Figure 5AA It shows Figure 1 and Figure 2 The diagram shows an example layout of the metal layers in the first plurality of metal layers of the structure. Line AA indicates... Figure 1 and Figure 2 The cross-sections corresponding to the views of metal layers 136a and 136b shown are shown. (Reference) Figure 5AA as well as Figure 1 and Figure 2 Metal layers 136a and 136b in the first plurality of metal layers 136 can be electrically inactive (i.e., electrically floating). In other words, metal layers 136a and 136b can be not connected to a voltage or current source. Metal layers 136a and 136b can also be without any polarity (i.e., positive or negative charge). In one example, the first interconnect level 130 can have a first dielectric layer 134, and the second interconnect level 140 can have a second dielectric layer 142. Each metal layer 136a and 136b in the first plurality of metal layers 136 can be completely covered by the first dielectric layer 134 and the second dielectric layer 142, and directly contact the first dielectric layer 134 and the second dielectric layer 142. This advantageously ensures that the metal layers 136a and 136b in the first plurality of metal layers 136 are electrically inactive and do not directly contact any interconnect vias.

[0032] Figure 5AB It shows Figure 3 and Figure 4 The diagram shows an example layout of the metal layers in the first plurality of metal layers of the structure. Line AA indicates... Figure 3 and Figure 4 The cross-sections corresponding to the views of metal layers 136a, 136b, and 136c shown are shown. (Reference) Figure 5AB as well as Figure 3 and Figure 4 Metal layers 136a, 136b, and 136c of the first plurality of metal layers 136 may be electrically inactive. In other words, metal layers 136a, 136b, and 136c may not be connected to a voltage or current source. Metal layers 136a, 136b, and 136c may also be without any polarity (i.e., positive or negative charge). In one example, the first interconnect layer 130 may have a first dielectric layer 134, and the second interconnect layer 140 may have a second dielectric layer 142. Each metal layer 136a, 136b, and 136c of the first plurality of metal layers 136 may be completely covered by the first dielectric layer 134 and the second dielectric layer 142, and may be in direct contact with the first dielectric layer 134 and the second dielectric layer 142. This advantageously ensures that metal layers 136a, 136b, and 136c of the first plurality of metal layers 136 are electrically inactive and do not directly contact any interconnect vias.

[0033] Figure 5B and Figure 5C It shows Figure 1 , Figure 2 , Figure 3 and Figure 4 The illustrated structure shows an example layout of the individual metal layers in the second and third plurality of metal layers. Line BB represents a cross-section corresponding to the views shown regarding metal layers 146a, 146b, 146c, and 146d. Line CC represents a cross-section corresponding to the views shown regarding metal layers 156a, 156b, 156c, and 156d. Reference Figure 5B and Figure 5C as well as Figures 1 to 4 Metal layers 146a, 146b, 146c, 146d in the second plurality of metal layers 146 and metal layers 156a, 156b, 156c, 156d in the third plurality of metal layers 156 can be configured as capacitors (e.g., metal-oxide-metal capacitors or metal-insulator-metal capacitors). For example, the second plurality of metal layers 146 may include a first set of metal lines 146a, 146c intersecting with the second set of metal lines 146b, 146d. The first set of metal lines 146a, 146c may be connected to wiring 116 and can be biased by a first voltage. The second set of metal lines 146b, 146d may be connected to wiring 112 and can be biased by a second voltage, wherein the second voltage may be higher than the first voltage. In some embodiments, the first voltage may be described as a low voltage (e.g., a voltage value below 10V), and the second voltage may be described as a high voltage (e.g., a voltage value above 30V). In an alternative implementation, the second plurality of metal layers 146 may include alternating metal lines with different voltages.

[0034] Similarly, the third plurality of metal layers 156 may include a third set of metal lines 156a and 156c intersecting with the fourth set of metal lines 156b and 156d. The third set of metal lines 156a and 156c may be connected to wiring 104 and may be biased by a first voltage. The fourth set of metal lines 156b and 156d may be connected to wiring 118 and may be biased by a second voltage. In an alternative implementation, the third plurality of metal layers 156 may include alternating metal lines with different voltages. In contrast, due to the metal layers 136a and 136b in the first plurality of metal layers 136 (e.g., ... Figure 1 and Figure 3 (as shown) and 136c (as shown) Figure 2 and Figure 4 (As shown) is electrically inactive, therefore, Figure 5AA Metal layers 136a, 136b and 136b of the first plurality of metal layers 136 shown Figure 5AB None of the metal layers 136a, 136b, and 136c in the first plurality of metal layers 136 shown can be connected to Figure 5B and Figure 5C The wiring shown is 112, 116, 104, 118. Figure 5B The wiring 116 shown can be connected via vertical interconnects or interconnect vias (not shown in the figure) to Figure 5C The wiring shown is 104. Similarly, Figure 5B The wiring 112 shown can be connected via vertical interconnects or interconnect vias (not shown in the figure) to Figure 5C The wiring shown is 118.

[0035] refer to Figure 5AA , Figure 5AB , Figure 5B , Figure 5C , Figure 5AA Metal layers 136a, 136b, and 136b of the first plurality of metal layers 136 shown Figure 5AB The metal layers 136a, 136b, 136c of the first plurality of metal layers 136, the metal layers 146a, 146b, 146c, 146d of the second plurality of metal layers 146, and the metal layers 156a, 156b, 156c, 156d of the third plurality of metal layers 156 shown can be configured to extend along a horizontal plane (e.g., the XZ plane) parallel to the top surface of the substrate 102. Figure 5AA and Figure 5AB Each of the metal layers 136a, 136b, and 136c in the first plurality of metal layers 136 shown can be elongated with a longitudinal length 136L. Figure 5B Each of the metal layers 146a, 146b, 146c, and 146d in the second plurality of metal layers 146 shown can be elongated with a longitudinal length 146L. Figure 5C Each of the metal layers 156a, 156b, 156c, and 156d in the third plurality of metal layers 156 shown may extend with a longitudinal length 156L. In some embodiments, the length 136L of each metal layer in the first plurality of metal layers 136 may be substantially the same as the length 146L of each metal layer in the second plurality of metal layers 146, and substantially the same as the length of each metal layer in the third plurality of metal layers 156. The metal layers 146a, 146b, 146c, and 146d in the second plurality of metal layers 146 may extend in the same direction as the metal layers 156a, 156b, 156c, and 156d in the third plurality of metal layers 156 (e.g., along the x-axis) and may be parallel to the metal layers 156a, 156b, 156c, and 156d in the third plurality of metal layers 156. Each of the first plurality of metal layers 136a, 136b, 136c may extend in the same direction (e.g., along the x-axis) as each of the corresponding metal lines 146a, 146c in the first group of metal lines of the second plurality of metal layers 146, and may be parallel to each of the corresponding metal lines 146a, 146c in the first group of metal lines of the second plurality of metal layers 146.

[0036] Figure 5D It shows Figure 1 and Figure 3 The example layout of the metal layers in the fourth plurality of metal layers of the structure is shown. Line DD indicates... Figure 1 and Figure 3 The cross-sections corresponding to the views of metal layers 166a, 166b, and 166c shown are shown. (Reference) Figure 1 and Figure 3 as well as Figure 5D In some examples, metal layers 166a, 166b, and 166c of the fourth plurality of metal layers 166 formed in the fourth interconnect layer 160 can also be configured as capacitors (e.g., metal-oxide-metal capacitors or metal-insulator-metal capacitors). For example, the fourth plurality of metal layers 166 may include metal lines 166a and 166c interdigitated with metal line 166b, wherein metal lines 166a and 166c can be connected to wiring 128 and can be biased by a first voltage, and metal line 166b can be connected to wiring 129 and can be biased by a second voltage. In an alternative implementation, the fourth plurality of metal layers 166 may include alternating metal lines with different voltages. Although Figure 5D The example shows a single metal wire 166b connected to wiring 128, but it should be understood that two or more metal wires may be connected to wiring 128.

[0037] refer to Figure 2 and Figure 4In other examples, metal layers 166a, 166b (e.g., in the fourth plurality of metal layers 166 formed in the fourth interconnect layer 160) Figure 2 (as shown) and 166c (as shown) Figure 4 (As shown) can be electrically inactive, rather than as Figure 1 and Figure 3 The configuration is either as a capacitor or biased by voltage. For example... Figure 5AA and Figure 2 As shown, metal layers 166a and 166b may not be connected to a voltage or current source. Metal layers 166a and 166b may also be without any polarity (i.e., positive or negative charge). Similar to metal layers 136a and 136b in the first plurality of metal layers 136, metal layers 166a and 166b in the fourth plurality of metal layers 166 may be configured to extend along a horizontal plane parallel to the top surface of the substrate 102. Each metal layer 166a and 166b in the fourth plurality of metal layers 166 may extend in the same direction (e.g., along the x-axis) as each corresponding metal line 146a and 146c in the first set of metal lines of the second plurality of metal layers 146, and may be parallel to each corresponding metal line 146a and 146c in the first set of metal lines of the second plurality of metal layers 146.

[0038] like Figure 5AB and Figure 4 As shown, metal layers 166a, 166b, and 166c may not be connected to a voltage or current source. Metal layers 166a, 166b, and 166c may also be without any polarity (i.e., positive or negative charge). Similar to metal layers 136a, 136b, and 136c in the first plurality of metal layers 136, metal layers 166a, 166b, and 166c in the fourth plurality of metal layers 166 may be configured to extend along a horizontal plane parallel to the top surface of the substrate 102. Each metal layer 166a, 166b, and 166c in the fourth plurality of metal layers 166 may extend in the same direction (e.g., along the x-axis) as metal layers 146a, 146b, 146c, and 146d in the second plurality of metal layers 146, and may be parallel to metal layers 146a, 146b, 146c, and 146d in the second plurality of metal layers 146.

[0039] Figure 6A This is an enlarged cross-sectional view of each of the first plurality of metal layers 136 in the first interconnect layer 130. (Reference) Figure 6AUsing metal layer 136a as an illustrative example, each of the first plurality of metal layers 136 may have a top surface 137t, a bottom surface 137b, and a side surface 137s. The side surface 137s may intersect the top surface 137t at the top edges 135a, 135b, and the side surface 137s may intersect the bottom surface 137b at the bottom edges 133a, 133b. Each of the first plurality of metal layers 136 may have a line height 137H defined as the vertical distance between the top surface 137t and the bottom surface 137b, and a line width 137W defined as the horizontal distance between the top edges 135a, 135b, wherein the horizontal distance spans the top surface 137t of the metal layer.

[0040] Figure 6B This is an enlarged cross-sectional view of each of the second plurality of metal layers 146 in the second interconnect layer 140. (Reference) Figure 6B Using metal layer 146a as an illustrative example, each metal layer may have a top surface 147t, a bottom surface 147b, and side surfaces 147s. Side surfaces 147s may intersect the top surface 147t at top edges 145a, 145b, and side surfaces 147s may intersect the bottom surface 147b at bottom edges 143a, 143b. Each of the second plurality of metal layers 146 may have a line height 147H, defined as the vertical distance between the top surface 147t and the bottom surface 147b, and a line width 147W, defined as the horizontal distance between the top edges 145a, 145b, wherein the horizontal distance spans the top surface 147t of the metal layer. In some embodiments, the line width 147W and line height 147H of each metal layer in the second plurality of metal layers 146 may be the same as the line width 137W and line height 137H of each metal layer in the first plurality of metal layers 136. Although not shown in the accompanying drawings, each of the third plurality of metal layers 156 may be formed to have the same line width and line spacing as each of the second plurality of metal layers 146.

[0041] Figure 6C yes Figure 1 and Figure 3 Enlarged cross-sectional view of each of the fourth plurality of metal layers 166 in the fourth interconnect layer 160 of the structure shown. (Reference) Figure 6CUsing metal layer 166a as an illustrative example, each metal layer may have a top surface 167t, a bottom surface 167b, and side surfaces 167s. Side surfaces 167s may intersect the top surface 167t at top edges 165a and 165b, and side surfaces 167s may intersect the bottom surface 167b at bottom edge 163. Each of the fourth plurality of metal layers 166 may have a line height 167H defined as the vertical distance between the top surface 167t and the bottom surface 167b, and a line width 167W defined as the horizontal distance between the top edges 165a and 165b, wherein the horizontal distance spans the top surface 167t of the metal layer. The line height 167H of each of the fourth plurality of metal layers 166 may be greater than the line height 137H of each of the first plurality of metal layers 136 and the line height 147H of each of the second plurality of metal layers 146. The linewidth 167W of each metal layer in the fourth plurality of metal layers 166 can be greater than the linewidth 137W of each metal layer in the first plurality of metal layers 136 and the linewidth 147W of each metal layer in the second plurality of metal layers 146.

[0042] refer to Figure 7 , Figure 8 , Figure 9 and Figure 10The first plurality of metal layers 136 may have a line spacing 138S and a line pitch 138P; the second plurality of metal layers 146 may have a line spacing 148S and a line pitch 148P; the third plurality of metal layers 156 may have a line spacing 158S and a line pitch 158P; and the fourth plurality of metal layers 166 may have a line spacing 168S and a line pitch 168P. The line pitches 138P, 148P, 158P, and 168P can be defined as the lateral distance measured between the centers of two adjacent metal layers in the respective plurality of metal layers 136, 146, 156, and 166 described herein. The line spacings 138S, 148S, 158S, and 168S can be defined as the minimum lateral distance between two adjacent metal layers in the respective plurality of metal layers 136, 146, 156, and 166 described herein, wherein the lateral distance can be measured between the top edges of the two adjacent metal layers. As an illustrative example, the line spacing 138S in the first plurality of metal layers 136 can be measured from the top edge 135b of metal layer 136a to the top edge 135a of metal layer 136b. The line spacing 148S in the second plurality of metal layers 146 can be measured from the top edge 145b of metal layer 146a to the top edge 145a of metal layer 146b. The line spacing 158S in the third plurality of metal layers 156 can be measured from the top edge 155b of metal layer 156a to the top edge 155a of metal layer 156b. The line spacing 168S in the fourth plurality of metal layers 166 can be measured from the top edge 165b of metal layer 166a to the top edge 165a of metal layer 166b.

[0043] In some embodiments, each of the first, second, third, and fourth plurality of metal layers 136, 146, 156, 166 may have a constant line spacing and a constant line pitch. Using the second plurality of metal layers 146 as an illustrative example to define the term "constant" when used with line spacing and line pitch, the line spacing and line pitch between metal layers 146a and 146b may be the same as the line spacing and line pitch between metal layers 146b and 146c and the line spacing and line pitch between metal layers 146c and 146d.

[0044] exist Figure 1 , Figure 2 , Figure 3 and Figure 4In the example shown, the dielectric layer 134 in the first interconnect layer 130 may be laterally located between two adjacent metal layers in the first plurality of metal layers 136. For example, each metal layer 136a in the first plurality of metal layers 136 may be separated from an adjacent metal layer 136b by the dielectric layer 134 in the first interconnect layer 130 or located above one or more dielectric materials included in the first interconnect layer 130. The dielectric layer 144 in the second interconnect layer 140 may be laterally located between two adjacent metal layers in the second plurality of metal layers 146. For example, each metal layer 146a, 146b, 146c, 146d in the second plurality of metal layers 146 may be separated from an adjacent metal layer by the dielectric layer 144 in the second interconnect layer 140. Similarly, the dielectric layer 154 in the third interconnect layer 150 may be laterally located between two adjacent metal layers in the third plurality of metal layers 156. For example, each of the third plurality of metal layers 156a, 156b, 156c, 156d can be separated from an adjacent metal layer by a dielectric layer 154 in the third interconnect layer 150. When used herein to describe metal layers in an interconnect layer, the term “adjacent” means two metal layers that are laterally adjacent to each other within the same interconnect layer, and there is no intermediate metal layer laterally placed between these two metal layers. As an illustrative example, in the second interconnect layer 140, metal layer 146a is adjacent to metal layer 146b, while metal layer 146a is not adjacent to metal layer 146c. The above illustrative example of the term “adjacent” also applies to the metal layers in the various interconnect layers 130, 150, 160.

[0045] refer to Figure 2 and Figure 4 The dielectric layer 164 in the fourth interconnect layer 160 may be laterally located between two adjacent metal layers in the fourth plurality of metal layers 166. For example, each metal layer 166a in the fourth plurality of metal layers 166 may be separated from an adjacent metal layer 166b by the dielectric layer 164 in the fourth interconnect layer 160 or located above one or more dielectric materials included in the fourth interconnect layer 160. Each metal layer 166a, 166b, 166c in the fourth plurality of metal layers 166 may be completely covered by the dielectric layer 164 in the fourth interconnect layer 160 and the dielectric layer 172 in the fifth interconnect layer 170, and may be in direct contact with the dielectric layer 164 in the fourth interconnect layer 160 and the dielectric layer 172 in the fifth interconnect layer 170. This advantageously ensures that the metal layers 166a, 166b, 166c in the fourth plurality of metal layers 166 are electrically inactive and do not directly contact any interconnect vias. The fourth plurality of metal layers 166 can be formed vertically on the metal layers configured as capacitors (e.g., such as...). Figure 2 and Figure 4Between the second plurality of metal layers 146 and the third plurality of metal layers 156 shown, and the conductors 176 in the fifth interconnect layer 170. Figure 2 and Figure 4 In the example shown where the structure is modified to omit the third interconnect layer 150 (not shown), the fourth interconnect layer 160 (and the fourth plurality of metal layers 166) can be formed directly above the second interconnect layer (and the second plurality of metal layers 146) and directly below the fifth interconnect layer 170 (and the wires 176).

[0046] refer to Figure 1 and Figure 2 Each metal layer 136a, 136b in the first plurality of metal layers 136 may be vertically aligned only below each metal line 146a, 146c in the first group of metal lines of the second plurality of metal layers 146. Each metal line 146b, 146d in the second group of metal lines of the second plurality of metal layers 146 may be vertically aligned only above the dielectric layer 134 in the first interconnect layer 130 or above one or more dielectric materials included in the first interconnect layer 130. Advantageously, by vertically aligning only each of the first plurality of metal layers 136a, 136b with each of the first set of metal lines 146a, 146c of the second plurality of metal layers 146, each of the second set of metal lines 146b, 146d of the second plurality of metal layers 146 can be vertically aligned only with the dielectric material in the first interconnect layer 130, and not vertically aligned above any metal or conductive material (such as metal layers 136a, 136b) in the first interconnect layer 130.

[0047] Refer to each Figure 7 and Figure 8 as well as Figure 1 and Figure 2 Each of the first plurality of metal layers can be positioned equidistant from two adjacent metal lines in the second group of metal lines of the second plurality of metal layers. As an example, metal layer 136b of the first plurality of metal layers 136 is vertically aligned only below metal line 146c in the first group of metal lines 146a and 146c of the second plurality of metal layers 146, and can be positioned equidistant from two adjacent metal lines 146b and 146d in the second group of metal lines 146b and 146d of the second plurality of metal layers 146. Metal line 146c in the first group of metal lines 146a and 146c, vertically aligned above metal layer 136b of the first plurality of metal layers 136, can be positioned immediately adjacent to two adjacent metal lines 146b and 146d and laterally positioned between the two adjacent metal lines 146b and 146d. Figure 7 and Figure 8As shown, positioning the metal layer 136b equidistant from two adjacent metal lines 146b and 146d can mean that the distance 106x between the top edge 135a of the metal layer 136b in the first interconnect layer 130 and the bottom edge 143b of the metal line 146b in the second interconnect layer 140 is approximately equal to the distance 106y between the top edge 135b of the metal layer 136b in the first interconnect layer 130 and the bottom edge 143a of the metal line 146d in the second interconnect layer 140.

[0048] Each of the first plurality of metal layers may be spaced apart from its adjacent metal layer by a lateral distance (e.g., line spacing 138S), which is greater than the linewidth of each metal layer in the second plurality of metal layers. The lateral distance (e.g., line spacing 138S) separating two adjacent metal layers in the first plurality of metal layers may be greater than the sum of the line spacing and the linewidth of each metal layer in the second plurality of metal layers. For example, as... Figure 7 and Figure 8 As shown, the line spacing 138S and line pitch 138P in the first plurality of metal layers 136 can be greater than the line spacing 148S and line pitch 148P in the second plurality of metal layers 146, respectively. The line spacing 138S in the first plurality of metal layers 136 can be greater than the sum of the line width 146W of each metal layer 146a, 146b, 146c, 146d in the second plurality of metal layers 146 and the line spacing 148S in the second plurality of metal layers 146. The line spacing 138S in the first plurality of metal layers 136 can be substantially equal to the sum of the line width 146W of each metal layer 146a, 146b, 146c, 146d in the second plurality of metal layers 146 and twice the line spacing 148S in the second plurality of metal layers 146. The line pitch 138P in the first plurality of metal layers 136 can be twice the line pitch 148P in the second plurality of metal layers 146.

[0049] refer to Figure 2In embodiments where metal layers 166a and 166b in the fourth plurality of metal layers 166 are electrically inactive, each metal layer 166a and 166b in the fourth plurality of metal layers 166 may be vertically aligned only above each metal line 146a and 146c in the first group of metal lines of the second plurality of metal layers 146. Each metal line 146b and 146d in the second group of metal lines of the second plurality of metal layers 146 may be vertically aligned only below the dielectric layer 164 in the fourth interconnect layer 160 or below one or more dielectric materials included in the fourth interconnect layer 160. Advantageously, by vertically aligning only each metal layer 166a, 166b of the fourth plurality of metal layers 166 with each metal line 146a, 146c of the first group of metal lines of the second plurality of metal layers 146, each metal line 146b, 146d of the second group of metal lines of the second plurality of metal layers 146 can be vertically aligned only below the dielectric material in the fourth interconnect layer 160, and not below any metal or conductive material (such as metal layers 166a, 166b) in the fourth interconnect layer 160. The metal layers 166a, 166b of the fourth plurality of metal layers 166 can be vertically aligned with the metal layers 136a, 136b of the first plurality of metal layers 136.

[0050] refer to Figure 8 and Figure 2 Each of the fourth plurality of metal layers can be vertically aligned above only each metal line in the third group of metal lines of the second plurality of metal layers, and each of the fourth plurality of metal layers can also be positioned equidistant from two adjacent metal lines in the fourth group of metal lines of the second plurality of metal layers. As an example, metal layer 166b in the fourth plurality of metal layers 166 can be vertically aligned above only metal line 156c in the third group of metal lines 156a and 156c of the third plurality of metal layers 156, and can be positioned equidistant from two adjacent metal lines 156b and 156d in the third group of metal lines 156b and 156d of the third plurality of metal layers 156. Metal line 156c in the first group of metal lines 156a and 156c, vertically aligned below metal layer 166b in the fourth plurality of metal layers 166, can be positioned adjacent to two adjacent metal lines 156b and 156d and laterally positioned between the two adjacent metal lines 156b and 156d. Figure 8 As shown, positioning the metal layer 166b equidistant from two adjacent metal lines 156b and 156d can mean that the distance 108x between the bottom edge 163a of the metal layer 166b in the fourth interconnect layer 160 and the top edge 155b of the metal line 156b in the third interconnect layer 150 is approximately equal to the distance 108y between the bottom edge 163b of the metal layer 166b in the fourth interconnect layer 160 and the top edge 155a of the metal line 156d in the third interconnect layer 150.

[0051] Each of the fourth plurality of metal layers can be spaced apart from its adjacent metal layer by a lateral distance (e.g., line spacing 168S), which is greater than the line width of each metal layer in the third plurality of metal layers. The lateral distance separating two adjacent metal layers in the fourth plurality of metal layers (e.g., line spacing 138S) can be greater than the sum of the line spacing in the third plurality of metal layers and the line width of each metal layer in the third plurality of metal layers. For example, as... Figure 8 As shown, the line spacing 168S and line pitch 168P in the fourth plurality of metal layers 166 can be greater than the line spacing 158S and line pitch 158P in the third plurality of metal layers 156, respectively. The line spacing 168S in the fourth plurality of metal layers 166 can be greater than the sum of the line width 156W of each metal layer 156a, 156b, 156c, 156d in the third plurality of metal layers and the line spacing 158S in the third plurality of metal layers 156. The line spacing 168S in the fourth plurality of metal layers 166 can be approximately equal to the sum of the line width 156W of each metal layer 156a, 156b, 156c, 156d in the third plurality of metal layers 156 and twice the line spacing 158S in the third plurality of metal layers 156. The line pitch 168P in the fourth plurality of metal layers 166 can be twice the line pitch 158P in the third plurality of metal layers 156.

[0052] refer to Figure 9 and Figure 10 as well as Figure 3 and Figure 4 Each of the first plurality of metal layers can be positioned equidistant from two adjacent metal layers in the second plurality of metal layers. As an example, metal layer 136c in the first plurality of metal layers 136 can be positioned equidistant from two adjacent metal layers 146c and 146d in the second plurality of metal layers 146. Figure 9 and Figure 10 As shown, positioning metal layer 136c equidistant from two adjacent metal layers 146c and 146d can mean that the distance 106x between the bottom edge 143b of metal layer 146c in the second interconnect layer 140 and the top edge 135a of metal layer 136c in the first interconnect layer 130 is approximately equal to the distance 106y between the bottom edge 143a of metal layer 146d in the second interconnect layer 140 and the top edge 135b of metal layer 136c in the first interconnect layer 130.

[0053] Similarly, each of the second plurality of metal layers can be positioned equidistant from two adjacent metal layers in the first plurality of metal layers. As an example, metal layer 146c in the second plurality of metal layers 146 can be positioned equidistant from two adjacent metal layers 136b and 136c in the first plurality of metal layers 136. Figure 9 and Figure 10 As shown, positioning metal layer 146c equidistant from two adjacent metal layers 136b and 136c can mean that the distance 106x between the bottom edge 143b of metal layer 146c in the second interconnect layer 140 and the top edge 135a of metal layer 136c in the first interconnect layer 130 is approximately equal to the distance 107y between the bottom edge 143a of metal layer 146c in the second interconnect layer 140 and the top edge 135b of metal layer 136b in the first interconnect layer 130.

[0054] Advantageously, by positioning each of the first plurality of metal layers equidistant from two adjacent metal layers in the second plurality of metal layers, or by positioning each of the second plurality of metal layers equidistant from two adjacent metal layers in the first plurality of metal layers, it is found that each of the second plurality of metal layers 146a, 146b, 146c, 146d can be vertically aligned only above the dielectric layer 134 located laterally between two adjacent metal layers in the first plurality of metal layers 136, and not above any metal or conductive material (such as metal layers 136a, 136b, 136c) in the first interconnect layer 130. Similarly, it was found that each of the first plurality of metal layers 136a, 136b, 136c can be vertically aligned only below the dielectric layer 144 located laterally between two adjacent metal layers in the second plurality of metal layers 146, and cannot be vertically aligned below any metal or conductive material (such as metal layers 146a, 146b, 146c, 146d) in the second interconnect layer 140.

[0055] Each of the first plurality of metal layers may be spaced apart from its adjacent metal layer by a lateral distance (e.g., line spacing 138S), which is greater than the line width of each of the second plurality of metal layers. For example, as Figure 9 and Figure 10 as well as Figure 6B As shown, the line spacing 138S and line pitch 138P in the first plurality of metal layers 136 can be greater than the line width 146W of each metal layer 146a, 146b, 146c, 146d in the second plurality of metal layers 146. Similarly, as Figure 9 and Figure 10 as well as Figure 6AAs shown, the line spacing 148S and line pitch 148P in the second plurality of metal layers 146 can be greater than the line width 136W of each metal layer 136a, 136b, 136c in the first plurality of metal layers 136.

[0056] refer to Figure 10 and Figure 4 In embodiments where metal layers 166a and 166b of the fourth plurality of metal layers 166 are electrically inactive, each metal layer of the fourth plurality of metal layers can be positioned equidistant from two adjacent metal layers of the third plurality of metal layers. As an example, metal layer 166c of the fourth plurality of metal layers 166 can be positioned equidistant from two adjacent metal layers 156c and 156d of the third plurality of metal layers 156. Figure 10 As shown, positioning metal layer 166c equidistant from two adjacent metal layers 156c and 156d can mean that the distance 108x between the bottom edge 163a of metal layer 166c in the fourth interconnect layer 160 and the top edge 155b of metal layer 156c in the third interconnect layer 150 is approximately equal to the distance 108y between the bottom edge 163b of metal layer 166c in the fourth interconnect layer 160 and the top edge 155a of metal layer 156d in the third interconnect layer 150.

[0057] Advantageously, by positioning each of the fourth plurality of metal layers equidistant from two adjacent metal layers in the third plurality of metal layers, it was found that each of the fourth plurality of metal layers 166a, 166b, 166c can be vertically aligned only above the dielectric layer 154 located laterally between two adjacent metal layers in the third plurality of metal layers 156, and not above any metal or conductive material (such as metal layers 156a, 156b, 156c, 156d) in the third interconnect layer 150.

[0058] Each of the fourth plurality of metal layers may be spaced apart from its adjacent metal layer by a lateral distance (e.g., line spacing 168S), which is greater than the linewidth of each of the second plurality of metal layers or the linewidth of each of the third plurality of metal layers. For example, as Figure 9 and Figure 10 as well as Figure 6B As shown, the line spacing 168S and line pitch 168P in the fourth plurality of metal layers 166 can be greater than the line width 146W of each metal layer 146a, 146b, 146c, 146d in the second plurality of metal layers 146.

[0059] As disclosed herein, the metal layers in the first plurality of metal layers may be electrically inactive, while the metal layers in the second plurality of metal layers may be configured as capacitors or biased by voltage. Placing the electrically inactive first plurality of metal layers 136 in an interconnect level 130 vertically located between an interconnect level 140 containing the second plurality of metal layers 146 and an interconnect level 120 containing conductors 126 can advantageously prevent breakdown between the metal layers 146a, 146b, 146c, 146d of the second plurality of metal layers 146 and the conductors 126 in the interconnect level 120. Meanwhile, compared to interconnect level 130 containing only dielectric material, including the first plurality of metal layers 136 in interconnect level 130 can advantageously comply with the minimum density design rules of semiconductor manufacturing, while increasing design flexibility, reducing the spacing rules between adjacent P-cells (i.e., not wasting board space between adjacent P-cells), and reducing circuit footprint.

[0060] Figure 9 and Figure 10 The illustrated embodiment can be modified to include a plurality of interconnect layers vertically located between interconnect layer 140 and interconnect layer 120, wherein each of the plurality of interconnect layers includes an electrically inactive metal layer. Figure 11 An example of this variation is shown, wherein multiple interconnect layers containing electrically inactive layers can be vertically arranged between a second plurality of metal layers 146 in interconnect layer 140 and wires 126 in interconnect layer 120. For simplicity, the interconnect layers above interconnect layer 140 are not shown.

[0061] refer to Figure 11 Where the same reference numeral indicates Figure 9 and Figure 10 With the same characteristics as in interconnect layers 130 and 120, interconnect layers 231 and 221 can be formed vertically between interconnect layers 130 and 120. Interconnect layers 221 and 231 can each include multiple metal layers 227 and 237, respectively. Similar to metal layers 136a, 136b, 136c, 136d, and 136e in the multiple metal layers 136 of interconnect layer 130, each metal layer 237a, 237b, 237c, 227a, and 227b in the corresponding multiple metal layers 237 and 227 can be electrically inactive. Similar to interconnect layer 130, interconnect layers 221 and 231 can each contain one or more dielectric materials. One or more dielectric materials in the corresponding interconnect layers 221 and 231 can be laterally located between two adjacent metal layers in the corresponding multiple metal layers 227 and 237.

[0062] Multiple metal layers 227 may have a line spacing 228S and a line pitch 228P. Multiple metal layers 237a, 237b, and 237c may have a line spacing 238S and a line pitch 238P. The line pitch 228P of multiple metal layers 227 and the line pitch 238P of multiple metal layers 237 may be substantially equal to twice the line pitch 138P of multiple metal layers 136. The line spacing 228S of multiple metal layers 227 and the line spacing 238S of multiple metal layers 237 may be substantially equal to the sum of the line width 137W of each metal layer 136a, 136b, 136c, 136d, and 136e in the multiple metal layers 136 and twice the line spacing 138S in the multiple metal layers 136, respectively. Each of the plurality of metal layers 237, 237a, 237b, 237c, may not overlap with or be vertically aligned above each of the plurality of metal layers 227, 227a, 227b. In other words, each of the plurality of metal layers 237, 237a, 237b, 237c, may be vertically aligned above one or more dielectric materials that are laterally located between two adjacent metal layers in the plurality of metal layers 227.

[0063] Throughout this disclosure, it should be understood that if a method is described herein as comprising a series of steps, the order of such steps presented herein is not necessarily the only possible order in which these steps can be performed, and certain steps may be omitted and / or other specific steps not described herein may be added to the method. Furthermore, the terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or not inherent to those processes, methods, articles, or devices. The appearance of the phrase “in an embodiment” herein does not necessarily indicate the same embodiment.

[0064] The description of various embodiments of this disclosure is provided for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. Furthermore, it is not intended to be limited to any theory set forth in the foregoing background or the following detailed description. Additionally, the various tasks and processes described herein can be incorporated into a more comprehensive program or process with additional functionality not described in detail herein.

[0065] References to terms modified by approximate language such as “about,” “roughly,” and “basically” in this document are not limited to the specified precise values. Approximate language may correspond to the accuracy of the instrument used to measure the value, and may indicate + / - 10% of the value unless otherwise dependent on the accuracy of the instrument.

[0066] After reading this application in its entirety, those skilled in the art will readily understand that the structures in the disclosed semiconductor devices and the methods for forming such structures can be used to manufacture a variety of different integrated circuit products, including but not limited to logic devices, memory devices, radio frequency applications, high-power applications, etc.

Claims

1. A structure located in a semiconductor device, comprising: The first interconnect layer is located above the substrate; A plurality of first metal layers, which are located in the first interconnect layer, wherein the metal layers in the plurality of first metal layers are electrically inactive; A second interconnect layer, which is located above the first interconnect layer; and A second plurality of metal layers, located within the second interconnect layer, wherein the second plurality of metal layers includes a first set of metal lines intersecting with the second set of metal lines, and In this configuration, each of the first plurality of metal layers is vertically aligned only below each of the first group of metal lines in the second plurality of metal layers.

2. The structure of claim 1, wherein, The first group of metal wires is biased by a first voltage, and the second group of metal wires is biased by a second voltage, which is higher than the first voltage.

3. The structure according to claim 1, wherein, The first interconnect layer includes a first dielectric layer, the second interconnect layer includes a second dielectric layer, the second dielectric layer in the second interconnect layer is directly located on the first dielectric layer in the first interconnect layer, and the first dielectric layer includes a dielectric material different from the second dielectric layer.

4. The structure according to claim 3, wherein, Each of the first plurality of metal layers is completely covered by the first dielectric layer in the first interconnect layer and the second dielectric layer in the second interconnect layer, and directly contacts the first dielectric layer in the first interconnect layer and the second dielectric layer in the second interconnect layer.

5. The structure according to claim 4, wherein, The first dielectric layer in the first interconnect layer is laterally located between two adjacent metal layers in the first plurality of metal layers.

6. The structure according to claim 5, wherein, Each metal line in the second group of metal lines of the second plurality of metal layers is vertically aligned above the first dielectric layer in the first interconnect layer.

7. The structure according to claim 5, wherein, Each metal wire in the second group is equidistant from two adjacent metal layers in the first plurality of metal layers.

8. The structure according to claim 1, wherein, Each of the second plurality of metal layers has a linewidth, and each of the first plurality of metal layers is spaced apart from its adjacent metal layer by a lateral distance, the lateral distance being greater than the linewidth of each of the second plurality of metal layers.

9. The structure according to claim 8, wherein, The second plurality of metal layers have a line spacing, and the lateral distance separating two adjacent metal layers in the first plurality of metal layers is greater than the sum of the line spacing of the second plurality of metal layers and the line width of each of the second plurality of metal layers.

10. The structure according to claim 1, wherein, The second interconnect layer is located directly above the first interconnect layer.

11. A structure located in a semiconductor device, comprising: The first interconnect layer is located above the substrate; A plurality of first metal layers, which are located in the first interconnect layer, wherein the metal layers in the plurality of first metal layers are electrically inactive; A second interconnect layer, which is located above the first interconnect layer; and The second plurality of metal layers are located in the second interconnect layer. Each of the first plurality of metal layers is positioned equidistant from two adjacent metal layers in the second plurality of metal layers.

12. The structure according to claim 11, wherein, Each of the second plurality of metal layers has a linewidth, and each of the first plurality of metal layers is spaced apart from its adjacent metal layer by a lateral distance, the lateral distance being greater than the linewidth of each of the second plurality of metal layers.

13. The structure according to claim 11, wherein, The first interconnect layer includes a first dielectric layer, the second interconnect layer includes a second dielectric layer, the second dielectric layer in the second interconnect layer is directly located on the first dielectric layer in the first interconnect layer, and the first dielectric layer includes a dielectric material different from the second dielectric layer.

14. The structure according to claim 13, wherein, Each of the first plurality of metal layers is completely covered by the first dielectric layer in the first interconnect layer and the second dielectric layer in the second interconnect layer, and directly contacts the first dielectric layer in the first interconnect layer and the second dielectric layer in the second interconnect layer.

15. The structure according to claim 14, wherein, The first dielectric layer in the first interconnect layer is laterally located between two adjacent metal layers in the first plurality of metal layers.

16. The structure according to claim 15, wherein, Each of the second plurality of metal layers is vertically aligned above the first dielectric layer in the first interconnect layer.

17. The structure according to claim 13, wherein, The metal layers in the second plurality of metal layers are separated from each other by the second dielectric layer, and each metal layer in the first plurality of metal layers is vertically aligned only below the second dielectric layer.

18. The structure according to claim 11, wherein, Each of the second plurality of metal layers is positioned equidistant from two adjacent metal layers in the first plurality of metal layers.

19. The structure according to claim 11, wherein, The second plurality of metal layers includes a first group of metal lines intersecting with the second group of metal lines, the first group of metal lines being biased by a first voltage, and the second group of metal lines being biased by a second voltage, wherein the second voltage is higher than the first voltage.

20. The structure according to claim 11, wherein, The second interconnect layer is located directly above the first interconnect layer.

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