Chip packaging structure and preparation method thereof
By arranging identical dies on the silicon bridge die and performing rotationally symmetric interconnection, the high cost and high latency problems of chip packaging in the prior art are solved, realizing an efficient chip packaging structure design that supports high-speed interfaces and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAFENG INTEGRATED ELECTRONICS CO LTD
- Filing Date
- 2025-12-03
- Publication Date
- 2026-04-17
AI Technical Summary
In existing technologies, increasing the area of a single die or using advanced process technology to improve computing power results in problems such as decreased wafer yield, high cost, high technical barriers, high power consumption and high latency. Heterogeneous chip integration relies on high-speed serial interfaces, leading to complex communication systems and high interface IP costs.
Multiple identical dies are arranged on a silicon bridge die, with adjacent dies aligned and rotated symmetrically and interconnected by the silicon bridge to form the shortest point-to-point interconnection path. The interconnection of the drive port and the receiver port is achieved using 2.5D packaging technology.
It improves connection density and signal integrity, reduces signal transmission delay and power consumption, supports multiple high-speed interfaces, meets the high-speed interconnection requirements of chips, and reduces production complexity and cost.
Smart Images
Figure CN121889018A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, specifically to a chip packaging structure and its fabrication method. Background Technology
[0002] With the rapid development of technologies such as artificial intelligence and high-performance computing, the demand for die-based computing power continues to grow. Currently, computing power is mainly improved by increasing the area of a single die or by adopting more advanced manufacturing processes. However, increasing the area of a single die leads to a significant decrease in tape-out yield, while development costs and risks increase dramatically. Advanced manufacturing processes are not only expensive but also have high technical barriers and long development cycles. In addition, when expanding functionality at the system level, it is often necessary to integrate dies with different processes and functions (i.e., heterogeneous chip units). Current solutions generally rely on high-speed serial interfaces for heterogeneous interconnection, which not only introduces complex communication subsystems but also results in high power consumption, high latency, and high interface IP costs. Summary of the Invention
[0003] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a chip packaging structure and a method for fabricating the same.
[0004] To achieve the above objectives, this application adopts the following technical solution: a chip packaging structure, including a silicon bridge die and at least two dies of the same specifications disposed on the silicon bridge die, each die having multiple driving ports and multiple receiving ports arranged along its periphery, and the number and arrangement of the driving ports in each die being consistent with the number and arrangement of the receiving ports;
[0005] The two adjacent dies are aligned and rotate symmetrical about the center point between them, and the drive port and the receive port in one die are respectively connected to the receive port and the drive port in the other die through the silicon bridge die.
[0006] The application of this application has the following beneficial effects: By designing the structure of the dies and the arrangement between adjacent dies, the drive port and receive port of one die can be matched one-to-one with the receive port and drive port of the other die, thus forming a point-to-point shortest interconnection path between the drive port of one die and the receive port of the other die. This interconnection of corresponding drive and receive ports not only shortens the connection distance but also avoids cross-wiring, effectively improving connection density and signal integrity. This yields several advantages: chips with the same computing power as large dies can be packaged from multiple identical and smaller dies; multiple high-speed interfaces are supported to meet the high-speed interconnection requirements of chips; signal transmission delay is reduced and transmission power consumption is decreased.
[0007] Optionally, each of the die has multiple edges and the drive port and the receive port are arranged on at least one edge, and both the drive port and the receive port are configured to be selectively opened and closed.
[0008] Optionally, the chip package structure includes two dies, each die being rectangular and having the drive port and receive port arranged on one of its edges, the two dies being aligned and rotated symmetrically about a center point between them; or, the chip package structure includes at least four dies, each die being square and having the drive port and receive port arranged on two of its edges, the plurality of dies being aligned and adjacent dies being rotated symmetrically about a center point between them.
[0009] Optionally, interconnect leads for interconnecting drive ports and receiver ports are formed on the silicon bridge die. Interconnect microbumps are formed at both ends of the interconnect leads. Both the drive port and the receiver port are formed with mating microbumps, and the mating microbumps are flip-bonded to the interconnect microbumps.
[0010] Optionally, the length of the interconnecting lead is no greater than 2 mm.
[0011] Optionally, the spacing between two adjacent interconnect leads is no greater than 2 μm.
[0012] Optionally, the dies have the same function to form a homogeneous chip unit; or, the dies have different functions to form a heterogeneous chip unit.
[0013] Optionally, the dies are arranged in a lateral alignment and / or a vertical alignment on the silicon bridge die.
[0014] In addition, this application also provides a method for fabricating a chip packaging structure, including:
[0015] At least two bare dies are provided, each of which has multiple drive ports and multiple receive ports arranged along its periphery, and the number and arrangement of the drive ports in each of the bare dies are consistent with the number and arrangement of the receive ports;
[0016] A silicon bridge die is provided, and all the dies are arranged in an aligned manner on the silicon bridge die, such that two adjacent dies are rotated symmetrical about a center point between them, so that the drive port and the receive port of one of the two adjacent dies correspond one-to-one with the receive port and the drive port of the other die.
[0017] The corresponding drive ports and receiver ports are interconnected.
[0018] The chip packaging method provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned chip packaging structure, and will not be repeated here.
[0019] Optionally, interconnecting the corresponding drive ports and receiver ports includes:
[0020] The drive port and receiver port are interconnected using a 2.5D packaging process with a silicon interposer.
[0021] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description
[0022] The following description, in conjunction with the accompanying drawings, further illustrates this application:
[0023] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram showing two adjacent dies interconnected by a silicon bridge in the chip packaging structure.
[0025] Figure 3 for Figure 2 A schematic diagram of the bare die after removing the silicon bridge;
[0026] Figure 4 for Figure 2 An enlarged schematic diagram of part A in the middle;
[0027] Figure 5 This is a schematic diagram of the chip packaging structure in another implementation method;
[0028] Figure 6 This is a schematic diagram of a chip packaging structure in one optional implementation.
[0029] Figure 7 This is a schematic diagram of a chip packaging structure in another alternative implementation.
[0030] Among them, 1. First die; 10. First driver port group; 100. First driver terminal docking microbump; 11. First receiver port group; 110. First receiver terminal docking microbump; 2. Second die; 20. Second driver port group; 200. Second driver terminal docking microbump; 21. Second receiver port group; 210. Second receiver terminal docking microbump; 3. Silicon bridge die; 30. Interconnect lead; 31. Interconnect microbump; 4. Third die; 5. Fourth die; 6. Fifth die; 7. Sixth die. Detailed Implementation
[0031] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.
[0032] The terms "an embodiment," "example," or "trademark" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.
[0033] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.
[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0035] This embodiment provides a chip packaging structure, such as Figure 1 , Figure 2 and Figure 3 As shown, the chip package structure includes a silicon bridge die 3 and two identical dies disposed on the silicon bridge die 3. Wherein, as... Figure 3 As shown, each die has multiple drive ports (not shown) and multiple receive ports (not shown) arranged along its periphery, and the number and arrangement of drive ports in each die are consistent with the number and arrangement of receive ports. Furthermore, adjacent dies are aligned and arranged with rotational symmetry about their center point. The drive ports and receive ports in one die are interconnected with the receive ports and drive ports in the other die via silicon bridge die 3, corresponding one-to-one. In this embodiment, "same specifications" means that the two dies have identical physical parameters (die size, number and definition of pins, package type, etc.) and identical electrical parameters (supply voltage range, operating temperature range, interface level standard, power consumption level, etc.). However, it does not limit whether the specific functions of the two dies are the same.
[0036] By structurally designing the dies and the arrangement of adjacent dies, the drive and receive ports of one die can be matched one-to-one with the receive and drive ports of the other die. This creates a point-to-point shortest interconnect path between the drive port of one die and the receive port of another. Interconnecting the corresponding drive and receive ports not only shortens the connection distance but also avoids cross-wiring, effectively improving connection density and signal integrity. This yields several benefits: chips with the same computing power as large dies can be packaged from multiple identical and smaller dies; multiple high-speed interfaces can be supported to meet the high-speed interconnect requirements of chips; signal transmission latency and power consumption are reduced.
[0037] It is understandable that the drive port and the receive port are two different types of ports on the die. The drive port is used to provide signals or data to the outside, while the receive port is used to receive signals or data from the outside.
[0038] For ease of understanding and distinction, in this embodiment, one of the two bare wafers is named "First Bare Wafer 1," and the other is named "Second Bare Wafer 2." For example... Figure 3As shown, a first die 1 has a first driving port group 10 and a first receiving port group 11 arranged around its periphery. The first driving port group 10 includes multiple first driving ports, which are also the aforementioned driving ports. The first receiving port group 11 includes multiple first receiving ports, which are also the aforementioned receiving ports. A second die 2 has a second driving port group 20 and a second receiving port group 21 arranged around its periphery. The second driving port group 20 includes multiple second driving ports, which are also the aforementioned driving ports. The second receiving port group 21 includes multiple second receiving ports, which are also the aforementioned receiving ports. Therefore, specifically in this embodiment, the aforementioned "the driving port and receiving port in one die are interconnected with the receiving port and driving port in the other die one-to-one through the silicon bridge die 3" means that the first driving port and the second receiving port are interconnected one-to-one through the silicon bridge die 3, and the first receiving port and the second driving port are interconnected one-to-one through the silicon bridge die 3.
[0039] It is easy to understand that each die has multiple edges. Taking a rectangular die as an example, a rectangular die has four edges. As long as the driving port and receiving port are arranged on one of the edges, interconnection between two adjacent dies can be achieved. This embodiment uses the arrangement of two dies on the silicon bridge die 3 as an example. Both dies have the driving port and receiving port arranged on one edge. Specifically, as shown... Figure 3 As shown, the first die 1 and the second die 2 are arranged in an aligned configuration, and are rotationally symmetrical about their center point. This alignment can refer to either a horizontal or vertical arrangement of the two dies, as long as they are aligned along the arrangement direction. Alignment along the arrangement direction ensures symmetry about a virtual center line, further ensuring rotational symmetry about their center point. It should be noted that the drive and receive ports on each die are configured to be selectively open and closed. With this design, drive and receive ports requiring interconnection can be opened, while those on the outer edges without interconnection requirements can be closed.
[0040] Figure 5An alternative embodiment of the chip package structure is illustrated, comprising four dies, which are designated as die 4 (third die), die 5 (fourth die), die 6 (fifth die), and die 7 (sixth die). Dies 4, 5, 6, and 7 are all square and have drive and receive ports on two of their edges. The four dies are arranged in a symmetrical configuration, with two dies arranged horizontally and two vertically, and any two adjacent dies are rotationally symmetrical about their center point. Specifically, die 4 and 5 are rotationally symmetrical about their center points, 5 and 6 are rotationally symmetrical about their center points, 6 and 7 are rotationally symmetrical about their center points, and 7 and 4 are rotationally symmetrical about their center points.
[0041] It is easy to understand that, with Figure 2 Taking the chip packaging structure shown as an example, the number of bare dies can continue to increase along the arrangement direction. Correspondingly, the drive port and receiver port are formed on the two opposite edges of the bare dies, and adjacent bare dies are rotationally symmetrical about their center point by 180°. Similarly, taking... Figure 5 Taking the chip packaging structure shown as an example, the number of bare dies can be further increased along the arrangement direction, and correspondingly, the drive port and receiver port can be formed on all four edges of the bare die. For example, refer to... Figure 6 As shown, Figure 6 The chip package structure shown includes sixteen dies, each with drive and receive ports formed along its four edges. The drive and receive ports on each die can be selectively turned on or off as needed for interconnection; the drive and receive ports on the outer edges of the outer dies can be turned off. Figure 6 The chip package structure shown can be understood as four identical dies forming a die group, and then the four die groups are arranged 90° rotationally symmetrical about the center point. It is easy to understand that a die group can also be formed by eight or sixteen or more (powers of four) identical dies, and then the chip package structure is obtained by arranging four die groups 90° rotationally symmetrical about the center point.
[0042] In addition, the above-mentioned Figure 2 or Figure 5 or Figure 6 In the chip packaging structures shown, each silicon bridge die 3 has two identical dies mounted on it. However, in other alternative embodiments, each silicon bridge die 3 may have four identical dies mounted on it, such as... Figure 7In the chip package structure shown, four identical dies are interconnected through a silicon bridge die 3.
[0043] In this embodiment, the silicon bridge die 3 is a silicon die. Through rewiring and microbumps, a 2.5D or 3D packaging process is used to interconnect the first driving port and the second receiving port, and to interconnect the second driving port and the first receiving port. Specifically, in conjunction with... Figure 2 and Figure 3 As shown, interconnect leads 30 for interconnecting drive ports and receiver ports are formed on the silicon bridge die 3, and interconnect microbumps 31 are formed at both ends of the interconnect leads 30. Correspondingly, mating microbumps are formed on both the drive port and the receiver port, and the mating microbumps are flip-bonded to the interconnect microbumps 31 during assembly. For ease of understanding, in this embodiment, the mating microbump formed on the first drive port is named the first drive end mating microbump 100, the mating microbump formed on the first receiver port is named the first receiver end mating microbump 110, the mating microbump formed on the second drive port is named the second drive end mating microbump 200, and the mating microbump formed on the second receiver port is named the second receiver end mating microbump 210.
[0044] When interconnecting the drive port and the receiver port using 2.5D packaging technology, the first drive end mating microbump 100 on the first drive port is flip-bonded to the corresponding interconnect microbump 31, the second receiver end mating microbump 210 on the second receiver port is flip-bonded to the corresponding interconnect microbump 31, the second drive end mating microbump 200 on the second drive port is flip-bonded to the corresponding interconnect microbump 31, and the first receiver end mating microbump 110 on the first receiver port is flip-bonded to the corresponding interconnect microbump 31. This achieves the interconnection between the second drive port and the first receiver port, as well as the interconnection between the first drive port and the second receiver port.
[0045] The above structural design can significantly increase wiring density and reduce the overall size of the chip package structure. Specifically, for example... Figure 4 As shown, in this embodiment, the length of the interconnect lead 30 is designed to be 1.5 mm, the spacing between two adjacent interconnect leads 30 is designed to be 1 μm, and the density of the interconnect leads 30 is approximately 1000 lines per millimeter. In other optional embodiments, the length of the interconnect lead 30 can be designed to be no greater than 2 mm, and the spacing between two adjacent interconnect leads 30 can be designed to be no greater than 2 μm. By interconnecting the drive port and the receiver port through the high-density micro-bump structure and the interconnect leads 30, the signal path can be made more compact, while reducing inductance and resistance, and improving the speed and quality of signal transmission.
[0046] In this embodiment, the first die 1 and the second die 2 have the same function, forming a homogeneous chip unit. The advantage of this design is that multiple dies with the same function can be packaged using this chip packaging structure. Using small-sized dies of the same specifications reduces the design complexity of the dies. Furthermore, it allows the use of dies with the same manufacturing process, simplifying production costs and improving production efficiency. Additionally, it reduces the number of tape-out cycles and the risk of each tape-out, reducing defect rates and improving overall yield.
[0047] In other alternative embodiments, the first die 1 and the second die 2 may be designed to have different functions, so that they form a heterogeneous chip unit. For example, the heterogeneous chip unit composed of the first die 1 and the second die 2 may respectively include a CPU chip and an NPU chip. In other alternative embodiments, the heterogeneous chip unit includes at least two of the following: a CPU chip, an NPU chip, and a memory chip.
[0048] As mentioned above, Figure 2 The diagram shows the arrangement of the first bare plate 1 and the second bare plate 2 vertically aligned. Figure 5 The diagram illustrates a configuration where the third die 4, fourth die 5, fifth die 6, and sixth die 7 are aligned both vertically and horizontally. Therefore, the dies in this chip packaging unit can be arranged horizontally and / or vertically on the silicon bridge die 3, depending on design requirements. This lowers the design threshold for the chip packaging unit and expands its applicability to more scenarios.
[0049] It should be noted that in this embodiment, the silicon bridge die 3 is used to connect the first die 1 and the second die 2. The size of the silicon bridge die 3 is equal to a specified value, for example, in one feasible implementation, the specified value is 3mm*8mm. As mentioned above, when the spacing between adjacent interconnect leads 30 is 1μm, the density of interconnect leads 30 is approximately 1000 lines per millimeter. Therefore, when the size of the silicon bridge die 3 is 3mm*8mm, approximately 8000 interconnect leads 30 can be arranged per layer. It should be noted that in other optional embodiments, the specific dimensions of the die and interconnect substrate are set according to actual needs, and this embodiment does not limit them.
[0050] Furthermore, this embodiment also provides a method for fabricating a chip packaging structure, which can be used to fabricate the aforementioned chip packaging structure. The fabrication method includes the following steps:
[0051] Step S100: Provide at least two bare dies, wherein each bare die has multiple drive ports and multiple receive ports arranged along its periphery, and the number and arrangement of drive ports in each bare die are consistent with the number and arrangement of receive ports. Specifically, in this embodiment, a first bare die 1 and a second bare die 2 are provided, and the arrangement of drive ports and receive ports of the two bare dies satisfies the above requirements.
[0052] Step S200: Provide a silicon bridge die 3, and arrange all dies on the silicon bridge die 3 in an aligned manner, such that adjacent dies are rotationally symmetrical about the center between them, so that the drive port and receive port of one die corresponds one-to-one with the receive port and drive port of the other die. Specifically, in this embodiment, when arranging the first die 1 and the second die 2 in an aligned manner on the interconnect substrate, it is also necessary to ensure that the first die 1 and the second die 2 are rotationally symmetrical about the center between them.
[0053] Step S300: Interconnect the corresponding drive ports and receiver ports. Specifically, in this embodiment, using a silicon interposer and a 2.5D packaging process, the first drive terminal mating microbump 100 on the first drive port is flip-bonded to the corresponding interconnect microbump 31, and the second receiver terminal mating microbump 210 on the second receiver port is flip-bonded to the corresponding interconnect microbump 31. The interconnection between the first drive port and the second receiver port is then achieved through interconnect leads 30. Similarly, using a silicon interposer and a 2.5D packaging process, the second drive terminal mating microbump 200 on the second drive port is flip-bonded to the corresponding interconnect microbump 31, and the first receiver terminal mating microbump 110 on the first receiver port is flip-bonded to the corresponding interconnect microbump 31. The interconnection between the second drive port and the first receiver port is then achieved through interconnect leads 30.
[0054] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.
Claims
1. A chip package structure, characterized by, The device includes a silicon bridge die and at least two identical dies disposed on the silicon bridge die. Each die has multiple drive ports and multiple receive ports arranged along its periphery, and the number and arrangement of the drive ports in each die are consistent with the number and arrangement of the receive ports. Two adjacent dies are aligned and rotate symmetrical about the center point between them, and the drive port and the receive port in one die are respectively connected to the receive port and the drive port in the other die through the silicon bridge die.
2. The chip packaging structure as described in claim 1, characterized in that, Each of the die has multiple edges and the drive port and the receive port are arranged on at least one edge, and both the drive port and the receive port are configured to be selectively opened and closed.
3. The chip packaging structure as described in claim 2, characterized in that, The chip package structure includes two bare dies, each of which is rectangular and has a drive port and a receive port arranged on one of its edges. The two bare dies are aligned and arranged in a 180° rotational symmetry about the center point between them. Alternatively, the chip package structure includes at least four dies, each die being square and having the drive port and receive port arranged on its two edges, with multiple dies arranged in an aligned manner and adjacent dies being rotationally symmetrical about a center point between them at 90°.
4. The chip packaging structure as described in any one of claims 1 to 3, characterized in that, The silicon bridge die has interconnect leads formed for interconnecting the drive port and the receiver port. Interconnect microbumps are formed at both ends of the interconnect leads. Both the drive port and the receiver port have mating microbumps, and the mating microbumps are flip-bonded to the interconnect microbumps.
5. The chip packaging structure as described in claim 4, characterized in that, The length of the interconnecting lead is no greater than 2 mm.
6. The chip packaging structure as described in claim 4, characterized in that, The spacing between two adjacent interconnect leads is no greater than 2 μm.
7. The chip packaging structure as described in any one of claims 1 to 3, characterized in that, The bare dies have the same function to form a homogeneous chip unit; Alternatively, the bare dies may have different functions to form heterogeneous chip units.
8. The chip packaging structure as described in any one of claims 1 to 3, characterized in that, The dies are arranged in a horizontal alignment and / or a vertical alignment on the silicon bridge die.
9. A method for fabricating a chip packaging structure, characterized in that, include: At least two bare dies are provided, each of which has multiple drive ports and multiple receive ports arranged along its periphery, and the number and arrangement of the drive ports in each of the bare dies are consistent with the number and arrangement of the receive ports; A silicon bridge die is provided, and all the dies are arranged in an aligned manner on the silicon bridge die, such that two adjacent dies are rotationally symmetrical about the center point between them, so that the drive port and the receive port of one of the two adjacent dies correspond one-to-one with the receive port and the drive port of the other die. The corresponding drive ports and receiver ports are interconnected.
10. The preparation method according to claim 9, characterized in that, The step of interconnecting the one-to-one corresponding drive port and the receiver port includes: The drive port and receiver port are interconnected using a 2.5D packaging process with a silicon interposer.