Processing unit including dynamically allocable vector register file for non-vector instruction processing

Abstract

A processing unit is disclosed that includes a dynamically allocatable vector register file for non-vector instruction processing. The processing unit includes integer execution circuitry for processing integer instructions and an integer register file. The processing unit also includes vector execution circuitry and a vector register file to process the vector instruction. The integer and vector register files are each sized at design time. A processing unit may be invoked to perform a varying workload that varies between integer operations and vector operations. The processor is configured to dynamically allocate portions of a vector register in the vector register file for execution of the integer instruction, rather than statically specifying the entire vector register file to the vector register.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 475,320, filed September 27, 2023, entitled “Processing Unit Including an Actively Allocable Vector Register File for Non-Vector Instruction Processing,” the entire contents of which are incorporated herein by reference. Background Technology

[0002] I. Technical Field

[0003] The technology disclosed herein relates in general to processor pipeline microarchitecture.

[0004] II. Background Technology

[0005] Microprocessors, also known as processing units (PUs), perform computational tasks in a wide variety of applications. One type of conventional microprocessor or PU is the Central Processing Unit (CPU). Another type of microprocessor or PU is a dedicated processing unit called a Graphics Processing Unit (GPU). GPUs are designed with dedicated hardware to accelerate the rendering of graphics and video data to be displayed. GPUs can be implemented as integrated components of a general-purpose CPU or as discrete hardware components separate from the CPU. The PU executes software instructions that command the processor to fetch data from locations in memory and use the fetched data to perform one or more processor operations. The results can then be stored in memory.

[0006] Modern instruction set architectures (ISAs) for PUs have added advanced multimedia and machine learning / artificial intelligence (ML / AI) instructions capable of handling multidimensional data structures. For example, for x86 Intel… ® Advanced Vector Extensions (AVX) for instruction set architectures and for Arm ® The Scalable Vector Extensions (SVE) and SVE2 of the v8 instruction set architecture allow computer workloads to expand from those utilizing integer operations to include workloads utilizing vector operations. Integer operations are performed by specially designed integer circuitry that executes integer instructions. Floating-point operations and vector instructions that operate on operand arrays are performed by specially designed vector circuitry that executes vector instructions. During instruction execution, both integer and vector circuitry utilize a dedicated register file as a local fast storage device to maintain one or more copies of the schema registers to facilitate out-of-order instruction processing and avoid pipeline stalls. Summary of the Invention

[0007] The aspects disclosed in the detailed description include a processing unit that includes a dynamically allocable vector register file for processing non-vector instructions. The processing unit includes integer execution circuitry and an integer register file for processing and executing integer instructions. The processing unit also includes vector execution circuitry and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time based on a anticipated trade-off between memory area and power consumption relative to the expected workload. However, the processing unit can be invoked to perform varying workloads that differ between integer and vector operations. In this regard, in an exemplary aspect, instead of statically allocating vector registers in the vector register file to the vector execution circuitry, the processor is configured to dynamically allocate portions of the vector registers in the vector register file for executing integer instructions based on the relative workload of integer instructions relative to vector instructions. The processing unit is also configured to dynamically reallocate portions of the vector registers in the vector register file back to the vector execution circuitry. By advantageously allocating and reallocating vector registers in the vector register file for integer instructions, the size of the integer vector file can be reduced or maintained while increasing throughput for heavy integer-based workloads.

[0008] In one aspect, an apparatus including a processing unit is disclosed. The processing unit includes: one or more non-vector processing circuits; a vector register file including a first portion designated for vector registers; and a queue buffer configured to receive a plurality of vector instructions. The processing unit is configured to: determine vector register requirements for executing the plurality of vector instructions; and, in response to determining that the vector register requirements for executing the plurality of vector instructions are less than substantially all of the first portion designated for vector registers, allocate a first subset of the first portion designated for vector registers to the one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for vector registers. The processing unit executes the plurality of vector instructions.

[0009] In another aspect, a method for dynamically allocating an adaptive vector register file is disclosed. The method includes: assigning a first portion of the register file to a vector register; receiving a plurality of vector instructions; determining vector register requirements for executing the plurality of vector instructions; and, in response to determining that the vector register requirements for executing the plurality of vector instructions are less than substantially all of the first portion assigned to the vector register, allocating a first subset of the first portion assigned to the vector register to one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion assigned to the vector register.

[0010] In another aspect, an apparatus is disclosed. The apparatus includes: means for assigning a first portion of a register file to a vector register; means for assigning the first portion of the register file to the vector register; means for determining vector register requirements for executing a plurality of vector instructions; and means for allocating a first subset of the first portion of the vector register to one or more non-vector processing circuits in response to determining that the vector register requirements for executing the plurality of vector instructions are less than substantially all of the first portion assigned to the vector register, thereby leaving a supplementary portion of the first portion assigned to the vector register. Attached Figure Description

[0011] Figure 1 This is a block diagram of an exemplary processor-based system including a processing unit that includes a dynamically allocatable vector register file for non-vector instruction processing;

[0012] Figure 2 This is a block diagram of an exemplary dynamically allocable vector register file for non-vector instruction processing;

[0013] Figure 3 yes Figure 1 and Figure 2 A timing diagram of an exemplary sequence of allocation and reallocation of vector registers in the data space of the dynamically allocable vector register file discussed in the article;

[0014] Figure 4 This is a flowchart illustrating an exemplary process for dynamically allocating a vector register file, the vector register file including... Figure 1 and Figure 2 A dynamically allocable adaptive vector register file; and

[0015] Figure 5 This is an exemplary block diagram of a processor-based system that may include a dynamically allocable vector register file, the dynamically allocable vector register file including... Figure 1 and Figure 2 The dynamically allocable adaptive vector register file in and according to, but not limited to, Figure 4 An example process in [the text]. Detailed Implementation

[0016] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0017] The aspects disclosed in the detailed description include a processing unit that includes a dynamically allocable vector register file for non-vector processing. The processing unit includes integer execution circuitry and an integer register file for processing and executing integer instructions. The processing unit also includes vector execution circuitry and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time based on a anticipated trade-off between memory area and power consumption relative to the expected workload. However, the processing unit can be invoked to perform varying workloads that differ between integer and vector operations. In this regard, in an exemplary aspect, instead of statically allocating vector registers in the vector register file to the vector execution circuitry, the processor is configured to dynamically allocate portions of the vector registers in the vector register file for executing integer instructions based on the relative workload of integer instructions relative to vector instructions. The processing unit is also configured to dynamically reallocate portions of the vector registers in the vector register file back to the vector execution circuitry. By advantageously allocating and reallocating vector registers in the vector register file for integer instructions, the size of the integer vector file can be reduced or maintained while increasing throughput for heavy integer-based workloads.

[0018] in this regard, Figure 1 This is a block diagram of an exemplary processor-based system 100 including a processing unit 102, which includes a dynamically allocable vector register file (also referred to as adaptive vector register file 104) for non-vector processing. As described in more detail below, the adaptive vector register file 104 is configured to dedicate a portion of the adaptive vector register file 104 to vector registers and to allocate a subset of the dedicated portion of the adaptive vector register file 104 to one or more non-vector processing circuits. For example, the non-vector processing circuits may include, but are not limited to, one or more circuits, including integer instruction scheduler circuitry 106, load / store buffer circuitry 108, or miss buffer circuitry 110. A portion of the adaptive vector register file 104 may include the entire capacity of the adaptive vector register file 104. Figure 2 The collaboration between the non-vector processing circuitry and the adaptive vector register file 104 is described in more detail so that a subset of the dedicated portion of the adaptive vector register file 104 can be used for non-vector processing operations. Figures 3 to 4 Described Figure 1 Exemplary operation of the adaptive vector register file 104 of the processor-based system 100. In the description Figure 1 Before detailing the collaboration between the non-vector processing circuitry and the adaptive vector register file 104, the following first describes... Figure 1 Other components of the processing unit 102.

[0019] As an example, processing unit 102 may be located in system-on-chip (SoC) 112. In this regard, instructions 114, including integer and vector instructions, are fetched from instruction memory 118 by instruction fetch circuitry 116. As an example, instruction memory 118 may be located in or as part of system memory in processor-based system 100. Instruction cache 120 may also be located in processing unit 102 to cache instructions 114 from instruction memory 118 in order to reduce the latency of instruction fetch circuitry 116 fetching instructions 114. Instruction fetch circuitry 116 is configured to provide instructions 114 as fetched instructions 114F to one or more instruction pipelines I0-I in processing unit 102. N The instructions 114F are preprocessed and then extracted to reach the execution circuits (such as the integer execution circuit 122 and vector execution circuit 124 in the processing unit 102) for execution. Instruction pipeline I0-I N Different processing circuits or levels across processing unit 102 are configured to preprocess and process the extracted instructions 114F in a series of steps that can be executed concurrently to improve throughput before the extracted instructions 114F are executed in integer execution circuit 122 and vector execution circuit 124.

[0020] Continue to refer to Figure 1 Furthermore, a prediction circuit 126 (e.g., a branch prediction circuit) is provided to infer or predict the target address of the control flow-fetched instruction 114F (such as a conditional branch instruction). The prediction of the target address by the prediction circuit 126 is used by the instruction fetching circuit 116 to determine the next fetched instruction 114F to be fetched based on the predicted target address. The instruction decoding circuit 128 is configured to decode the fetched instruction 114F fetched by the instruction fetching circuit 116 into a decoded instruction 114D to determine the type of instruction 114 and the required action, which is then used to determine which instruction pipeline I0-I the fetched instruction 114F should be placed in. N middle.

[0021] Continue to refer to Figure 1 In this example, the decoded instruction 114D is then placed in instruction pipeline I0-I. N One or more instructions are passed through the instruction pipeline and then provided to dispatch and scheduler circuit 130. Dispatch and scheduler circuit 130 is configured to divide the decoded instruction 114D into a series of instructions including integer instructions INT. o -INT y Integer instruction pipeline and including vector instructions V o -V zThe vector instruction pipeline. The dispatch and scheduler circuit 130 determines whether any register names in the decoded instruction 114D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing of instruction 114. If possible, Figure 1 The processing unit 102 can process the fetched instructions 114F out of order to achieve greater throughput performance and parallelism. However, the number of logical (i.e., architectural) registers set in the processing unit 102 is limited by the architectural size of the integer register file 132 and the adaptive vector register file 104.

[0022] In this regard, dispatch and scheduler circuit 130 is configured to invoke a register map (RMT) to rename logical source register operands and / or write the destination register operand of instruction 114 to an available physical register in a physical register file (such as integer register file 132 or adaptive vector register file 104). Specifically, integer instruction scheduler circuit 106 is configured to rename integer instructions (such as integer instructions INT) in integer register file 132. o -INT y The vector instruction scheduler circuit 134 is configured to rename vector instructions (such as vector instruction V) in the adaptive vector register file 104. This includes the source register operand of the instruction and / or the destination register operand of the integer instruction. o -V z The source register operands of the vector instruction and / or the destination register operands of the instruction are written to. To rename the trace registers of the integer instruction scheduler circuit 106, the integer instruction scheduler circuit 106 can access a fixed amount of data space associated with the scoring board application techniques used to utilize its respective instruction trace registers. (As will be...) Figure 2 As further discussed, if the adaptive vector register file 104 has allocated a subset of the first part of the adaptive vector register file 104, which was originally assigned to the vector register, to the integer instruction scheduler circuit 106, the integer instruction scheduler circuit 106 can expand its fixed amount of data space for scoreboard applications in order to additionally rename the logical source register operands of the integer instructions and / or write the destination register operands of the integer instructions in the adaptive vector register file 104, thereby advantageously providing support for instruction workloads with a greater focus on integer instructions.

[0023] Possible Expectations Figure 1 The processing unit 102 has visibility of a large number of future instructions 114 (i.e., instruction windows) in order to extract a large number of instructions 114 that can be executed independently and out of order for performance improvement.

[0024] In this respect, dispatch and scheduler circuit 130 is configured to provide the generated value retrieved from executed instruction 114E as the source register operand of instruction 114 to be executed. Dispatch and scheduler circuit 130 is configured to dispatch decoded instruction 114D to instruction queue circuit 136 to wait for dispatch to integer execution circuit 122 or vector execution circuit 124 for execution when all source register operands of decoded instruction 114D are available. Instruction queue circuit 136 includes queue buffer 138 configured to receive one or more integer instructions and queue buffer 140 configured to receive one or more vector instructions. Vector instruction scheduler circuit 134 is configured to analyze vector instructions (such as vector instruction V) in queue buffer 140. o -V z The vector instruction scheduler circuit 134 determines whether substantially all of the vector instructions in the vector instruction queue buffer 140 need to be assigned to the first portion of the adaptive vector register file 104 for execution. If not, the vector instruction scheduler circuit 134 allocates a first subset of the first portion of the vector register to one or more non-vector processing circuits. The supplementary portion of the first portion assigned to the vector register remains assigned to the vector register. The one or more non-vector processing circuits include the integer instruction scheduler circuit 106, the load / store buffer circuit 108, and the miss buffer circuit 110.

[0025] When the source register operand is available, the integer execution circuit 122 executes one or more integer instructions (such as the integer instruction INT) from the integer instruction queue buffer 138. o -INT y 114I). Similarly, when the source register operand is available, the vector execution circuit 124 executes one or more vector instructions 114V (such as vector instruction V) from the vector instruction queue buffer 140. o -V zThe load / store buffer circuit 108 receives the result of the executed instruction 114E and writes it back to memory, including data cache 142, for use by subsequent instructions. The load / store buffer circuit 108 has a fixed amount of space to store the result of the executed instruction 114E. However, if the adaptive vector register file 104 has allocated a subset of the first part of the adaptive vector register file 104, which was initially assigned to the vector register, to the load / store buffer circuit 108, the load / store buffer circuit 108 can additionally store more results of the executed instruction 114E in the adaptive vector register file 104, thereby advantageously increasing the capacity of the space in the load / store buffer circuit 108 that was originally fixed at design time. Therefore, increasing the capacity of the load / store buffer circuit 108 by utilizing the adaptive vector register file 104 provides the ability to store and retrieve more data from the local buffers instead of accessing them from the relatively slow cache memory. This advantageous dynamic capacity increase results in improved performance of load and store memory instructions, which are inherently relatively slow due to memory access times. The increased capacity leads to faster dependency resolution and is generally beneficial for all workloads that are more focused on integer instructions.

[0026] Load / store buffer circuit 108 is also configured to load data from data cache 142 in response to execution instruction 114E. Data cache 142 includes miss buffer circuit 110 to temporarily store addresses of data retrieved from system memory that are not in data cache 142 when requested from load / store buffer circuit 108 (i.e., cache miss). Addresses stored in the miss buffer are analyzed to examine patterns among addresses that caused cache misses. These patterns are fed back to prediction circuit 126 to enhance predictive instruction prefetching. Miss buffer circuit 110 has a fixed capacity at design time. However, if adaptive vector register file 104 has allocated a subset of the first portion of the adaptive vector register file 104, initially assigned to the vector register, to miss buffer circuit 110, the capacity of miss buffer circuit 110 is advantageously increased to allow detection of more complex memory request patterns and prefetching them into cache memory before instructions request them, and to reduce cache misses and longer wait times, thereby increasing the throughput of processing unit 102.

[0027] Figure 2 It is an exemplary dynamically allocable vector register file for non-vector processing (e.g., Figure 1 A block diagram of the adaptive vector register file (104) in the file. Figure 1 The processing unit 102 in the middle and Figure 2Common components among the elements of the processing unit 102 are shown by common component numbers. The adaptive vector register file 104 includes an adaptive control unit 200 for interfacing with the extended circuitry of the non-vector processing circuitry 202 and a data space 204, which includes a first portion designated for the vector register 206, and as... Figure 2 As shown, a fixed design capacity for expanding non-vector processing circuitry 202 has been allocated, including but not limited to integer instruction scheduler circuitry 106, load / store buffer circuitry 108, and miss buffer circuitry 110. Optionally, data space 204 may include a guard region 208 to facilitate the allocation and reallocation of a first portion designated for vector registers to and from non-vector processing circuitry 202. Adaptive control unit 200 includes configuration and decoding circuitry 210 that communicates with separate expansion circuitry 212A-212C associated with each of the non-vector processing circuits 202. Optionally, a single expansion circuitry shared among all non-vector processing circuits 202 and separate configuration and decoding circuitry interfacing with the individual expansion circuitry 212A-212C may exist.

[0028] In operation, the vector instruction scheduler circuit 134 analyzes the queue buffer 140 and determines the vector instruction V to be executed. o -V z The vector register requirement is specified. The vector instruction scheduler circuit 134 transmits the determined requirement 213 to the adaptive control unit 200. In response, the adaptive control unit 200 determines the vector instruction V to be executed. o -V zThe vector register requirement is smaller than substantially all of the first portion assigned to the vector register. Configuration and decoding circuitry 210 is configured to allocate a subset 214 of the first portion assigned to the vector register to one or more non-vector processing circuits 202, such as a portion 216 of data space 204 allocated to an extension of the static data space associated with load / store buffer circuitry 108, a portion 218 of data space 204 allocated to an extension of the static data space associated with miss buffer circuitry 110, and a portion 220 of data space 204 allocated to an extension of the static data space associated with integer scheduler circuitry 106. Configuration and decoding circuitry 210 can be configured using various algorithms based on the minimum extension capacity of each non-vector processing circuit 202, and the size of subset 214 can be used to determine how much of subset 214 is allocated to one or more non-vector processing circuits 202. Based on the allocation of subset 214 to non-vector processing circuits 202, configuration and decoding circuitry 210 configures its decoding circuitry to map addresses allocated to individual non-vector processing circuits 202 to specific locations within the allocated subset. Based on the remaining portion (also called the supplementary portion) of the first part assigned to the vector register, the configuration and decoding circuit 210 configures its decoding circuitry to map the address of the vector register to the remaining portion. The configuration and decoding circuit 210 communicates 222, respectively, to the expansion circuits 212A-212C, the memory mapping for each non-vector processing circuit 202 assigned to each allocated subset of the non-vector processing circuit 202. When a read or write request arrives from a non-vector processing circuit, if the request falls within the memory mapping, the expansion circuits 212A-212C forward the request to the configuration and decoding circuit 210, where appropriate translations and boundary checks are performed to achieve accurate and secure access to the allocation of subset 214.

[0029] Once communicated, extension circuits 212A-212C each configure themselves to transmit a memory address request 224 (e.g., a read or write request) falling within the memory mapping of the communicated data to configuration and decoding circuit 210. For example, integer instruction scheduler circuit 106 may have been allocated a kilobyte (1KB) data space with memory addresses 0x0000…0x03E8 in the subset allocated to non-vector processing circuit 202. If integer instruction scheduler circuit 106 processes memory addresses falling within this memory range, instead of resolving the data location of the memory address using its normally defined memory source, extension circuit 212A will communicate with configuration and decoding circuit 210 of adaptive control unit 200 to retrieve data 226 from the allocated 1KB data space in a subset 214 of adaptive vector register file 104. The previously described operation is similar for load / store buffer circuit 108 and miss buffer circuit 110, varying primarily with the specific address regions mapped for those particular non-vector processing circuits 202. (See reference...) Figure 3 The redistribution operation of the expansion circuits 212A-212C and the adaptive vector register file 104 is discussed.

[0030] Figure 3 It is a dynamically allocable vector register file (such as...) Figure 1 and Figure 2 Timing diagram 300 illustrates an exemplary sequence of allocation and reallocation of vector registers in data space 204 of the adaptive vector register file 104 (discussed in the diagram). At time t... o Data space 204 includes a first portion 302 assigned to the vector register and an optional protection region 304. The optional protection region 304 is not designated for the vector register or non-vector processing circuitry. At time t1, data space 204 is shown as reflecting that the vector instruction scheduler circuit 134 has analyzed the queue buffer 140 and determined the parameters for executing the vector instruction V. o -V zThe adaptive control unit 200 has determined that the vector register requirement for executing vector instructions in queue buffer 140 is less than substantially all of the first portion 302 assigned to the vector register, and the configuration and decoding circuit 210 has allocated a subset 306 of the first portion 302 assigned to the vector register to one or more non-vector processing circuits, thus leaving a supplementary portion 308 of the first portion 302 for the vector register. At time t2, data space 204 is shown as reflecting that the vector instruction scheduler circuit 134 has analyzed queue buffer 140 and determined the vector register requirement for executing vector instructions. The adaptive control unit 200 has determined that the vector register requirement for executing vector instructions in queue buffer 140 is greater than the supplementary portion 308 assigned to the vector register at time t1, and the configuration and decoding circuit 210 has reallocated a second portion 310 of the subset 306 back to the vector register and allocated a guard region 304 to the vector register. If the optional protection region 304 is not configured, the adaptive control unit 200 can be configured to reallocate portions of the data space 204 shown at t1 that have been allocated to other non-vector processing circuitry. In this example, the second portion 310 was previously allocated to the miss buffer circuit 110 and the load / store buffer circuit 108. The data space 204 in the second portion 310 previously allocated to the miss buffer circuit 110, as well as the protection region 304, can be immediately recaptured for use by the vector execution circuit 124.

[0031] At time t3, data space 204 is shown as reflecting that vector instruction scheduler circuit 134 has analyzed queue buffer 140 and determined the vector register requirements for executing vector instructions. Adaptive control unit 200 has determined that the vector register requirements for executing vector instructions in queue buffer 140 are greater than the portion 312 assigned to the vector register at time t2, and configuration and decoding circuit 210 has reallocated the third portion 314 of subset 306 back to the vector register. In this example, the third portion 314 was previously allocated to load / store buffer circuit 108 and integer instruction scheduler circuit 106. After load / store buffer circuit 108 and integer instruction scheduler circuit 106 have finished using their respective data, data space 204 previously allocated to load / store buffer circuit 108 and integer instruction scheduler circuit 106 can be recaptured for the vector register. For example, when its corresponding data is written to data cache 142, load / store buffer circuit 108 will release its corresponding portion of data space 204 for recapture. For example, when the integer instruction scheduler circuit 106 finishes processing the associated integer instruction, it releases a corresponding portion of the data space 204 for recapture. Since the portion of the data space 204 allocated to the miss buffer circuit 110 can be recaptured immediately, while the portion allocated to other non-vector processing circuits 202 is only recaptured after those non-vector processing circuits 202 have finished using their data, the adaptive control unit 200 can prioritize reallocating the data space 204 allocated to the miss buffer circuit 110 before reallocating it to the load / store buffer circuit 108 or the integer instruction scheduler circuit 106. Given that the arrival rate of vector instructions can be random, the adaptive control unit 200 can be further configured to utilize the protection region 304 to handle instances where the arrival rate of vector instructions is faster than the rate at which the adaptive control unit 200 recaptures the data space 204 from the data allocated to the non-vector processing circuits.

[0032] Figure 4 This is a flowchart illustrating an exemplary process 400 for dynamically allocating a vector register file, the vector register file including... Figure 1 and Figure 2 The dynamically allocable adaptive vector register file 104. In this regard, Figure 4A first exemplary step in process 400 may include assigning a first portion 302 of vector register file 104 to a vector register (box 402). A next step in process 400 may include receiving multiple vector instructions (box 404). A next step in process 400 may include determining vector register requirements for executing the multiple vector instructions (box 406). For example, a register file (such as adaptive vector register file 104) may have a fixed size of 128K bits. This size would accommodate eight copies of 32 vector registers, each copy having 512 bits. Exemplary register requirements for the multiple vector registers may only require 16K bits or one copy of the 32 registers, leaving 112K bits unused when executing multiple vector registers. The next step in process 400 may include, in response to determining that the vector register requirement for execution is less than substantially all of the first portion 302 designated for the vector register, allocating a first subset 306 of the first portion 302 designated for the vector register to one or more non-vector processing circuits (106, 108, 110), thereby leaving a supplementary portion 308 (box 408) of the first portion 302 designated for the vector register. Continuing with the previous example, 112K bits will be allocated to the non-vector processing circuits, while 16K bits will continue to be used for the vector register. The next step in process 400 may include executing multiple vector instructions (box 410).

[0033] Electronic devices including a processing unit can be located in or integrated into any processor-based device, the processing unit including a dynamically allocatable vector register file for non-vector instruction processing, such as Figures 1 to 3 The process described herein and, in accordance with, but not limited to, any exemplary process (such as...) Figure 4 The process in 400) and any aspect disclosed herein. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, and multirotor aircraft.

[0034] in this regard, Figure 5An example of a processor-based system 500 is illustrated, which may include a dynamically allocatable vector register file. Figure 1 and Figure 2 The dynamically allocable adaptive vector register file in and according to, but not limited to, Figure 4 The exemplary process described herein and any exemplary aspects disclosed herein. In this example, a processor-based system 500 may be configured as an IC 501 and include a dynamically allocable vector register file 502 (such as an adaptive vector register file 104) and may be configured as a system-on-a-chip (SoC) 506. The processor-based system 500 includes a processor 504, which includes one or more processing units (PUs) 510, which may also be referred to as PU cores or processor cores. PU 510 may have a cache memory 512 coupled to PU 510 for fast access to temporarily stored data. PU 510 is coupled to a system bus 514 and may interactively couple master and slave devices included in the processor-based system 500. As is well known, PU 510 communicates with these other devices by exchanging address, control, and data information on the system bus 514. For example, PU 510 may communicate a bus transaction request to a memory controller 516, which is an example of a slave device. Although in Figure 5 Not illustrated, but multiple system buses 514 may be provided, each of which constitutes a different texture.

[0035] Other master and slave devices can be connected to system bus 514. For example... Figure 5 As illustrated, these devices may include a memory system 520, one or more input devices 522, one or more output devices 524, one or more network interface devices 526, and one or more display controllers 528, the memory system including a memory controller 516 and a memory array 518. Each of the memory system 520, one or more input devices 522, one or more output devices 524, one or more network interface devices 526, and one or more display controllers 528 may be located in the same or different electronic devices. Input devices 522 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 524 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 526 may be any device configured to allow data exchange to and from network 530. Network 530 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™Networks and the Internet. Network interface device 526 can be configured to support any type of communication protocol desired.

[0036] PU 510 can also be configured to access display controller 528 via system bus 514 to control information transmitted to one or more displays 532. Display controller 528 transmits information to be displayed to the displays 532 via one or more video processors 534, which process the information to be displayed into a format suitable for the displays 532. As an example, display controller 528 and video processor 534 can be included as ICs in the same or different electronic devices, which include PU 510 and a dynamically assignable vector register file 502. Display 532 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0037] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0038] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0039] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0040] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0041] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0042] Specific implementation examples are described in the following numbered clauses:

[0043] 1. An apparatus, the apparatus comprising:

[0044] Processing unit, the processing unit comprising:

[0045] One or more non-vector processing circuits;

[0046] Vector register file, the vector register file comprising:

[0047] The first part, which is designated for use with the vector register; and

[0048] A queue buffer configured to receive multiple vector instructions;

[0049] The processing unit is configured as follows:

[0050] Determine the vector register requirements for executing the plurality of vector instructions;

[0051] In response to determining that the vector register required for executing the plurality of vector instructions is less than substantially all of the first portion designated for the vector register, a first subset of the first portion designated for the vector register is allocated to the one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for the vector register; and

[0052] Execute the plurality of vector instructions.

[0053] 2. The apparatus according to Clause 1, wherein the processing unit is further configured to, in response to determining that the vector register for executing the plurality of vector instructions requires a supplementary portion designated for the first portion of the vector register:

[0054] The second part of the first subset is reassigned to the vector register.

[0055] 3. The apparatus according to clause 1 or 2, wherein the vector register file further includes a protection region not dedicated to the vector register or the one or more non-vector processing circuits.

[0056] 4. The apparatus according to any one of clauses 1 to 3, wherein the one or more non-vector processing circuits comprise one or more circuits selected from the group consisting of an integer instruction scheduler circuit, a load / store buffer circuit, and a miss buffer circuit.

[0057] 5. The apparatus according to Clause 2, wherein the one or more non-vector processing circuits comprise:

[0058] Buffer circuit missed;

[0059] Load / store buffer circuitry; and

[0060] Integer instruction scheduler circuit,

[0061] The processing unit configured to reallocate the second portion of the first subset to the vector register is further configured to:

[0062] The second portion of the first subset of the missed buffer circuits is reallocated.

[0063] 6. The apparatus according to Clause 2, wherein the one or more non-vector processing circuits comprise:

[0064] Buffer circuit missed;

[0065] Load / store buffer circuitry; and

[0066] Integer instruction scheduler circuit,

[0067] The processing unit configured to reallocate the second portion of the first subset to the vector register is further configured to:

[0068] The second portion of the first subset of the missed buffer circuit and the load / store buffer circuit is reallocated.

[0069] 7. The apparatus according to Clause 2, wherein the one or more non-vector processing circuits comprise:

[0070] Buffer circuit missed;

[0071] Load / store buffer circuitry; and

[0072] Integer instruction scheduler circuit,

[0073] The processing unit configured to reallocate the second portion of the first subset to the vector register is further configured to:

[0074] The second portion of the first subset of the circuits allocated to the miss buffer circuit, the load / store buffer circuit, and the integer instruction scheduler circuit is reallocated.

[0075] 8. The apparatus according to any one of clauses 1 to 7, wherein the apparatus further comprises:

[0076] Integer register file; and

[0077] An integer execution circuit configured to execute integer instructions using the first subset of the first portion and the integer register file.

[0078] 9. The apparatus according to claim 8, further comprising vector execution circuitry configured to execute a vector instruction from the plurality of vector instructions from the queue buffer using the supplementary portion designated for the first portion of the vector register.

[0079] 10. A method for dynamically allocating an adaptive vector register file, the method comprising:

[0080] Assign the first part of the vector register file to the vector register;

[0081] Receive multiple vector commands;

[0082] Determine the vector register requirements for executing the plurality of vector instructions; and

[0083] In response to determining that the vector register required to execute the plurality of vector instructions is less than substantially all of the first portion designated for the vector register, a first subset of the first portion designated for the vector register is allocated to one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for the vector register.

[0084] 11. The method according to Clause 10, the method further comprising, in response to determining that the vector register required for executing the plurality of vector instructions requires a larger portion than the supplementary portion assigned to the first portion of the vector register, reallocating a second portion of the first subset to the vector register.

[0085] 12. The method according to Clause 10 or 11, wherein the vector register file includes a protection region not dedicated to the vector register or the one or more non-vector processing circuits.

[0086] 13. The method according to any one of Clauses 10 to 12, wherein the one or more non-vector processing circuits comprise one or more circuits selected from the group consisting of an integer instruction scheduler circuit, a load / store buffer circuit, and a miss buffer circuit.

[0087] 14. The method according to Clause 11, wherein allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises:

[0088] The first subset of the first portion designated for the first part of the vector register will be allocated to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and

[0089] The reallocation of the second portion of the first subset to the vector register further includes:

[0090] The data space previously allocated to the missed buffer circuit is recaptured.

[0091] 15. The method according to Clause 11, wherein allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises:

[0092] The first subset of the first portion designated for the first part of the vector register will be allocated to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and

[0093] The reallocation of the second portion of the first subset to the vector register further includes:

[0094] The data space previously allocated to the miss buffer circuit and the load / store buffer circuit is recaptured.

[0095] 16. The method according to Clause 11, wherein allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises:

[0096] The first subset of the first portion designated for the vector register will be allocated to the load / store buffer circuit and the integer instruction scheduler circuit; and

[0097] The reallocation of the second portion of the first subset to the vector register further includes:

[0098] The data space previously allocated to the load / store buffer circuit is recaptured.

[0099] 17. The method according to any one of clauses 10 to 16, the method further comprising using the first subset of the first portion and the integer register file to execute integer instructions.

[0100] 18. An apparatus comprising:

[0101] The component used to assign the first part of the vector register file to the vector register;

[0102] A component for determining the vector register requirements for executing multiple vector instructions; and

[0103] In response to determining that the vector register required to execute the plurality of vector instructions is less than substantially all of the first portion designated for the vector register, a first subset of the first portion designated for the vector register is allocated to components of one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for the vector register.

[0104] 19. The apparatus according to Clause 18, further comprising, in response to determining that the vector register for executing the plurality of vector instructions requires a larger portion than the supplementary portion designated for the vector register, a means for reallocating a second portion of the first subset to the vector register.

[0105] 20. The apparatus according to clause 18 or 19, wherein the vector register file includes a protection region not dedicated to the vector register or the one or more non-vector processing circuits.

[0106] 21. The apparatus according to any one of Clauses 18 to 20, wherein the one or more non-vector processing circuits comprise one or more circuits selected from the group consisting of an integer instruction scheduler circuit, a load / store buffer circuit, and a miss buffer circuit.

[0107] 22. The apparatus according to claim 19, wherein the component for allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises:

[0108] Components for allocating the first subset of the first portion designated for the vector register to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and

[0109] The component for reallocating the second portion of the first subset to the vector register further includes:

[0110] A component used to restore the data space previously allocated to the missed buffer circuit.

[0111] 23. The apparatus according to claim 19, wherein the component for allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises:

[0112] Components for allocating the first subset of the first portion designated for the vector register to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and

[0113] The component for reallocating the second portion of the first subset to the vector register further includes:

[0114] A component used to restore the data space previously allocated to the miss buffer circuit and the load / store buffer circuit.

[0115] 24. The apparatus according to claim 19, wherein the component for allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises:

[0116] Components for allocating the first subset of the portion designated for the first part of the vector register to the load / store buffer circuit and the integer instruction scheduler circuit; and

[0117] The component for reallocating the second portion of the first subset to the vector register further includes:

[0118] A component used to restore the data space previously allocated to the load / store buffer circuit.

[0119] 25. The apparatus according to any one of clauses 18 to 24, the apparatus further comprising a component for executing integer instructions using the first subset of the first portion and the integer register file.

Claims

1. An apparatus, the apparatus comprising: Processing unit, the processing unit comprising: One or more non-vector processing circuits; Vector register file, the vector register file comprising: The first part, which is designated for use with the vector register; and A queue buffer configured to receive multiple vector instructions; The processing unit is configured as follows: Determine the vector register requirements for executing the plurality of vector instructions; In response to determining that the vector register required for executing the plurality of vector instructions is less than substantially all of the first portion designated for the vector register, a first subset of the first portion designated for the vector register is allocated to the one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for the vector register; and Execute the plurality of vector instructions.

2. The apparatus of claim 1, wherein the processing unit is further configured to, in response to determining that the vector register for executing the plurality of vector instructions requires a supplementary portion designated for the first portion of the vector register: The second part of the first subset is reassigned to the vector register.

3. The apparatus of claim 1, wherein the vector register file further includes a protection region not dedicated to the vector register or the one or more non-vector processing circuits.

4. The apparatus of claim 1, wherein the one or more non-vector processing circuits comprise one or more circuits selected from the group consisting of an integer instruction scheduler circuit, a load / store buffer circuit, and a miss buffer circuit.

5. The apparatus of claim 2, wherein the one or more non-vector processing circuits comprise: Buffer circuit missed; Load / store buffer circuit; and Integer instruction scheduler circuit, The processing unit configured to reallocate the second portion of the first subset to the vector register is further configured to: The second portion of the first subset of the missed buffer circuits is reallocated.

6. The apparatus of claim 2, wherein the one or more non-vector processing circuits comprise: Buffer circuit missed; Load / store buffer circuit; and Integer instruction scheduler circuit, The processing unit configured to reallocate the second portion of the first subset to the vector register is further configured to: The second portion of the first subset of the missed buffer circuit and the load / store buffer circuit is reallocated.

7. The apparatus of claim 2, wherein the one or more non-vector processing circuits comprise: Buffer circuit missed; Load / store buffer circuit; and Integer instruction scheduler circuit, The processing unit configured to reallocate the second portion of the first subset to the vector register is further configured to: The second portion of the first subset of the circuits allocated to the miss buffer circuit, the load / store buffer circuit, and the integer instruction scheduler circuit is reallocated.

8. The apparatus according to claim 1, further comprising: Integer register file; and An integer execution circuit configured to execute integer instructions using the first subset of the first portion and the integer register file.

9. The apparatus of claim 8, further comprising vector execution circuitry configured to execute a vector instruction from the plurality of vector instructions from the queue buffer using the supplementary portion designated for the first portion of the vector register.

10. A method for dynamically allocating an adaptive vector register file, the method comprising: Assign the first part of the vector register file to the vector register; Receive multiple vector commands; Determine the vector register requirements for executing the plurality of vector instructions; as well as In response to determining that the vector register required to execute the plurality of vector instructions is less than substantially all of the first portion designated for the vector register, a first subset of the first portion designated for the vector register is allocated to one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for the vector register.

11. The method of claim 10, further comprising, in response to determining that the vector register required to execute the plurality of vector instructions requires a larger portion than the supplementary portion assigned to the first portion of the vector register, reallocating a second portion of the first subset to the vector register.

12. The method of claim 10, wherein the vector register file includes a protected region not dedicated to the vector register or the one or more non-vector processing circuits.

13. The method of claim 10, wherein the one or more non-vector processing circuits comprise one or more circuits selected from the group consisting of an integer instruction scheduler circuit, a load / store buffer circuit, and a miss buffer circuit.

14. The method of claim 11, wherein allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises: The first subset of the first portion designated for the vector register will be allocated to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and The reallocation of the second portion of the first subset to the vector register further includes: The data space previously allocated to the missed buffer circuit is recaptured.

15. The method of claim 11, wherein allocating the first subset of the first portion designated for the first part of the vector register to the one or more non-vector processing circuits further comprises: The first subset of the first portion designated for the vector register will be allocated to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and The reallocation of the second portion of the first subset to the vector register further includes: The data space previously allocated to the miss buffer circuit and the load / store buffer circuit is recaptured.

16. The method of claim 11, wherein allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises: The first subset of the first portion designated for the vector register will be allocated to the load / store buffer circuit and the integer instruction scheduler circuit; and The reallocation of the second portion of the first subset to the vector register further includes: The data space previously allocated to the load / store buffer circuit is recaptured.

17. The method of claim 10, further comprising using the first subset of the first portion and the integer register file to execute integer instructions.

18. An apparatus comprising: The component used to assign the first part of the vector register file to the vector register; Components used to determine the vector register requirements for executing multiple vector instructions; and In response to determining that the vector register required to execute the plurality of vector instructions is less than substantially all of the first portion designated for the vector register, a first subset of the first portion designated for the vector register is allocated to components of one or more non-vector processing circuits, thereby leaving a supplementary portion of the first portion designated for the vector register.

19. The apparatus of claim 18, further comprising, in response to determining that the vector register for executing the plurality of vector instructions requires a larger portion than the supplementary portion designated for the vector register, means for reallocating a second portion of the first subset to the vector register.

20. The apparatus of claim 18, wherein the vector register file includes a protection region not dedicated to the vector register or the one or more non-vector processing circuits.

21. The apparatus of claim 18, wherein the one or more non-vector processing circuits comprise one or more circuits selected from the group consisting of an integer instruction scheduler circuit, a load / store buffer circuit, and a miss buffer circuit.

22. The apparatus of claim 19, wherein the component for allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises: Components for allocating the first subset of the first portion designated for the first part of the vector register to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and The component for reallocating the second portion of the first subset to the vector register further includes: A component used to restore the data space previously allocated to the missed buffer circuit.

23. The apparatus of claim 19, wherein the component for allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises: Components for allocating the first subset of the first portion designated for the first part of the vector register to the load / store buffer circuit, the integer instruction scheduler circuit, and the miss buffer circuit; and The component for reallocating the second portion of the first subset to the vector register further includes: A component used to restore the data space previously allocated to the miss buffer circuit and the load / store buffer circuit.

24. The apparatus of claim 19, wherein the component for allocating the first subset of the first portion designated for the vector register to the one or more non-vector processing circuits further comprises: Components for allocating the first subset of the first portion designated for the first part of the vector register to the load / store buffer circuit and the integer instruction scheduler circuit; and The component for reallocating the second portion of the first subset to the vector register further includes: A component used to restore the data space previously allocated to the load / store buffer circuit.

25. The apparatus of claim 18, further comprising a component for executing integer instructions using the first subset of the first portion and the integer register file.

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