Frequency tuning for clock distribution over transmission line

Abstract

Embodiments herein relate to a clock distribution network (CDN) having an adjustable path length, thus having an adjustable resonant frequency. In one method, the CDN includes a first transmission line and a second transmission line to distribute a first differential clock and a second differential clock to one or more data channels. Each transmission line includes a signal conductor and a return conductor. Each data channel may receive a clock signal from a respective tap on a signal conductor of a transmission line. The return conductor includes switching points at different locations along the length of the return conductor, the switching points coupled to respective switches. When the selected switch is closed, the return conductors are short-circuited to each other to reduce their effective length, thereby reducing the resonant frequency of the CDN.

Description

Technical Field

[0001] This application generally relates to the field of clock distribution networks. Background Technology

[0002] Clock distribution networks consist of transmission lines, such as metal traces and vias, used to distribute clock signals to different components of an integrated circuit or chip. Clock signals can be used to synchronize the operation of different circuits on a chip, such as for sending and receiving data. However, various challenges exist in operating clock distribution networks. Attached Figure Description

[0003] The embodiments of this disclosure will be more fully understood through the accompanying drawings, which are given below with reference to the specific embodiments and various examples of this disclosure. However, these drawings should not be construed as limiting this disclosure to the particular embodiments, but are for explanation and understanding only.

[0004] Figure 1A An example clock distribution network (CDN) 100 according to various embodiments is depicted. The CDN 100 includes a first transmission line and a second transmission line with fixed lengths and each data channel has a tap point.

[0005] Figure 1B Depicting various embodiments of the relationship with Figure 1A The CDN is consistent with the example of inverted clock signals clkp and clkn.

[0006] Figure 2 An example CDN 200 according to various embodiments is depicted, the CDN 200 including a first transmission line and a second transmission line of fixed length and each data channel having two tap points.

[0007] Figure 3 The termination at the load resistor Z according to various embodiments is described. L Example lossless transmission line 300 in the example.

[0008] Figure 4 Example lossless transmission lines terminated in a short-circuit manner according to various embodiments are depicted.

[0009] Figure 5 Depicting various embodiments Figure 4 Example curve of clock signal amplitude in a lossless transmission line.

[0010] Figure 6 Depicting similarities according to various embodiments Figure 2 The example CDN is CDN 600, but the return conductor is shortened.

[0011] Figure 7A Depicting similarities according to various embodiments Figure 1A The example CDN is CDN 700, but it provides switches SW1-SW4 to couple the return conductors to each other at different locations.

[0012] Figure 7B Depicting various embodiments Figure 7A The switch SW1 is used as an example implementation of the transmission gate.

[0013] Figure 7C Description of control according to various embodiments Figure 7A Example implementation of the processor and memory for the switch.

[0014] Figure 8 Depicting similarities according to various embodiments Figure 2 The example CDN is CDN 800, but it provides switches to couple return conductors to each other at different locations.

[0015] Figure 9A Example data tables according to various embodiments are depicted, which associate codewords, frequencies, and communication protocols for control purposes. Figure 7A and Figure 8 The CDN switch.

[0016] Figure 9B A flowchart depicts an example process for adjusting the resonant frequency of a CDN according to various embodiments.

[0017] Figure 10 An example transmitter 1000 according to various embodiments is depicted. The transmitter 1000 is used to receive a single-ended clock input, such as from... Figure 7A One of the CDN's tap points 730, 732, 734, and 736.

[0018] Figure 11 An example transmitter 1100 according to various embodiments is depicted for receiving differential clock inputs, such as from... Figure 8 The CDN's tap pairs are 831 and 841, 832 and 842, 833 and 843, and 834 and 844.

[0019] Figure 12 An example receiver 1200 according to various embodiments is depicted, and a transmitter 1100 is used to receive a single-ended clock input, such as from... Figure 7A One of the CDN's tap points 730, 732, 734, and 736.

[0020] Figure 13 An example receiver 1300 according to various embodiments is depicted, the receiver 1300 being used to receive differential clock inputs, such as from... Figure 8The CDN's tap pairs are 831 and 841, 832 and 842, 833 and 843, and 834 and 844.

[0021] Figure 14 Depicting various embodiments Figure 8 Example graph of the CDN's AC response in decibels (dB) compared to frequency.

[0022] Figure 15 Depicting various embodiments Figure 8 Example graph showing the length of the CDN's return path compared to the reciprocal of the frequency.

[0023] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E Various embodiments are described respectively. Figure 8 Example clock waveforms for 16 GHz, 14 GHz, 12 GHz, 10 GHz and 9 GHz clock frequencies in a CDN.

[0024] Figure 17 Examples of components that may exist in computing system 1750 for implementing the techniques described herein (e.g., operations, processes, methods, and methodologies) are shown. Detailed Implementation

[0025] As mentioned earlier, there are various challenges in operating clock distribution networks.

[0026] On-chip transmission lines can achieve high clock speeds with low jitter and reduced power over long distances, but their distribution is limited to a narrow bandwidth due to the inherent resonant frequency of the transmission line. On-chip transmission lines can be fabricated, for example, on the top metal layer of the chip. The resonant frequency is the frequency at which the clock signal can resonate, and it is a function of characteristics such as the transmission line length. Therefore, clocks with frequencies deviating from their bandwidth will experience swing attenuation, duty cycle degradation, and severe distortion due to harmonic effects.

[0027] One approach is to use inductor and capacitor assemblies in the clock distribution network to provide a resonant clock distribution that can be tuned to support a variety of frequencies. However, inductors and capacitors consume area and may reduce the maximum operating frequency capability of the transmission line design.

[0028] Another approach is to provide a transmission line-based clock distribution without requiring tunable inductor and capacitor components. However, such a design can only support multiple frequencies with a relatively narrow bandwidth and separate clock distribution, resulting in a loss of area and power consumption.

[0029] The solution presented in this paper addresses the aforementioned and other drawbacks. In one aspect, a clock distribution network (CDN) with an adjustable resonant frequency is provided. This CDN is referred to as an adjustable or tunable CDN. A CDN may include one or more switches that are controllable to short-circuit the return conductors of the transmission line to each other at different locations along the transmission line length. This effectively reduces the transmission line length and the resonant frequency.

[0030] The frequency tuning process can directly modulate the transmission line length and the corresponding resonant frequency to support a wide frequency range without adding inductor or capacitor components. While the solution presented in this paper allows tuning the resonant frequency of a CDN without adding inductor and / or capacitor components, it is also possible to tune the resonant frequency by including inductor and / or capacitor components in an adjustable CDN.

[0031] These solutions offer numerous advantages. For instance, they enable standing wave clock distributions on transmission lines that are easily tuned to support a wide range of clock frequencies, while also saving area and power consumption. For example, in input / output (I / O) physical layer (PHY) designs, this solution eliminates the need for separate fast and slow clock distributions and facilitates PHY designs where a single phase-locked loop (PLL) is used instead of two when the PLL has a sufficient frequency range.

[0032] In an exemplary embodiment, the CDN has an adjustable path length, and therefore an adjustable resonant frequency. The CDN may include a first transmission line and a second transmission line to distribute a first differential clock and a second differential clock to one or more data channels. Each transmission line includes a signal conductor and a return conductor. Each data channel may receive a clock signal from a corresponding tap on the signal conductor of the transmission line. The return conductor includes switching points at different locations along its length, coupled to corresponding switches. When a selected switch is closed, the return conductors are shorted together to reduce their effective length, thereby lowering the resonant frequency of the CDN.

[0033] These and other characteristics will become more apparent based on the following discussion.

[0034] Figure 1AAn example clock distribution network (CDN) 100 according to various embodiments is depicted. CDN 100 includes a first transmission line and a second transmission line of fixed length, and each data channel has a tap point. A transmission line is a conductive path that may include two parts. The first part of the transmission line is a signal conductor or path that carries a clock signal to one or more tap points on the signal conductor for use by circuitry, such as in one or more data channels. The second part of the transmission line is a return conductor or path. The return conductors of the first and second transmission lines may be coupled to corresponding signal conductors at one end and shorted to each other at the other end. In one approach, the signal conductor and the return conductor have equal lengths, which is half the length of the transmission line.

[0035] In data communication, a data channel can refer to a separate channel or path used to independently transmit data within a wider communication interface or link. Data channels are typically associated with high-speed serial communication interfaces such as PCI Express (PCIe), Universal Serial Bus (USB), and MIPI (Mobile Industrial Processor Interface) used in various electronic devices, such as computers, smartphones, and digital cameras.

[0036] In parallel communication, multiple data channels are used to transmit data simultaneously. In contrast, serial communication uses a single data channel to transmit one bit of data at a time. Furthermore, the data channel can have single-ended inputs, at which it receives a clock signal from one transmission line in the CDN, or the data channel can have differential inputs, at which it receives inverted clock signals from two transmission lines in the CDN. The inverted clock signals or differential clock signals have a 180-degree phase difference. The data channel can include a transmitter and / or receiver using one or more clock signals from the CDN. See, for example, [link to example]. Figures 10-13 .

[0037] CDN 100 includes a first transmission line 110, which includes a first signal conductor 111 (depicted by a solid line) and a first return conductor 112 (depicted by a dashed line). The second transmission line 120 includes a second signal conductor 121 (depicted by a solid line) and a second return conductor 122 (depicted by a dashed line).

[0038] In the first transmission line 110, the first signal conductor 111 is coupled at one end 113 to a first clock source 130 that outputs the clock signal clkn, and at the opposite end 124 to a first return conductor 112. In the second transmission line 120, the second signal conductor 121 is coupled at one end 123 to a second clock source 140 that outputs a clock signal clkp that is inverted (in one method) by clkn, and at the opposite end 125 to a second return conductor 122.

[0039] The first return conductor 112 is also coupled to and shorted to the second return conductor 122 at point 135. In one method, the lengths of the first signal conductor and the second signal conductor, as well as the first return conductor and the second return conductor, can all be the same. Furthermore, in one method, the length of the first signal conductor can be the same as the length of the first return conductor, and the length of the second signal conductor can be the same as the length of the second return conductor. In one method, equal lengths can refer to being equal within a tolerance range of + / - 1-5%.

[0040] For simplicity, the CDN grounding wire is not shown.

[0041] Each signal conductor may include one or more taps where a clock signal is tapped or derived from the signal conductor for use by the circuitry. For example, the first signal conductor 111 includes tap 115 coupled to input path 116 for use by data channel DL1, and tap 117 coupled to input path 118 for use by data channel DL3. The second signal conductor 121 includes tap 126 coupled to input path 127 for use by data channel DL2, and tap 128 coupled to input path 129 for use by data channel DL4. For example, the clock signal on the input path can be used by the transmitter and / or receiver of the data channel. clkn is provided to DL1 and DL3 via taps 115 and 117, respectively, and clkp is provided to DL2 and DL4 via taps 126 and 128, respectively. The input paths are single-ended input paths.

[0042] The common channel (CL) includes the transmission line portion that is not in the data channel. In this example, the signal conductor initially extends in the CL along a first direction (vertical on the page), then turns 90 degrees to the right and extends along a second direction (horizontal on the page), with the tap point located on the signal conductor extending along the second direction. This approach is a ridge configuration because it provides a straight section, or ridge, extending along the second direction for the tap points of different data channels.

[0043] CDNs can be used for high-speed clock distribution in various applications. An example application is the PCIe interface, such as a 64Gbps PCIe 6 interface. PCIe is a high-speed serial computer expansion bus standard. It is a common motherboard interface used for personal computer (PC) graphics cards, sound cards, hard drive host adapters, solid-state drives, Wi-Fi, and Ethernet hardware connections. The clock is driven differentially from a common channel (origin) to four data channels (receivers), where the clock is tapped in alternating single-ended phases. The differential clock return path folds back near the origin at point 135 and shorts, forming a virtual ground. This design can provide a high-speed clock without inductors or capacitors, and the resonant frequency is tuned for operation by adjusting the width and spacing of the conductive paths (including the ground metal). However, once the transmission lines are laid out, the resonant frequency is fixed and cannot be tuned to support a wide frequency range. Therefore, two clock distributions can be implemented, each tuned to individually support a fast or slow clock. Figure 1B Depicting various embodiments of the relationship with Figure 1A The CDN-compliant inverted clock signals clkp and clkn are shown below. The vertical axis represents voltage, and the horizontal axis represents time. Curve 150 (solid line) depicts clkp (positive clock), and curve 151 (dashed line) depicts clkn (negative clock) formed by inverting clkp. The phase shift is 180 degrees, such that clkp is high when clkn is low, and clkp is low when clkn is high.

[0044] Figure 2 An example CDN 200 according to various embodiments is depicted. The CDN 200 includes a first transmission line and a second transmission line of fixed length, and each data channel has two taps. In this example, each data channel receives clkn via one tap and clkp via the other tap. For example, a first signal conductor 111 includes first taps 115, 226, 117, and 228, respectively coupled to first input paths 116, 227, 118, and 229, to provide clkn for use by DL1, DL2, DL3, and DL4, respectively. A second signal conductor 121 includes second taps 215, 126, 217, and 128, respectively coupled to second input paths 216, 127, 218, and 129, to provide clkp for use by DL1, DL2, DL3, and DL4, respectively. Thus, each data channel receives a differential clock input.

[0045] This approach is suitable when the data channel uses differential clocking for data communication. This may involve transmitting data by comparing the voltage levels of two complementary signals with opposite phases, rather than using a single signal and a ground reference, as... Figure 1A This is used for single-ended inputs. This method can improve signal integrity, reduce electromagnetic interference (EMI), and enhance noise immunity. Specifically, the data signal is represented by the voltage difference between two wires or lines. One line carries a positive or high-level signal, while the other line carries a complementary negative or low-level signal.

[0046] In addition to transmitting data, the clock signal can also be transmitted differentially, where the rising edge of the clock is represented by an increase in voltage on one line and a decrease in voltage on another. This helps the receiver accurately detect the clock edge and synchronize with the transmitted data.

[0047] At the receiving end, the differential receiver compares the voltage levels between the positive and negative signals to determine the data state (0 or 1). The differential receiver also uses a differential clock to synchronize with the data stream.

[0048] Figure 3 The termination at load resistor 310 (with impedance Z) according to various embodiments is depicted. L Example lossless transmission line 300 in ( ). The transmission line includes a signal conductor 301 and a return conductor 304, with a voltage drop between nodes 302 and 303. The horizontal axis represents the length "l" of the signal conductor 301 and the return conductor 304 extending away from the load resistor at position 0.

[0049] For simplicity, low-loss transmission lines used for clock distribution can use characteristic impedance Z0 and any load Z. L It is modeled as lossless. In the case of load mismatch, the reflected wave at the load generates a standing wave on the transmission line (the distance between its successive crests and troughs is...). 4‎, where λ is the wavelength). Both the phase velocity and characteristic impedance are independent of frequency, and the wave propagates without dispersion. The waveform has voltage V(z) and current I(z) as functions of impedance. V(z) can be expressed by equation (1), where, It is the reflection coefficient. It is the propagation coefficient, and p It is the phase velocity. Z0, , , λ and p These are represented by equations (2)-(6), respectively. L and C represent the inductance and capacitance per unit length of the transmission line, respectively.

[0050] Figure 4 An example lossless transmission line 400 terminated with a short circuit 410 according to various embodiments is depicted. The transmission line includes a signal conductor 401 and a return conductor 404, wherein there is no voltage drop (V) between nodes 402 and 403.L =0) or impedance (Z) L =0). The horizontal axis represents the distance z that the signal conductor 401 and the return conductor 404 extend away from the load resistor at position 0. V(z) can be represented by equation (7). “l” represents the length of the conductor.

[0051] Figure 5 Depicting various embodiments Figure 4 An example graph of the clock signal amplitude in a lossless transmission line. The vertical axis represents voltage, and the horizontal axis represents distance z. When the transmission line is short-terminated (terminated at one end by a short circuit), the voltage amplitude on the line becomes a sine wave at z=0 and The swing amplitude at position 2 is 0V, and... The maximum amplitude is located at position 4. Furthermore, near the quarter-wavelength position, harmonics of the wave frequency (e.g., 2f, 3f… where f is the frequency) generate voltage troughs or peaks, thus having almost no distortion effect on the clock waveform. Therefore, the voltage peaks and troughs are located at… Odd and even multiples of 4. To operate at different frequencies, when the short-circuit position is fixed, the maximum swing position (indicated by arrow 510) needs to shift with the frequency. Conversely, if the maximum swing position is fixed, the short-circuit position needs to shift with the frequency to maintain a quarter-wavelength distance. Frequency tuning schemes can be designed to utilize the quarter-wavelength rule in the clock distribution.

[0052] The above analysis shows that the resonant frequency can be tuned by modulating the distance between the short-circuit position and the maximum swing position. This method is likely much more effective than adjusting the LC characteristics of the transmission line through metal layers / width / spacing, as the former has very limited adjustment space in practical designs. An example is provided below. Figure 6 Depicting similarities according to various embodiments Figure 2Example CDN 600 is provided, but the return conductor is shortened. CDN 600 includes a first transmission line 610, which includes a first signal conductor 611 (depicted by a solid line) and a first return conductor 612 (depicted by a dashed line). A second transmission line 620 includes a second signal conductor 621 (depicted by a solid line) and a second return conductor 622 (depicted by a dashed line). The first signal conductor 611 includes first taps 615, 676, 617, and 678, respectively, coupled to first input paths 616, 677, 618, and 679, to provide clkn for use by DL1, DL2, DL3, and DL4, respectively. The second signal conductor 621 includes second taps 665, 626, 667, and 628, respectively, coupled to second input paths 666, 627, 668, and 629, to provide clkp for use by DL1, DL2, DL3, and DL4, respectively.

[0053] In the first transmission line 610, the first signal conductor 611 is coupled to the first clock source 130 at one end 613 and to the first return conductor 612 at the opposite end (point 624). In the second transmission line 620, the second signal conductor 621 is coupled to the second clock source 140 at one end 623 and to the second return conductor 622 at the opposite end (point 625).

[0054] The first return conductor 612 is also coupled to and shorted to the second return conductor 622 at point 635. The lengths of the first signal conductor and the second signal conductor (the first length) can be equal, and the lengths of the first return conductor and the second return conductor can be equal but less than the first length. That is, the lengths of the first return conductor and the second return conductor are shorter than the lengths of the first signal conductor and the second signal conductor. The lengths of the first transmission line and the second transmission line can be equal to each other. The length of the first transmission line can be equal to the sum of the lengths of the first signal conductor and the first return conductor, and the length of the second transmission line can be equal to the sum of the lengths of the second signal conductor and the second return conductor.

[0055] This CDN is designed to tune its resonant frequency by adjusting the distance between the short-circuit position (point 635) and the maximum swing position. The short-circuit position is no longer as... Figure 1A or Figure 2 Instead of being located at the clock origin, the frequency is moved to one of the data channels (e.g., DL2) to tune the resonant frequency. The resonant frequency can be chosen to be higher than the operating frequency to account for the four tap points and skew variations, because the near-end data channel DL1 has tap points further from the short-circuit position and a lower resonant frequency compared to the other data channels (DL2-DL4).

[0056] Figure 7A Depicting similarities according to various embodiments Figure 1AThe example CDN 700 includes switches SW1-SW4 to couple return conductors to each other at different locations. CDN 700 includes a first transmission line 710, which includes a first signal conductor 711 (depicted by a solid line) and a first return conductor 712 (depicted by a dashed line). A second transmission line 720 includes a second signal conductor 721 (depicted by a solid line) and a second return conductor 722 (depicted by a dashed line). The first signal conductor 711 includes taps 730 and 734 coupled to corresponding input paths to provide clkn for use by DL1 and DL3, respectively. The second signal conductor 721 includes taps 732 and 736 coupled to corresponding input paths to provide clkp for use by DL2 and DL4, respectively.

[0057] In the first transmission line 710, the first signal conductor 711 is coupled to the first clock source 130 at one end 713 and to the first return conductor 712 at the opposite end (point 724). In the second transmission line 720, the second signal conductor 721 is coupled to the second clock source 140 at one end 723 and to the second return conductor 722 at the opposite end (point 725).

[0058] The first return conductor 712 is also coupled to and shorted to the second return conductor 722 at point 735.

[0059] Each switch is coupled to the first return conductor 712 and the second return conductor 722 at the corresponding switching point of the conductor. For example, SW1 is coupled to the first return conductor 712 at switching point 790 and to the second return conductor 722 at switching point 780. SW2 is coupled to the first return conductor 712 at switching point 791 and to the second return conductor 722 at switching point 781. SW3 is coupled to the first return conductor 712 at switching point 792 and to the second return conductor 722 at switching point 782. SW4 is coupled to the first return conductor 712 at switching point 793 and to the second return conductor 722 at switching point 783. When the switches are open (non-conductive), they do not short-circuit the first return conductor 712 to the second return conductor 722 at the corresponding switching point. When one of the switches is closed (conductive), it short-circuits the first return conductor 712 to the second return conductor 722 at the corresponding switching point.

[0060] Each switch can be controlled to an open or closed position based on a control signal from the processor. See, for example... Figure 7CFor example, SW1, SW2, SW3, and SW4 can be left open by default. When the control signal has the corresponding value, such as en1, en2, en3, or en4 for SW1, SW2, SW3, and SW4 respectively, one of the switches can be selectively closed. The control signal may include one or more digital codewords, such as... Figure 9A As shown, the values ​​of different bits in the codeword indicate whether the corresponding switch should be closed. In another method, each switch receives a separate control signal with a high or low value indicating whether the switch is open or closed. For example, the switch may include one or more transistors. See also Figure 7B .

[0061] In one method, all switches are open, causing the first return conductor 712 to be shorted to the second return conductor 722 at point 735. This is the location of the fixed short circuit. In this case, the return conductor has a length l1. When SW1 is closed, the first return conductor 712 is shorted to the second return conductor 722 at switch points 790 and 780, causing the length of the return conductor to decrease to l2 < l1. When SW2 is closed, the first return conductor 712 is shorted to the second return conductor 722 at switch points 791 and 781, causing the length of the return conductor to decrease to l3 < l2. When SW3 is closed, the first return conductor 712 is shorted to the second return conductor 722 at switch points 792 and 782, causing the length of the return conductor to decrease to l4 < l3. When SW4 is closed, the first return conductor 712 is shorted to the second return conductor 722 at switch points 793 and 783, causing the length of the return conductor to decrease to l5 < l4. The resonant frequency of the clock signal is a function of the length of the return conductor (and therefore a function of the transmission line length). A longer transmission line corresponds to a lower resonant frequency. By allowing the length of the transmission line to be adjusted, the resonant frequency of the clock signal (or generally any periodic signal) on the transmission line can be adjusted. This allows the CDN 700 to be used in different applications, such as for different versions of interfaces using different clock frequencies (e.g., PCIe and USB).

[0062] CDNs are not limited to supporting narrow bandwidths but can be tuned to support a wide range of frequencies. Tuning can be achieved by placing several pass gates or other switches at different locations along the transmission line to enable / disable switching, thereby effectively adjusting the transmission line length. A quarter-wavelength distance can be maintained by adjusting the short-circuit position relative to the tap point. Furthermore, the return path can be further extended in the common channel (CL) to improve support for lower frequencies. See, for example, the section on example CDNs. Figure 8 This example CDN includes a switch in the public channel to provide additional options for adjusting the transmission line length.

[0063] It should be noted that while this example includes two transmission lines to carry the inverted clock signals clkp and clkn, a CDN can also have a single transmission line to provide a single clock signal to one or more data channels.

[0064] It should also be noted that closing the switch does not prevent the use of the data channel, because the short circuit occurs on the return conductor, not on the signal conductor that provides the clock signal to the data channel.

[0065] Figure 7B Depicting various embodiments Figure 7A The switch SW1 is used as an example implementation of a transmission gate. Other switches can be configured similarly. Each switch may include a transmission gate comprising a p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) and a corresponding n-type MOSFET (nMOSFET). Other switch types are also possible. For example, SW1 includes a pMOSFET 761 with a control gate coupled to a signal en1_b and an nMOSFET 763 with a control gate coupled to a control signal en1, where en1_b is the inverted signal of en1. When en1 is high and en1_b is low, the transmission gate is turned on, causing switch point 790 to couple to switch point 780. Therefore, return conductors 712 and 722 are coupled to provide a short circuit. When en1 is low and en1_b is high, the transmission gate is not turned on, causing switch point 790 to not couple to switch point 780. Therefore, return conductors 712 and 722 are not coupled through SW1.

[0066] Figure 7C Description of control according to various embodiments Figure 7A An example implementation of a processor and memory for a switch. Processor 770 (including, for example, a controller or other control circuitry) can communicate with memory 771, which stores instructions 772 to be executed by the processor. Instructions can access, for example... Figure 9A The data table shown determines the value of the control signal to control the corresponding switch.

[0067] Figure 8 Depicting similarities according to various embodiments Figure 2This is an example CDN 800, but it includes switches to couple return conductors to each other at different locations. CDN 800 includes a first transmission line 810, which includes a first signal conductor 811 (depicted by a solid line) and a first return conductor 812 (depicted by a dashed line). A second transmission line 820 includes a second signal conductor 821 (depicted by a solid line) and a second return conductor 822 (depicted by a dashed line). The first signal conductor 811 includes first taps 841, 842, 843, and 844 coupled to corresponding first input paths to provide clkn for use by DL1, DL2, DL3, and DL4, respectively. The second signal conductor 821 includes second taps 831, 832, 833, and 834 coupled to corresponding second input paths to provide clkp for use by DL1, DL2, DL3, and DL4, respectively.

[0068] In the first transmission line 810, the first signal conductor 811 is coupled to the first clock source 130 at one end 813 and to the first return conductor 812 at the opposite end (point 824). In the second transmission line 820, the second signal conductor 821 is coupled to the second clock source 140 at one end 823 and to the second return conductor 822 at the opposite end (point 825).

[0069] The first return conductor 812 is also coupled to and shorted to the second return conductor 822 at point 835. Return conductors 812 and 822 are rotated or folded 180 degrees at points 871 and 872, respectively. This helps to provide a more compact layout.

[0070] Each switch is coupled to a first return conductor 812 and a second return conductor 822 at a corresponding switching point on the conductor. For example, SW1 is coupled to the first return conductor 812 at switching point 851 and to the second return conductor 822 at switching point 881. SW2 is coupled to the first return conductor 812 at switching point 852 and to the second return conductor 822 at switching point 882. SW3 is coupled to the first return conductor 812 at switching point 853 and to the second return conductor 822 at switching point 883. SW4 is coupled to the first return conductor 812 at switching point 854 and to the second return conductor 822 at switching point 884.

[0071] As previously described, each switch SW1-SW4 can be controlled to an open or closed position based on a control signal from the processor. These switches are located in the data channel. In the common channel, an additional switch SW0 is located near the corresponding ends 813 and 823 of the first signal conductor 811 and the second signal conductor 821. SW0 can also be selectively opened or closed by a control signal having a corresponding value (e.g., en0). This additional switch provides greater flexibility in adjusting the length of the transmission line.

[0072] In this example, the first return conductor 812 splits into a first branch 877 and a second branch 875 at point 871, and the second return conductor 822 splits into a first branch 878 and a second branch 876 at point 872. The first branch 877 of the first return conductor is shorted to the first branch 878 of the second return conductor at point 835 (e.g., a permanent no-switch short circuit), and the second branch 875 of the first return conductor is coupled to the second branch 876 of the second return conductor via a corresponding switch SW0. Furthermore, the length of the first branch of the first return conductor is different from the length of the second branch of the first return conductor, and the length of the first branch of the second return conductor is different from the length of the second branch of the second return conductor. The lengths of the first and second branches of the first and second return conductors can be equal, and the lengths of the first and second branches of the first and second return conductors can be equal. In this example, the length of the first branch (e.g., from point 871 to point 835 and from point 872 to point 835) is greater than the length of the second branch (e.g., from point 871 to switch SW0 and from point 872 to switch SW0).

[0073] The CDN also includes example grounding conductors 873 and 874.

[0074] Figure 9A Example data tables according to various embodiments are depicted, which associate codewords, frequencies, and communication protocols for control purposes. Figure 7A and Figure 8 The CDN switches. As mentioned above, the processor can provide control signals to the switches, indicating whether each switch should be open or closed. In some cases, all switches are open, making the fixed short circuit between the return conductors effective; in other cases, selected switches are closed while the rest are open, thus providing a new short circuit between the return conductors.

[0075] The first, second, and third columns represent the five-bit codeword, frequencies f1-f6, and communication protocols P1-P6, respectively. For example, the codeword 1xxxx corresponds to f1 and P1 (x represents bit 0 or 1), the codeword 01xxx corresponds to f2 and P2, the codeword 001xx corresponds to f3 and P3, the codeword 0001x corresponds to f4 and P4, the codeword 00001 corresponds to f5 and P5, and the codeword 00000 corresponds to f6 and P6. For example, P1-P6 represent multiple available communication protocols for the computing device. The codewords 1xxxx, 01xxx, 001xx, 0001x, and 00001 can correspond to the enable signals en4, en3, en2, en1, and en0, respectively, to close switches SW4, SW3, SW2, SW1, and SW0, or... Figure 8 The CDN 800 code 00000 disconnects all switches.

[0076] In one example, the communication protocol is a different version of PCIe (e.g., version 1.x, 2.x, 3.x, 4.0, 5.0, 6.0, or 7.0) or USB (e.g., version 1.0x, 2.0, 3.x, or 4). Other protocols are also possible.

[0077] Processors or other control circuitry can determine the communication protocol of the transmitter or receiver of a data channel in various ways. For example, when a peripheral device is connected to a computer or other host system via a USB connection, the USB controller and USB driver on the host system play a role in determining the device's USB version. When physically connected, a USB device undergoes an enumeration process, during which the device communicates with the host system's USB controller to negotiate its capabilities and establish a connection. This includes identifying the device's USB version. USB devices also contain descriptors that provide information about the device's capabilities, including its USB version. The host system reads these descriptors during enumeration to determine the USB versions supported by the device.

[0078] For PCIe, the motherboard of a computing device contains PCIe slots and connectors that support a specific version of PCIe. These slots are physically designed to accommodate PCIe cards and devices of a specific generation / version. PCIe cards (e.g., graphics cards, network adapters, and storage controllers) are designed to operate under a specific PCIe version. This information is encoded in the card's own hardware, indicating the maximum PCIe version that the card can use. When a PCIe card is inserted into a PCIe slot on the motherboard, a negotiation process is performed to determine the highest general-purpose PCIe version supported by the motherboard slot and the card. This negotiation is automatic and is part of the PCIe standard. Some motherboards allow users to configure PCIe settings in the Basic Input / Output System (BIOS) / Unified Extensible Firmware Interface (UEFI) firmware. These settings are typically related to the PCIe link speed (e.g., 1x, 2x, 4x, 8x, 16x) rather than the actual PCIe version.

[0079] The adjustable CDN provided in this article can be advantageously and automatically adjusted to adapt to different versions of USB and PCIe devices.

[0080] Figure 9BA flowchart illustrating an example process for adjusting the resonant frequency of a CDN according to various embodiments is provided. Operation 901 includes determining the communication protocol of the transmitter or receiver. For example, as mentioned above, this may involve a negotiation process. Operation 902 includes adjusting the lengths of a first transmission line and a second transmission line of the CDN based on the communication protocol. Operation 903 indicates that this may involve selecting a switch among a plurality of switches closed at different locations along the first and second transmission lines. For example, this may involve... Figure 9A Example table.

[0081] Figure 10 An example transmitter 1000 according to various embodiments is depicted for receiving a single-ended clock input, such as from... Figure 7A The data path can be one of taps 730, 732, 734, and 736 in the CDN. As mentioned above, the data path can have a single-ended input at which it receives a clock signal from a transmission line in the CDN. The data path can include a transmitter and / or receiver that uses a clock signal from the CDN. In this example, transmitter (Tx) 1000 uses a clock signal to transmit data to receiver (Rx) 1002 on path 1001. The transmission can be synchronous data transmission, where the data transmission is synchronized with a common clock signal generated by the transmitter and used by both the transmitter and the receiver. This ensures that the two devices are synchronized and ready to receive or transmit data simultaneously.

[0082] Figure 11 An example transmitter 1100 according to various embodiments is depicted for receiving differential clock inputs, such as from... Figure 8 The CDN uses tap pairs 831 and 841, 832 and 842, 833 and 843, and 834 and 844. In this example, the transmitter (Tx) uses clock signals to transmit data to the receiver (Rx) 1103 on paths 1101 and 1102. Here, the data path has differential inputs, at which it receives inverted clock signals clkp and clkn from two transmission lines in the CDN. The inverted clock signals, or differential clock signals, have a 180-degree phase difference. This type of transmission involves transmitting data by comparing the voltage levels of complementary signals with opposite phases, rather than using a single signal and a ground reference.

[0083] Figure 12 An example receiver 1200 according to various embodiments is depicted for receiving a single-ended clock input, such as from... Figure 7A One of the taps 730, 732, 734, and 736 in the CDN. In this example, receiver 1200 uses a clock signal to receive data transmitted by transmitter 1202 on path 1201.

[0084] Figure 13 An example receiver 1300 according to various embodiments is depicted for receiving differential clock inputs, such as from... Figure 8 The CDN uses one of the following tap pairs: 831 and 841, 832 and 842, 833 and 843, and 834 and 844. In this example, receiver 1300 uses a clock signal to receive data transmitted by transmitter 1303 on paths 1301 and 1302.

[0085] Figure 14 Depicting various embodiments Figure 8 Example graphs of the AC response of a CDN, expressed in decibels (dB), compared to frequency. The graphs show the simulated AC response of an adjustable CDN and a relatively fixed CDN, which allows for frequency tuning using switches. In the simulation, the transmission gates have an equivalent resistance of 10 ohms. The transition resonant frequency (peak frequency) is evident across various settings. For example, in the adjustable CDN, curve 1400 corresponds to f=12.7 GHz and 5.08 dB, curve 1401 corresponds to f=13.8 GHz and 5.11 dB, curve 1402 corresponds to f=16.0 GHz and 5.18 dB, curve 1404 corresponds to f=18.6 GHz and 4.58 dB, curve 1405 corresponds to f=21.6 GHz and 3.39 dB, and curve 1406 corresponds to f=25.7 GHz and 3.04 dB.

[0086] Compared to a fixed design, the adjustable CDN exhibits a slightly lower peak amplitude due to the transmission gate resistance, but the peak frequency remains essentially unchanged. For example, at f=18.6 GHz, the AC response of the adjustable CDN (curve 1404) of 4.58 dB is compared with that of the fixed CDN (curve 1403) of 5.0 dB.

[0087] Figure 15 Depicting various embodiments Figure 8 An example graph comparing the length of the return path of a CDN to the reciprocal of its frequency. The length of the return path (e.g., the return conductor of a transmission line) is plotted against the reciprocal of the simulated peak frequency. The scaling relationship validates the wavelength model from the transmission line analysis with short terminations. This graph is a linear fit to the data points represented by circles.

[0088] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E Various embodiments are described respectively. Figure 8Example clock waveforms at clock frequencies of 16 GHz, 14 GHz, 12 GHz, 10 GHz, and 9 GHz in the CDN are shown. The graphs depict the voltage versus time relationship of a single clock pulse, comparing the adjustable CDN to a fixed CDN tuned to operate at 16 GHz. Figure 16A Curves 1600 and 1601 for the adjustable CDN and fixed CDN at a clock frequency of 16 GHz are plotted respectively. Figure 16B Curves 1610 and 1611 for the adjustable CDN and fixed CDN at a clock frequency of 14 GHz are plotted respectively. Figure 16C Curves 1620 and 1621 for adjustable CDN and fixed CDN at a clock frequency of 12 GHz are plotted respectively. Figure 16D Curves 1630 and 1631 for adjustable CDN and fixed CDN at a clock frequency of 10 GHz are plotted respectively. Figure 16E Curves 1640 and 1641 for adjustable CDN and fixed CDN at a clock frequency of 9 GHz are plotted respectively.

[0089] Therefore, the simulated transient clock waveform has a frequency that varies between approximately 9 GHz and 16 GHz. Fixed CDN designs (tuned for operation at 16 GHz) exhibit some distortion and swing reduction when used for clocks from 9 GHz to 14 GHz due to the fixed resonant frequency and harmonic distortion (curves 1611, 1621, 1631, and 1641). In contrast, adjustable CDNs reduce or eliminate distortion while also improving the swing of the clock waveform from 9 GHz to 14 GHz (curves 1610, 1620, 1630, and 1640).

[0090] Specifically, for a clock frequency of 16 GHz, the swing change of the adjustable CDN compared to the fixed CDN is -7.4%, and the worst deterministic jitter (DJ) change is -12%. For a clock frequency of 14 GHz, the swing change of the adjustable CDN compared to the fixed CDN is +2.4%, and the worst DJ change is -36%. For a clock frequency of 12 GHz, the swing change of the adjustable CDN compared to the fixed CDN is +9.4%, and the worst DJ change is -91%. For a clock frequency of 10 GHz, the swing change of the adjustable CDN compared to the fixed CDN is +18%, and the worst DJ change is -80%. For a clock frequency of 9 GHz, the swing change of the adjustable CDN compared to the fixed CDN is +29%, and the worst DJ change is -74%.

[0091] In this example, the adjustable CDN thus improves the operational bandwidth from, for example, 2 GHz (14 GHz to 16 GHz) to 7 GHz (9 GHz to 16 GHz).

[0092] The swing amplitude is taken from the average value of four taps at a typical process corner, while the DJ value is taken from the worst value among the four taps at typical / fast / slow process corners.

[0093] Figure 17 Examples of components that may exist in computing system 1750 for implementing the techniques described herein (e.g., operations, processes, methods, and methodologies) are shown. Voltage regulator 1700 may provide voltage Vout to one or more components of computing system 1750. Clock circuitry 1790 may include the clock distribution network discussed herein, including... Figure 7A and Figure 8 Those shown in the diagram. Memory circuitry 1754 can store instructions, and processor circuitry 1752 can execute instructions to perform the functions described herein.

[0094] Computing system 1750 may include any combination of the hardware or logic components referenced herein. These components may be implemented as an IC, portions thereof, discrete electronic devices or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or combinations thereof suitable for computing system 1750, or may be implemented as components otherwise incorporated into a larger system chassis. In one embodiment, at least one processor 1752 may be packaged together with computing logic 1782 and configured to practice aspects of the various example embodiments described herein to form a system-in-package (SiP) or system-on-a-chip (SoC).

[0095] System 1750 includes processor circuitry in the form of one or more processors 1752. Processor circuitry 1752 includes circuitry such as, but not limited to, one or more processor cores and one or more of the following: cache, low-dropout regulator (LDO), interrupt controller, serial interface (e.g., SPI, I2C, or general-purpose programmable serial interface circuitry), real-time clock (RTC), timer counters including interval and watchdog timers, general-purpose I / O, memory card controller (e.g., Secure Digital / Multimedia Card (SD / MMC) or the like), interface, Mobile Industrial Processor Interface (MIPI) interface, and Joint Test Access Group (JTAG) test access port. In some implementations, processor circuitry 1752 may include one or more hardware accelerators (e.g., the same as or similar to accelerator circuitry 1764), which may be microprocessors, programmable processing devices (e.g., FPGAs, ASICs, etc.), etc. One or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, processor circuitry 1752 may include on-chip memory circuitry, which may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0096] Processor circuitry 1752 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing element, or any suitable combination thereof. Processor (or core) 1752 may be coupled to or may include a memory / storage device and may be configured to execute instructions stored in the memory / storage device to enable various applications or an operating system running on platform 1750. Processor (or core) 1752 is configured to operate application software to provide specific services to users of platform 1750. In some embodiments, processor(s) 1752 may be one or more dedicated processors / controllers configured (or configurable) to operate according to various embodiments herein.

[0097] As an example, processor(s) 1752 may include: Intel® Architecture Core™ based processors, such as i3, i5, i7, i9 based processors; Intel® microcontroller based processors, such as Quark™, ​​Atom™, or other MCU-based processors; or one or more Pentium® processors, one or more Xeon® processors, or other such processors available from Intel® Inc. in Santa Clara, California. However, any number of other processors may be used, such as one or more of the following: AMD Zen® architecture, such as one or more Ryzen® or EPYC® processors, Accelerated Processing Units (APUs), MxGPUs, one or more EPYC® processors, etc.; one or more A5-A12 and / or S1-S4 processors from Apple®, one or more Snapdragon™ or Centriq™ processors from Qualcomm® Technologie, one or more Open Multimedia Application Platform (OMAP™) processors from Texas Instruments®; MIPS-based designs from MIPS Technologies, such as MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holding, such as ARM Cortex-A, Cortex-R, and Cortex-M series processors; ThunderX2® from Cavium™, etc. In some implementations, the processor(s) 1752 may be part of a system-on-a-chip (SoC), a system-in-package (SiP), a multi-chip package (MCP), etc., where the processor(s) 1752 and other components are formed as a single integrated circuit or a single package, such as an Intel® Edison™ or Galileo™ SoC board. Other examples of the processor(s) 1752 are mentioned elsewhere in this disclosure.

[0098] System 1750 may include or be coupled to acceleration circuitry 1764, which may be embodied by: one or more AI / ML accelerators, neural computation sticks, neuromorphic hardware, FPGAs, GPU arrays, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, application-specific integrated circuits (including programmable ASICs), PLDs (e.g., complex PLDs (CPLDs) or high-complexity PLDs (HCPLDs)) and / or other forms of dedicated processors or circuitry designed to perform one or more dedicated tasks. These tasks may include AI / ML processing (e.g., including training, inference, and classification operations), visual data processing, network data processing, object detection, rule analysis, etc. In an FPGA-based implementation, acceleration circuitry 1764 may include logic blocks or logic structures and other interconnect resources that can be programmed (configured) to perform various functions, such as the processes, methods, functions, etc., of the various embodiments discussed herein. In such an implementation, the acceleration circuit 1764 may also include memory cells (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.)) for storing logic blocks, logic structures, data, etc. in the LUT, etc.

[0099] In some implementations, processor circuitry 1752 and / or acceleration circuitry 1764 may include hardware elements specifically tailored for machine learning and / or artificial intelligence (AI) functions. In these implementations, processor circuitry 1752 and / or acceleration circuitry 1764 may be or may include an AI engine chip that, once loaded with appropriate weights and training code, can run many different types of AI instruction sets. Alternatively or concurrently, processor circuitry 1752 and / or acceleration circuitry 1764 may be or may include one or more AI accelerators, which may be one or more of the aforementioned hardware accelerators designed for hardware acceleration of AI applications. For example, one or more of these processors or accelerators may be: an artificial intelligence (AI) GPU cluster, a tensor processing unit (TPU) developed by Google®, a Rayleigh AI processor (RAPs™) provided by AlphaIC®, a Nervana™ neural network processor (NNP) provided by Intel®, an Intel® Movidius™ Myriad™ X vision processing unit (VPU), an NVIDIA® PX™-based GPU, an NM500 chip provided by General Vision®, a Hardware 3 provided by Tesla®, an Epiphany™-based processor provided by Adapteva®, etc. In some embodiments, the processor circuitry 1752 and / or the acceleration circuitry 1764 and / or the hardware accelerator circuitry may be implemented as one or more AI acceleration coprocessors, such as the Hexagon 685 DSP provided by Qualcomm®, the PowerVR 2NX neural network accelerator (NNA) provided by Imagination Technologies Limited®, the Neural Engine core in the Apple® A11 or A12 Bionic SoC, the Neural Processing Unit (NPU) in the HiSilicon Kirin 1770 provided by Huawei®, etc. In some hardware-based implementations, the various subsystems of system 1750 can be operated by the following items: corresponding AI acceleration coprocessors (one or more), AI GPUs, TPUs or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), which are configured with appropriate logic blocks, bit streams (one or more) to perform their respective functions.

[0100] System 1750 also includes system memory 1754. Any number of memory devices can be used to provide a fixed amount of system memory. As an example, memory 1754 may be or include volatile memory, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other desired type of volatile memory device. Alternatively or concurrently, memory 1754 may be or include non-volatile memory, such as read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, non-volatile RAM, ferroelectric RAM, phase-change memory (PCM), and / or any other desired type of non-volatile memory device. Access to memory 1754 is controlled by a memory controller. The individual memory devices can be any number of different package types, such as a single-die package (SDP), a dual-die package (DDP), or a quad-die package (Q17P). Any number of other memory implementations can be used, such as different kinds of dual in-line memory modules (DIMMs), including but not limited to microDIMMs or miniDIMMs.

[0101] Storage device circuitry 1758 provides persistent storage for information such as data, applications, and operating systems. In one example, storage device circuitry 1758 may be implemented via a solid-state drive (SSDD) and / or high-speed electrically erasable memory (commonly referred to as "flash memory"). Other devices that can be used with storage device circuitry 1758 include flash memory cards, such as SD cards, microSD cards, XD picture cards, etc., as well as USB flash drives. In one example, the memory device may be or may include memory devices using the following: chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase-change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) incorporating memristor technology, phase-change RAM (PRAM), resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), or spin-transfer torque (STT)-MRAM, spintronic junction-based devices, magnetic tunnel junction (MTJ-based devices, domain wall (DW) and spin-orbit torque (SOT)-based devices, thyristor-based memory devices, hard disk drives (HDDs), micro HDDs, combinations of the above and / or any other memory. Memory circuitry 1754 and / or storage device circuitry 1758 may also include three-dimensional (3D) crosspoint (XPOINT) memory from Intel® and Micron®.

[0102] Memory circuitry 1754 and / or storage device circuitry 1758 are configured to store computational logic 1783 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. Computational logic 1783 can be used to store working copies and / or persistent copies of programming instructions or data for creating programming instructions for use by various components of system 1750 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of system 1750, the operation of one or more applications, and / or for performing the embodiments discussed herein. Computational logic 1783 can be stored as instruction 1782 or as data that creates instruction 1782, or loaded into memory circuitry 1754, and then accessed by processor circuitry 1752 to perform the functions described herein. Processor circuitry 1752 and / or acceleration circuitry 1764 access memory circuitry 1754 and / or storage device circuitry 1758 via interconnect (IX) 1756. Instruction 1782 directs processor circuitry 1752 to execute a specific sequence or flow of actions, such as those described in one or more flowcharts and block diagrams of the operations and functions previously described. Various elements can be implemented by assembly instructions or a high-level language (which can be compiled into instruction 1488 or data that creates instruction 1488) supported by processor circuitry 1752 for execution by processor circuitry 1452. A persistent copy of the programming instructions can be placed in the persistent storage device of storage device circuitry 1458 at the factory or in the field via: for example, a distribution medium (not shown), a communication interface (e.g., from a distribution server (not shown)), over-the-air (OTA) download, or any combination thereof.

[0103] IX 1756 couples processor 1752 to communication circuitry 1766 for communication with other devices, such as a remote server (not shown). Communication circuitry 1766 is a hardware element or collection of hardware elements for communicating via one or more networks 1763 and / or with other devices. In one example, communication circuitry 1766 is or includes transceiver circuitry configured to implement wireless communication using any number of frequencies and protocols, such as IEEE 802.11 (and / or variations thereof), IEEE 802.23.4, Bluetooth® and / or Bluetooth® Low Energy (BLE), ZigBee®, LoRaWAN™ (Long Range Wide Area Network), cellular protocols (e.g., 3GPP LTE and / or 5G / New Radio (NR)), etc. Alternatively, the communication circuit 1766 is or includes one or more network interface controllers (NICs) to enable wired communication using, for example, Ethernet connections, controller area networks (CAN), local area networks (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET.

[0104] The IX 1756 also couples processor 1752 to interface circuitry 1770, which connects system 1750 to one or more external devices 1772. External devices 1772 may include, for example, sensors, actuators, positioning circuitry (e.g., Global Navigation Satellite System (GNSS) / Global Positioning System (GPS) circuitry), client devices, servers, network devices (e.g., switches, hubs, routers, etc.), integrated photonic devices (e.g., optical neural network (ONN) integrated circuits (ICs), etc.) and / or other similar devices.

[0105] In some alternative examples, various input / output (I / O) devices may exist within or be connected to system 1750; these devices are referred to as input circuitry 1786 and output circuitry 1784. Input circuitry 1786 and output circuitry 1784 include one or more user interfaces designed to enable users to interact with platform 1750 and / or peripheral component interfaces designed to facilitate interaction between peripheral components and platform 1750. Input circuitry 1786 may include any physical or virtual device for accepting input, including one or more physical or virtual buttons (e.g., a reset button), a physical keyboard, keypad, mouse, touchpad, touchscreen, microphone, scanner, headphones, etc. Output circuitry 1784 may be included to display or otherwise convey information, such as sensor readings, actuator(s) position, or other similar information. Data and / or graphics may be displayed on one or more user interface components of output circuitry 1784. Output circuitry 1784 may include any number and / or combination of audio or visual displays, including one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light-emitting diodes (LEDs)) and multi-character visual outputs), or more complex outputs (e.g., display devices or touchscreens (e.g., liquid crystal displays (LCDs), LED displays, quantum dot displays, projectors, etc.)), wherein the output of characters, graphics, multimedia objects, etc., is generated or produced by the operation of platform 1450. Output circuitry 1484 may also include speakers and / or other audio emitting devices, one or more printers, etc. Additionally or alternatively, one or more sensors may be used as input circuitry 1484 (e.g., image collecting devices, motion collecting devices, etc.), and one or more actuators may be used as output device circuitry 1784 (e.g., actuators providing haptic feedback, etc.). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power interfaces, etc. In some embodiments, within the context of this system, the display or console hardware may be used to provide outputs from the edge computing system and receive inputs from the edge computing system; manage components or services of the edge computing system; identify the status of edge computing components or services; or perform any other number of management or operational functions or service use cases.

[0106] Components of the System 1750 can communicate via the IX 1756. The IX 1756 can include any number of technologies, including ISA, Extended ISA, I2C, SPI, Point-to-Point Interface, Power Management Bus (PMBus), PCI, PCIe, PCIx, Intel® UPI, Intel® Accelerator Link, Intel® CXL, CAPI, OpenCAPI, Intel® QPI, UPI, Intel® OPA IX, RapidIO™ System IX, CCIX, Gen-Z Alliance IX, HyperTransport Interconnect, NVIDIA® NVLink, Time Triggered Protocol (TTP) Systems, FlexRay Systems, PROFIBUS, and / or any number of other IX technologies. The IX 1756 can be a proprietary bus, for example, for use in SoC-based systems.

[0107] The number, capabilities, and / or capacity of the components in system 1750 may vary depending on whether computing system 1750 is used as a fixed computing device (e.g., a server computer, workstation, desktop computer, etc. in a data center) or a mobile computing device (e.g., a smartphone, tablet computing device, laptop computer, game console, IoT device, etc.). In various implementations, computing device system 1450 may include one or more components of the following: data center, desktop computer, workstation, laptop computer, smartphone, tablet computer, digital camera, smart appliance, smart home hub, network device, and / or any other device / system for processing data.

[0108] The techniques described herein can be executed, in whole or in part, by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions for implementing any other processes discussed herein). Instructions associated with and executed to implement embodiments of the disclosed subject matter, and performed in accordance with flowcharts (and / or various embodiments), can be implemented as part of an operating system or a particular application, component, program, object, module, routine, or other sequence or organization of instructions.

[0109] Storage media can be tangible, non-transitory machine-readable media, such as read-only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., optical disc read-only memory (CD ROM), digital versatile disk (DVD)), etc.

[0110] Storage media can be included in, for example, communication devices, computing devices, network devices, personal digital assistants, manufacturing tools, mobile communication devices, cellular phones, laptops, tablets, game consoles, set-top boxes, embedded systems, televisions (TVs), or personal desktop computers.

[0111] The following are some non-limiting examples of various embodiments.

[0112] Example 1 includes an apparatus comprising: a first transmission line including a first signal conductor and a first return conductor, wherein the first signal conductor is coupled to a first clock source and includes one or more taps, and the first return conductor includes one or more switching points; a second transmission line including a second signal conductor and a second return conductor, wherein the second signal conductor is coupled to a second clock source and includes one or more taps, and the second return conductor includes one or more switching points; and one or more switches coupled to one or more switching points of the first return conductor and one or more switching points of the second return conductor.

[0113] Example 2 includes the apparatus of Example 1, wherein the resonant frequency of the first transmission line can be adjusted based on which of the one or more switches is closed.

[0114] Example 3 includes the apparatus of Example 1 or 2, wherein: one or more taps of the first signal conductor include taps for an input path of a first data channel; and one or more taps of the second signal conductor include taps for an input path of a second data channel.

[0115] Example 4 includes an apparatus of any one of Examples 1-3, wherein: one or more taps of the first signal conductor include taps for a first input path of the first data channel; and one or more taps of the second signal conductor include taps for a second input path of the first data channel.

[0116] Example 5 includes the apparatus of Example 1, wherein one end of the first return conductor is shorted to one end of the second return conductor.

[0117] Example 6 includes an apparatus of any one of Examples 1-5, wherein: one or more switching points of the first return conductor include a plurality of switching points at different locations along the first return conductor; one or more switching points of the second return conductor include a plurality of switching points at different locations along the second return conductor; and each switching point of the first return conductor is coupled to a corresponding switching point of the second return conductor via a corresponding switch of the one or more switches.

[0118] Example 7 includes the apparatus of Example 6, wherein the lengths of the first return conductor and the second return conductor are adjustable based on which of the one or more switches is closed.

[0119] Example 8 includes an apparatus of any one of Examples 1-7, wherein: the first return conductor is divided into a first branch and a second branch; the second return conductor is divided into a first branch and a second branch; the first branch of the first return conductor is shorted to the first branch of the second return conductor; and the second branch of the first return conductor is coupled to the second branch of the second return conductor via a corresponding switch.

[0120] Example 9 includes the apparatus of Example 8, wherein the length of the first branch of the first return conductor is different from the length of the second branch of the first return conductor.

[0121] Example 10 includes an apparatus of any one of Examples 1-9, and further includes at least one of an integrated circuit, a system-on-a-chip, a system-in-package, or a computing device, wherein the first transmission line, the second transmission line, and the one or more switches are provided in the at least one, wherein the computing device includes at least one of a processor circuit, a memory circuit, a storage device circuit, an acceleration circuit, a communication circuit, an input circuit, an output circuit, an interface circuit, or an external device.

[0122] Example 11 includes an apparatus comprising: a memory for storing instructions; and a processor coupled to the memory, wherein the processor executes the instructions to: determine a communication protocol for a transmitter; and, based on the communication protocol, adjust the lengths of a first transmission line and a second transmission line of a clock distribution network, wherein the transmitter is coupled to at least one of the first or second transmission line to receive a clock signal having a clock frequency corresponding to the communication protocol.

[0123] Example 12 includes the apparatus of Example 11, wherein the adjusted lengths of the first transmission line and the adjusted lengths of the second transmission line are used to provide a resonant frequency of the clock distribution network corresponding to the clock frequency.

[0124] Example 13 includes the apparatus of Example 11 or 12, wherein: a plurality of switches are coupled to the first transmission line and the second transmission line at different locations along the first transmission line and the second transmission line; and in order to adjust the length of the first transmission line and the second transmission line, the processor closes a selected switch among the plurality of switches based on the communication protocol.

[0125] Example 14 includes the apparatus of Example 13, wherein the communication protocol of the transmitter is determined from a plurality of available communication protocols, and each communication protocol corresponds to an identifier of a corresponding switch among the plurality of switches.

[0126] Example 15 includes the apparatus of Example 14, wherein the plurality of available communication protocols include at least one of different versions of Fast Peripheral Component Interconnect (PCIe) or different versions of Universal Serial Bus (USB).

[0127] Example 16 includes a clock distribution network comprising: a first transmission line coupled to a first clock source and including one or more taps; a second transmission line coupled to a second clock source and including one or more taps; and a plurality of switches, wherein each of the plurality of switches is coupled to the first transmission line and the second transmission line to short the first transmission line to the second transmission line at a corresponding location along the first transmission line and the second transmission line.

[0128] Example 17 includes the clock distribution network of Example 16, wherein each of the plurality of switches is coupled to the return conductor of the first transmission line and the return conductor of the second transmission line.

[0129] Example 18 includes the clock distribution network of Example 16 or 17, wherein the lengths of the first transmission line and the second transmission line are adjustable depending on which of the plurality of switches is closed.

[0130] Example 19 includes a clock distribution network of any of Examples 16-18, wherein the resonant frequencies of the first transmission line and the second transmission line are adjustable depending on which of the plurality of switches is closed.

[0131] Example 20 includes a clock distribution network of any of Examples 16-19, wherein the clock signal of the first clock source is the inverted signal of the clock signal of the second clock source.

[0132] Example 21 includes a method comprising: determining a communication protocol for a transmitter; and adjusting the lengths of a first transmission line and a second transmission line of a clock distribution network based on the communication protocol, wherein the transmitter is coupled to at least one of the first transmission line or the second transmission line to receive a clock signal having a clock frequency corresponding to the communication protocol.

[0133] Example 22 includes the method of Example 21, wherein: a plurality of switches are coupled to the first transmission line and the second transmission line at different locations along the first transmission line and the second transmission line; and adjusting the length of the first transmission line and the second transmission line includes closing a selected switch among the plurality of switches based on the communication protocol.

[0134] Example 23 includes a non-transitory machine-readable storage device, comprising machine-readable instructions that, when executed, cause a processor or other circuitry or computing device to implement the method of Example 21.

[0135] Example 24 includes a computer program that includes instructions that, when executed by a computer, cause the computer to perform the method of Example 21.

[0136] Various operations can be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations necessarily depend on the order. Specifically, these operations may not be performed in the order presented. The operations may be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0137] The terms “basically,” “close to,” “approximately,” “near,” and “about” generally refer to within + / - 10% of the target value. Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe a common object merely indicates that different instances of similar objects are being referred to, and does not mean that the objects described must be in a given order, whether in time, space, ranking, or any other way.

[0138] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” refer to (A), (B), or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” refer to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0139] The specification may use the phrases "in one embodiment" or "in an embodiment," each phrase referring to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used for embodiments of this disclosure are synonyms.

[0140] As used herein, the term "circuit" may refer to, be, or include: an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or grouped), combinational logic circuitry, and / or other suitable hardware group that provides the said functionality. As used herein, "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet computer, a laptop computer, a set-top box, a game console, etc.

[0141] This document uses the terms “coupling,” “communication coupling,” and their derivatives. The term “coupling” can refer to two or more elements in direct physical or electrical contact with each other; it can refer to two or more elements in indirect contact with each other, but still cooperating or interacting with each other; and / or it can refer to one or more other elements coupled or connected between the elements referred to as being coupled to each other. The term “direct coupling” can refer to two or more elements in direct contact with each other. The term “communication coupling” can refer to two or more elements being in contact with each other through communication means, including through wired or other interconnections, through wireless communication channels or links, etc.

[0142] The terms "embodiment," "one embodiment," or "some embodiments" used in the specification refer to specific features, structures, or characteristics described in connection with an embodiment that are included in at least some embodiments, but not necessarily in all embodiments. The appearance of "embodiment," "one embodiment," or "some embodiments" in various places does not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "may," or "can" be included, it is not mandatory to include that particular component, feature, structure, or characteristic. If the specification or claims refer to an element "a" or "an," this does not mean that there is only one element. If the specification or claims refer to an "additional" element, it does not exclude the existence of multiple additional elements.

[0143] Furthermore, in one or more embodiments, specific features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment, provided that the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0144] While this disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of this disclosure are intended to include all such alternatives, modifications, and variations falling within the broad scope of the appended claims.

[0145] Furthermore, to simplify the description and discussion, and to avoid obscuring this disclosure, well-known power / ground connections for integrated circuit (IC) chips and other components may or may not be shown in the presented figures. Additionally, arrangements may be illustrated in block diagram form to avoid obscuring this disclosure, also taking into account the fact that details regarding the implementation of such block diagram arrangements are highly dependent on the platform on which this disclosure is implemented (i.e., such details should be entirely within the scope of those skilled in the art). In the context of setting forth specific details (e.g., circuits) to describe exemplary embodiments of this disclosure, it should be apparent to those skilled in the art that this disclosure can be practiced without these specific details or with variations thereof. Therefore, the description should be considered illustrative rather than restrictive.

[0146] An abstract is provided to enable the reader to identify the nature and key points of the technical disclosure. The abstract is submitted on the premise that it is not used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, each claim existing independently as a separate embodiment.

Claims

1. An apparatus comprising: A first transmission line includes a first signal conductor and a first return conductor, wherein the first signal conductor is coupled to a first clock source and includes one or more tap points, and the first return conductor includes one or more switching points; The second transmission line includes a second signal conductor and a second return conductor, wherein the second signal conductor is coupled to a second clock source and includes one or more tap points, and the second return conductor includes one or more switching points; and One or more switches are coupled to one or more switch points of the first return conductor and one or more switch points of the second return conductor.

2. The apparatus according to claim 1, wherein, The resonant frequency of the first transmission line can be adjusted based on which of the one or more switches is closed.

3. The apparatus according to claim 1 or 2, wherein: One or more taps of the first signal conductor include taps for the input path of the first data channel; and One or more taps of the second signal conductor include taps for the input path of the second data channel.

4. The apparatus according to any one of claims 1 to 3, wherein: One or more taps of the first signal conductor include taps for the first input path of the first data channel; and One or more taps of the second signal conductor include taps for the second input path of the first data channel.

5. The apparatus according to claim 1, wherein, One end of the first return conductor is shorted to one end of the second return conductor.

6. The apparatus according to any one of claims 1 to 5, wherein: The first return conductor has one or more switching points, including multiple switching points at different locations along the first return conductor; One or more switching points of the second return conductor include multiple switching points at different locations along the second return conductor; and Each switching point of the first return conductor is coupled to a corresponding switching point of the second return conductor through a corresponding switch of one or more of the switches.

7. The apparatus according to claim 6, wherein, The lengths of the first return conductor and the second return conductor can be adjusted based on which of the one or more switches is closed.

8. The apparatus according to any one of claims 1 to 7, wherein: The first return conductor is divided into a first branch and a second branch; The second return conductor is divided into a first branch and a second branch; The first branch of the first return conductor is shorted to the first branch of the second return conductor; and The second branch of the first return conductor is coupled to the second branch of the second return conductor through a corresponding switch.

9. The apparatus according to claim 8, wherein, The length of the first branch of the first return conductor is different from the length of the second branch of the first return conductor.

10. The apparatus according to any one of claims 1-9, further comprising at least one of an integrated circuit, a system-on-a-chip, a system-in-package, or a computing device, wherein the first transmission line, the second transmission line, and the one or more switches are provided in said at least one, wherein, The computing device includes at least one of a processor circuit, a memory circuit, a storage device circuit, an acceleration circuit, a communication circuit, an input circuit, an output circuit, an interface circuit, or an external device.

11. An apparatus comprising: Memory, used to store instructions; as well as A processor, coupled to the memory, wherein the processor executes the instructions to: Determine the communication protocol of the transmitter; Based on the communication protocol, the lengths of the first and second transmission lines of the clock distribution network are adjusted, wherein the transmitter is coupled to at least one of the first or second transmission lines to receive a clock signal having a clock frequency corresponding to the communication protocol.

12. The apparatus according to claim 11, wherein, The adjusted lengths of the first transmission line and the second transmission line are used to provide the resonant frequency of the clock distribution network corresponding to the clock frequency.

13. The apparatus according to claim 11 or 12, wherein: Multiple switches are coupled to the first and second transmission lines at different locations along the first and second transmission lines; and In order to adjust the lengths of the first transmission line and the second transmission line, the processor will close a selected switch among the plurality of switches based on the communication protocol.

14. The apparatus according to claim 13, wherein, The communication protocol of the transmitter is determined from a plurality of available communication protocols, and each communication protocol corresponds to the identifier of a corresponding switch among the plurality of switches.

15. The apparatus according to claim 14, wherein, The available communication protocols include at least one of different versions of Fast Peripheral Component Interconnect (PCIe) or different versions of Universal Serial Bus (USB).

16. A clock distribution network, comprising: A first transmission line, coupled to a first clock source, and including one or more taps; A second transmission line is coupled to a second clock source and includes one or more tap points; as well as A plurality of switches, wherein each of the plurality of switches is coupled to the first transmission line and the second transmission line to short the first transmission line to the second transmission line at a corresponding location along the first transmission line and the second transmission line.

17. The clock distribution network according to claim 16, wherein, Each of the plurality of switches is coupled to the return conductor of the first transmission line and the return conductor of the second transmission line.

18. The clock distribution network according to claim 16 or 17, wherein, The lengths of the first transmission line and the second transmission line can be adjusted depending on which of the plurality of switches is closed.

19. The clock distribution network according to any one of claims 16-18, wherein, The resonant frequencies of the first and second transmission lines can be adjusted depending on which of the plurality of switches is closed.

20. The clock distribution network according to any one of claims 16 to 19, wherein, The clock signal of the first clock source is the inverted signal of the clock signal of the second clock source.

21. A method comprising: Determine the communication protocol of the transmitter; as well as Based on the communication protocol, the lengths of the first and second transmission lines of the clock distribution network are adjusted, wherein the transmitter is coupled to at least one of the first or second transmission lines to receive a clock signal having a clock frequency corresponding to the communication protocol.

22. The method according to claim 21, wherein: Multiple switches are coupled to the first and second transmission lines at different locations along the first and second transmission lines; and Adjusting the lengths of the first and second transmission lines includes closing a selected switch among the plurality of switches based on the communication protocol.

23. A non-transitory machine-readable storage device, comprising machine-readable instructions that, when executed, cause a processor or other circuitry or computing device to implement the method of claim 21.

24. A computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of claim 21.

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