Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: a glass layer; an insulating member penetrating the glass layer; and a via electrode penetrating the insulating member, in which a central axis in a horizontal direction of the via electrode and a central axis in a horizontal direction of the insulating member are offset from each other.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a semiconductor packaging substrate including the circuit board. Background Technology

[0002] With the increasing performance of electrical / electronic products, techniques for arranging a greater number of semiconductor devices on semiconductor packaging substrates of limited size have been proposed and studied. However, since typical semiconductor packages are generally configured to mount only one semiconductor device, there are limitations in achieving the desired performance.

[0003] Therefore, recently, a semiconductor package has been provided in which multiple semiconductor devices are arranged using multiple circuit boards. This semiconductor package has a structure in which multiple semiconductor devices are interconnected on a circuit board in a horizontal and / or vertical direction. Therefore, the advantage of this semiconductor package is that it effectively utilizes the mounting area of ​​the semiconductor devices and can transmit high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Furthermore, semiconductor packaging used in products providing IoT (Internet of Things), autonomous vehicles, high-performance servers, etc., is conceptually expanding to semiconductor chiplets as the number of semiconductor devices and / or the size of each semiconductor device increases according to the trend of high integration or the functional parts of semiconductor devices are divided.

[0005] On the other hand, as the number of semiconductor devices and / or semiconductor chips mounted on semiconductor packages increases, the area of ​​the semiconductor package tends to increase. Furthermore, as the area of ​​semiconductor packages becomes wider, there is a problem of significantly increased circuit board distortion. When the circuit board is significantly distorted, semiconductor devices may not be stably attached to the circuit board. For example, the circuit board includes pads for terminals connected to semiconductor devices. Moreover, when the circuit board is significantly distorted in a particular direction, the height of multiple pads becomes inconsistent, thus potentially leading to unstable attachment of the semiconductor devices.

[0006] Conventionally, to improve the rigidity of a circuit board, a core layer with a predetermined thickness is provided. The core layer includes reinforcing members such as glass fiber and serves as the core of the circuit board. However, although a core layer including glass fiber is effective in improving rigidity and serves as the core of a circuit board, it suffers from significant signal transmission loss due to its low dielectric constant and high surface roughness.

[0007] Therefore, a method is needed to improve the rigidity of the circuit board to prevent it from twisting significantly in a certain direction, while mitigating the twisting of the circuit board, thereby allowing semiconductor devices to attach stably and minimizing signal transmission loss, so that the semiconductor devices can operate stably. Summary of the Invention

[0008] Technical issues

[0009] The embodiments provide a circuit board with a novel structure and a semiconductor package including the circuit board.

[0010] Furthermore, the embodiments provide a circuit board having a structure in which distortion in a particular direction is mitigated, and a semiconductor package including the circuit board.

[0011] Furthermore, the embodiments provide a circuit board in which signal transmission characteristics are disclosed, and a semiconductor package including the circuit board.

[0012] Furthermore, the embodiments provide a circuit board in which connecting members can be stably embedded, and a semiconductor package including the circuit board.

[0013] The technical problems to be solved by the proposed embodiments are not limited to those described above, and those skilled in the art to which the embodiments described below pertain will clearly understand other technical problems not mentioned.

[0014] Technical solution

[0015] The circuit board according to an embodiment includes: a glass layer; an insulating member penetrating the glass layer; and a via electrode penetrating the insulating member, wherein the central axis of the via electrode in the horizontal direction and the central axis of the insulating member in the horizontal direction are shifted relative to each other.

[0016] Furthermore, the insulating member has an inclined portion in which the width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer, wherein the via electrode includes: a first portion having an inclined portion in which the width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer; and a second portion disposed below the first portion and having an inclined portion in which the width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer, wherein the inclination angle of the second portion is different from the inclination angle of the insulating member.

[0017] Furthermore, the inclined portion of the insulating member is inclined in the same direction as the inclined portion of the first part, and the inclined portion of the second part is inclined in a different direction than the inclined portion of the insulating member and the inclined portion of the first part.

[0018] Furthermore, the horizontal central axis of the via electrode is closer to the horizontal central axis of the glass layer than the horizontal central axis of the insulating member.

[0019] Furthermore, each of the insulating member and the via electrode is configured as a plurality, spaced apart from each other in the horizontal direction, wherein the offset direction of the central axis of each of the plurality of via electrodes relative to the central axis of each of the plurality of insulating members in the horizontal direction includes a first offset direction and a second offset direction that are different from each other.

[0020] Furthermore, at least one of the plurality of via electrodes has the same thickness in the vertical direction as the first portion in the vertical direction as the second portion.

[0021] Furthermore, at least one of the plurality of via electrodes has a thickness in the vertical direction of the first portion that is different from the thickness in the vertical direction of the second portion.

[0022] Furthermore, the plurality of via electrodes includes a first via electrode and a second via electrode, wherein the thickness of a first portion of the first via electrode in the vertical direction is greater than the thickness of a second portion of the first via electrode in the vertical direction, and wherein the thickness of a first portion of the second via electrode in the vertical direction is less than the thickness of a second portion of the second via electrode in the vertical direction.

[0023] Furthermore, the insulating member includes a third part and a fourth part, the third part having an inclined portion in which the width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer, and the fourth part being disposed below the third part and having an inclined portion in which the width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer.

[0024] Furthermore, the horizontal central axis of the third part of the insulating member and the horizontal central axis of the fourth part of the insulating member are offset from each other, wherein the vertical thickness of the third part at the first side end of the insulating member and the vertical thickness of the third part at the second side end of the insulating member are different from each other, and wherein the vertical thickness of the fourth part at the first side end of the insulating member and the vertical thickness of the fourth part at the second side end of the insulating member are different from each other.

[0025] Furthermore, the horizontal central axis of the first part of the via electrode and the horizontal central axis of the second part of the via electrode are offset from each other. The vertical thickness of the first part at the first side end of the via electrode and the vertical thickness of the first part at the second side end of the via electrode are different from each other. The vertical thickness of the second part at the first side end of the via electrode and the vertical thickness of the second part at the second side end of the via electrode are also different from each other.

[0026] In addition, the circuit board also includes a resin layer disposed inside the via electrode, and the via electrode is configured to surround the resin layer.

[0027] Furthermore, the thickness of the via electrode in the horizontal direction at the first end of the resin layer and the thickness of the via electrode in the horizontal direction at the second end of the resin layer are different from each other.

[0028] In addition, the circuit board also includes: a first stacked layer disposed on the upper surface of the glass layer; a second stacked layer disposed below the lower surface of the glass layer; and a connecting member embedded in the first stacked layer.

[0029] In addition, the glass layer is provided with a cavity recessed from the upper surface of the glass layer toward the lower surface of the glass layer, and the connecting member is disposed in the cavity of the glass layer. The glass layer includes a sidewall forming the cavity, a bottom surface, and a boundary surface between the sidewall and the bottom surface, and the boundary surface includes a curved surface with a predetermined curvature.

[0030] Furthermore, the inclination of the cavity sidewall relative to the upper and / or lower surface of the glass layer is closer to 90° than the inclination of the insulating member relative to the upper and / or lower surface of the glass layer and the inclination of the via electrode relative to the upper and / or lower surface of the glass layer.

[0031] On the other hand, the circuit board according to the embodiment includes: a glass layer having a cavity on its upper surface; and a connecting member disposed in the cavity of the glass layer, wherein the cavity includes a sidewall, a bottom surface, and a boundary surface between the sidewall and the bottom surface, the boundary surface including a curved surface having a predetermined curvature, and the central axis of the connecting member in the horizontal direction and the central axis of the cavity in the horizontal direction are offset from each other.

[0032] In addition, the circuit board also includes: an insulating member that is horizontally spaced from the cavity and penetrates the glass layer; and a via electrode that penetrates the insulating member, wherein the central axis of the via electrode in the horizontal direction and the central axis of the insulating member in the horizontal direction are offset from each other.

[0033] Furthermore, the horizontal central axis of the connecting member is closer to the horizontal central axis of the glass layer than the horizontal central axis of the cavity, and the horizontal central axis of the via electrode is closer to the horizontal central axis of the glass layer than the horizontal central axis of the insulating member.

[0034] Beneficial effects

[0035] The circuit board according to an embodiment includes a glass layer, an insulating member penetrating the glass layer, and a via electrode penetrating the insulating member. Furthermore, the horizontal central axis of the via electrode and the horizontal central axis of the insulating member are offset from each other. For example, the horizontal central axis of the via electrode may be offset in a specific direction relative to the horizontal central axis of the insulating member. Therefore, depending on the offset direction and offset distance of the horizontal central axis of the via electrode from the horizontal central axis of the insulating member, the twisting of the circuit board in a specific direction can be mitigated.

[0036] Specifically, the central axis of the via electrode can be offset relative to the central axis of the insulating member based on the direction of circuit board twisting. Therefore, it can prevent the circuit board from twisting in a specific direction and avoid excessive stress being applied to the circuit board. This improves the mechanical and / or electrical reliability of the circuit board. Furthermore, the embodiment can mitigate circuit board twisting, allowing semiconductor devices to be stably attached to the circuit board. In this case, when the circuit board twists in a specific direction, height deviations may occur between multiple joints disposed on the circuit board, and the terminals of the semiconductor devices may not be stably engaged with the multiple joints. Conversely, the embodiment can mitigate the overall twisting of the circuit board by offsetting the horizontal central axis of the via electrode from the horizontal central axis of the insulating member, allowing the semiconductor devices to be stably attached to the circuit board. Therefore, the embodiment allows the semiconductor devices to operate stably, thereby improving product reliability. Furthermore, the embodiment can allow products with semiconductor packaging applications, such as servers, to operate stably.

[0037] Furthermore, the circuit board of the embodiment may include multiple insulating members and multiple via electrodes respectively disposed in the multiple insulating members. Moreover, the offset direction and / or offset distance of the horizontal central axis of at least one of the multiple via electrodes may differ from the offset direction and / or offset distance of the horizontal central axis of at least another via electrode. For example, the horizontal central axis of each of the multiple via electrodes may be offset in a direction from the horizontal central axis of each insulating member toward the horizontal central axis of the glass layer. Therefore, the embodiment can further improve the overall torsion characteristics of the circuit board by allowing each of the multiple via electrodes to have a different offset direction and / or offset distance.

[0038] Furthermore, the insulating member of the embodiment may have an inclined portion in which the width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer. Additionally, the via electrode may include a first portion and a second portion. The first portion has an inclined portion in which the width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer, and the second portion is disposed below the first portion and has an inclined portion in which the width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer. That is, the embodiment may allow the insulating member to have only one inclination, thus simplifying the process of setting through holes in the glass layer to form the insulating member, thereby improving the yield. Furthermore, by allowing the via electrode to include first and second portions with different inclinations, the process characteristics in the electroplating process for electroplating the via electrode can be improved, and therefore, the mechanical and / or electrical reliability of the circuit board can be improved.

[0039] Furthermore, the thicknesses of the first and second portions of the via electrode in the vertical direction can differ from each other. Therefore, the process capability in the electroplating of the via electrode can be improved by adjusting the ratio of the thickness of the first portion in the vertical direction to that of the second portion. As a result, the embodiment can reduce circuit board manufacturing time and increase yield. Furthermore, the embodiment can prevent the formation of voids in the via electrode and prevent cracks from forming in the via electrode due to stress from thermal cycling, thereby improving the electrical reliability of the circuit board. Moreover, the ratio of the thickness of the first portion in the vertical direction to that of the second portion can be determined taking into account the direction of circuit board twist; therefore, the embodiment can more effectively prevent circuit board twisting in a specific direction and allows for more stable mounting of semiconductor devices.

[0040] Furthermore, the insulating member may include a first portion and a second portion with different inclinations, thus reducing the size of the through-hole in the glass layer in which the insulating member is disposed. Therefore, embodiments can further improve the rigidity of the circuit board by reducing the area of ​​the through-hole disposed in the glass layer.

[0041] Furthermore, the horizontal central axes of the first and second portions of the insulating member can be offset from each other. Alternatively, the horizontal central axes of the first and second portions of the via electrode can be offset from each other. That is, considering the direction of circuit board twist, each central axis of the first and second portions of the insulating member can be offset from each other, or each central axis of the first and second portions of the via electrode can be offset from each other, and thus, the overall twist characteristics of the circuit board can be further improved.

[0042] Furthermore, the circuit board may also include a resin layer disposed inside the via electrode, and the via electrode may be configured to surround the resin layer. Therefore, as the thickness of the glass layer in the vertical direction increases, voids can be prevented from forming inside the via electrode, and thus, the electrical and / or mechanical reliability of the circuit board can be further improved.

[0043] Furthermore, the horizontal thickness of the via electrode can include a first thickness and a second thickness that differ from each other along the circumference of the resin layer, thereby further improving the overall torsion characteristics of the circuit board. For example, considering the direction of circuit board torsion, the embodiment can allow the horizontal central axis of the insulating member and the horizontal central axis of the via electrode to be offset from each other as described above, while allowing the via electrode to have different horizontal thicknesses along the circumference of the resin layer, thus further improving the overall torsion characteristics of the circuit board.

[0044] Furthermore, a cavity recessed towards the lower surface of the glass layer can be formed on the upper surface of the glass layer, and a connecting member can be disposed within the cavity. Therefore, by allowing the connecting member to be disposed within a glass layer with relatively high rigidity, the flatness and rigidity of the connecting member can be improved, and thus, the overall torsional characteristics of the circuit board and semiconductor package can be further improved. Additionally, the alignment between the pad portions disposed in the connecting member and the circuit layer and the via electrodes of the first stacked layer can be improved.

[0045] Furthermore, the glass layer may include sidewalls forming the cavity, a bottom surface, and a boundary surface between the sidewalls and the bottom surface. The sidewalls of the cavity forming the glass layer may be closer to 90° than the inclination of the insulating member and the inclination of the via electrode. Therefore, the rigidity of the glass layer can be maintained by minimizing the area occupied by the cavity in the glass layer, and thus, the torsion characteristics of the circuit board and semiconductor package can be further improved. Furthermore, the boundary surface between the cavity sidewalls and the bottom surface can be configured as a curved surface with a predetermined curvature. Therefore, this embodiment can improve the mechanical reliability of the circuit board and semiconductor package. For example, when the boundary between the cavity sidewalls and the bottom surface is right-angled, stress may concentrate at the boundary in the manufacturing environment and / or operating environment of the circuit board, thus potentially causing cracks. Conversely, the embodiment can prevent stress concentration on the boundary surface by allowing the boundary surface between the sidewalls and the bottom surface to be circular, and thus, the mechanical reliability of the circuit board and semiconductor package can be improved.

[0046] Furthermore, the horizontal central axis of the connecting member and the horizontal central axis of the cavity can be offset from each other. Additionally, each of the connecting members and cavities can be configured as multiple, and the horizontal central axis of each connecting member can be offset from the horizontal central axis of each cavity at different directions and distances. Therefore, the embodiment can further reduce the twisting of the circuit board. Attached Figure Description

[0047] Figure 1a This is a cross-sectional view of a circuit board according to the first embodiment.

[0048] Figure 1b and Figure 1c This is a cross-sectional view of a circuit board according to the second embodiment.

[0049] Figure 2a and Figure 2b This is a cross-sectional view showing the core via electrode according to the first embodiment.

[0050] Figure 3 It is shown Figure 2a and Figure 2b A cross-sectional view of an example arrangement of the core via electrodes.

[0051] Figure 4 To show in more detail Figure 3 A plan view illustrating an example of the arrangement of the core via electrodes.

[0052] Figure 5 This is a cross-sectional view showing the core via electrode according to the second embodiment.

[0053] Figure 6 This is a cross-sectional view showing the core via electrode according to the third embodiment.

[0054] Figure 7 This is a cross-sectional view showing the core via electrode according to the fourth embodiment.

[0055] Figure 8 This is a cross-sectional view showing the core via electrode according to the fifth embodiment.

[0056] Figure 9 This is a cross-sectional view showing the core via electrode according to the sixth embodiment.

[0057] Figure 10 This is a cross-sectional view showing the core via electrode according to the seventh embodiment.

[0058] Figure 11 This is a cross-sectional view of a circuit board according to a third embodiment.

[0059] Figure 12 This is a cross-sectional view of a circuit board according to the fourth embodiment.

[0060] Figure 13 This is a cross-sectional view of a circuit board according to the fifth embodiment.

[0061] Figure 14 To show in more detail Figure 13 A cross-sectional view of a portion of the layers of a circuit board.

[0062] Figure 15 To show in more detail Figure 14 A plan view of the arrangement of cavities and connecting components of the circuit board.

[0063] Figure 16 This is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0064] Figure 17 This is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0065] Figures 18a to 18h This is a cross-sectional view showing the method of manufacturing a circuit board according to an embodiment, in the order of process steps. Detailed Implementation

[0066] In the following description, embodiments of the present disclosure will be illustrated in detail with reference to the accompanying drawings.

[0067] However, the spirit and scope of this disclosure are not limited to the portion of the described embodiments, and may be implemented in a variety of other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of this disclosure.

[0068] Furthermore, unless otherwise expressly defined and described, the terms (including technical and scientific terms) used in the embodiments of this disclosure may be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and terms such as those defined in common dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant field. Moreover, the terminology used in the embodiments of this disclosure is for describing embodiments and is not intended to limit this disclosure.

[0069] In this specification, unless specifically stated in the phrase, the singular form may also include the plural form, and when described as “at least one (or more) of A (and), B and C”, it may include at least one of all combinations that can be combined with A, B and C. Furthermore, in the elements describing embodiments of this disclosure, terms such as first, second, A, B, (a) and (b) may be used.

[0070] These terms are used only to distinguish one element from another, and are not limited to the nature, order, or sequence of the elements. Furthermore, when an element is described as being “connected,” “joined,” or “in contact” with another element, this may include not only cases where the element is directly “connected,” “joined,” or “in contact” with other elements, but also cases where the element is “connected,” “joined,” or “in contact” with another element through which the element is connected.

[0071] Furthermore, when described as being formed or disposed "above" or "below" each element, "above" or "below" can include not only cases where two elements are directly connected to each other, but also cases where one or more other elements are formed or disposed between the two elements. Additionally, when expressed as "above" or "below," it can include not only an upward direction based on a single element, but also a downward direction based on a single element.

[0072] The terminology used in this application is for describing specific embodiments only and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “comprising” or “having” specify the presence of features, quantities, steps, operations, components, portions, or combinations thereof described in the specification, and should not be construed as pre-excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, portions, or combinations thereof.

[0073] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the prior art, and shall not be interpreted in an ideal or overly formal sense unless expressly defined in this application.

[0074] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and regardless of the reference numerals in the drawings, the same or corresponding parts will be given the same reference numerals, and redundant descriptions will be omitted.

[0075] Before describing the embodiments, a semiconductor-packaged electronic device (not shown) of the application embodiments will be briefly described. The electronic device may be a smartphone, personal digital assistant, digital camera, digital still camera, vehicle, high-performance server, network system, computer, monitor, tablet computer, laptop, netbook, television, video game, smartwatch, automobile, etc. However, the electronic device is not limited to these and may be any other electronic device that processes data.

[0076] The electronic device includes a motherboard (not shown). The motherboard can be physically and / or electrically connected to various components. For example, the motherboard can be connected to a semiconductor package according to an embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor device, a junction for electrically connecting the semiconductor device and the circuit board, a resin portion filling the space between the semiconductor device and the circuit board, and a molding portion completely surrounding the semiconductor device.

[0077] Semiconductor devices can include active and / or passive devices and can have a variety of functions. Active devices can be in the form of integrated circuits (ICs), in which hundreds to millions or more transistors are integrated into a single semiconductor device, and can be, for example, logic chips, memory chips, etc. For example, a logic chip can be an application processor (AP) device that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or a group of devices that includes specific combinations of those listed above. Memory chips can be stacked memories such as HBM. Furthermore, memory chips can include memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), flash memories, etc.

[0078] The semiconductor package of the embodiment can be any of, but is not limited to, CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package Plug-in), and SIP (System-in-Package).

[0079] Figure 1a This is a cross-sectional view of a circuit board according to the first embodiment. Figure 1b and 1c This is a cross-sectional view of a circuit board according to the second embodiment. Figure 2a and 2b This is a cross-sectional view showing the core via electrode according to the first embodiment. Figure 3 It is shown Figure 2a and Figure 2b A cross-sectional view of an example arrangement of the core via electrodes. Figure 4 To show in more detail Figure 3 A plan view illustrating an example of the arrangement of the core via electrodes. Figure 5 This is a cross-sectional view showing the core via electrode according to the second embodiment. Figure 6 This is a cross-sectional view showing the core via electrode according to the third embodiment. Figure 7 This is a cross-sectional view showing the core via electrode according to the fourth embodiment. Figure 8 This is a cross-sectional view showing the core via electrode according to the fifth embodiment. Figure 9This is a cross-sectional view showing the core via electrode according to the sixth embodiment. Figure 10 This is a cross-sectional view showing the core via electrode according to the seventh embodiment. Figure 11 This is a cross-sectional view of a circuit board according to a third embodiment. Figure 12 This is a cross-sectional view of a circuit board according to the fourth embodiment. Figure 13 This is a cross-sectional view of a circuit board according to the fifth embodiment. Figure 14 To show in more detail Figure 13 A cross-sectional view of a portion of the layers of a circuit board. Figure 15 To show in more detail Figure 14 A plan view of the arrangement of cavities and connecting components on the circuit board. Figure 16 This is a cross-sectional view showing a semiconductor package according to the first embodiment, and Figure 17 This is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0080] In the following text, references will be made to Figures 1 to 12. Figure 17 A circuit board according to an embodiment and a semiconductor package including the circuit board are described in detail.

[0081] Reference Figure 1a The circuit board 100 includes a glass layer 101, a first stacked layer 102 disposed on a first surface of the glass layer 101, and a second stacked layer 103 disposed on a second surface of the glass layer 101. Here, the disposal on the first and second surfaces is not limited to a configuration that is in direct contact with the first and second surfaces, but should also be understood to include another configuration between the first surface and the first stacked layer 102 and between the second surface and the second stacked layer 103.

[0082] Glass layer 101 is an insulating layer of sheet-like glass material and is used to improve the rigidity of circuit board 100 by serving as the core of circuit board 100. For example, glass layer 101 may include, but is not limited to, pure silicon oxide (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc., and may also include fluorine glass, phosphate glass, chalcogenide glass, etc., in addition to silicon-based glass compositions. Furthermore, glass layer 101 may include other additives to form glass with specific physical properties. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda ash), and may also include carbonates and / or oxides of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as these and other elements. Glass layer 101 may also be referred to as a "core layer" or "glass core," which serves as the core of circuit board 100.

[0083] Recently, with the increase in the number of terminals of semiconductor devices disposed on circuit board 100, wiring has become more complex, and therefore, the thickness of the first stacked layer 102 and the second stacked layer 103 tends to increase. Therefore, the glass layer 101 of this embodiment can have a thickness of 200 μm to 1200 μm to improve the overall rigidity of circuit board 100 and prevent excessive signal loss. The glass layer 101 can have a higher dielectric constant and lower surface roughness than conventional core layers including glass fibers, thereby improving the rigidity of circuit board 100 while minimizing signal transmission loss and improving the electrical and / or mechanical reliability of circuit board 100 and the semiconductor package including it.

[0084] Through-holes penetrating the first and second surfaces of glass layer 101 can be formed in glass layer 101. Through-holes in glass layer 101 can be formed using methods such as CO2 lasers. For example, the crystallinity of a region of glass layer 101 irradiated with a CO2 laser is altered, and through-holes can be formed by removing the region of glass layer 101 where the crystallinity is altered using wet etching with hydrofluoric acid (HF). However, this embodiment is not limited to this, and through-holes in glass layer 101 can be formed by various methods. For example, when a through-hole is formed in glass layer 101 using mechanical drilling, the inclination of the through-hole can be perpendicular to the first and / or second surfaces of glass layer 101. However, when the inclination of the through-hole is perpendicular to the first and / or second surfaces of glass layer 101, it may be difficult to densely fill the interior of the through-hole with a metallic material during an electroplating process that fills the through-hole with a conductive material. Furthermore, when forming through holes in the glass layer 101 using mechanical drilling, damage such as cracking of the glass layer 101 may occur during the drilling process, and therefore, the yield may be reduced. Therefore, the glass layer 101 may include angled through holes such that the width in the horizontal direction gradually decreases and / or increases from the first surface toward the second surface.

[0085] A core via electrode 141 can be disposed in a through-hole of the glass layer 101. The core via electrode 141 is used to electrically connect the first deposited layer 102 and the second deposited layer 103. Preferably, the core via electrode 141 densely fills the through-hole for resistive or heat dissipation functions. However, when the insulating layer used as the core is a glass layer 101 comprising a glass material, it may be difficult to form a seed layer of core via electrode 141 with a uniform thickness on the inner wall of the through-hole of the glass layer 101. For example, to form the core via electrode 141, a process such as electroless plating, such as sputtering, is performed on the inner wall of the through-hole of the glass layer 101 to form the seed layer. When the seed layer is formed of copper, problems such as peeling between the seed layer and the glass layer 101 may occur due to poor adhesion between the copper and the glass layer 101. However, when the seed layer is formed of titanium (Ti), chromium (Cr), etc., which have good adhesion to the glass layer 101, sputtering can be used to set the seed layer. However, when sputtering equipment suitable for panel processing is unavailable and the seed layer is formed of copper, the core via electrode 141 can be formed by electroplating after the insulating member 142 is disposed in the through-hole of the glass layer 101 and a copper material with good adhesion to the insulating member 142 is disposed as the seed layer. For example, the glass layer 101 includes a through-hole, the core via electrode 141 is disposed in the through-hole of the glass layer 101, and the insulating member 142 is disposed between the inner wall of the through-hole of the glass layer 101 and the outer surface of the core via electrode 141 to surround the core via electrode 141. That is, the glass layer 101 includes a through-hole, the insulating member 142 is disposed in the through-hole of the glass layer 101, and also includes a via, and the core via electrode 141 can be disposed in the via of the insulating member 142. Here, for the sake of distinction, the hole penetrating the glass layer 101 is referred to as a "through-hole," and the hole penetrating the insulating member 142 is referred to as a "via." Therefore, the core via electrode 141 can contact the insulating member 142 without contacting the glass layer 101. Consequently, a smooth electroplating process can be performed in the process of forming the core via electrode 141, thereby improving the yield and ensuring adhesion between the core via electrode 141 and the insulating member 142, thereby improving the mechanical and / or electrical reliability of the core via electrode 141. Furthermore, by mitigating the difference in the coefficient of thermal expansion between the core via electrode 141 and the glass layer 101, peeling and / or cracking of the core via electrode 141 can be prevented.

[0086] In this case, the insulating member 142 can be disposed on the inner wall of the through hole in the glass layer 101, and therefore can be used to improve adhesion to the core through hole electrode 141. Figure 1aIn one embodiment, the insulating member 142 may not contact the upper and lower surfaces of the glass layer 101. That is, compared to forming a seed layer in the through-holes of the glass layer 101, a seed layer formed on the upper and / or lower surfaces of the glass layer 101 for forming the circuit layers described later can ensure adhesion, and therefore, the insulating member 142 can be selectively disposed only in the through-holes of the glass layer 101 without contacting the upper and lower surfaces of the glass layer 101. However, the embodiments are not limited thereto. Figure 1b In some embodiments, the insulating member 142A may also be disposed on the upper and / or lower surface of the glass layer 101 to improve the adhesion between the glass layer 101 and the circuit layer. For example, the insulating member 142A may include a first portion 142A1 disposed on the inner wall of a through hole penetrating the glass layer 101 and a second portion 142A2 disposed on the upper and / or lower surface of the glass layer 101. In this case, the insulating member 142A may be made of the same insulating material as the insulating material of the plurality of insulating layers 106, 107, 108, 109 and 110 of the first stacked layer 102 and / or the plurality of insulating layers 111, 112, 113, 114 and 115 of the second stacked layer 103. In this case, when the insulating member 142A includes the second portion 142A2 disposed on the upper and lower surfaces of the glass layer 101, the adhesion between the glass layer 101 and the circuit layers 121 and 122 can be further improved, and the reliability problem of the circuit layers 121 and 122 peeling off from the glass layer 101 can be solved. In addition, according to Figure 1cIn some embodiments, the insulating member 142B may also be disposed on the upper and / or lower surface and the outer surface of the glass layer 101 to improve the adhesion between the glass layer 101 and the circuit layer. For example, the insulating member 142B may include a first portion 142B1 disposed on the inner wall of a through hole penetrating the glass layer 101, a second portion 142B2 disposed on the upper and / or lower surface of the glass layer 101, and a third portion 142B3 disposed on the outer surface of the glass layer 101. In this case, the insulating member 142B may be made of the same insulating material as the insulating material of the plurality of insulating layers 106, 107, 108, 109 and 110 of the first stacked layer 102 and / or the plurality of insulating layers 111, 112, 113, 114 and 115 of the second stacked layer 103. In this case, when the insulating member 142B further includes a third portion 142B2 disposed on the outer surface of the glass layer 101, reliability issues such as cracks in the glass layer 101 that may occur during the circuit board manufacturing process can be further improved, thereby further increasing the yield. For example, a circuit board can be manufactured in a panel unit. In this case, cracks in the glass layer 101 may occur during the process of separating the panel unit into a unit package, and therefore, the yield may decrease. Therefore, the insulating member 142B may also include a third portion 142B3 disposed on the outer surface of the glass layer 101, and can solve problems such as cracking that may occur during the process of separating the panel unit into a unit package. Furthermore, the third portion 142B3 of the insulating member 142B disposed on the outer surface of the glass layer 101 can serve as a buffer layer that alleviates stress caused by thermal shrinkage and / or thermal expansion generated during the circuit board manufacturing process and / or the circuit board operating environment, and therefore can solve the problem of the circuit board twisting significantly in a particular direction and / or the reliability problem of multiple components of the circuit board separating from each other due to the aforementioned stress. In the following, based on Figure 1a The insulating member 142 shown is described.

[0087] A first deposited layer 102 is disposed on a first surface of glass layer 101. The first deposited layer 102 includes a plurality of insulating layers 106, 107, 108, 109 and 110, a plurality of circuit layers 116, 117, 118, 119, 120 and 121, and a first protective layer 104.

[0088] The plurality of circuit layers 116, 117, 118, 119, 120 and 121 of the first stacked layer 102 may include a first circuit layer 116 that is furthest from the glass layer 101 in the vertical direction, a second circuit layer 117 that is closer to the glass layer 101 in the vertical direction than the first circuit layer 116, a third circuit layer 118 that is closer to the glass layer 101 in the vertical direction than the second circuit layer 117, a fourth circuit layer 119 that is closer to the glass layer 101 in the vertical direction than the third circuit layer 118, a fifth circuit layer 120 that is closer to the glass layer 101 in the vertical direction than the fourth circuit layer 119, and a sixth circuit layer 121 that is closer to the glass layer 101 in the vertical direction than the fifth circuit layer 120.

[0089] The first to sixth circuit layers 116, 117, 118, 119, 120, and 121 can be used for electrical connections to semiconductor devices disposed on the circuit board 100. Each of the first to sixth circuit layers 116, 117, 118, 119, 120, and 121 can be freely designed considering impedance. Furthermore, via electrodes 131, 132, 133, 134, and 135 can be provided to connect the first to sixth circuit layers 116, 117, 118, 119, 120, and 121. For example, the first via electrode 131 is disposed between the first circuit layer 116 and the second circuit layer 117, the second via electrode 132 is disposed between the second circuit layer 117 and the third circuit layer 118, the third via electrode 133 is disposed between the third circuit layer 118 and the fourth circuit layer 119, the fourth via electrode 134 is disposed between the fourth circuit layer 119 and the fifth circuit layer 120, and the fifth via electrode 135 is disposed between the fifth circuit layer 120 and the sixth circuit layer 121, thereby electrically connecting the first to the sixth circuit layers 116, 117, 118, 119, 120 and 121.

[0090] In the process of setting the first to fifth circuit layers 116, 117, 118, 119, and 120, the first to fifth via electrodes 131, 132, 133, 134, and 135 can be formed simultaneously. For example, in the process of setting the fifth circuit layer 120 on the sixth circuit layer 121, a through-hole can be formed in the fifth insulating layer 110 to expose a portion of the sixth circuit layer 121, and therefore, the fifth circuit layer 120 can be set together with the fifth via electrode 135 filling the through-hole in the fifth insulating layer 110. Thus, the fifth via electrode 135 can be distinguished as a protrusion of the fifth circuit layer 120. Similarly, each of the first to fourth via electrodes 131, 132, 133, and 134 can be distinguished as a protrusion of each of the first to fourth circuit layers 116, 117, 118, and 119, and can be connected to another circuit layer disposed below each circuit layer.

[0091] The sixth circuit layer 121 can contact the first surface of the glass layer 101. In this case, a portion of the sixth circuit layer 121 can be configured to cover the aforementioned insulating member 142. That is, the lower surface of the sixth circuit layer 121 may include a first portion of the upper surface of the contact core via electrode 141, a second portion of the upper surface of the contact insulating member 142, and a third portion of the upper surface of the glass layer 101.

[0092] The plurality of insulating layers 106, 107, 108, 109 and 110 of the first stacked layer 102 may include a first insulating layer 106 that is furthest from the glass layer 101 in the vertical direction, a second insulating layer 107 that is closer to the glass layer 101 in the vertical direction than the first insulating layer 106, a third insulating layer 108 that is closer to the glass layer 101 in the vertical direction than the second insulating layer 107, a fourth insulating layer 109 that is closer to the glass layer 101 in the vertical direction than the third insulating layer 108, and a fifth insulating layer 110 that is closer to the glass layer 101 in the vertical direction than the fourth insulating layer 109.

[0093] The first to fifth insulating layers 106, 107, 108, 109, and 110 are configured for insulation in the vertical direction between the first to sixth circuit layers 116, 117, 118, 119, 120, and 121. For example, the first to sixth insulating layers 106, 107, 108, 109, and 110 can use thermosetting insulating materials in which inorganic fillers are contained in the resin, and Ajinomoto's ABF (Ajinomoto deposited film) can be used. However, the embodiments are not limited to this, and photoimageable dielectrics (PIDs) can be used to form fine patterns.

[0094] The first protective layer 104 protects the first circuit layer 116 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 100 using materials such as solder, the first protective layer 104 prevents short circuits between solders due to low wettability with the solder. The first protective layer 104 can be made of a photocurable insulating material, and for example, a solder resist can be used.

[0095] The second deposited layer 103 is disposed on the second surface of the glass layer 101. The second deposited layer 103 includes a plurality of insulating layers 111, 112, 113, 114 and 115, a plurality of circuit layers 122, 123, 124, 125, 126 and 127, and a second protective layer 127.

[0096] The plurality of circuit layers 122, 123, 124, 125, 126, and 127 of the second stacked layer 103 may include, in the vertical direction, a seventh circuit layer 122 closest to the glass layer 101, an eighth circuit layer 123 disposed below the seventh circuit layer 116, a ninth circuit layer 124 disposed below the eighth circuit layer 123, a tenth circuit layer 125 disposed below the ninth circuit layer, an eleventh circuit layer 126 disposed below the tenth circuit layer 125, and a twelfth circuit layer 127 disposed below the eleventh circuit layer 126. The seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127 can be used to electrically connect a motherboard (not shown) of an electronic device to semiconductor devices disposed on the circuit board 100. Each of the seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127 can be freely designed considering impedance.

[0097] Furthermore, via electrodes 136, 137, 138, 139, and 140 can be provided to connect each of the seventh circuit layers 122, 123, 124, 125, 126, and 127. The sixth via electrode 136 is disposed between the seventh circuit layer 122 and the eighth circuit layer 123; the seventh via electrode 137 is disposed between the eighth circuit layer 123 and the ninth circuit layer 124; the eighth via electrode 138 is disposed between the ninth circuit layer 124 and the tenth circuit layer 125; the ninth via electrode 139 is disposed between the tenth circuit layer 125 and the eleventh circuit layer 126; and the tenth via electrode 140 is disposed between the eleventh circuit layer 126 and the twelfth circuit layer 127, thereby electrically connecting the seventh circuit layers 122, 123, 124, 125, 126, and 127.

[0098] Similar to the above description of the first to fifth via electrodes 131, 132, 133, 134, and 135 of the first stacked layer 102, the sixth to tenth via electrodes 136, 137, 138, 139, and 140 can also be configured simultaneously during the process of configuring the eighth to twelfth circuit layers 123, 124, 125, 126, and 127. Therefore, similar to the above description, the seventh via electrode 137 can be distinguished as a protrusion of the ninth circuit layer 124. However, since the eighth to twelfth circuit layers 123, 124, 125, 126, and 127 are stacked in a different direction than the first stacked layer 102, the tilt direction of each via electrode 131, 132, 133, 134, and 135 of the first stacked layer 102 can be opposite to the tilt direction of each via electrode 136, 137, 138, 139, and 140 of the second stacked layer 103. For example, each via electrode 131, 132, 133, 134, and 135 of the first stacked layer 102 may have a sloped portion in which the width becomes narrower toward the glass layer 101, and each via electrode 136, 137, 138, 139, and 140 of the second stacked layer 103 may also have a sloped portion in which the width becomes narrower toward the glass layer 101. For example, the sloped portions of each via electrode 131, 132, 133, 134, and 135 of the first stacked layer 102 may be symmetrical with respect to the sloped portions of the glass layer 101 of each via electrode 136, 137, 138, 139, and 140 of the second stacked layer 103.

[0099] The seventh circuit layer 122 can contact the second surface of the glass layer 101. In this case, a portion of the seventh circuit layer 122 can be configured to cover the aforementioned insulating member 142. That is, the lower surface of the seventh circuit layer 122 may include a first portion of the lower surface of the contact core via electrode 141, a second portion of the lower surface of the contact insulating member 142, and a third portion of the lower surface of the glass layer 101.

[0100] The plurality of insulating layers 111, 112, 113, 114, and 115 of the second stacked layer 103 may include a sixth insulating layer 111 closest to the glass layer 101 in the vertical direction, a seventh insulating layer 112 disposed below the sixth insulating layer 111, an eighth insulating layer 113 disposed below the seventh insulating layer 112, a ninth insulating layer 114 disposed below the eighth insulating layer 113, and a tenth insulating layer 115 disposed below the ninth insulating layer 114. The sixth to tenth insulating layers 111, 112, 113, 114, and 115 are configured for vertical insulation between the seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127. Furthermore, for example, the sixth to tenth insulating layers 111, 112, 113, 114, and 115 may use a thermosetting insulating material in which inorganic fillers are contained in the resin, and Ajinomoto's ABF (Ajinomoto stacked film) may be used. However, the embodiments are not limited to this, and photoimageable dielectrics (PIDs) can be used to form fine patterns.

[0101] The second protective layer 105 protects the twelfth circuit layer 127 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 100 using materials such as solder, the second protective layer 105 prevents short circuits between solders due to low wettability with the solder. The second protective layer 105 can be made of a photocurable insulating material, and for example, a solder resist can be used.

[0102] The above-described structure of circuit board 100 is merely for describing embodiments of this disclosure, and the technical concept of this disclosure is not limited to the stacked structure of this embodiment.

[0103] Depending on the heat and / or pressure applied during the process, the thickness of each insulating layer, the thickness of each protective layer, and the density or thickness of the circuit layers, distortion may occur in the circuit board 100. Distortion includes distortion in the smiling direction (U) and distortion in the crying direction (∩), and distortion in these two directions can be applied in combination. Distortion in the smiling direction means that the upper and / or lower surfaces of the circuit board 100 are concavely distorted, such that the center is lower than the edges of the circuit board 100, and may also be referred to as the concave direction. Furthermore, distortion in the crying direction is the opposite direction to distortion in the smiling direction, and means that the upper and / or lower surfaces of the circuit board 100 are convexly distorted, such that the center is higher than the edges of the circuit board 100, and may also be referred to as the convex direction.

[0104] This distortion of the circuit board 100 can be a factor causing uneven bonding, such as solder jointing, between the semiconductor devices disposed on the first protective layer 104 and the circuit board 100 throughout the circuit board 100, thus reducing the reliability of the semiconductor package. To address this issue, embodiments modify the position of the via electrode 141 within the insulating member 142 disposed in the glass layer 101. That is, when the insulating member 142 and the via electrode 141 are disposed without considering the direction of the circuit board distortion, the horizontal central axis of the insulating member 142 and the horizontal central axis of the via electrode 141 can coincide (or align) with each other. Conversely, embodiments can modify the position of the via electrode 141 within the insulating member 142 considering the direction of the circuit board 100 distortion, and therefore, the horizontal central axis of the insulating member 142 and the horizontal central axis of the via electrode 141 can be offset from each other.

[0105] Figure 2a and Figure 2b An example is shown showing the positional relationship between the horizontal central axis of the insulating member 142 and the horizontal central axis of the core via electrode 141. For example, the circuit board 100 includes a plurality of core via electrodes 141. Figure 2a One of a plurality of through-hole electrodes 141 may be shown, and Figure 2b Another of the multiple core via electrodes 141 can be shown.

[0106] exist Figure 2a In the diagram, (a) is a cross-sectional view showing one of the plurality of through-hole electrodes 141, and (b) is... Figure 2a A plan view of the core via electrode shown in (a).

[0107] Reference Figure 2aIn (a) and (b), the glass layer 201 includes a through-hole, and an insulating member 204 is disposed in the through-hole of the glass layer 201. In this case, the through-hole of the glass layer 201 is formed by performing a laser process on the upper surface of the glass layer 201, and therefore, it can have an inclined portion such that the width in the horizontal direction gradually decreases along the direction from the upper surface to the lower surface. For example, the through-hole in the glass layer 201 can be formed by irradiating the glass layer 201 with a CO2 laser to change the crystallinity of a region of the glass layer 201, and then removing the region of the glass layer 201 in which the crystallinity has been changed by wet etching with hydrofluoric acid (HF) or the like. However, this is not a limitation. The insulating member 204 is disposed in the through-hole of the glass layer 201 and has an inclined portion corresponding to the inner wall of the through-hole of the glass layer 201. That is, the insulating member 204 can be inclined such that the width in the horizontal direction gradually decreases along the direction from the upper surface to the lower surface. When the insulating member 204 has a slope such that its width gradually decreases along the direction from the upper surface to the lower surface, the manufacturing process of the circuit board 100 can be simplified, and thus the yield can be improved. For example, a through-hole can be formed by performing a laser process on each of the upper and lower surfaces of the glass layer 201, so each of the through-hole in the glass layer 201 and the insulating member 204 can have an hourglass shape. In this case, the laser process for forming the through-hole in the glass layer 201 should be performed separately on both surfaces of the glass layer 201, and thus the number of manufacturing processes may increase, and the yield may decrease as the laser process is performed on both sides of the glass layer 201. Conversely, the through-hole and the insulating member 204 provided in the glass layer 201 can have a slope such that the width in the horizontal direction gradually decreases along the direction from the upper surface to the lower surface, and thus the manufacturing process can be simplified to improve the yield. Furthermore, the through-hole is a space filled with the insulating member 204 rather than the via electrode, and therefore, unlike the via electrode, it is not necessary to consider the electroplating processability and dimensions (e.g., the width of the upper surface and the width of the lower surface) as much. Therefore, the insulating member 204 can have only one inclined portion, such that the width gradually decreases along the direction from the upper surface to the lower surface, and thus, the yield can be improved.

[0108] The insulating member 204 includes a through-hole. The through-hole, disposed in the insulating member 204, penetrates both the upper and lower surfaces of the insulating member 204. The through-hole may include a first portion and a second portion. The first portion is inclined such that its width in the horizontal direction gradually decreases along the direction from the upper surface of the insulating member 204 towards the lower surface. The second portion is disposed below the first portion and is also inclined such that its width in the horizontal direction gradually increases along the direction from the upper surface of the insulating member 204 towards the lower surface. A core through-hole electrode 205 is disposed in the through-hole of the insulating member 204. The core through-hole electrode 205 electrically connects circuit layers 202 and 203, respectively disposed on the upper and lower surfaces of the glass layer 201. The core through-hole electrode 205 has an inclined portion corresponding to the inclined portion of the inner wall of the through-hole of the insulating member 204. The via electrode 205 may include a first portion 206 and a second portion 207. The first portion 206 is inclined such that its width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer 201 toward the lower surface of the glass layer 201. The second portion 207 is inclined such that its width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer 201 toward the lower surface of the glass layer 201. Each of the inclined portions of the first portion 206 and the second portion 207 of the via electrode 205 overlaps with the inclined portion of the insulating member 204 in the horizontal direction. The inclination angle of the inclined portion of the second portion 207 of the via electrode 205 may be different from the inclination angle of the inclined portion of the insulating member 204. The inclination angle of the inclined portion of the first portion 206 of the via electrode 205 may correspond to the inclination angle of the inclined portion of the insulating member 204. Here, "corresponding" may mean that the two inclined portions are inclined in the same direction and the difference between their angles is within 10 degrees. That is, the inclined portion of the insulating member 204 and the inclined portion of the first part 206 of the core through-hole electrode 205 are inclined in the same direction, and the inclined portion of the second part 207 of the core through-hole electrode 205 can be inclined in a direction different from the inclined direction of each of the inclined portions of the insulating member 204 and the inclined portion of the first part 206.

[0109] That is, the core via electrode 205 can be divided into multiple parts based on the inclined portion of the side surface. By allowing the core via electrode 205 to include a first part 206 and a second part 207 with different inclined portions, the machinability in the electroplating process of the core via electrode 205 can be improved, and therefore, the electrical reliability can be improved.

[0110] For example, the via electrode 205 may include only one inclined portion identical to the inclined portion of the insulating member 204. In this case, the difference between the width of the upper surface of the via electrode 205 and the width of the lower surface of the via electrode 205 increases to correspond to the inclined portion of the via electrode 205, and therefore, the electrical characteristics may be degraded during signal transmission. Furthermore, when the difference between the width of the upper surface of the via electrode 205 and the width of the lower surface of the via electrode 205 increases, in order for the via electrode 205 to penetrate the insulating member 204, the width of the upper surface of the via electrode 205 may be excessively increased compared to the embodiment, and therefore, the circuit integration density may be reduced. In addition, when the width of the upper surface of the via electrode 205 increases, the via electrode 205 may not be densely filled in the via of the insulating member 204, and therefore, gaps are provided in the via electrode 205. Furthermore, voids expand due to heat generated during semiconductor packaging operations and become a factor reducing the mechanical reliability of the circuit board. Therefore, the embodiments allow the via electrode 205 to include a first portion 206 and a second portion 207 with different tilted portions, thereby preventing an increase in the size of the via electrode 205 and preventing voids from being formed in the via electrode 205. Therefore, the embodiments can improve the circuit integration of the circuit board and can improve electrical and / or mechanical reliability.

[0111] Furthermore, in one embodiment, the vertical length of the first portion 206 of the via electrode 205 may correspond to the vertical length of the second portion 207. Here, "corresponding" may mean that the deviation between their lengths is within 5%. By allowing the vertical lengths of the first portion 206 and the second portion 207 of the via electrode 205 to correspond to each other, the electroplating process of the via electrode 205 can be performed more smoothly, and furthermore, distortion of the circuit board 100 in a specific direction due to the asymmetrical structure of the first portion 206 and the second portion 207 of the via electrode 205 can be prevented.

[0112] In this case, the horizontal central axis x1 of the insulating member 204 may not be aligned with the horizontal central axis x2 of the core via electrode 205, and they may be spaced apart in the horizontal direction. That is, the horizontal central axis x1 of the insulating member 204 and the horizontal central axis x2 of the core via electrode 205 may be offset from each other. Here, when the upper surface of the insulating member 204 has a circular or elliptical shape, the horizontal central axis x1 of the insulating member 204 may refer to the intersection of the major and minor axes of the upper surface of the insulating member 204. Alternatively, when the upper surface of the insulating member 204 has a rectangular shape, the horizontal central axis x1 of the insulating member 204 may refer to the point where the line segments connecting two opposite vertices on the upper surface of the insulating member 204 meet. Correspondingly, the horizontal central axis x2 of the core via electrode 205 may refer to the intersection of the major and minor axes, or the point where the two line segments connecting two opposite vertices meet.

[0113] The horizontal central axis x1 of the insulating member 204 and the horizontal central axis x2 of the core via electrode 205 are offset from each other, and for example, they may have a horizontal spacing distance w2. For example, the central axis x2 of the core via electrode 205 may be offset horizontally by a spacing distance w2 relative to the central axis x1 of the insulating member 204. Here, offset may mean that the central axis x2 of the core via electrode 205 and the central axis x1 of the insulating member 204 are not aligned in the vertical direction and are offset from each other. For example, the aforementioned offset may mean applying different horizontal distances from the horizontal central axis x0 of the glass layer to the central axis x2 of the core via electrode 205 and from the horizontal central axis x0 of the glass layer to the central axis x1 of the insulating member 204, and for example, it may mean that the horizontal distance from the horizontal central axis x0 of the glass layer to the central axis x2 of the core via electrode 205 is less than the horizontal distance from the horizontal central axis x0 of the glass layer to the central axis x1 of the insulating member 204. Furthermore, the aforementioned offset refers to the relationship between the central axis x0 of the glass layer in the horizontal direction and the central axis x2 of the core via electrode 205, and in the following text, for ease of description, the term "offset" will be used in the above sense.

[0114] The twisting of the circuit board 100 in a specific direction can be mitigated based on the offset direction and distance of the central axis x2 of the via electrode 205 relative to the central axis x1 of the insulating member 204. In this case, the twisting of the circuit board 100 in a specific direction may occur based on the offset direction and distance of the central axis x2 of the via electrode 205 relative to the central axis x1 of the insulating member 204, and the aforementioned mitigation may mean offsetting the central axis x2 of the via electrode 205 such that the twisting of the circuit board occurs in a direction opposite to the twisting direction of the circuit board 100 before the aforementioned offset is performed. By offsetting the central axis x2 of the via electrode 205 relative to the central axis x1 of the insulating member 204 with the twisting direction of the circuit board 100 as a reference, the twisting of the circuit board 100 in a specific direction can be prevented, excessive stress can be avoided on the circuit board, and thus, the mechanical and / or electrical reliability of the circuit board can be improved. Furthermore, the embodiment can mitigate the twisting of the circuit board, allowing semiconductor devices to be stably attached to the circuit board. In this situation, when the circuit board is twisted in a particular direction, height discrepancies may occur between multiple joints on the circuit board, and the terminals of the semiconductor devices may not be stably attached to the multiple joints. Conversely, the embodiment can mitigate the overall twisting of the circuit board by offsetting the central axis x2 of the via electrode 205, and can allow the semiconductor devices to be stably attached to the circuit board. Therefore, the embodiment can allow the semiconductor devices to operate stably, thereby improving product reliability. Furthermore, the embodiment can allow products such as servers using semiconductor packaging to operate stably.

[0115] Furthermore, since the central axis x2 of the core via electrode 205 in the horizontal direction is offset relative to the central axis x1 of the insulating member 204 in the horizontal direction, the width of the insulating member 204 in the horizontal direction can have different widths in the horizontal direction along the circumferential direction of the upper surface of the core via electrode 205.

[0116] That is, the insulating member 204 may have a first width w1 in the horizontal direction at the first side end of the core via electrode 205, with a vertical cross-section as a reference, and may have a second width w2 in the horizontal direction, different from the first width w1, at the second side end opposite to the first side end. Furthermore, the insulating member 204 is arranged along the circumference of the core via electrode 205, and its width in the horizontal direction may vary along the circumference of the core via electrode 205. Furthermore, the width of the insulating member 204 in the horizontal direction can be determined based on the offset direction and offset distance of the central axis x2 of the core via electrode 205. Moreover, the embodiment can reduce the overall distortion of the circuit board 100 by allowing the widths of the insulating members 204 in the horizontal direction to differ from each other along the circumference of the core via electrode 205.

[0117] in this case, Figure 2a It is shown that the central axis x2 of the core via electrode 205 in the horizontal direction is offset relative to the central axis x1 of the insulating member 204 in the horizontal direction in the first horizontal direction, and Figure 2b The core via electrode is shown offset in a second horizontal direction opposite to the first horizontal direction.

[0118] Reference Figure 2b In (a) and (b), the glass layer 208 includes a through hole, and an insulating member 211 is disposed in the through hole of the glass layer 208. The insulating member 211, disposed in the through hole of the glass layer 208, also has an inclined portion corresponding to the inner wall of the through hole of the glass layer 208. That is, the insulating member 211 can be inclined such that its width in the horizontal direction gradually decreases along the direction from the upper surface to the lower surface. The insulating member 211 includes a through hole. The through hole disposed in the insulating member 211 penetrates both the upper and lower surfaces of the insulating member 211. The through hole disposed in the insulating member 211 may include a first portion and a second portion, the first portion being inclined such that its width in the horizontal direction gradually decreases along the direction from the upper surface to the lower surface of the insulating member 211, and the second portion being disposed below the first portion and inclined such that its width in the horizontal direction gradually increases along the direction from the upper surface to the lower surface of the insulating member 211. A core through-hole electrode 212 is disposed in the through hole of the insulating member 211. The via electrode 212 has an inclined portion corresponding to the inclined portion of the inner wall of the via of the insulating member 211. The via electrode 212 may include a first portion 213 and a second portion 214. The first portion 213 is inclined such that its width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer 208 toward the lower surface of the glass layer 208, and the second portion 214 is inclined such that its width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer 208 toward the lower surface of the glass layer 208. Each of the inclined portions of the first portion 213 and the second portion 214 of the via electrode 212 overlaps with the inclined portion of the insulating member 211 in the horizontal direction. The inclination angle of the inclined portion of the second portion 214 of the via electrode 212 may be different from the inclination angle of the inclined portion of the insulating member 211. The inclination angle of the inclined portion of the first portion 213 of the via electrode 212 may correspond to the inclination angle of the inclined portion of the insulating member 211. Here, "corresponding" can mean that the two inclined portions are inclined in the same direction and the difference between their angles is within 10 degrees. That is, the inclined portion of the insulating member 211 and the inclined portion of the first part 213 of the core through-hole electrode 212 are inclined in the same direction, and the inclined portion of the second part 214 of the core through-hole electrode 212 can be inclined in a direction different from the inclined direction of each of the inclined portions of the insulating member 211 and the first part 213.

[0119] The horizontal central axis x3 of the insulating member 211 may not be aligned with the horizontal central axis x4 of the core via electrode 212, and may be spaced apart in the horizontal direction. That is, the horizontal central axis x3 of the insulating member 211 and the horizontal central axis x4 of the core via electrode 212 may be offset from each other. The horizontal central axis x3 of the insulating member 211 and the horizontal central axis x4 of the core via electrode 214 are offset from each other, and for example, may have a horizontal spacing distance w4. For example, the central axis x4 of the core via electrode 212 may be offset horizontally by a spacing distance w6 relative to the central axis x3 of the insulating member 211. Furthermore, depending on the offset direction and offset distance of the central axis x4 of the core via electrode 212 relative to the central axis x3 of the insulating member 211, the twisting of the circuit board 100 in a certain direction can be mitigated. In this case, based on the offset direction and offset distance of the central axis x4 of the via electrode 214 relative to the central axis x3 of the insulating member 211, a twist in a specific direction of the circuit board 100 can be generated. The aforementioned mitigation can refer to the offset of the central axis x4 of the via electrode 212, causing the twist of the circuit board to occur in a direction opposite to the twist direction of the circuit board 100 before the aforementioned offset was performed. By offsetting the central axis x4 of the via electrode 212 relative to the central axis x3 of the insulating member 211 with the twist direction of the circuit board 100 as a reference, twisting of the circuit board 100 in a specific direction can be prevented, excessive stress can be avoided on the circuit board, and thus, the mechanical and / or electrical reliability of the circuit board can be improved. Furthermore, the embodiment can mitigate the twist of the circuit board, allowing semiconductor devices to be stably attached to the circuit board. In this case, when the circuit board twists in a specific direction, height deviations may occur between multiple joints disposed on the circuit board, and the terminals of the semiconductor devices may not be stably attached to the multiple joints. Conversely, the embodiment can mitigate overall circuit board distortion by offsetting the central axis x4 of the via electrode 212, and can allow semiconductor devices to be stably attached to the circuit board. Therefore, the embodiment can allow semiconductor devices to operate stably, thereby improving product reliability. Furthermore, the embodiment can allow products such as servers that utilize semiconductor packaging to operate stably.

[0120] Furthermore, since the horizontal central axis x4 of the via electrode 212 is offset relative to the horizontal central axis x3 of the insulating member 211, the horizontal width of the insulating member 211 can have different widths in the horizontal direction along the circumferential direction of the upper surface of the via electrode 212. That is, the insulating member 211 can have a fourth width w4 in the horizontal direction at the first side end of the via electrode 212, based on a vertical cross-section, and can have a fifth width w5 in the horizontal direction at the second side end opposite to the first side end, which is different from the fourth width w4. Furthermore, the insulating member 211 is arranged along the circumference of the via electrode 212, and its horizontal width can vary along the circumferential direction of the via electrode 212. Furthermore, the horizontal width of the insulating member 211 can be determined based on the offset direction and offset distance of the central axis x4 of the via electrode 212. Moreover, the embodiment can reduce the overall distortion of the circuit board 100 by allowing the horizontal widths of the insulating members 211 to differ from each other along the circumferential direction of the via electrode 212.

[0121] In this case, the aforementioned offset direction and offset distance can be determined based on the twisting direction of the circuit board 100 and the position of the core via electrode within the circuit board. For example, multiple core via electrodes can be provided in the circuit board 100, and these multiple core via electrodes can have different offset directions and offset distances depending on their respective positions. Here, the offset direction and offset distance can be determined by the direction pointed to by the central axis x0 in the horizontal direction of the glass layer and the distance spaced from the central axis x0 in the horizontal direction of the glass layer.

[0122] according to Figure 3 In one embodiment, the circuit board includes a plurality of insulating members 304 and 306 disposed in a glass layer 301, and a plurality of via electrodes 305 and 307. Furthermore, the plurality of via electrodes 305 and 307 electrically connect circuit layers 302 and 303 disposed on the upper and lower surfaces of the glass layer 301. In this case, the plurality of via electrodes 305 and 307 may be located in different directions relative to the central axis x0 of the glass layer 301. In this case, the central axis x0 of the glass layer 301 may refer to the point where two line segments connecting two opposite vertices of a plane relative to the glass layer 301 meet.

[0123] The plurality of insulating members 304 and 306 include a first insulating member 304 located at a first side end relative to the central axis x0 of the glass layer 301, and a second insulating member 306 located at a second side end opposite to the first side end relative to the central axis x0 of the glass layer 301. Furthermore, the plurality of via electrodes 305 and 307 include a first via electrode 305 penetrating the first insulating member 304 and a second via electrode 306 penetrating the second insulating member 305. Moreover, the offset direction of the central axis x1 of the first via electrode 305 in the first insulating member 304 may differ from the offset direction of the central axis x4 of the second via electrode 306 in the second insulating member 305.

[0124] That is, the central axis x2 of the first via electrode 305 can be offset relative to the central axis x1 of the first insulating member 304 in a first horizontal direction (offset 1). Specifically, the central axis x2 of the first via electrode 305 can be offset relative to the central axis x1 of the first insulating member 304 in a direction toward the central axis x0 in the horizontal direction toward the glass layer 301 (offset 1). Conversely, the central axis x4 of the second via electrode 307 can be offset relative to the central axis x3 of the second insulating member 306 in a second horizontal direction opposite to the first horizontal direction (offset 2). Specifically, the central axis x4 of the second via electrode 307 can be offset relative to the central axis x3 of the second insulating member 306 in a direction toward the central axis x0 in the horizontal direction toward the glass layer 301 (offset 2). That is, the multiple via electrodes 305 and 307 can be offset in a direction toward the central axis x0 of the glass layer 301 in each insulating member 304 and 306, and therefore, the twisting of the circuit board 100 in a specific direction can be further reduced. For example, when the circuit board 100 is twisted in the slant direction, the first core via electrode 305 located at the first side end of the central axis x0 in the horizontal direction of the glass layer 301 can be offset relative to the first insulating member 304 in the first horizontal direction (offset 1), and the second core via electrode 307 located at the second side end of the central axis x0 in the horizontal direction of the glass layer 301 can be offset relative to the second insulating member 306 in the second horizontal direction opposite to the first horizontal direction (offset 2), and thus, the overall twist of the circuit board can be further reduced. Conversely, when the circuit board 100 is twisted in the welt direction, the first core via electrode 305 located at the first side end of the central axis x0 in the horizontal direction of the glass layer 301 can be offset relative to the first insulating member 304 in the second horizontal direction (offset 2), and the second core via electrode 307 located at the second side end of the central axis x0 in the horizontal direction of the glass layer 301 can be offset relative to the second insulating member 306 in the first horizontal direction opposite to the second horizontal direction (offset 1), and thus, the overall twist of the circuit board can also be further reduced.

[0125] according to Figure 4 In one embodiment, the glass layer 401 includes a plurality of insulating members 402, 404, 406, 408, 410, 412, 414, and 416 located in different horizontal directions relative to the central axis x0 in the horizontal direction of the glass layer 401, and a plurality of via electrodes 403, 405, 407, 409, 411, 413, 415, and 417. The plurality of via electrodes 403, 405, 407, 409, 411, 413, 415, and 417 may be offset in different directions within each insulating member 402, 404, 406, 408, 410, 412, 414, and 416, and for example, may be offset in the direction toward the central axis x0 in the horizontal direction of the glass layer 401.

[0126] For example, a first insulating member 402 and a first core via electrode 403 are disposed to the left of the central axis x0 in the horizontal direction of the glass layer 401. The first core via electrode 403 can be offset (offset 1) in the first horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 401 within the first insulating member 402.

[0127] Furthermore, a second insulating member 404 and a second core via electrode 405 are provided to the right of the central axis x0 in the horizontal direction of the glass layer 401. The second core via electrode 405 can be offset (offset 2) in a second horizontal direction within the second insulating member 404 toward the central axis x0 in the horizontal direction of the glass layer 401.

[0128] Furthermore, a third insulating member 406 and a third core via electrode 407 are provided on the rear side of the central axis x0 in the horizontal direction of the glass layer 401. The third core via electrode 407 can be offset (offset 3) in the third horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 401 within the third insulating member 406.

[0129] Furthermore, a fourth insulating member 408 and a fourth core via electrode 409 are provided on the front side of the central axis x0 in the horizontal direction of the glass layer 401. The fourth core via electrode 409 can be offset (offset 4) in the fourth horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 401 within the fourth insulating member 408.

[0130] Furthermore, a fifth insulating member 410 and a fifth core via electrode 411 are provided on the left rear side of the central axis x0 in the horizontal direction of the glass layer 401. The fifth core via electrode 411 can be offset (offset 5) within the fifth insulating member 410 in the fifth horizontal direction toward the central axis x0 in the horizontal direction of the glass layer 401.

[0131] Furthermore, a sixth insulating member 412 and a sixth core via electrode 413 are provided on the right rear side of the central axis x0 in the horizontal direction of the glass layer 401. The sixth core via electrode 413 can be offset (offset 6) in the sixth horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 401 within the sixth insulating member 412.

[0132] Furthermore, a seventh insulating member 414 and a seventh core via electrode 415 are provided on the left front side of the central axis x0 in the horizontal direction of the glass layer 401. The seventh core via electrode 415 can be offset (offset 7) within the seventh insulating member 414 in the seventh horizontal direction toward the central axis x0 in the horizontal direction of the glass layer 401.

[0133] Furthermore, an eighth insulating member 416 and an eighth core via electrode 417 are provided on the right front side of the central axis x0 in the horizontal direction of the glass layer 401. The eighth core via electrode 417 can be offset (offset 7) within the eighth insulating member 416 in the eighth horizontal direction toward the central axis x0 in the horizontal direction of the glass layer 401.

[0134] Furthermore, the plurality of via electrodes spaced apart from each other on one side of the central axis x0 in the horizontal direction of the glass layer 401 can be offset by different offset distances in the same direction. That is, the plurality of via electrodes disposed on one side of the central axis x0 in the horizontal direction of the glass layer 401 can be offset in a direction toward the central axis x0 in the horizontal direction of the glass layer 401, and the offset distance can be increased according to the distance spaced apart from the central axis x0 in the horizontal direction of the glass layer 401. For example, the via electrodes spaced apart at a first distance on one side of the central axis x0 in the horizontal direction of the glass layer 401 can be offset by a first offset distance toward the central axis x0 in the horizontal direction of the glass layer 401, and the via electrodes spaced apart at a second distance greater than the first distance on one side of the central axis x0 in the horizontal direction of the glass layer 401 can be offset by a second offset distance greater than the first offset distance toward the central axis x0 in the horizontal direction of the glass layer 401.

[0135] As described above, considering the placement positions of the corresponding insulating members and the core via electrodes relative to the central axis x0 in the horizontal direction of the glass layer 401, the multiple core via electrodes 403, 405, 407, 409, 411, 413, 415 and 417 can be offset in different directions and / or different distances within the respective insulating members 402, 404, 406, 408, 410, 412, 414 and 416, and thus, the overall distortion of the circuit board can be further reduced, allowing for a more stable placement of semiconductor devices.

[0136] In the following text, although references to Figure 1 to 1 are included... Figure 5The described structure (e.g., the offset direction of the core via electrode within the insulating member and the individual offset directions of the plurality of core via electrodes) is used as the basic structure, but various variations of the insulating member and / or the core via electrode will be described.

[0137] according to Figure 5 In one embodiment, the circuit board includes a glass layer 501 having a plurality of through holes spaced apart from each other in a horizontal direction, and includes a plurality of insulating members 504 and 508 disposed in the through holes of the glass layer 501, as well as a plurality of core via electrodes 505 and 509. Furthermore, the plurality of core via electrodes 505 and 509 electrically connect circuit layers 502 and 503 disposed on the upper and lower surfaces of the glass layer 501. In this case, the plurality of core via electrodes 505 and 509 may be located in different directions relative to the central axis x0 of the glass layer 501. In this case, the central axis x0 of the glass layer 501 may refer to the point where two line segments connecting two opposite vertices relative to the plane of the glass layer 501 meet.

[0138] The plurality of insulating members 504 and 508 include a first insulating member 504 located on a first side relative to the central axis x0 of the glass layer 501, and a second insulating member 508 located on a second side opposite to the first side relative to the central axis x0 of the glass layer 501. Furthermore, the plurality of via electrodes 505 and 509 include a first via electrode 505 penetrating the first insulating member 504 and a second via electrode 509 penetrating the second insulating member 505. Moreover, the offset direction of the central axis of the first via electrode 505 in the first insulating member 504 may differ from the offset direction of the central axis of the second via electrode 509 in the second insulating member 505. For example, each of the first via electrode 505 and the second via electrode 509 may be offset (offset 1, offset 2) within the respective insulating members 504 and 508 in a direction toward the central axis in the horizontal direction toward the glass layer 501.

[0139] The first via electrode 505 and the second via electrode 509 can have different vertical cross-sectional shapes. For example, the first via electrode 505 includes a first portion 506 and a second portion 507. The first portion 506 has an inclined portion such that its width in the horizontal direction gradually decreases along the vertical direction from the upper surface of the glass layer 501 toward the lower surface of the glass layer 501. The second portion 507 is disposed below the first portion 506 and has an inclined portion such that its width in the horizontal direction gradually increases along the vertical direction from the upper surface of the glass layer 501 toward the lower surface of the glass layer 501. In this case, the thickness T1 in the vertical direction of the first portion 506 and the thickness T2 in the vertical direction of the second portion 507 can be different from each other. For example, in the previous embodiment, the first portion and the second portion of the via electrode can have corresponding thicknesses in the vertical direction and can have a symmetrical shape. Alternatively, the first portion 506 and the second portion 507 of the first via electrode 505 can have different thicknesses in the vertical direction. For example, the vertical thickness T1 of the first portion 506 of the first via electrode 505 can be greater than the vertical thickness T2 of the second portion 507 of the first via electrode 505. Furthermore, the second via electrode 509 includes a first portion 510 and a second portion 511. The first portion 510 has an inclined portion such that its horizontal width gradually decreases along a vertical direction from the upper surface of the glass layer 501 toward the lower surface of the glass layer 501. The second portion 511 is disposed below the first portion 510 and has an inclined portion such that its horizontal width gradually increases along a vertical direction from the upper surface of the glass layer 501 toward the lower surface of the glass layer 501. In this case, the vertical thickness T3 of the first portion 510 and the vertical thickness T4 of the second portion 511 can be different from each other. For example, the vertical thickness T3 of the first portion 510 of the second via electrode 509 can be less than the vertical thickness T4 of the second portion 511 of the second via electrode 509. Therefore, the embodiment can improve the electroplating capability in the process of electroplating multiple core via electrodes 505 and 509 by adjusting the thicknesses T1, T2, T3, and T4 in the vertical direction of the first portions 506 and 510 and the second portions 507 and 511 of the multiple core via electrodes 505 and 509. For example, the ratio of the thickness T1 in the vertical direction of the first portion 506 of the first core via electrode 505 to the thickness T2 in the vertical direction of the second portion 507 can satisfy a range of 7:3 to 8:2.When the ratio of the thickness T1 in the vertical direction of the first portion 506 of the first via electrode 505 to the thickness T2 in the vertical direction of the second portion 507 is outside the range of 7:3 to 8:2, the problems of voids in the first via electrode 505 due to its small width at the midpoint where the first portion 506 and the second portion 507 meet, and the reduced flatness of the circuit layers 502 and 503 connected to the first via electrode 505 due to its large width at the midpoint where the first portion 506 and the second portion 507 meet, can be solved. Furthermore, correspondingly, the ratio of the thickness T3 in the vertical direction of the first portion 510 of the second via electrode 509 to the thickness T4 in the vertical direction of the second portion 511 can satisfy the range of 2:8 to 3:7, and therefore, the problems of voids in the second via electrode 509 and the reduced flatness of the circuit layers 502 and 503 can be solved. Furthermore, by adjusting the ratio of the thicknesses T1, T2, T3, and T4 in the vertical direction of the first portions 506 and 510 and the second portions 507 and 511 of the multiple via electrodes 505 and 509, the process capability in the electroplating process of the multiple via electrodes 505 and 509 can be improved, thereby reducing manufacturing time and increasing yield. Additionally, by preventing gaps in the multiple via electrodes 505 and 509, cracks in the multiple via electrodes 505 and 509 due to stress from thermal cycling can be prevented, thereby improving the electrical reliability of the circuit board. Furthermore, the ratio of the thicknesses T1, T2, T3, and T4 in the vertical direction of the first portions 506 and 510 and the second portions 507 and 511 of the multiple via electrodes 505 and 509 can be determined considering the direction of the circuit board 100's twist. For example, when the circuit board is twisted in a smiling shape such as "∪", the first via electrode 505 and the second via electrode 509 can both be configured such that the thickness of the first portions 506 and 511 in the vertical direction is greater than the thickness of the second portions 507 and 511 in the vertical direction. Furthermore, when the circuit board is twisted in a crying shape such as "∩", the first via electrode 505 and the second via electrode 509 can both be configured such that the thickness of the first portions 506 and 511 in the vertical direction is less than the thickness of the second portions 507 and 511 in the vertical direction. That is, the first via electrode 505 and the second via electrode 509 can have the same shape depending on the direction of the circuit board twist, while the ratio of the thickness of the first portions 506 and 511 in the vertical direction to the thickness of the second portions 507 and 511 in the vertical direction can be changed. Therefore, the embodiment can more effectively prevent the circuit board from twisting in a particular direction and can allow for more stable mounting of semiconductor devices.

[0140] according to Figure 6In one embodiment, the circuit board includes a glass layer 601, an insulating member 605 penetrating the glass layer 601, and a core via electrode 608 penetrating the insulating member 605. The core via electrode 608 can electrically connect circuit layers 602 and 603 disposed on the upper and lower surfaces of the glass layer 601.

[0141] The insulating member 605 may have a shape corresponding to the via electrode 608. That is, in the previous embodiment, the insulating member may only include a sloping portion in which the width in the horizontal direction decreases along a vertical direction from the upper surface of the glass layer toward the lower surface. Conversely, the insulating member 605 may include a first portion 606 and a second portion 607, the first portion 606 having a sloping portion such that its width in the horizontal direction narrows along a vertical direction from the upper surface of the glass layer 601 toward the lower surface of the glass layer 601, and the second portion 607 having a sloping portion such that its width in the horizontal direction widens along a vertical direction from the upper surface of the glass layer 601 toward the lower surface of the glass layer 601. Therefore, the size of the insulating member 605 surrounding the via electrode 608 can be reduced. For example, when the insulating member includes only one sloping portion as in the previous embodiment, the size of the via in the glass layer and the size of the corresponding insulating member should increase, and therefore, the rigidity of the circuit board may decrease corresponding to the area occupied by the via in the glass layer. Conversely, when the insulating member 605 includes a first portion 606 and a second portion 607 with different inclined sections, the area occupied by the through-hole in the glass layer 601 can be reduced, and therefore, the rigidity of the circuit board can be further improved. In this case, although not shown in the figures, the thickness of the first portion 606 and the thickness of the second portion 607 in the vertical direction of the glass layer 601 can be the same as or different from each other.

[0142] Furthermore, the via electrode 608 is configured to penetrate the insulating member 605. The via electrode 608 may include a first portion 609 and a second portion 610. The first portion 609 is inclined such that its width in the horizontal direction narrows along a vertical direction from the upper surface of the glass layer 601 toward the lower surface of the glass layer 601. The second portion 610 is disposed below the first portion 609 and is inclined such that its width in the horizontal direction widens along a vertical direction from the upper surface of the glass layer 601 toward the lower surface of the glass layer 601. Furthermore, the vertical thickness of the first portion 609 and the vertical thickness of the second portion 610 of the via electrode 608 may be the same as or different from each other.

[0143] Furthermore, considering the direction of circuit board twist, the vertical thickness of the first portion 606 of glass layer 601 can be greater than the vertical thickness of the second portion 607 of glass layer 601, and the vertical thickness of the first portion 609 of via electrode 608 can be less than the vertical thickness of the second portion 610 of via electrode 608. Conversely, considering the direction of circuit board twist, the vertical thickness of the first portion 606 of glass layer 601 can be less than the vertical thickness of the second portion 607 of glass layer 601, and the vertical thickness of the first portion 609 of via electrode 608 can be greater than the vertical thickness of the second portion 610 of via electrode 608. Therefore, considering the direction of circuit board twist, the embodiment can further improve the overall twist of the circuit board by additionally adjusting the shape of glass layer 601 and the vertical thickness of the first and second portions of glass layer 601.

[0144] according to Figure 7 In one embodiment, the circuit board includes a glass layer 701, an insulating member 705 penetrating the glass layer 701, and a core via electrode 708 penetrating the insulating member 705. The core via electrode 708 can electrically connect circuit layers 702 and 703 disposed on the upper and lower surfaces of the glass layer 701.

[0145] The insulating member 705 may include a first portion 706 and a second portion 707. The first portion 706 has an inclined portion such that its width in the horizontal direction narrows along a vertical direction from the upper surface of the glass layer 701 toward the lower surface of the glass layer 701. The second portion 707 has an inclined portion such that its width in the horizontal direction widens along a vertical direction from the upper surface of the glass layer 701 toward the lower surface of the glass layer 701. Here, the first portion 706 and the second portion 707 of the insulating member 705 may be determined based on the inclined portions of the side surfaces of the insulating member 705.

[0146] In this case, Figure 6 In this embodiment, the thickness of the first portion 606 on one side of the insulating member 605 in the vertical direction and the thickness of the first portion 606 on the other side of the insulating member 605 in the vertical direction can be the same. Furthermore, the thickness of the second portion 607 on one side of the insulating member 605 in the vertical direction and the thickness of the second portion 607 on the other side of the insulating member 605 in the vertical direction can be the same. That is, in the previous embodiment, the horizontal central axis of the first portion 606 of the insulating member 605 and the horizontal central axis of the second portion 607 can be aligned with or coincide with each other.

[0147] Conversely, according to Figure 7In this embodiment, the horizontal central axis of the first portion 706 of the insulating member 705 and the horizontal central axis of the second portion 707 of the insulating member 705 can be offset from each other. Therefore, the vertical thickness T11 of the first portion 706 on one side of the insulating member 705 can be different from the vertical thickness T12 of the first portion 706 on the other side of the insulating member 705. For example, the vertical thickness T11 of the first portion 706 on one side of the insulating member 705 can be less than the vertical thickness T12 of the first portion 706 on the other side of the insulating member 705. Accordingly, the vertical thickness T13 of the second portion 707 on one side of the insulating member 705 can be different from the vertical thickness T14 of the second portion 707 on the other side of the insulating member 705. For example, the thickness T11 of the first portion 706 in the vertical direction on one side of the insulating member 705 can be less than the thickness T13 of the second portion 707 in the vertical direction on one side of the insulating member 705, and the thickness T12 of the first portion 706 in the vertical direction on the other side of the insulating member 705 can be greater than the thickness T14 of the second portion 707 in the vertical direction on the other side of the insulating member 705. That is, the embodiment can further improve the overall torsion characteristics of the circuit board by additionally allowing the insulating member 705 to include the first portion 706 and the second portion 707 and allowing the horizontal central axis of the first portion 706 and the horizontal central axis of the second portion 707 to be offset from each other.

[0148] In this configuration, the via electrode 708 is configured to penetrate the insulating member 705. The via electrode 708 may include a first portion 709 and a second portion 710. The first portion 709 is inclined such that its width in the horizontal direction narrows along a vertical direction from the upper surface of the glass layer 701 toward the lower surface of the glass layer 701. The second portion 710 is disposed below the first portion 709 and is also inclined such that its width in the horizontal direction widens along a vertical direction from the upper surface of the glass layer 701 toward the lower surface of the glass layer 701. Furthermore, the central axis in the horizontal direction of the first portion 709 of the via electrode 708 may coincide with the central axis in the horizontal direction of the second portion 710 of the via electrode 708.

[0149] according to Figure 8 In one embodiment, the circuit board includes a glass layer 801, an insulating member 805 penetrating the glass layer 801, and a core via electrode 808 penetrating the insulating member 805. The core via electrode 808 can electrically connect circuit layers 802 and 803 disposed on the upper and lower surfaces of the glass layer 801.

[0150] The insulating member 805 may include a first portion 806 and a second portion 807. The first portion 806 has an inclined portion such that its width in the horizontal direction narrows along a vertical direction from the upper surface of the glass layer 801 toward the lower surface of the glass layer 801. The second portion 807 has an inclined portion such that its width in the horizontal direction widens along a vertical direction from the upper surface of the glass layer 801 toward the lower surface of the glass layer 801. Furthermore, the central axis in the horizontal direction of the first portion 806 of the insulating member 805 may be offset from the central axis in the horizontal direction of the second portion 807 of the insulating member 805.

[0151] The via electrode 808 is configured to penetrate the insulating member 805. The via electrode 808 may include a first portion 809 and a second portion 810. The first portion 809 is inclined such that its width in the horizontal direction narrows along a vertical direction from the upper surface of the glass layer 801 toward the lower surface of the glass layer 801. The second portion 810 is disposed below the first portion 809 and is inclined such that its width in the horizontal direction widens along a vertical direction from the upper surface of the glass layer 801 toward the lower surface of the glass layer 801. Furthermore, the horizontal central axis of the first portion 809 of the via electrode 808 may be offset from the horizontal central axis of the second portion 810 of the via electrode 808.

[0152] In summary, the horizontal central axis of the first portion 806 of the insulating member 805 and the horizontal central axis of the first portion 809 of the core through-hole electrode 808 can be offset from each other, and the horizontal central axis of the second portion 807 of the insulating member 805 and the horizontal central axis of the second portion 710 of the core through-hole electrode 808 can be offset from each other.

[0153] That is, the embodiment can further improve the twist characteristics of the circuit board by allowing the central axis in the horizontal direction of the first portion 809 and the central axis in the horizontal direction of the second portion 810 of the core via electrode 808 to be offset from each other according to the direction of the circuit board twist.

[0154] according to Figure 9 In one embodiment, the circuit board includes a glass layer 901, an insulating member 904 penetrating the glass layer 901, and a core via electrode 905 penetrating the insulating member 904. The core via electrode 905 can electrically connect circuit layers 902 and 903 disposed on the upper and lower surfaces of the glass layer 901.

[0155] Preferably, for resistive or heat dissipation purposes, the via electrodes 905 densely fill the vias provided in the insulating member 905. However, when the thickness of the glass layer 901 increases as described above, it may be difficult for the via electrodes 905 to densely fill the vias in the insulating member 905. For example, when attempting to fill the vias in the insulating member 905 that penetrate the thick glass layer 901 as described above by an electroplating process, voids may be generated inside the via electrodes 905. These voids expand due to the heat generated during semiconductor packaging and become a factor reducing the mechanical reliability of the circuit board. Therefore, via electrodes 905 with a predetermined thickness are provided on the inner wall of the vias in the insulating member 905. Here, the thickness of the via electrodes 905 refers to the thickness in the horizontal direction perpendicular to the stacking direction of the first stacked layer 102, the glass layer 901, and the second stacked layer 103, rather than the thickness in the vertical direction of the stacking of the first stacked layer 102, the glass layer 901, and the second stacked layer 103. The thickness of the core via electrode 905 can be from 5 μm to 20 μm to prevent voltage drop and voids as the thickness of the glass layer 901 and insulating member 904 increases. It is difficult to densely fill the metal inside the core via electrode 905 using processes such as electroplating, and therefore, empty spaces may form on its inner side. These empty spaces can cause problems because it is difficult to set the first stacked layer 102 flat when stacking it. Therefore, a resin layer 906 can be disposed inside the core via electrode 905, thus ensuring the flatness of the glass layer 901, the first stacked layer 102, and the second stacked layer 103. The upper surface of the resin layer 906 can be coplanar with the upper surface of the glass layer 901, or it can be configured to be closer to the first stacked layer 102 along the vertical direction than the upper surface of the glass layer 901. The lower surface of the resin layer 906 may be coplanar with the lower surface of the glass layer 901, or it may be configured to be closer to the second stacked layer 103 in the vertical direction than the lower surface of the glass layer 901. This can be freely designed to ensure flatness and / or ensure the flatness of the aforementioned circuit layers 902 and 903 when stacking the first stacked layer 102 and the second stacked layer 103.

[0156] Furthermore, on the glass layer 901, the portion of the circuit layer 902 covering the resin layer 906 can have a smaller thickness than other portions that do not overlap with the resin layer 906 in the vertical direction. Here, the thickness of the circuit layer 902 refers to the thickness along the vertical direction. When designing the circuit layer 902, depending on the degree of freedom in wiring, the circuit layer 902 may or may not cover the resin layer 906, and thus, the degree of freedom in wiring connections can be increased. When the circuit layer 902 does not cover the resin layer 906, the resin layer 906 can directly contact the fifth insulating layer 110. Compared to the case where the resin layer 906 directly contacts the fifth insulating layer 110, the case where the circuit layer 902 and the fifth insulating layer 110 are in contact with each other can provide better bonding strength and can facilitate heat dissipation. However, to reduce manufacturing costs, the circuit layer 902 may be configured not to cover the resin layer 906. Furthermore, depending on the design of the fifth via electrode 135, the circuit layer 902 may or may not cover the resin layer 906. For example, when a fifth via electrode 135 is disposed that overlaps with circuit layer 902 in the vertical direction, circuit layer 902 can be configured to cover resin layer 906 to ensure electrical connectivity and / or mechanical bonding between circuit layer 902 and fifth via electrode 135. Furthermore, when a fifth via electrode 135 is not disposed that overlaps with circuit layer 902 in the vertical direction, circuit layer 902 can be disposed without covering resin layer 906.

[0157] Accordingly, a portion of the circuit layer 903 disposed on the lower surface of the glass layer 901 can be configured to cover the resin layer 906. The portion of the circuit layer 903 covering the resin layer 906 can have a smaller thickness than other portions that do not overlap with the resin layer 906 in the vertical direction. Here, the thickness of the circuit layer 903 refers to the thickness along the vertical direction. When designing the circuit layer 903, depending on the degree of freedom in wiring, the circuit layer 903 can or can not cover the resin layer 906, and thus, the degree of freedom in wiring connections can be increased. When the circuit layer 903 does not cover the resin layer 906, the resin layer 906 can directly contact the sixth insulating layer 111. Compared to the case where the resin layer 906 directly contacts the sixth insulating layer 111, the case where the circuit layer 903 contacts the sixth insulating layer 111 provides better bonding strength and is beneficial for heat dissipation. However, to reduce manufacturing costs, the circuit layer 903 can be configured not to cover the resin layer 906. Furthermore, depending on the design of the sixth via electrode 136, the circuit layer 903 may or may not cover the resin layer 906. For example, when the sixth via electrode 136 is disposed in a vertical direction overlapping the circuit layer 903, the circuit layer 903 may be configured to cover the resin layer 906 to ensure electrical connectivity and / or mechanical bonding between the circuit layer 903 and the sixth via electrode 136. Alternatively, when the sixth via electrode 136 is not disposed in a vertical direction overlapping the circuit layer 903, the circuit layer 903 may be disposed without covering the resin layer 906.

[0158] according to Figure 10 In one embodiment, the circuit board includes a glass layer 1001, an insulating member 1004 penetrating the glass layer 1001, and a via electrode 1005 penetrating the insulating member 1004. The via electrode 1005 can electrically connect circuit layers 1002 and 1003 disposed on the upper and lower surfaces of the glass layer 1001. Furthermore, a resin layer 1006 can be disposed inside the via electrode 1005.

[0159] In this configuration, the core via electrode 1005 can be positioned around the outer side of the resin layer 1006. Furthermore, with... Figure 9 In different embodiments, the core via electrode 1005 may have different thicknesses in the horizontal direction along the circumferential direction of the resin layer 1006.

[0160] That is, the core via electrode 1005 may have a seventh thickness w7 on one side of the resin layer 1006, and may have an eighth thickness w8 on the other side of the resin layer 1006, which is different from the seventh thickness w7. The core via electrode 1005 may have different thicknesses in the horizontal direction along the circumferential direction of the resin layer 1006, thus further improving the overall twist characteristics of the circuit board. For example, considering the direction of circuit board twist, the embodiment may allow the horizontal central axis of the insulating member and the horizontal central axis of the core via electrode to be offset from each other, and may allow the core via electrode to have different thicknesses in the horizontal direction along the circumferential direction of the resin layer 1006, thereby further improving the overall twist characteristics of the circuit board.

[0161] according to Figure 11 The circuit board of one embodiment includes a stacked structure 1100 and a joint provided on the stacked structure 1100. Here, the stacked structure 1100 has a connection with... Figure 1a The circuit board shown has a glass layer, a first stacked layer, and a second stacked layer corresponding to its structure, and therefore, will be referred to... Figure 1a The accompanying reference numerals are used for description.

[0162] A portion of the first circuit layer 116 may include pads exposed from the first protective layer 1101. Furthermore, as the density of semiconductor device terminals increases, solder short circuits may occur between adjacent pads joined with conventional solder. Therefore, to reduce the amount of solder used as the terminal density of semiconductor devices increases, the semiconductor devices and the circuit board can be joined together by thermocompression bonding. When using thermocompression bonding, the circuit board may also include a bonding portion 1102 protruding from the first protective layer 1101. The bonding portion 1102 may have a protrusion protruding from the upper surface of the first protective layer 1101 and a through portion 1103 penetrating the first protective layer 1101 to contact the first circuit layer 116. Furthermore, when the circuit board 100 is joined to the semiconductor device by thermocompression bonding, cracks may occur at the through portion 1103 of the bonding portion 1102 due to the load generated therefrom. Therefore, the through portion 1103 of the joint 1102 can be prevented from cracking by providing a material with a higher elasticity than the first circuit layer 116 at the portion adjacent to the first circuit layer 116. This material can be nickel (Ni), but is not limited to it, and can also be a copper layer with low grain density formed by electroless plating.

[0163] It can be set in various ways Figure 11The shown portions are the joint 1102 and the through portion 1103. For example, an opening in the first protective layer 1101 can be formed by exposing and developing the first protective layer 1101, and then a process can be performed to form the joint 1102 and the through portion 1103 in the opening. Alternatively, a through hole can be formed in the first protective layer 1101 using a laser, and then a process can be performed to form the joint 1102 and the through portion 1103 in the opening. Furthermore, a dry film resist (DFR) can first be applied to the area where the through portion 1103 is to be formed, then the first protective layer 1101 can be configured to cover the DFR, then a portion of the first protective layer 1101 can be etched with a chemical solution to expose the DFR, then the DFR can be peeled off to form an opening in the first protective layer 1101, and then the joint 1102 and the through portion 1103 can be formed. Therefore, the through portion 1103 can have various shapes depending on the process method. For example, when the opening of the first protective layer 1101 is formed by an exposure process, the side surface of the through-hole 1103 may have a structure in which the width gradually decreases toward the first circuit layer 116; when the opening of the first protective layer 1101 is formed by a laser process, the side surface of the through-hole 1103 may have a vertical side surface and a curved recessed portion adjacent to the first circuit layer 116; and when the opening of the first protective layer 1101 is formed using DFR, the side surface of the through-hole 1103 may only have a vertical side surface. As described above, when the semiconductor device is bonded to the circuit board 100 by thermocompression bonding, a load can be applied to the through-hole 1103, and in this case, stress can be uniformly applied to the through-hole 1103 formed using DFR, thereby improving manufacturing yield. Furthermore, as Figure 11 As shown, the via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 of the first stacked layer 102 and the second stacked layer 103 can have a structure in which at least a portion of them overlap each other along the vertical direction. Therefore, voltage drop and / or signal loss problems can be solved, and the degree of freedom in wiring design can be increased. However, when semiconductor devices are mounted on circuit board 100, if a load is applied to the vertically overlapping via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 due to the load applied to circuit board 100, cracks may occur at the interfaces between via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 and circuit layers 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, and 127. To solve this problem, the junction 1102 may have a structure that does not overlap with the via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 in the vertical direction.

[0164] Reference Figure 12 The circuit board 100 may also include at least one connecting member 1200. (Refer to...) Figure 1a describe Figure 12 Components not shown in the diagram.

[0165] Recently, with the increase in the number of signals processed by semiconductor devices, the area of ​​semiconductor devices has tended to increase, and this increase in area leads to a decrease in the yield of semiconductor devices. Therefore, there is a trend to divide the semiconductor devices into pattern sizes or functional portions and to place small chips on a circuit board 100 and embed connection members 1200 that electrically connect the small chips in the circuit board 100. However, the connection members 1200 are not limited to this and can also connect semiconductor devices to another semiconductor device with a different function, such as a memory. Furthermore, embedding the connection members 1200 in the first stacked layer 102 is advantageous for preventing signal loss. That is, the connection members 1200 electrically connect multiple semiconductor devices disposed on the circuit board 100, and therefore, reducing the signal transmission distance by being adjacent to multiple semiconductor devices can help reduce signal transmission loss. Therefore, the connection members 1200 can be disposed on the upper part of the first stacked layer 102 of the circuit board 100. As an embodiment, the connection members 1200 according to this disclosure will be described as being disposed on the upper part of the first stacked layer 102.

[0166] Reference Figure 12 (a) The second insulating layer 1212 and the third insulating layer 1213 may have through holes, and the cavity may be formed by the upper surface of the insulating layer disposed below the third insulating layer 1213 and the through holes of the second insulating layer 1212 and the third insulating layer 1213.

[0167] The connecting member 1200 may be disposed in the cavity, and the connecting member 1200 may be embedded with a first insulating layer 1211. The connecting member 1200 is disposed on the upper surface of the fourth insulating layer 1214 that overlaps perpendicularly with the cavity, and the first insulating layer 1214 may be configured to fill the cavity and surround the side portion of the connecting member 1200 embedded in the cavity.

[0168] In the prior art, only the third insulating layer 1213 has a through hole and the connecting member 1200 is embedded in the second insulating layer 1212, or only the second insulating layer 1212 has a through hole and the connecting member 1200 is embedded in the first insulating layer 1211. In these cases, the flatness of the upper surface of the first insulating layer 1211 may be reduced. Furthermore, when the thickness of the connecting member 1200 is greater than the thickness of the second insulating layer 1212 and / or the thickness of the third insulating layer 1213, the flatness of the upper surface of the first insulating layer 1211 may be further reduced. Therefore, it is necessary to improve the flatness of the upper surface of the first insulating layer 1211 by reducing the difference between the thickness of the connecting member 1200 and the depth of the cavity.

[0169] Reference Figure 12 (a) and Figure 5 (b) The upper surface of the connecting member 1200 is shown to be positioned closer to the glass layer 101 than the upper surface of the second insulating layer 1212. However, when the vertical length difference between the upper surface of the connecting member 1200 and the upper surface of the second insulating layer 1212 is within 1 μm to 5 μm, the upper surface of the connecting member 1200 may be positioned closer to the first protective layer 104 than the upper surface of the second insulating layer 1212.

[0170] according to Figure 12 (a) and Figure 12 (b) To reduce the difference between the cavity depth and the thickness of the connecting member 1200, it is advantageous to form a cavity above the second insulating layer 1212 and the third insulating layer 1213. In this case, the through hole of the third insulating layer 1213 can be formed with a second inclination angle having a first inclination angle greater than the first inclination angle of the inner wall forming the through hole of the second insulating layer 1212. (Refer to...) Figure 12 (a) and Figure 12 (b) The inclination angle of the inner wall of the through hole forming the second insulating layer 1212 and the inclination angle of the inner wall of the through hole forming the third insulating layer 1213 can be different from each other in order to improve the alignment accuracy of the connecting member 1200 and prevent gaps from being generated when the first insulating layer 1201 is embedded in the cavity.

[0171] exist Figure 12 In (a), the inclination angle of the inner wall of the through-hole forming the second insulating layer 1212 is shown to be gentler than the inclination angle of the inner wall of the through-hole forming the third insulating layer 1213. However, the embodiments are not limited thereto, and as... Figure 12 As shown in (b), the inclination angle of the inner wall of the through hole forming the third insulating layer 1213 can be gentler than the inclination angle of the inner wall of the through hole forming the second insulating layer 1212.

[0172] Furthermore, to improve alignment accuracy when embedding the connecting member 1200, a metal member 1215 can be provided around the cavity. Therefore, alignment accuracy can be improved, thereby enhancing the alignment accuracy between the via electrode and the circuit layer in subsequent processes.

[0173] Furthermore, the first via electrode penetrating the first insulating layer 1211 can have different widths depending on its position. For example, the first via electrode may include a first via portion 1216 that overlaps with the connecting member 1200 in the vertical direction and a second via portion 1217 that overlaps with the first via portion 1216 in the horizontal direction but does not overlap with the connecting member 1200 in the vertical direction. The first via portion 1216 can be directly connected to a pad portion 1201 disposed on the upper surface of the connecting member 1200. In this case, the width of the pad portion 1201 can be smaller than the width of the circuit layer 1218 embedded in the lower surface of the first insulating layer 1211. Therefore, the width of the first via portion 1216 in the horizontal direction can be smaller than the width of the second via portion 1217 in the horizontal direction.

[0174] Reference Figure 13 The circuit board may include a glass layer 1301, a first stacked layer 1302 disposed on the glass layer 1301, a second stacked layer 1303 disposed below the glass layer 1301, an insulating member 1304 penetrating the glass layer 1301, and a core via electrode 1305 penetrating the insulating member 1304.

[0175] In addition, the glass layer 1301 may include a cavity 1306 and may include a connecting member 1311 attached to an adhesive member 1310 disposed on the bottom surface 1308 of the cavity 1306.

[0176] Glass layer 1301 has a cavity 1306. Furthermore, a connecting member 1311 is disposed within the cavity 1306 in glass layer 1301. That is, by disposing the connecting member 1311 within the cavity 1306, the embodiment prevents the connecting member 1311 from twisting in a specific direction, and thus allows the connecting member 1311 to operate stably. Specifically, by disposing the connecting member 1311 within the relatively rigid glass layer 1301, the flatness of the connecting member 1311 can be improved, and the rigidity of the connecting member 1311 can also be improved, thereby further improving the overall twist characteristics of the circuit board and semiconductor package. Furthermore, the alignment accuracy between the pad portion of the connecting member 1311 and the circuit layer and via electrodes of the first stacked layer 1301 can be improved.

[0177] In this configuration, cavity 1306 is disposed within glass layer 1301. Cavity 1306 can be configured as a non-through cavity that does not penetrate glass layer 1301. For example, cavity 1306 can be a recessed portion recessed from the upper surface of glass layer 1301 toward the lower surface of glass layer 1301. Therefore, the embodiment can maximize the area of ​​glass layer 1301 and improve the rigidity of the circuit board and semiconductor package, thereby improving overall torsional characteristics.

[0178] The glass layer 1301 may include a sidewall 1307 forming the cavity 1306, a bottom surface 1308 forming the cavity 1306, and a boundary surface 1309 between the sidewall 1307 and the bottom surface 1308.

[0179] The inclination of the sidewall 1307 of the cavity 1306 in glass layer 1301 can be closer to 90° than the inclination of the insulating member 1304 and the inclination of the via electrode 1305. For example, the inclination of the sidewall 1307 of the cavity 1306 in glass layer 1301 relative to the upper and / or lower surface of glass layer 1301 can be 90°. Therefore, the embodiment can minimize the area occupied by the cavity 1306 in glass layer 1301, and thus maintain the rigidity of glass layer 1301 and improve the torsion characteristics of circuit board 100 and semiconductor package. For example, when the inclination of the sidewall 1307 is greater than or less than 90°, the area occupied by the cavity 1306 in glass layer 1301 may increase accordingly, and the rigidity of glass layer 1301 may decrease. Conversely, since the sidewall 1307 of the cavity 1306 of the glass layer 1301 has a 90° angle with the upper and / or lower surface of the glass layer 1301, the embodiment can maintain the rigidity of the glass layer 1301 by minimizing the area occupied by the cavity 1306, thereby further improving the torsion characteristics of the circuit board and semiconductor package.

[0180] In this case, the near-vertical sidewall 1307 of the cavity 1306 of the glass layer 1301 can be achieved by performing multiple processing steps to form a cavity 1306 in the glass layer 1301.

[0181] An embodiment can form a cavity 1306 of a predetermined depth in the glass layer 1301 using a wet etching process. However, the sidewalls 1307 of the cavity 1306 formed by the wet etching process can have an obtuse angle relative to the bottom surface 1308 of the cavity 1306. Therefore, an embodiment can perform a sandblasting process on the cavity 1306 formed by the wet etching process, and thus, the sidewalls 1307 of the cavity 1306 can be nearly perpendicular to the upper and / or lower surfaces of the glass layer 1301.

[0182] Furthermore, as the cavity 1306 is formed through wet etching and sandblasting processes, the boundary surface 1309 between the sidewall 1307 and the bottom surface 1308 of the cavity 1306 can have a circular shape. For example, the boundary surface 1309 between the sidewall 1307 and the bottom surface 1308 can be configured as a curved surface with a predetermined curvature. Therefore, the embodiment can improve the mechanical reliability of the circuit board and semiconductor package. For example, when the boundary between the sidewall 1307 and the bottom surface 1308 of the cavity 1306 is at a right angle, stress may concentrate on the boundary in the manufacturing environment and / or operating environment of the circuit board, and therefore, cracks may occur. Conversely, the embodiment can prevent stress concentration on the boundary surface 1309 by allowing the boundary surface 1309 between the sidewall 1307 and the bottom surface 1308 to be circular, thereby improving the mechanical reliability of the circuit board and semiconductor package.

[0183] Cavity 1306 may have a predetermined depth H1 within glass layer 1301. In this case, the depth H1 of cavity 1306 may be less than half the thickness of glass layer 1301. That is, the via electrode 1305 is configured to penetrate the insulating member 1304 disposed within glass layer 1301. The via electrode 1305 may include a first portion and a second portion. The first portion is inclined such that its width in the horizontal direction gradually decreases along the direction from the upper surface of glass layer 1301 toward the lower surface of glass layer 1301. The second portion is disposed below the first portion and is inclined such that its width in the horizontal direction gradually increases along the direction from the upper surface of glass layer 1301 toward the lower surface of glass layer 1301. Furthermore, the depth H1 of cavity 1306 may be less than the vertical thickness H2 of the first portion of via electrode 1305. When the depth H1 of cavity 1306 is greater than the thickness H2 in the vertical direction of the first part of the core via electrode 1305, cracks may occur in glass layer 1301 during the process of forming cavity 1306, and therefore, the mechanical reliability of the circuit board may be reduced.

[0184] Furthermore, the insulating member 1304 can be configured to penetrate the glass layer 1301, and can be disposed on each of the upper and lower surfaces of the glass layer 1301. Additionally, a cavity 1306 can be formed with the insulating member 1304 disposed on the upper surface of the glass layer 1301. Therefore, the insulating member 1304 may not be disposed in the region forming the cavity 1306.

[0185] The adhesive member 1310 may be disposed on the bottom surface 1308 of the cavity 1306. The adhesive member 1310 may be a non-conductive paste (NCP), but is not limited thereto, and any material having adhesive strength may be used as the adhesive member 1310.

[0186] The connecting member 1311 can be attached to the adhesive member 1310.

[0187] The first stacked layer 1302 may be disposed on the glass layer 1301, and the second stacked layer 1303 may be disposed below the glass layer 1301. The first stacked layer 1302 and the second stacked layer 1303 correspond to the structure of the previous embodiment, and their detailed description will be omitted.

[0188] The insulating layer of the first stacked layer 1302 can be configured to fill the cavity 1306 of the glass layer 1301. That is, the insulating layer of the first stacked layer 1302 can be configured to surround the connecting member 1311 disposed in the cavity 1306, thereby stably protecting the connecting member 1311.

[0189] The via electrode and circuit layer disposed in the first stacked layer 1302 may include a first portion that overlaps with the connecting member 1311 in the vertical direction and a second portion that does not overlap with the connecting member 1311 in the vertical direction, and the width of the first portion in the horizontal direction may be smaller than the width of the second portion in the horizontal direction.

[0190] according to Figure 14 In one embodiment, the glass layer 1401 may include a plurality of cavities 1402 and 1406 spaced apart from each other in a horizontal direction. Furthermore, connecting members 1405 and 1409 may be disposed in the plurality of cavities 1402 and 1406. In this case, the connecting members 1405 and 1409 may be configured to be biased along a specific direction within each cavity 1402 and 1406.

[0191] For example, multiple cavities 1402 and 1406 may include a first cavity 1402 and a second cavity 1406 that are spaced apart from each other in the horizontal direction.

[0192] The first connecting member 1405 may be disposed in the first cavity 1402. The first connecting member 1405 may be disposed offset in the first cavity 1402 in the direction of the central axis in the horizontal direction toward the glass layer 1401.

[0193] For example, glass layer 1401 includes sidewalls 1403 and 1404 forming a first cavity 1402, and sidewalls 1403 and 1404 may include a first portion 1403 disposed on one side of the first connecting member 1405 and a second portion 1404 disposed on the other side of the first connecting member 1405. Furthermore, the spacing distance d1 between the first portion 1403 and the first connecting member 1405 may be different from the spacing distance d2 between the second portion 1404 and the first connecting member 1405. For example, the spacing distance d1 between the first portion 1403 and the first connecting member 1405 may be greater than the spacing distance d2 between the second portion 1404 and the first connecting member 1405. For example, the horizontal central axis of the first connecting member 1405 may be offset from the horizontal central axis of the first cavity 1402, and preferably, the horizontal central axis of the first connecting member 1405 may be offset relative to the horizontal central axis of the first cavity 1402 in a direction toward the horizontal central axis of the glass layer 1401.

[0194] The second connecting member 1409 may be disposed in the second cavity 1406. The second connecting member 1409 may be disposed offset in the direction of the central axis in the horizontal direction toward the glass layer 1401 within the second cavity 1406.

[0195] For example, glass layer 1401 includes sidewalls 1407 and 1408 forming the second cavity 1406, and sidewalls 1407 and 1408 may include a third portion 1407 disposed on one side of the second connecting member 1409 and a fourth portion 1408 disposed on the other side of the second connecting member 1409. Furthermore, the spacing distance d3 between the third portion 1407 and the second connecting member 1409 may be different from the spacing distance d4 between the fourth portion 1408 and the second connecting member 1409. For example, the spacing distance d3 between the third portion 1407 and the second connecting member 1409 may be greater than the spacing distance d4 between the fourth portion 1408 and the second connecting member 1409. For example, the horizontal central axis of the second connecting member 1409 may be offset from the horizontal central axis of the second cavity 1406, and preferably, the horizontal central axis of the second connecting member 1409 may be offset relative to the horizontal central axis of the second cavity 1406 in a direction toward the horizontal central axis of the glass layer 1401.

[0196] Therefore, the embodiments can allow the widths of the insulating layers of the first stacked layers disposed along the circumferential side surfaces of the connecting members 1405 and 1409 to differ in the horizontal direction. For example, cavities 1402 and 1406 are filled with the insulating layers of the first stacked layers. In this case, the spacing between the sidewalls of each of cavities 1402 and 1406 and each of the connecting members 1405 and 1409 can include different spacing distances along the circumferential direction of each of the connecting members 1405 and 1409. Therefore, the insulating layer of the first stacked layer 1302 can have different widths in the horizontal direction along the circumferential direction of each of the connecting members 1405 and 1409. Thus, taking into account the direction of circuit board twist, the embodiments can allow the connecting members 1405 and 1409 to have different spacing distances with the sidewalls of the cavities along the circumferential direction, thereby further reducing circuit board twist.

[0197] according to Figure 15 In one embodiment, the glass layer 1501 includes a plurality of cavities 1502, 1504, 1506, 1508, 1510, 1512, 1514, and 1516, and a plurality of connecting members 1503, 1505, 1507, 1509, 1511, 1513, 1515, and 1517, which are located in different horizontal directions relative to the central axis x0 of the glass layer 1501 in the horizontal direction. The plurality of connecting members 1503, 1505, 1507, 1509, 1511, 1513, 1515, and 1517 may be offset in different directions within each cavity 1502, 1504, 1506, 1508, 1510, 1512, 1514, and 1516, and may be offset, for example, in a direction toward the central axis x0 of the glass layer 1501 in the horizontal direction.

[0198] For example, a first cavity 1502 and a first connecting member 1503 are provided on the left side of the central axis x0 in the horizontal direction of the glass layer 1501. The first connecting member 1503 can be offset (offset 1) in a first horizontal direction toward the central axis x0 in the horizontal direction of the glass layer 1501 within the first cavity 1502.

[0199] Furthermore, a second cavity 1504 and a second connecting member 1505 are provided to the right of the central axis x0 in the horizontal direction of the glass layer 1501. The second connecting member 1505 can be offset (offset 2) in a second horizontal direction toward the central axis x0 in the horizontal direction of the glass layer 1501 within the second cavity 1504.

[0200] Furthermore, a third cavity 1506 and a third connecting member 1507 are provided on the rear side of the central axis x0 in the horizontal direction of the glass layer 1501. The third connecting member 1507 can be offset (offset 3) in a third horizontal direction toward the central axis x0 in the horizontal direction of the glass layer 1501 within the third cavity 1506.

[0201] Furthermore, a fourth cavity 1508 and a fourth connecting member 1509 are provided on the front side of the central axis x0 in the horizontal direction of the glass layer 1501. The fourth connecting member 1509 can be offset (offset 4) in the fourth horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 1501 within the fourth cavity 1508.

[0202] Furthermore, a fifth cavity 1510 and a fifth connecting member 1511 are provided on the left rear side of the central axis x0 in the horizontal direction of the glass layer 1501. The fifth connecting member 1511 can be offset (offset 5) in the fifth horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 1501 within the fifth cavity 1510.

[0203] Furthermore, a sixth cavity 1512 and a sixth connecting member 1513 are provided on the right rear side of the central axis x0 in the horizontal direction of the glass layer 1501. The sixth connecting member 1513 can be offset (offset 6) in the sixth horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 1501 within the sixth cavity 1512.

[0204] Furthermore, a seventh cavity 1514 and a seventh connecting member 1515 are provided on the left front side of the central axis x0 in the horizontal direction of the glass layer 1501. The seventh connecting member 1515 can be offset (offset 7) in the seventh horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 1501 within the seventh cavity 1514.

[0205] Furthermore, an eighth cavity 1516 and an eighth connecting member 1517 are provided on the right front side of the central axis x0 in the horizontal direction of the glass layer 1501. The eighth connecting member 1517 can be offset (offset 7) in the eighth horizontal direction towards the central axis x0 in the horizontal direction of the glass layer 1501 within the eighth cavity 1516.

[0206] As described above, considering the placement positions of the corresponding cavities and connecting members relative to the central axis x0 in the horizontal direction of the glass layer 1501, the multiple connecting members 1503, 1505, 1507, 1509, 1511, 1513, 1515 and 1517 can be offset in different directions and / or different distances within the respective cavities 1502, 1504, 1506, 1508, 1510, 1512, 1514 and 1516, and thus, the overall distortion of the circuit board can be further reduced, allowing for a more stable placement of semiconductor devices.

[0207] The circuit board described above can be used as a semiconductor packaging substrate for semiconductor packaging. (See reference...) Figure 16 In one embodiment, the semiconductor package includes a semiconductor package substrate 1600, a bonding member 1610, and semiconductor devices 1620 and 1630. The semiconductor package substrate 1600 provides space for mounting the semiconductor devices 1620 and 1630 and can be connected to a motherboard of an electronic device.

[0208] Furthermore, the aforementioned circuit board can be used as an intermediary layer between a semiconductor packaging substrate and a semiconductor packaged semiconductor device. (See reference...) Figure 17 In one embodiment, the semiconductor package includes an interposer 1700, a first bonding member 1710, a plurality of semiconductor devices 1720 and 1730, a second bonding member 1740, and a semiconductor package substrate 1750.

[0209] Intermediate layer 1700 can refer to Figure 1 to... Figure 17 The circuit board 100 described above. That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and therefore, the thickness of the circuit board increases, and with the increase in thickness, the yield of the circuit board may decrease. Therefore, the circuit board can be divided and used as an interposer layer 1700 and a semiconductor packaging substrate 1750, and the aforementioned circuit board 100 can be used as... Figure 16 The semiconductor packaging substrate 1600 in the embodiments can also be used as, for example Figure 17 Intermediate layer 1700 in the embodiment.

[0210] Semiconductor devices 1720 and 1730 are disposed on the interposer layer 1700. Semiconductor devices 1720 and 1730 may be disposed in multiple units on the interposer layer 1700, spaced apart from each other in the horizontal direction, but are not limited thereto. For example, semiconductor devices 1720 and 1730 may be stacked on the interposer layer 1700 not only in the horizontal direction but also in the vertical direction. Connecting members 620 for electrically connecting semiconductor devices 1720 and 1730 are disposed in the interposer layer 1700.

[0211] The first bonding member 1710 may be disposed between the interposer 1700 and the semiconductor devices 1720 and 1730. A bonding portion disposed on the interposer 1700 (see...) Figure 11 A first bonding member 1710 is provided on the interposer 1700, and thus, semiconductor devices 1720 and 1730 can be attached to the interposer 1700 by thermo-press bonding. In this case, semiconductor devices 1720 and 1730 include terminals 1725 and 1735, and terminals 1725 and 1735 can be electrically connected to the junction of the interposer 1700 and the circuit layer through the first bonding member 1710.

[0212] A semiconductor packaging substrate 1750 is disposed on the lower surface of the interposer 1700. The semiconductor packaging substrate 1750 can electrically connect the motherboard of an electronic device and the interposer 1700.

[0213] In this case, a second bonding member 1740 can be provided between the interposer 1700 and the semiconductor packaging substrate 1750, and thus the interposer 1700 and the semiconductor packaging substrate 1750 can be electrically bonded to each other.

[0214] In the following, the method of manufacturing the circuit board according to the embodiment will be described in process order. Figures 18a to 18h This is a cross-sectional view showing the method of manufacturing a circuit board according to an embodiment, in the order of process steps.

[0215] Reference Figure 18a The embodiment prepares a core component as the basis for manufacturing a circuit board. For this purpose, the embodiment can prepare a glass layer 1801. Next, the embodiment can perform a process to form a through-hole 1801T in the prepared glass layer 1801. For example, the embodiment can form the through-hole 1801T by processing the glass layer 1801 with nanoparticles, picopitographs, focused discharge (FED), wet etching, etc. In this case, the process of forming the through-hole 1801T can be performed on one surface of the glass layer 1801. In this case, the through-hole 1801T can have a slope such that its width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer 1801 toward the lower surface of the glass layer 1801.

[0216] Next, refer to Figure 18b The embodiment can perform a process of forming an insulating member 1802 in a through-hole 1801T formed in the glass layer 1801. In this case, as Figure 18b As shown in (a), the insulating member 1802 may be provided only in the through hole 1801T of the glass layer 1801. Furthermore, as... Figure 18b As shown in (b), the insulating member 1802 can be formed not only in the through hole 1801T of the glass layer 1801, but also on the upper and lower surfaces of the glass layer 1801 with a predetermined thickness.

[0217] Next, refer to Figure 18cThe embodiment can perform a process to form a cavity 1803 in the glass layer 1801. In this case, the embodiment can form the cavity 1803 by wet etching the glass layer 1801. In this case, when the insulating member 1802 is disposed on the upper surface of the glass layer 1801, a portion of the insulating member 1802 disposed on the upper surface of the glass layer 1801 can also be removed together with the glass layer 1801 during the process of forming the cavity 1803. Furthermore, the cavity 1803 formed by the wet etching process can have an inclined portion such that its width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer 1801 toward the lower surface of the glass layer 1801.

[0218] Next, refer to Figure 18d The embodiment may perform an additional processing step to form the final cavity 1804 by further processing the cavity 1803 formed by the wet etching process. Preferably, the embodiment may perform a sandblasting process on the cavity 1803 formed in one step by the wet etching process. Therefore, the sidewalls of the finally formed cavity 1804 may be perpendicular to the upper and / or lower surfaces of the glass layer 1801. Furthermore, the boundary surface between the sidewalls and the bottom surface of the cavity 1804 may include a curved surface with a predetermined curvature.

[0219] Next, refer to Figure 18e The embodiment can perform a process for forming a via 1805 in the insulating member 1802. For example, the embodiment can perform a first via forming process on the upper surface of the insulating member 1802, and then perform a second via forming process on the lower surface of the insulating member 1802. Therefore, the via 1805 formed in the insulating member 1802 can include a first portion and a second portion, the first portion having an inclined portion such that its width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer 1801 toward the lower surface of the glass layer 1801, and the second portion being disposed below the first portion and having an inclined portion such that its width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer 1801 toward the lower surface of the glass layer 1801. Furthermore, a plurality of vias 1805 can be formed, and each of the plurality of vias can be formed in each insulating member, taking into account the direction of the twist of the circuit board 100. For example, taking into account the direction of the twist of the circuit board, the central axis in the horizontal direction of each insulating member and the central axis in the horizontal direction of each via can be offset from each other. For example, the horizontal central axis of each through hole can be offset relative to the horizontal central axis of each insulating member in the direction of the horizontal central axis toward the glass layer 1801.

[0220] Next, refer to Figure 18fIn this embodiment, a core via electrode 1806 can be formed by filling the via 1805 formed in the insulating member 1802 with a conductive material, and circuit layers 1807 and 1808 connected to the core via electrode 1806 can be formed.

[0221] Next, refer to Figure 18g In this embodiment, an adhesive member 1809 may be formed on the bottom surface of the cavity 1804 formed in the glass layer 1801. Furthermore, the embodiment may perform a process of attaching a connecting member 1810 to the adhesive member 1809. In this case, taking into account the direction of circuit board twist, the connecting member 1810 may be attached while being offset within the cavity 1804 along a specific horizontal direction. For example, the central axis of the connecting member 1810 in the horizontal direction may be offset relative to the central axis of the cavity 1804 in a direction toward the central axis of the circuit board 100 in the horizontal direction.

[0222] Next, refer to Figure 18h The embodiments can perform processes for forming a first deposited layer 1811 on the upper portion of the glass layer 1801 and a second deposited layer 1812 on the lower portion of the glass layer 1801. Therefore, the embodiments can manufacture a circuit board with improved twist characteristics. Furthermore, the embodiments can perform processes for mounting semiconductor devices on the manufactured circuit board, thereby manufacturing a semiconductor package.

[0223] On the other hand, when a circuit board having the features of the above-described invention is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current or electrical short circuits between terminals or electrical open circuits at terminals used to supply power to the semiconductor chip. Furthermore, when the circuit board is responsible for signal transmission, it can solve noise problems. Thus, a circuit board having the features of the above-described invention can maintain the stable function of IT devices or home appliances, enabling the entire product and the circuit board using the present invention to achieve functional integrity or technical interlocking.

[0224] When a circuit board having the features of the above invention is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or can safely protect the semiconductor chip used to control the transportation device from external influences, and solve the problems of leakage current or electrical short circuits between terminals or electrical open circuits at terminals used to supply power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board using the present invention can achieve functional integrity or technical interlocking with each other.

[0225] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, even with respect to other embodiments, those skilled in the art to which the embodiments pertain can combine or modify the features, structures, and effects shown in each embodiment. Therefore, it should be understood that anything related to such combinations and modifications is included within the scope of the embodiments.

[0226] The description focuses on the embodiments, but is illustrative only and does not limit the embodiments. Those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Furthermore, it should be understood that differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: Glass layer; An insulating component that penetrates the glass layer; as well as The via electrode penetrates the insulating component. The central axis of the via electrode in the horizontal direction and the central axis of the insulating member in the horizontal direction are offset from each other.

2. The circuit board according to claim 1, wherein, The insulating member has an inclined portion whose width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer. The via electrode comprises a first portion and a second portion. The first portion has an inclined portion whose width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer. The second portion is disposed below the first portion and has an inclined portion whose width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer. The tilt angle of the second part is different from that of the insulating member.

3. The circuit board according to claim 2, wherein, The inclined portion of the insulating member is inclined in the same direction as the inclined portion of the first part. The tilting direction of the second part is different from the tilting direction of the inclined part of the insulating member and the tilting direction of the first part.

4. The circuit board according to claim 1, wherein, The central axis of the via electrode in the horizontal direction is closer to the central axis of the glass layer in the horizontal direction than the central axis of the insulating member in the horizontal direction.

5. The circuit board according to claim 4, wherein, The insulating member and the via electrode are respectively configured as a plurality of insulating members and a plurality of via electrodes spaced apart from each other in the horizontal direction. The offset direction of the central axis of each of the plurality of through-hole electrodes relative to the central axis of each of the plurality of insulating members in the horizontal direction includes a first offset direction and a second offset direction that are different from each other.

6. The circuit board according to claim 4, wherein, The thickness of the first portion of at least one of the via electrodes in the vertical direction is the same as the thickness of the second portion in the vertical direction.

7. The circuit board according to claim 4, wherein, The thickness of the first portion of at least one of the via electrodes in the vertical direction is different from the thickness of the second portion in the vertical direction.

8. The circuit board according to claim 7, wherein, The plurality of via electrodes includes a first via electrode and a second via electrode. Wherein, the thickness of the first portion of the first via electrode in the vertical direction is greater than the thickness of the second portion of the first via electrode in the vertical direction, and Wherein, the thickness of the first portion of the second via electrode in the vertical direction is less than the thickness of the second portion of the second via electrode in the vertical direction.

9. The circuit board according to claim 1, wherein, The insulating member includes a third portion and a fourth portion, the third portion having an inclined portion whose width in the horizontal direction gradually decreases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer, and the fourth portion being disposed below the third portion and having an inclined portion whose width in the horizontal direction gradually increases along the direction from the upper surface of the glass layer toward the lower surface of the glass layer.

10. The circuit board according to claim 9, wherein, The horizontal central axis of the third portion of the insulating member and the horizontal central axis of the fourth portion of the insulating member are offset from each other. Wherein, the thickness of the third part in the vertical direction at the first side end of the insulating member and the thickness of the third part in the vertical direction at the second side end of the insulating member are different from each other, and The thickness of the fourth part in the vertical direction at the first side end of the insulating member and the thickness of the fourth part in the vertical direction at the second side end of the insulating member are different from each other.

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