Mask for deposition and display system

Abstract

The invention relates to a mask for deposition and a display system. The mask for deposition includes a deposition region and a non-deposition region, the mask including: a wafer substrate including a plurality of first openings spaced apart from each other; an inorganic layer disposed on the wafer substrate and including a plurality of second openings each overlapping a respective one of the plurality of first openings in a plan view; a pattern layer disposed on the inorganic layer and doped with an impurity to have conductivity; and at least one electrode terminal electrically connected to the pattern layer to apply an external voltage to the pattern layer. A wafer substrate and an inorganic layer are formed in a deposition region and a non-deposition region, a pattern layer is formed in the deposition region, and at least one electrode terminal is formed in the non-deposition region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0143154, filed on October 18, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application generally relates to masks and display systems used for deposition. Background Technology

[0004] With the development of multimedia, the importance of display devices has increased. Therefore, various types of display devices are used, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs).

[0005] For example, organic light-emitting display devices can be used in mobile devices such as smartphones, computers and tablet PCs, or in electronic devices such as televisions, outdoor billboards and displays for exhibitions.

[0006] An organic light-emitting display device may include an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode, which are disposed on a substrate. The organic light-emitting layer may be formed using a mask for deposition.

[0007] The information disclosed in this background section is intended only to enhance the understanding of the background art of this disclosure, and therefore may contain information that does not form prior art known to a person skilled in the art in this country. Summary of the Invention

[0008] Embodiments of this application provide a deposition mask and a display system, the mask being able to improve adhesion to a substrate.

[0009] According to embodiments of the present disclosure, a deposition mask including deposition regions and non-deposition regions may include: a wafer substrate including a plurality of first openings spaced apart from each other; an inorganic layer disposed on the wafer substrate and including a plurality of second openings, each of the plurality of second openings overlapping a corresponding one of the plurality of first openings in a plan view; a patterned layer disposed on the inorganic layer, doped with impurities to be conductive, and including a plurality of third openings, the plurality of third openings overlapping a first opening of the plurality of first openings and a second opening of the plurality of second openings in a plan view, wherein the first opening and the second opening overlap each other; and at least one electrode terminal electrically connected to the patterned layer to apply an external voltage to the patterned layer. The wafer substrate and the inorganic layer may be formed in the deposition regions and non-deposition regions, the patterned layer may be formed in the deposition regions, and at least one electrode terminal may be formed in the non-deposition regions.

[0010] The wafer substrate may include monocrystalline silicon or polycrystalline silicon.

[0011] The inorganic layer may include silicon oxide (SiO2). x Silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y ( ) at least one of the following, x can be a rational number, and y can be another rational number.

[0012] The patterned layer may include silicon (Si) and silicon oxide (SiO2). x Silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y ( ) at least one of the following, x can be a rational number, and y can be another rational number.

[0013] At least one electrode terminal may be made of a conductive material.

[0014] At least one electrode terminal and the patterned layer can be made of substantially the same material.

[0015] In a plan view, one of a plurality of first openings, one of a plurality of second openings, and a plurality of third openings that overlap with each other can form a unit opening region. The unit opening region can define the display area of ​​the display panel.

[0016] The patterned layer can form a single entity throughout the entire depositional area.

[0017] The mask may also include an insulating layer disposed on a patterned layer in the deposition region and on an inorganic layer in the non-deposition region, and includes a plurality of fourth openings, each of which overlaps with a corresponding one of a plurality of third openings in a plan view.

[0018] The entire top surface of the insulating layer facing the substrate on which the deposited material is deposited can be formed to be substantially flat.

[0019] The insulating layer may include at least one of inorganic insulating materials and organic insulating materials.

[0020] The patterned layer may include: at least one first patterned layer electrically connected to at least one electrode terminal; a plurality of second patterned layers spaced apart from the at least one first patterned layer in a first direction; a plurality of third patterned layers spaced apart from the at least one first patterned layer in a second direction intersecting the first direction; and a plurality of fourth patterned layers spaced apart from one of the plurality of third patterned layers in the first direction. The mask may also include a bridging element that electrically connects the at least one first patterned layer to the plurality of second, third, and fourth patterned layers.

[0021] An external voltage applied to at least one first patterned layer via at least one electrode terminal can be applied to multiple second patterned layers, multiple third patterned layers, and multiple fourth patterned layers via a bridging element.

[0022] The bridging element and the pattern layer can be made of essentially the same material.

[0023] The bridging element can be disposed on the inorganic layer between adjacent patterned layers in at least one first patterned layer, a plurality of second patterned layers, a plurality of third patterned layers, and a plurality of fourth patterned layers.

[0024] The bridging element may include: a plurality of first bridging elements electrically connecting at least one of a plurality of second patterned layers arranged in a first direction and at least one of a plurality of first patterned layers to each other, and electrically connecting at least one of a plurality of third patterned layers arranged in the first direction and at least one of a plurality of fourth patterned layers to each other; and a plurality of second bridging elements electrically connecting at least one of a plurality of third patterned layers arranged in a second direction and at least one of a plurality of first patterned layers to each other, and electrically connecting at least one of a plurality of second patterned layers arranged in the second direction and at least one of a plurality of fourth patterned layers to each other.

[0025] The mask may also include an insulating layer disposed in the deposition region on a portion of the inorganic layer between at least one first patterned layer, a plurality of second patterned layers, a plurality of third patterned layers, and a plurality of fourth patterned layers, at least one first patterned layer, a plurality of second patterned layers, a plurality of third patterned layers, and a plurality of fourth patterned layers, and on a bridging element, disposed in the non-deposition region on another portion of the inorganic layer, and including a plurality of fourth openings, each of the plurality of fourth openings overlapping a corresponding one of the plurality of third openings in a plan view.

[0026] The entire top surface of the insulating layer facing the substrate on which the deposited material is deposited can be formed to be substantially flat.

[0027] According to embodiments of this disclosure, the display system may include an organic light-emitting layer disposed between a cathode electrode and an anode electrode. The organic light-emitting layer may be formed by a mask. Attached Figure Description

[0028] Embodiments will now be described more fully below with reference to the accompanying drawings; however, embodiments may be implemented in different forms and should not be construed as limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals denote the same elements throughout.

[0030] Figure 1 This is a plan view illustrating an embodiment of the mask used for deposition.

[0031] Figure 2 It is along Figure 1 The schematic cross-sectional view shown is taken by line I-I'.

[0032] Figure 3 This is a schematic diagram illustrating pixels formed using a mask for deposition according to an embodiment of the present disclosure.

[0033] Figure 4 It shows including Figure 3 A schematic cross-sectional view of the display panel of the pixels shown.

[0034] Figure 5 It shows the use Figure 1 Mask fabrication for deposition shown Figure 4 A schematic cross-sectional view of the manufacturing process of the display panel shown.

[0035] Figure 6 This is a plan view illustrating another embodiment of the mask used for deposition.

[0036] Figure 7 It is along Figure 6 The schematic cross-sectional view shown is taken from line II-II'.

[0037] Figure 8 This is a plan view showing another embodiment of the mask used for deposition.

[0038] Figure 9 yes Figure 8 The enlarged plan view of region AA shown.

[0039] Figure 10 It is along Figure 9 The schematic cross-sectional view shown is taken from line III-III'.

[0040] Figure 11It is along Figure 9 The schematic cross-sectional view shown is taken by line IV-IV'.

[0041] Figure 12 It is shown Figure 10 A schematic cross-sectional view of another embodiment.

[0042] Figure 13 It is shown Figure 11 A schematic cross-sectional view of another embodiment.

[0043] Figure 14 This is a schematic block diagram illustrating an implementation of the display system.

[0044] Figures 15 to 18 It is shown Figure 14 The image shows a perspective view of an application example of the display system. Detailed Implementation

[0045] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the description below, only portions necessary for understanding operation according to the present disclosure are described, and descriptions of other portions are omitted so as not to unnecessarily obscure the subject matter of the disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein, but can be implemented in various different forms. Rather, the embodiments described herein are provided to thoroughly and completely describe the disclosure and to fully convey the ideas of the disclosure to those skilled in the art.

[0046] When a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, it can be directly on, directly connected to, or directly attached to the other component or layer, or there may be an intervening component or layer. However, when a component or layer is referred to as being "directly" on, directly connected to, or directly attached to another component or layer, there is no intervening component or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intervening component. Furthermore, when a component is referred to as being "in contact" or "in contact with" another component, the component can be in "electrical contact" or "physical contact" with the other component; or in "indirect contact" or "direct contact" with the other component.

[0047] The technical terms used herein are for illustrative purposes only and are not intended to limit the implementation. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “comprising” specify the presence of the stated feature, integral, step, operation, element, component, and / or group thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of..." for purposes of its meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of its meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in combined or separate meanings and can be understood as equivalent to "and / or".

[0049] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the “first” element discussed below may also be referred to as the “second” element without departing from the teachings of this disclosure.

[0050] For ease of description, spatial relative terms such as “below” and “above” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations described herein and depicted in the accompanying drawings, the spatial relative terms and the illustrated configurations are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” other elements or features will be oriented “above” other elements or features. Therefore, the term “above” can include both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0051] Furthermore, embodiments of this disclosure are described herein with reference to schematic diagrams of the embodiments (and intermediate structures) so that variations in the shape shown may be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shape of the regions shown herein, but include shape deviations caused by, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of regions of the device, and do not limit the scope of this disclosure.

[0052] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted as having an ideal or overly formal meaning unless clearly defined in the specification.

[0053] Figure 1 This is a plan view illustrating an embodiment of the mask used for deposition. Figure 2 It is along Figure 1 The schematic cross-sectional view shown is taken by line I-I'.

[0054] refer to Figure 1 and Figure 2 According to embodiments of the present disclosure, a deposition mask MSK may include a wafer substrate WS, an inorganic layer IOL, a patterning layer PL, and electrode terminals ET.

[0055] The mask MSK for deposition can be an apparatus used in a deposition process to deposit deposition material on a target area of ​​a deposition target object, and can include multiple patterned apertures PH that allow the deposition material to pass through. The patterned apertures PH can be arranged in a regular pattern on a plane (hereinafter referred to as the "plane") formed by a first direction DR1 and a second direction DR2, and a specific number of patterned apertures PH can be defined as a single cell opening region CELO. Multiple cell opening regions CELO can be arranged side-by-side and spaced apart from each other on each of the first direction DR1 and the second direction DR2 on the plane.

[0056] Each cell opening region (CELO) can correspond one-to-one with a deposition target object. For example, a cell opening region (CELO) can define a display panel (see [link to CELO]). Figure 4 The display area of ​​the DP shown is shown. According to this structure, a deposition process can be performed simultaneously on multiple deposition target objects using a single deposition mask MSK. For example, in a deposition process, the deposition mask MSK can be aligned to face the deposition target object (e.g., Figure 5 (DP shown in the figure).

[0057] As described above, the mask MSK used for deposition allows the deposited material to pass through the cell opening regions CELO and blocks the deposited material in areas other than the cell opening regions CELO. Therefore, the deposited material can be selectively deposited only on the third-direction DR3 in specific areas of the deposition target object that overlap with the cell opening regions CELO (e.g., the display area of ​​a display panel). Therefore, for ease of description, a portion of the mask MSK used for deposition (where multiple cell opening regions CELO are grouped) will be referred to as the deposition region DA, and the area other than the deposition region DA will be referred to as the non-deposition region NDA.

[0058] The wafer substrate (WS) can be a component serving as the overall framework for a mask (MSK) used for deposition, and can be formed in the deposition region (DA) and the non-deposition region (NDA). The wafer substrate (WS) can have a circular shape in a planar view and is made of crystalline silicon materials such as monocrystalline or polycrystalline silicon. However, the materials and shapes constituting the wafer substrate (WS) are not limited to these. For example, the wafer substrate (WS) can be made of various materials and have various shapes in a planar view.

[0059] The wafer substrate WS may include a plurality of first openings OP1 spaced apart from each other. The first openings OP1 may overlap with cell opening regions CELO of the mask MSK used for deposition on a third direction DR3. In other words, the first openings OP1 may be formed in the deposition region DA. Therefore, similar to the cell opening regions CELO, the plurality of first openings OP1 may be arranged in a regular pattern on a first direction DR1 and a second direction DR2, and one of the first openings OP1 may overlap with a specific number of patterned holes PH on a third direction DR3. For example, refer to... Figure 1 It is possible to form four unit opening regions CELO along the first direction DR1 and four unit opening regions CELO along the second direction DR2, and therefore it is also possible to form four first openings OP1 along the first direction DR1 and four first openings OP1 along the second direction DR2.

[0060] In one embodiment, the inner surface of the wafer substrate WS surrounding each of the first openings OP1 may have a tapered shape in cross-sectional view. This may be because the first openings OP1 are formed by wet etching of the wafer substrate WS, but this disclosure is not necessarily limited thereto.

[0061] The inorganic layer IOL can be disposed between the wafer substrate WS and the patterned layer PL, which will be described below, and similarly to the wafer substrate WS, is formed in the deposited region DA and the non-deposited region NDA. Similar to the wafer substrate WS, the inorganic layer IOL can also have a circular shape in the planar view and comprises inorganic materials. For example, the inorganic layer IOL may comprise silicon oxide (SiO₂). x Silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y At least one of the following.

[0062] The inorganic layer IOL can be formed on the wafer substrate WS and includes a plurality of second openings OP2 overlapping the first opening OP1 on the third-direction DR3. In an embodiment, similar to the inner surface of the wafer substrate WS surrounding each of the first openings OP1, the inner surface of the inorganic layer IOL surrounding each of the second openings OP2 can have a tapered shape in cross-sectional view. This may be because the second openings OP2 are formed by wet etching of the inorganic layer IOL, but this disclosure is not necessarily limited thereto.

[0063] In one embodiment, the longest width of the second opening OP2 may be less than the longest width of the first opening OP1 that overlaps with the second opening OP2 on the third direction DR3. In another embodiment, the shortest width of the first opening OP1 may be substantially equal to the longest width of the second opening OP2 that overlaps with the first opening OP1 on the third direction DR3. This means that the inner surfaces of the first opening OP1 and the second opening OP2 that overlap each other on the third direction DR3 can be continuously connected to each other.

[0064] The patterned layer PL can be a component comprising multiple unit opening regions CELO and multiple patterned holes PH formed in each of the unit opening regions CELO, and can be formed in the deposition region DA. (Reference) Figure 1 and Figure 2 The pattern layer PL can be formed as a main body to overlap with the entire deposition area DA on the third-direction DR3.

[0065] The patterned layer PL may include silicon (Si) and silicon oxide (SiO2). x Silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N yAt least one of the following. In an embodiment, impurities may be doped into the patterned layer PL to make the patterned layer PL conductive. For example, when a Group V element such as phosphorus (P), arsenic (As), or antimony (Sb) is doped into the patterned layer PL, the patterned layer PL may have n-type semiconductor characteristics. For example, when a Group III element such as boron (B), gallium (Ga), or indium (In) is doped into the patterned layer PL, the patterned layer PL may have p-type semiconductor characteristics.

[0066] The patterned layer PL may include a plurality of third openings OP3 overlapping one of the first openings OP1 and one of the second openings OP2 on a third-direction DR3, wherein the one of the first openings OP1 and the one of the second openings OP2 overlap each other. In an embodiment, similar to the inner surface of the inorganic layer IOL surrounding each of the second openings OP2, the inner surface of the patterned layer PL surrounding some of the third openings OP3 located at the outermost portion of the plurality of third openings OP3 overlapping a unit opening region CELO may have a tapered shape, and the inner surfaces of the inorganic layer IOL surrounding each of the second openings OP2 and the inner surfaces of the patterned layer PL surrounding some of the third openings OP3 located at the outermost portion of the plurality of third openings OP3 overlapping a unit opening region CELO may be continuously connected to each other.

[0067] In this way, multiple third openings OP3, a second opening OP2 overlapping with the third opening OP3, and a first opening OP1 can be provided in a single unit opening region CELO. According to this structure, deposited material evaporated or sprayed toward the mask MSK used for deposition can enter through the first opening OP1 and sequentially pass through the second opening OP2 and the third opening OP3. The path of the deposited material formed by the overlapping first opening OP1, second opening OP2, and third opening OP3 as described above can be defined as a patterned aperture PH.

[0068] Electrode terminals ET can be electrically connected to the patterned layer PL to apply an external voltage to the patterned layer PL. For this purpose, electrode terminals ET can be made of a conductive material such as metal, but this disclosure is not necessarily limited to this. In embodiments, electrode terminals ET can be formed together with the patterned layer PL using the same process. Therefore, electrode terminals ET and patterned layer PL can be made of substantially the same material. For example, electrode terminals ET may include silicon (Si), silicon oxide (SiO₂), etc. x Silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N yAt least one of the following: Impurities may be doped into the electrode terminal ET to make the electrode terminal ET conductive. For example, when a Group V element such as phosphorus (P), arsenic (As), or antimony (Sb) is doped into the electrode terminal ET, the electrode terminal ET may have n-type semiconductor characteristics. For example, when a Group III element such as boron (B), gallium (Ga), or indium (In) is doped into the electrode terminal ET, the electrode terminal ET may have p-type semiconductor characteristics.

[0069] In one embodiment, the electrode terminal ET may be formed in the non-deposition region NDA and extend from a portion of the pattern layer PL in a direction toward the edge of the mask MSK used for deposition.

[0070] According to this structure, an external voltage applied to the electrode terminal ET can be applied to the entire patterned layer PL electrically connected to the electrode terminal ET. This is because the patterned layer PL has a structure in which the patterned layer PL is formed into a body. When a positive or negative voltage is applied to the electrode terminal ET during the deposition process, the patterned layer PL and the voltage applied to the electrode terminal ET can have the same polarity. During the deposition process, the display panel (see...) Figure 5 The substrate facing the patterned layer PL (see DP shown). Figure 5 The SUB shown can have a polarity opposite to that of the voltage applied to the electrode terminal ET, and therefore, the attractive force between the deposition mask MSK and the substrate SUB of the display panel DP can act between them. Thus, the gap between the deposition mask MSK and the display panel DP can be minimized by the attractive force generated between them, thereby improving the deposition accuracy of the material. Furthermore, the defect rate of the display panel DP can be reduced.

[0071] In the following text, reference will be made to Figure 3 and Figure 4 Describes the pixel formed using the mask MSK for deposition and the display panel DP including the pixel PXL.

[0072] Figure 3 This is a schematic diagram illustrating pixels formed using a mask for deposition according to an embodiment of the present disclosure.

[0073] refer to Figure 3 The pixel PXL can include pixel circuitry PC and organic light-emitting layer EL.

[0074] The pixel circuit PC can be connected to the gate line GL and the data line DL. The pixel circuit PC can control the organic light-emitting layer EL in response to a gate signal received via the gate line GL, thereby enabling the organic light-emitting layer EL to emit light according to a data signal received via the data line DL. For these operations, the pixel circuit PC may include circuit elements such as transistors and one or more capacitors.

[0075] An organic light-emitting layer (EL) can be connected between a first voltage node (VDDN) and a second voltage node (VSSN). The first voltage node (VDDN) can receive a first voltage. The second voltage node (VSSN) can receive a second voltage. The first voltage can have a higher voltage level than the second voltage.

[0076] An organic light-emitting layer (EL) can be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) can be connected to a first power voltage node (VDDN) via a pixel circuit (PC). For example, the anode electrode (AE) can be connected to the first power voltage node (VDDN) via one or more transistors included in the pixel circuit (PC). The cathode electrode (CE) can be connected to a second power voltage node (VSSN). The organic light-emitting layer (EL) can be configured to emit light according to the current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0077] Figure 4 It shows including Figure 3 A schematic cross-sectional view of the display panel of the pixels shown.

[0078] refer to Figure 4 The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a first anode electrode AE1, a second anode electrode AE2 and a third anode electrode AE3, a first organic light-emitting layer EL1, a second organic light-emitting layer EL2 and a third organic light-emitting layer EL3, a pixel limiting layer PDL and a cathode electrode CE.

[0079] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB may include a glass substrate. In another embodiment, the substrate SUB may include a polyimide substrate. In yet another embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes.

[0080] A pixel circuit layer (PCL) can be disposed on a substrate (SUB). The PCL may include an insulating layer, and semiconductor and conductive patterns disposed between the insulating layers. The conductive patterns of the PCL can be used as circuit elements, lines, etc. The circuit elements of the PCL can define a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. Each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be connected to... Figure 3 The gate line GL, data line DL, and first power voltage node VDDN are shown in the diagram.

[0081] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be disposed on the pixel circuit layer PCL. The first anode electrode AE1 can be connected to the first pixel circuit PC1. The second anode electrode AE2 can be connected to the second pixel circuit PC2. The third anode electrode AE3 can be connected to the third pixel circuit PC3.

[0082] A pixel defining layer (PDL) may be disposed on the pixel circuit layer (PCL) and the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The PDL may include a first pixel opening PO1, a second pixel opening PO2, and a third pixel opening PO3 exposing a portion of each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The PDL may include a light-blocking material to prevent light mixing between adjacent pixels. In some embodiments, the PDL may include organic materials. For example, the PDL may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. A spacer (SPC) may be disposed on a portion of the PDL.

[0083] A first organic light-emitting layer EL1 may be disposed on a portion of the first anode electrode AE1 exposed by the first pixel opening PO1 and on the side surface of the pixel defining layer PDL adjacent to the first anode electrode AE1. A second organic light-emitting layer EL2 may be disposed on a portion of the second anode electrode AE2 exposed by the second pixel opening PO2 and on the side surface of the pixel defining layer PDL adjacent to the second anode electrode AE2. A third organic light-emitting layer EL3 may be disposed on a portion of the third anode electrode AE3 exposed by the third pixel opening PO3 and on the side surface of the pixel defining layer PDL adjacent to the third anode electrode AE3. The first organic light-emitting layer EL1, the second organic light-emitting layer EL2, and the third organic light-emitting layer EL3 may comprise organic materials capable of emitting light based on signals provided from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3.

[0084] The cathode electrode CE can cover the pixel defining layer PDL and the first organic light-emitting layer EL1, the second organic light-emitting layer EL2, and the third organic light-emitting layer EL3. The cathode electrode CE can be connected to the first organic light-emitting layer EL1, the second organic light-emitting layer EL2, and the third organic light-emitting layer EL3. Thus, the cathode electrode CE can be a common electrode provided to the first organic light-emitting layer EL1, the second organic light-emitting layer EL2, and the third organic light-emitting layer EL3. The cathode electrode CE can be connected to the second power voltage node VSSN.

[0085] A first pixel can be provided, comprising a first pixel circuit PC1, a first anode electrode AE1, a cathode electrode CE, and a first organic light-emitting layer EL1 disposed between the first anode electrode AE1 and the cathode electrode CE. Similarly, a second pixel can be provided, comprising a second pixel circuit PC2, a second anode electrode AE2, a cathode electrode CE, and a second organic light-emitting layer EL2 disposed between the second anode electrode AE2 and the cathode electrode CE. A third pixel can also be provided, comprising a third pixel circuit PC3, a third anode electrode AE3, a cathode electrode CE, and a third organic light-emitting layer EL3 disposed between the third anode electrode AE3 and the cathode electrode CE.

[0086] Figure 5 It shows the use Figure 1 Mask fabrication for deposition shown Figure 4 A schematic cross-sectional view of the manufacturing process of the display panel shown.

[0087] refer to Figure 5 It can provide a display panel DP, which includes a substrate SUB, a pixel circuit layer PCL, a first anode electrode AE1, a second anode electrode AE2 and a third anode electrode AE3, and a pixel definition layer PDL.

[0088] refer to Figure 1 and Figure 2 The described deposition mask MSK can be configured to contact or be adjacent to the pixel-defining layer PDL of the display panel DP, while the pattern layer PL is aligned to face the pixel-defining layer PDL and approaches the display panel DP. Patterned apertures PH can expose first pixel openings to third pixel openings (see...). Figure 4 (PO1, PO2, and PO3 shown in the figures). Furthermore, although not shown in the figures, the patterned aperture PH can expose portions of the pixel-defining layer PDL adjacent to the first pixel opening PO1, the second pixel opening PO2, and the third pixel opening PO3.

[0089] In this state, a first organic light-emitting layer EL1, a second organic light-emitting layer EL2, and a third organic light-emitting layer EL3 can be deposited in the first pixel opening PO1, the second pixel opening PO2, and the third pixel opening PO3. Furthermore, although not shown in the accompanying drawings, the first organic light-emitting layer EL1, the second organic light-emitting layer EL2, and the third organic light-emitting layer EL3 can also be deposited on the portions of the pixel defining layer PDL adjacent to the first pixel opening PO1, the second pixel opening PO2, and the third pixel opening PO3. Afterwards, the mask MSK used for deposition can be removed, and a reference etched layer can be further formed on top of the first organic light-emitting layer EL1, the second organic light-emitting layer EL2, and the third organic light-emitting layer EL3. Figure 4 The cathode electrode CE is described.

[0090] Figure 6 This is a plan view illustrating another embodiment of the mask used for deposition. Figure 7 It is along Figure 6 The schematic cross-sectional view shown is taken from line II-II'.

[0091] refer to Figure 6 and Figure 7 According to embodiments of the present disclosure, a deposition mask MSK' may include a wafer substrate WS, an inorganic layer IOL, a patterning layer PL, electrode terminals ET, and an insulating layer IL.

[0092] Apart from Figure 6 and Figure 7 The components other than the insulating layer IL shown, namely the wafer substrate WS, the inorganic layer IOL, the patterning layer PL, and the electrode terminals ET, can be configured to interact with the reference. Figure 1 and Figure 2 The wafer substrate WS, inorganic layer IOL, patterned layer PL, and electrode terminals ET described are identical. Therefore, for ease of description, overlapping descriptions will be omitted below.

[0093] An insulating layer IL can be disposed on the patterned layer PL in the deposition region DA and on the inorganic layer IOL in the non-deposition region NDA. Similar to the wafer substrate WS and the inorganic layer IOL, the insulating layer IL can have a circular shape in the planar view and includes an insulating material. In embodiments, the insulating layer IL may include at least one of inorganic and organic insulating materials. For example, the insulating layer IL may include an inorganic insulating material such as silicon oxide (SiO2). x Silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N yFor example, the insulating layer IL may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the insulating materials constituting the insulating layer IL are not necessarily limited to the materials listed above.

[0094] The insulating layer IL may include a plurality of fourth openings OP4 overlapping the corresponding third openings OP3. In an embodiment, similar to the inner surface of the patterned layer PL surrounding each of the third openings OP3, the inner surface of the insulating layer IL surrounding each of the fourth openings OP4 may have a tapered shape in cross-sectional view. This may be because the fourth openings OP4 are formed by wet etching of the insulating layer IL, but this disclosure is not necessarily limited thereto.

[0095] In one embodiment, the longest width of the fourth opening OP4 may be less than the longest width of the third opening OP3 that overlaps with the fourth opening OP4 on the third-direction DR3. In another embodiment, the shortest width of the third opening OP3 may be substantially the same as the longest width of the fourth opening OP4 that overlaps with the third opening OP3 on the third-direction DR3. This means that the inner surfaces of the third opening OP3 and the fourth opening OP4 that overlap on the third-direction DR3 can be continuously connected to each other.

[0096] In this way, multiple fourth openings OP4, multiple third openings OP3 overlapping with the corresponding fourth openings OP4, and a second opening OP2 and a first opening OP1 overlapping with the fourth openings OP4 and the third openings OP3 can be provided in a single unit opening region CELO. According to this structure, deposited material evaporated or sprayed toward the mask MSK' used for deposition can enter through the first opening OP1 and sequentially pass through the second opening OP2, the third opening OP3, and the fourth opening OP4. The path of the deposited material formed by the overlapping first openings OP1, second openings OP2, third openings OP3, and fourth openings OP4 as described above can be defined as a patterned aperture PH.

[0097] In this implementation, the insulating layer IL is positioned to face the display panel (see [reference]). Figure 5 The substrate on which the DP shown has deposited material (see DP) is deposited (see DP) Figure 5 The entire top surface of the SUB shown can be formed to be substantially flat. According to this structure, compensation can be made for factors such as... Figure 2The height difference between the inorganic layer IOL and the pattern layer PL on the third-direction DR3 shown in the diagram may cause a gap between the inorganic layer IOL and the substrate SUB of the display panel DP. In other words, the insulating layer IL can cover both the deposition area DA and the non-deposition area NDA of the mask MSK' used for deposition with the same thickness, thereby minimizing the gap between the mask MSK' used for deposition and the display panel DP. Therefore, the deposition process can be performed stably. Furthermore, the defect rate of the display panel DP can be reduced.

[0098] Figure 8 This is a plan view showing another embodiment of the mask used for deposition. Figure 9 yes Figure 8 The enlarged plan view of region AA shown. Figure 10 It is along Figure 9 The schematic cross-sectional view shown is taken from line III-III'. Figure 11 It is along Figure 9 The schematic cross-sectional view shown is taken by line IV-IV'.

[0099] refer to Figures 8 to 11 According to embodiments of the present disclosure, a deposition mask MSK'' may include a wafer substrate WS, an inorganic layer IOL, a patterned layer PL', an electrode terminal ET, and a bridging element BR.

[0100] Figures 8 to 11 The components shown, excluding the patterned layer PL' and the bridging element BR, namely the wafer substrate WS, the inorganic layer IOL, and the electrode terminals ET, can be configured to interact with the reference. Figure 1 , Figure 2 , Figure 6 and Figure 7 The wafer substrate WS, inorganic layer IOL, and electrode terminals ET described are identical. Therefore, for ease of description, overlapping descriptions will be omitted below.

[0101] With Figure 1 , Figure 2 , Figure 6 and Figure 7 Unlike the pattern layer PL that forms a single entity shown, the pattern layer PL' can be configured with multiple pattern layer PL' blocks, each of which has a size corresponding to a unit opening region CELO. In an embodiment, the pattern layer PL' may include at least one first pattern layer PL1 corresponding to a first unit opening region CELO1, multiple second pattern layers PL2 each corresponding to a second unit opening region CELO2, multiple third pattern layers PL3 each corresponding to a third unit opening region CELO3, and multiple fourth pattern layers PL4 each corresponding to a fourth unit opening region CELO4.

[0102] The first pattern layer PL1 can be a pattern layer PL' block electrically connected to the electrode terminal ET, and can be located at the outermost part of the pattern layer PL' for physical connection to the electrode terminal ET. Figure 8 The diagram shows a first patterned layer PL1 connected to an electrode terminal ET. However, this disclosure is not necessarily limited to this. For example, the first patterned layer PL1 may correspond to... Figure 8 Four patterned layers PL' are disposed at the corners of the deposition region DA in the plurality of patterned layer PL' blocks shown. Although not shown in the figures, four electrode terminals ET may be provided for connection to the first patterned layer PL1, respectively. In the following description, for ease of description, it will be described as follows: Figure 8 The illustration provides an embodiment of a first pattern layer PL1.

[0103] The second pattern layer PL2 can be configured to be spaced apart from the first pattern layer PL1 in the first direction DR1.

[0104] The third pattern layer PL3 can be configured to be spaced apart from the first pattern layer PL1 in the second direction DR2.

[0105] The fourth pattern layer PL4 can be configured to be spaced apart from one of the third pattern layers PL3 in the first direction DR1.

[0106] The second pattern layer PL2, the third pattern layer PL3, and the fourth pattern layer PL4 may be pattern layer PL' blocks that are not physically connected to the electrode terminal ET, and may be electrically connected to the first pattern layer PL1 via the bridging element BR described below.

[0107] The bridging element BR can be disposed on the inorganic layer IOL between two adjacent patterns in the first pattern layer PL1, the second pattern layer PL2, the third pattern layer PL3, and the fourth pattern layer PL4, so as to electrically connect the first pattern layer PL1 to the other pattern layers PL2, PL3, and PL4.

[0108] Therefore, the bridging element BR can be made of a conductive material such as metal, but this disclosure is not necessarily limited to this. In embodiments, the bridging element BR can be formed together with the patterned layer PL' using the same process. Therefore, the bridging element BR and the patterned layer PL' can be made of substantially the same material. For example, similar to the patterned layer PL', the bridging element BR can include silicon (Si), silicon oxide (SiO2), etc. x Silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N yAt least one of the following: . Impurities can be doped into the bridging element BR to make the bridging element BR conductive. For example, when a Group V element such as phosphorus (P), arsenic (As), or antimony (Sb) is doped into the bridging element BR, the bridging element BR can have n-type semiconductor characteristics. For example, when a Group III element such as boron (B), gallium (Ga), or indium (In) is doped into the bridging element BR, the bridging element can have p-type semiconductor characteristics.

[0109] The bridging component BR may include multiple first bridging components BR_1 and multiple second bridging components BR_2.

[0110] The first bridging member BR_1 can electrically connect at least one of the second patterned layers PL2 arranged on the first direction DR1 and at least one of the first patterned layers PL1 to each other, and can electrically connect at least one of the third patterned layers PL3 arranged on the first direction DR1 and at least one of the fourth patterned layers PL4 to each other.

[0111] refer to Figure 9 The first pattern layer PL1 and the second pattern layer PL2, which is adjacent to the first pattern layer PL1 in the first direction DR1, can be electrically connected to each other through the first bridging member BR_1. Similarly, the third pattern layer PL3 and the fourth pattern layer PL4, which is adjacent to the third pattern layer PL3 in the first direction DR1, can also be electrically connected to each other through the first bridging member BR_1. In other words, the first bridging member BR_1 can electrically connect the pattern layer PL' blocks arranged in the first direction DR1 (i.e., the row direction) to each other.

[0112] The second bridging member BR_2 can electrically connect at least one of the third patterned layers PL3 arranged on the second direction DR2 and at least one of the first patterned layers PL1 to each other, and can electrically connect at least one of the second patterned layers PL2 arranged on the second direction DR2 and at least one of the fourth patterned layers PL4 to each other.

[0113] refer to Figure 9 The first pattern layer PL1 and the third pattern layer PL3 adjacent to the first pattern layer PL1 in the second direction DR2 can be electrically connected to each other through the second bridging member BR_2, and the second pattern layer PL2 and the fourth pattern layer PL4 adjacent to the second pattern layer PL2 in the second direction DR2 can be electrically connected to each other through the second bridging member BR_2. In other words, the second bridging member BR_2 can electrically connect the pattern layer PL' blocks arranged in the second direction DR2 (i.e., the column direction) to each other.

[0114] According to this structure, an external voltage applied to the electrode terminal ET can be applied to the first patterned layer PL1 electrically connected to the electrode terminal ET, and to the second patterned layers PL2 to the fourth patterned layers PL4 electrically connected to the first patterned layer PL1 via the first bridging member BR_1 and the second bridging member BR_2. This is because the patterned layer PL' blocks are arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2, but have a structure in which the patterned layer PL' blocks are electrically connected to each other via the first bridging member BR_1 and the second bridging member BR_2. When a positive or negative voltage is applied to the electrode terminal ET during the deposition process, the first patterned layer PL1, the second patterned layer PL2, the third patterned layer PL3, and the fourth patterned layer PL4, as well as the voltage applied to the electrode terminal ET, can have the same polarity. During the deposition process, the display panel (see...) Figure 5 The substrate facing the patterned layer PL' (as shown in DP) Figure 5 The SUB shown can have a polarity opposite to that of the voltage applied to the electrode terminal ET, and therefore, the attractive force between the deposition mask MSK'' and the substrate SUB of the display panel DP can act between them. Thus, the gap between the deposition mask MSK'' and the display panel DP can be minimized by the attractive force generated between them, thereby improving the deposition accuracy of the material. Furthermore, the defect rate of the display panel DP can be reduced.

[0115] Figure 12 It is shown Figure 10 A schematic cross-sectional view of another embodiment. Figure 13 It is shown Figure 11 A schematic cross-sectional view of another embodiment.

[0116] refer to Figure 12 and Figure 13 According to embodiments of the present disclosure, the deposition mask MSK''' may include a wafer substrate WS, an inorganic layer IOL, a patterned layer PL', electrode terminals ET, and an insulating layer IL'. For ease of description, a plan view of the patterned layer PL' is omitted, and... Figure 12 and Figure 13 The diagram shows the first pattern layer PL1 to the fourth pattern layer PL4, which are part of the pattern layer PL'.

[0117] Figure 12 and Figure 13 The components shown, excluding the insulating layer IL', namely the wafer substrate WS, inorganic layer IOL, patterned layer PL', and electrode terminals ET, can be configured to interact with the reference. Figures 8 to 11The wafer substrate WS, inorganic layer IOL, patterned layer PL', and electrode terminals ET described are identical. Therefore, for ease of description, overlapping descriptions will be omitted below.

[0118] An insulating layer IL' may be disposed in the deposition region DA on a portion of the inorganic layer IOL, between the first patterned layer PL1, the second patterned layer PL2, the third patterned layer PL3, and the fourth patterned layer PL4, on the first patterned layer PL1, the second patterned layer PL2, the third patterned layer PL3, and the fourth patterned layer PL4, and on the bridging element BR, and in the non-deposition region NDA on another portion of the inorganic layer IOL. Similar to the wafer substrate WS and the inorganic layer IOL, the insulating layer IL' may have a circular shape in a planar view and includes an insulating material. In embodiments, the insulating layer IL' may include at least one of inorganic insulating materials and organic insulating materials. For example, the insulating layer IL' may include an inorganic insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y For example, the insulating layer IL' may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the insulating materials constituting the insulating layer IL' are not necessarily limited to the materials listed above.

[0119] The insulating layer IL' may include a plurality of fourth openings OP4 overlapping with corresponding third openings OP3 on the third-direction DR3. In an embodiment, similar to the inner surface of the patterned layer PL' surrounding each of the third openings OP3, the inner surface of the insulating layer IL' surrounding each of the fourth openings OP4 may have a tapered shape in cross-sectional view. This may be because the fourth openings OP4 are formed by wet etching of the insulating layer IL', but this disclosure is not necessarily limited to this.

[0120] In this implementation, the longest width of any fourth opening OP4 may be less than the longest width of any third opening OP3 that overlaps with the corresponding fourth opening OP4 on the third-direction DR3. In this implementation, the shortest width of the third opening OP3 may be substantially the same as the longest width of the fourth opening OP4 that overlaps with the third opening OP3 on the third-direction DR3. This means that the inner surfaces of the third opening OP3 and the fourth opening OP4 that overlap on the third-direction DR3 can be continuously connected to each other.

[0121] In this way, multiple fourth openings OP4, multiple third openings OP3 overlapping the multiple fourth openings OP4, and a second opening OP2 and a first opening OP1 overlapping the fourth openings OP4 and the third openings OP3 can be provided in a single unit opening region CELO. According to this structure, deposited material evaporated or sprayed toward the mask MSK used for deposition can enter through the first opening OP1 and sequentially pass through the second opening OP2, the third opening OP3, and the fourth opening OP4. The path of the deposited material formed by the overlapping first opening OP1, second opening OP2, third opening OP3, and fourth opening OP4 as described above can be defined as a patterned aperture PH.

[0122] In this implementation, the insulating layer IL' is positioned to face the display panel (see [reference]). Figure 5 The substrate on which the DP shown has deposited material (see DP) is deposited (see DP) Figure 5 The entire top surface of the SUB shown can be formed to be substantially flat. According to this structure, compensation can be made for factors such as... Figure 11 The height difference between the inorganic layer IOL and the patterned layer PL' on the third-direction DR3 shown in the diagram may cause a gap between the inorganic layer IOL and the substrate SUB of the display panel DP. In other words, the insulating layer IL' can cover both the deposition area DA and the non-deposition area NDA of the mask MSK''' used for deposition with the same thickness, thereby minimizing the gap between the mask MSK''' and the display panel DP. Therefore, the deposition process can be performed stably. Furthermore, the defect rate of the display panel DP can be reduced.

[0123] Figure 14 This is a schematic block diagram illustrating an implementation of the display system.

[0124] refer to Figure 14 The display system 1000 may include a processor 1100 and a display device 1200.

[0125] The processor 1100 can perform various tasks and calculations. In implementations, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system to control the components of the display system 1000.

[0126] Processor 1100 can transmit image data IMG and control signal CTRL to display device 1200. Display device 1200 can display an image based on image data IMG and control signal CTRL. Display device 1200 may include a reference. Figure 4 The description refers to the display panel DP.

[0127] Display system 1000 may include a computing system for providing image display functionality, such as a smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (PMP), navigation system, or ultra-mobile computer (UMPC). Display system 1000 may include at least one of head-mounted display (HMD) device, virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0128] Figures 15 to 18 It is shown Figure 14 The image shows a perspective view of an application example of the display system.

[0129] refer to Figure 15 , Figure 14 The display system 1000 shown can be applied to a smartwatch 2000, which includes a display section 2100 and a band section 2200.

[0130] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 may have a structure in which the band portion 2200 can be mounted on the user's wrist. The display system 1000 and / or display device 1200 may be applied to the display portion 2100 so that image data including time information can be provided to the user.

[0131] refer to Figure 16 , Figure 14 The display system 1000 shown can be applied to an automotive display system 3000. The automotive display system 3000 may include a computing system disposed inside / outside the vehicle to provide image data.

[0132] For example, the display system 1000 and / or display device 1200 may be applied to at least one of the infotainment panel 3100, instrument panel 3200, passenger display 3300, head-up display 3400, side mirror display 3500 and rear seat display 3600 provided in the vehicle.

[0133] refer to Figure 17 , Figure 14 The display system 1000 shown can be applied to smart glasses 4000. Smart glasses 4000 can be a wearable electronic device that can be worn on a user's face. For example, smart glasses 4000 can be a wearable device for augmented reality (AR).

[0134] The smart glasses 4000 may include a frame 4100 and a lens portion 4200. The frame 4100 may include a housing 4110 supporting the lens portion 4200 and a temple portion 4120 for allowing a user to wear the smart glasses 4000. The temple portion 4120 may be hinged to the housing 4110 to fold or unfold relative to the housing 4110.

[0135] The battery, touchpad, microphone, camera, etc., can be built into the frame 4100. The projector for outputting light, the processor for controlling the light signal, etc., can be built into the frame 4100.

[0136] The lens portion 4200 can be an optical component that allows light to pass through or to be reflected. For example, the lens portion 4200 may include glass, transparent synthetic resin, etc.

[0137] To enable the user's eyes to recognize visual information, the lens portion 4200 can reflect an image caused by light signals transmitted from the projector of the frame 4100 through its rear surface (e.g., the surface facing the user's eyes). For example, the user can recognize information displayed on the lens portion 4200, including time, data, etc. The projector and / or lens portion 4200 can be a display device. The display device 1200 can be applied to the projector and / or lens portion 4200.

[0138] refer to Figure 18 , Figure 14 The display system 1000 shown can be applied to a head-mounted display device 5000.

[0139] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality (VR) or mixed reality (MR).

[0140] The head-mounted display device 5000 may include a headband 5100 and a display housing 5200. The headband 5100 may be connected to the display housing 5200. The headband 5100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 5000 to a user's head. The horizontal strap may be configured to surround the side portion of the user's head, and the vertical strap may be configured to surround the upper portion of the user's head. However, this disclosure is not limited thereto. For example, the headband 5100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0141] The display housing 5200 can accommodate the display system 1000 and / or the display device 1200.

[0142] In the mask and display system for deposition according to the present disclosure, adhesion to the substrate can be improved, thereby reducing deposition failure. For example, a voltage can be applied to the patterned layer of the mask for deposition, thereby allowing electrostatic forces to be used during deposition to reduce the gap between the mask for deposition and the substrate.

[0143] The above description is an example of the technical features of this disclosure, and those skilled in the art to which this disclosure pertains will be able to make various modifications and variations. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0144] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to describe it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirit within the equivalent scope is included within the scope of this disclosure.

Claims

1. A mask for deposition, the mask comprising a deposition region and a non-deposition region, the mask comprising: A wafer substrate, including a plurality of first openings spaced apart from each other; An inorganic layer is disposed on the wafer substrate and includes a plurality of second openings, each of the plurality of second openings overlapping a corresponding one of the plurality of first openings in a plan view; A patterned layer, disposed on the inorganic layer, is doped with impurities to be conductive, and includes a plurality of third openings, wherein the plurality of third openings overlap with one of the plurality of first openings and one of the plurality of second openings in a plan view, wherein the one of the first openings and the one of the second openings overlap each other; as well as At least one electrode terminal is electrically connected to the patterned layer to apply an external voltage to the patterned layer. The wafer substrate and the inorganic layer are formed in the deposition region and the non-deposition region, respectively. The pattern layer is formed in the deposition area, and At least one electrode terminal is formed in the non-deposition region.

2. The mask according to claim 1, wherein, The at least one electrode terminal is made of a conductive material.

3. The mask according to claim 1, wherein, The patterned layer forms a single entity throughout the entire deposition area.

4. The mask according to claim 1, further comprising: An insulating layer is disposed on the patterned layer in the deposition region and on the inorganic layer in the non-deposition region, and includes a plurality of fourth openings, each of the plurality of fourth openings overlapping a corresponding one of the plurality of third openings in a plan view.

5. The mask according to claim 1, wherein, The pattern layer includes: At least one first patterned layer is electrically connected to the at least one electrode terminal; Multiple second patterned layers are spaced apart from the at least one first patterned layer in a first direction; Multiple third patterned layers are spaced apart from the at least one first patterned layer in a second direction intersecting the first direction; and A plurality of fourth pattern layers, spaced apart from one of the plurality of third pattern layers in the first direction, and The mask further includes a bridging element that electrically connects the at least one first patterned layer to the plurality of second patterned layers, the plurality of third patterned layers, and the plurality of fourth patterned layers.

6. The mask according to claim 5, wherein, The external voltage applied to the at least one first patterned layer through the at least one electrode terminal is applied to the plurality of second patterned layers, the plurality of third patterned layers, and the plurality of fourth patterned layers through the bridging member.

7. The mask according to claim 5, wherein, The bridging element is disposed on the inorganic layer between adjacent patterned layers among the at least one first patterned layer, the plurality of second patterned layers, the plurality of third patterned layers, and the plurality of fourth patterned layers.

8. The mask according to claim 5, wherein, The bridging component includes: A plurality of first bridging elements electrically connect at least one of the plurality of second patterned layers arranged in the first direction and the at least one first patterned layer to each other, and electrically connect at least one of the plurality of third patterned layers arranged in the first direction and at least one of the plurality of fourth patterned layers to each other; and A plurality of second bridging elements electrically connect at least one of the plurality of third patterned layers arranged in the second direction and at least one of the plurality of first patterned layers to each other, and electrically connect at least one of the plurality of second patterned layers arranged in the second direction and at least one of the plurality of fourth patterned layers to each other.

9. The mask according to claim 5, further comprising: An insulating layer is disposed in the deposition region on a portion of the inorganic layer between the at least one first patterned layer, the plurality of second patterned layers, the plurality of third patterned layers, and the plurality of fourth patterned layers, on the at least one first patterned layer, the plurality of second patterned layers, the plurality of third patterned layers, and the plurality of fourth patterned layers, and on the bridging member; and in the non-deposition region on another portion of the inorganic layer, and includes a plurality of fourth openings, each of the plurality of fourth openings overlapping a corresponding one of the plurality of third openings in a plan view.

10. A display system, comprising: An organic light-emitting layer is disposed between the cathode electrode and the anode electrode. The organic light-emitting layer is formed from the mask according to claim 1.

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