Karatsuba large number multiplier based on FPGA

Abstract

The invention provides a Karatsuba large number multiplier based on an FPGA (Field Programmable Gate Array), a subtraction form of a Karatsuba algorithm is introduced, and the Karatsuba large number multiplier capable of carrying out multi-stage iteration is provided by carrying out symbol preprocessing until the Karatsuba large number multiplier is matched with a DSP (Digital Signal Processor) multiplier component primitive with symmetric or asymmetric input. The method has the advantages that the influence caused by intermediate multiplier bit width expansion can be eliminated through symbol preprocessing, the usage amount of DSP multipliers can be effectively reduced, and the operation efficiency of large number multiplication is improved.

Description

Technical Field

[0001] This application belongs to the fields of information security and hardware acceleration technology for large number multiplication, specifically relating to an FPGA-based Karatsuba large number multiplier. Background Technology

[0002] Elliptic Curve Cryptography (ECC) is an encryption technique based on the mathematical structure of elliptic curves, widely used in modern information security. The core of ECC lies in using point operations on elliptic curves to achieve encryption, decryption, signing, and key exchange. Compared to traditional asymmetric encryption algorithms such as RSA, ECC requires shorter key lengths and is more computationally efficient while providing the same level of security, making it particularly suitable for resource-constrained environments.

[0003] In ECC, scalar multiplication is one of the most important and time-consuming operations. Scalar multiplication involves multiplying a point on an elliptic curve by a scalar, which requires a large number of large number multiplication operations. The high computational complexity of large number multiplication is one of the key factors limiting ECC performance. To address this issue, improving the computational efficiency of large number multiplication has become a key focus of ECC optimization.

[0004] The Karatsuba algorithm is an efficient algorithm for large number multiplication. By decomposing large number multiplication into several smaller multiplication and addition operations, it reduces computational complexity and significantly improves computation speed. However, during the large number decomposition process, the expansion of the intermediate variable bit width requires a multiplier with a larger bit width, making multi-level iteration difficult and wasting on-chip resources.

[0005] Traditional textbook algorithms require four k / 2-bit multiplications to complete one k-bit multiplication calculation:

[0006] XY={X1,X2}{Y1,Y2}=X1Y12 k +(X2Y1+X1Y2)2 k / 2 +X2Y2

[0007] Where X1 and Y1 are the high k / 2 bits of X and Y, and X2 and Y2 are the low k / 2 bits of X and Y. The Karatsuba algorithm calculates X1Y2 + X2Y1 by repeatedly using the intermediate variables X1T1 and X2T2, which allows us to replace two multiplications and one addition with four additions and one multiplication:

[0008] X1Y2+X2Y1=(X1+X2)(Y1+Y2)-X1Y1-X2Y2

[0009] It should be noted that the introduction of addition requires a multiplier with a bit width of k / 2+1 bits to complete (X1+X2)(Y1+Y2), resulting in insufficient logic circuit resource consumption. Summary of the Invention

[0010] The purpose of this application is to overcome the shortcomings of existing large number multiplication methods, which consume a lot of resources.

[0011] To achieve the above objectives, this application proposes an FPGA-based Karatsuba large number multiplier for multiplying two unsigned numbers, including a level-2 Karatsuba multiplier module;

[0012] The level-2 Karatsuba multiplier module is used to perform multiplication of two m-bit unsigned numbers using Karatsuba subtraction; it includes:

[0013] The first decomposition unit is used to decompose the m-bit multipliers A and B into k numbers, each with a maximum length of n bits. bit, This represents rounding up, denoted as A0…A k-1 and B0…B k-1 The splitting results are output to the first level-1 Karatsuba multiplier submodule and the first subtraction unit;

[0014] The first level-1 Karatsuba multiplier submodule is used to compute A. e ×B e Get p e (0≤e≤k-1), output the multiplication result to the first addition / subtraction unit;

[0015] The first subtraction unit is used to calculate (A) e -A f ) and (B e -B f (0≤e≤k-1,0≤f≤k-1,e≠f), thus we obtain a ef and b ef The output is sent to the second level-1 Karatsuba multiplier submodule;

[0016] The second level-1 Karatsuba multiplier submodule is used to compute a. ef and b ef absolute value | a ef | and |b ef |, then calculate |a ef |×|b ef |, finally after a ef and bef XORing the highest bit and then performing sign extension yields p. ef (0≤e≤k-1,0≤f≤k-1,e≠f), output the multiplication result to the first addition / subtraction unit;

[0017] The first addition / subtraction unit is used to calculate the coefficients of each term in the multiplication result and output them to the first shift unit;

[0018] The first shift unit is used to calculate the various terms of the multiplication result and output them to the first adder unit; and

[0019] The first addition unit is used to add the terms of the multiplication result and output the multiplication result of two m-bit unsigned numbers.

[0020] As an improvement to the aforementioned large number multiplier

[0021] The first level-1 Karatsuba multiplier submodule and the second level-1 Karatsuba multiplier submodule are the same, both including:

[0022] The second splitting unit is used to split the two input n-bit unsigned numbers into r numbers, each with a maximum length of r bits. bit, This represents rounding up, denoted as C0…C l-1 and D0…D l-1 The output of each pair of split operation units is sent to the first DSP48E unit and the second subtraction unit.

[0023] The first DSP48E unit is used to calculate C. i ×D i Get q i (0≤i≤l-1), output the multiplication result to the first addition / subtraction unit;

[0024] The second subtraction unit is used to calculate (C) i -C j ) and (D i -D j (0≤i≤l-1, 0≤j≤l-1, i≠j), thus obtaining c ij and d ij The output is sent to the second DSP48E unit;

[0025] The second DSP48E unit is used to perform the multiplication of two signed numbers and calculate c. ij ×d ij , get q ij (0≤i≤l-1,0≤j≤l-1,i≠j), output the multiplication result to the second addition / subtraction unit;

[0026] The second addition / subtraction unit is used to calculate the coefficients of each term in the multiplication result and output them to the second shift unit;

[0027] The second shift unit is used to calculate the terms of the multiplication result and output them to the second adder unit; and

[0028] The second addition unit is used to add the terms and output the multiplication result of two n-bit unsigned numbers.

[0029] As an improvement to the aforementioned large number multiplier, the second splitting unit also supports asymmetric splitting.

[0030] Compared with existing technologies, the advantages of this application are:

[0031] 1. This invention can eliminate the influence of intermediate multiplier width expansion through symbol preprocessing, and can ignore the influence of bit width expansion during multi-level iteration.

[0032] 2. This invention uses the Karatsuba subtraction method to calculate multiplication, which can effectively reduce the consumption of on-chip DSP resources and improve the efficiency of large number calculation.

[0033] 3. Compared with existing methods, the present invention does not require an additional sign bit register. By comparing the size of the two subtrahends, the sign is stored in the sign bit register. The preprocessing and expansion of the sign can be completed only based on the highest bit of the subtraction result. Attached Figure Description

[0034] Figure 1 The diagram shown is a submodule structure diagram of the level-1 Karatsuba multiplier.

[0035] Figure 2 The diagram shown is a structural diagram of the level-2 Karatsuba multiplier module. Detailed Implementation

[0036] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0037] This application provides an FPGA-based Karatsuba large number multiplier for cryptographic applications based on elliptic cryptography. It introduces the subtraction form of the Karatsuba algorithm, performs symbol preprocessing, and conducts multi-level iterations of the Karatsuba large number multiplier, reducing the waste of on-chip resources and achieving efficient large number multiplication.

[0038] The FPGA-based Karatsuba large number multiplier provided in this application can be applied to accelerate large number multiplication in information security and other fields such as elliptic cryptography, RSA, homomorphic encryption, and privacy protection, thereby improving computational efficiency. This application will mainly use the large number multiplication adapted to FPGA multiplication components (but is not limited to FPGA multiplication components; it can also be used in multipliers within DSP or CPU chips) as an example to explain the implementation method in detail. Through two-level or multi-level splitting and iteration, it can be applied to scalar multiplication operations of common elliptic cryptography with bit widths of 256 bits, 384 bits, and 512 bits, as well as large number multiplication operations with bit widths of 1024 bits, 2048 bits, 4096 bits, and longer.

[0039] The FPGA-based Karatsuba large number multiplier includes a level-2 Karatsuba multiplier module. The workflow of the large number multiplier is as follows: The level-2 Karatsuba multiplier module decomposes the input m-bit unsigned number into m / k-bit arithmetic units. If m / k > n, the level-2 Karatsuba multiplier is recursively called; if m / k ≤ n, the level-1 Karatsuba multiplier is called. Calculations are performed according to the subtraction form of the Karatsuba algorithm. During the operation, intermediate values ​​undergo sign preprocessing to ensure they meet the maximum processing bit width of the multiplier. The level-1 Karatsuba multiplier submodule decomposes the input n-bit unsigned number into n / k-bit arithmetic units, and the correct result is obtained through on-chip DSP calculation.

[0040] The level-2 Karatsuba multiplier module performs m-bit unsigned number multiplication using Karatsuba subtraction and includes: a first splitting unit, a first level-1 Karatsuba multiplier submodule, a first subtraction unit, a second level-1 Karatsuba multiplier submodule, a first addition / subtraction unit, a first shifting unit, and a first addition unit.

[0041] The first decomposition unit is used to decompose the m-bit multipliers A and B into k numbers, each with a maximum length of n bits. bit( (This represents rounding up), denoted as A0…A k-1 and B0…B k-1 The splitting results are output to the first level-1 Karatsuba multiplier submodule and the first subtraction unit.

[0042] The first level-1 Karatsuba multiplier submodule is the same as the second level-1 Karatsuba multiplier submodule, performing n-bit unsigned number multiplication and finally outputting a 2n-bit unsigned number product. It includes: a second splitting unit, a first DSP48E unit, a second subtraction unit, a second DSP48E unit, a second addition / subtraction unit, a second shift unit, and a second addition unit.

[0043] The second splitting unit is used to split the two input n-bit unsigned numbers into r numbers, each with a maximum length of r bits. bit( (This represents rounding up), denoted as C0…C l -1 and D0…D l -1 outputs each pair of split operation units to the first DSP48E unit and the second subtraction unit.

[0044] The first DSP48E unit calculates C. i ×D i Get q i (0≤i≤l-1), output the multiplication result to the first addition / subtraction unit. It can perform a maximum of 24-bit × 17-bit signed number multiplication.

[0045] The second subtraction unit is used to calculate (C) i -C j ) and (D i -D j (0≤i≤l-1, 0≤j≤l-1, i≠j), thus obtaining c ij and d ij The output is sent to the second DSP48E unit.

[0046] The second DSP48E unit is used to perform the multiplication of two signed numbers and calculate c. ij ×d ij , get q ij (0≤i≤l-1,0≤j≤l-1,i≠j), output to the second addition / subtraction unit.

[0047] The second addition / subtraction unit is used to calculate the coefficients of each term and output them to the second shift unit.

[0048] The second shift unit is used to calculate the various terms and output them to the second adder unit.

[0049] The second addition unit is used to add the terms and output the multiplication result of two n-bit unsigned numbers.

[0050] The overall working process of the level-1 Karatsuba multiplier submodule is as follows: It splits the two input n-bit unsigned numbers into r bits, each with a maximum length of r bits. bit( (Indicates rounding up), multiplication is calculated using the Karatsuba subtraction method. The FPGA on-chip DSP48E unit can perform a maximum of 24-bit × 17-bit signed number multiplication, and the effect of sign extension can be ignored. The splitting is not limited to symmetric splitting. Asymmetric splitting can be performed when it can reduce the use of on-chip DSP resources and meet the requirements of 24-bit × 17-bit signed number multiplication.

[0051] The first level-1 Karatsuba multiplier submodule calculates A. e ×B e Get p e (0≤e≤k-1), output the multiplication result to the first addition / subtraction unit.

[0052] The first subtraction unit is used to calculate (A) e -A f ) and (B e -B f (0≤e≤k-1,0≤f≤k-1,e≠f), thus we obtain a ef and b ef The output is sent to the second level-1 Karatsuba multiplier submodule.

[0053] The second level-1 Karatsuba multiplier submodule calculates a. ef and b ef absolute value | a ef | and |b ef |, then calculate |a ef |×|b ef |, finally after a ef and b ef XORing the highest bit and then performing sign extension yields p. ef (0≤e≤k-1,0≤f≤k-1,e≠f), output the multiplication result to the first addition / subtraction unit.

[0054] The first addition / subtraction unit is used to calculate the coefficients of each term and output them to the first shift unit.

[0055] The first shift unit is used to calculate each term and output it to the first adder unit.

[0056] The first addition unit is used to add the various expressions and output the multiplication of two m-bit unsigned numbers.

[0057] The overall working process of the level-2 Karatsuba multiplier module is as follows: The m-bit multipliers A and B are decomposed into m / kbit (rounded up) arithmetic units. First, A is calculated... e Multiply by B e A e minus A f and B e minus B f , where A e Multiply by B e Executed by the first level-1 Karatsuba multiplier submodule (0≤e≤k-1, 0≤b≤k-1, e≠f), since the sign extension caused by the subtraction operation does not meet the maximum bit width of the level-1 Karatsuba multiplier, it is converted into an unsigned number through sign preprocessing, and then executed by the second level-1 Karatsuba multiplier submodule. e -A f Multiply by B e -B f After the multiplication operation is completed, the highest bit of the subtraction result is checked. If the highest bit is 1, the opposite number is taken; if it is 0, it remains unchanged. The sign of the product is extended by XORing the highest bits of the two subtraction results. If the XOR result is 0, the final result is positive; otherwise, it is negative. Finally, the final result is obtained through addition, subtraction, and shift operations, and a 2m-bit unsigned product is output.

[0058] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. These embodiments are used to illustrate the present invention and are not intended to limit the scope of protection of the present invention. The following explanation will take 256-bit large number multiplication as an example.

[0059] Figure 1 This is a diagram of the Level-1 Karatsuba multiplier submodule. The Level-1 Karatsuba multiplier performs 64-bit unsigned number multiplication using Karatsuba subtraction, decomposing the 64-bit multiplication operation into 16-bit multiplication operations, implemented by on-chip DSP resources. The final result is obtained through addition, subtraction, and shift operations. Below are the specific calculation steps, calculating the input 64-bit unsigned numbers X and Y respectively:

[0060] p0 = X[15:0]Y[15:0],

[0061] p1 = X[31:16]Y[31:16],

[0062] p2 = X[47:32]Y[47:32],

[0063] p3 = X[63:48]Y[63:48],

[0064] p 32 =(X[63:48]-X[47:32])(T[63:48]-T[47:32]),

[0065] p 31 =(X[63:48]-X[31:16])(Y[63:48]-Y[31:16]),

[0066] p 30 =(x[63:48]-X[15:0])(Y[63:48]-Y[15:0]),

[0067] p 21 =(X[47:32]-X[31:16])(Y[47:32]-Y[31:16]),

[0068] p 20 =(X[47:32]-X[15:0])(Y[47:32]-Y[15:0]),

[0069] p10=(X[31:16]-X[15:0])(Y[31:16]-Y[15:0]),

[0070] The above multiplication operations are performed using on-chip DSP resources, where p0, p1, p2, and p3 are performed by the first DSP48E unit. 32 p 31 p 30 p 21 p 20 p10 is performed by the second DSP48E unit. After completing the above multiplication operation, s1 = p1 + p0 - p 10 s2 = p2 + p1 + p0 - p 20 s3 = p3 + p0 - p 30 +p2+p1-p 21 s4 = p3 + p2 + p1 - p 31 s5 = p3 + p2 - p 32 Finally, Q = p0 + {s1, 16'b0} + {s2, 32'b0} + {s3, 48'b0} + {s4, 64'b0} + {s5, 80'b0} + {p3, 96'b0} is calculated, and Q is the product of two 64-bit unsigned numbers.

[0071] Figure 2This is a diagram of the level-2 Karatsuba multiplier module. The level-2 Karatsuba multiplier module performs 256-bit unsigned number multiplication using Karatsuba subtraction, decomposing the 256-bit multiplication operation into 64-bit multiplication operations. During the operation, the intermediate value undergoes sign preprocessing. The highest bit after subtraction is checked; if it is 1, the opposite is taken; if it is 0, it remains unchanged, ensuring it meets the maximum processing bit width of the level-1 Karatsuba multiplier submodule. Then, the sign is extended based on the XOR result of the highest bits of the two subtractions. If the XOR result is 0, the final result is positive; otherwise, it is negative. Finally, the final result is obtained through addition, subtraction, and shift operations. The specific calculation steps are as follows: Calculate the input 256-bit unsigned numbers X and Y respectively:

[0072] a 32 =X[255:192]-X[191:128],a 31 =X[255:192]-X[127:64],

[0073] a 30 =X[255:192]-X[63:0], a 21 =X[191:128]-X[127:64],

[0074] a 20 =X[191:128]-X[63:0], a 10 =X[127:64]-X[63:0],

[0075] b 32 =Y[255:192]-Y[191:128], b 31 =Y[255:192]-Y[127:64],

[0076] b 30 =Y[255:192]-Y[63:0], b 21 =Y[191:128]-Y[127:64],

[0077] b 20 =Y[191:128]-Y[63:0], b 10 =Y[127:64]-Y[63:0],

[0078] p0=X[63:0]Y[63:0], p1=X[127:64]Y[127:64],

[0079] p2=X[191:128]Y[191:128], p3=X[255:192]Y[255:192],

[0080] a′ 32 =a 32

[64] ==1?-a 32 :a 32 ,b′ 32 =b 32

[64] ==1?-b 32 :b 32 ,

[0081] a′ 31 =a 31

[64] ==1?-a 31 :a 31 ,b′ 31 =b 31

[64] ==1?-b 31 :b 31 ,

[0082] a′ 30 =a 30

[64] ==1?-a 30 :a 30 ,b′ 30 =b 30

[64] ==1?-b 30 :b 30 ,

[0083] a′ 21 =a 21

[64] ==1?-a 21 :a 21 ,b′ 21 =b 21

[64] ==1?-b 21 :b 21 ,

[0084] a′ 20 =a 20

[64] ==1?-a 20 :a 20 ,b′ 20 =b 20

[64] ==1?-b 20 :b 20 ,

[0085] a′ 10 =a 10

[64] ==1?-a 10 :a 10 ,b′ 10 =b 10

[64] ==1?-b 10 :b 10 ,

[0086] p′ 32 =a′ 32 b′ 32 , p′ 31 =a′ 31 b′ 31 , p′ 30 =a′ 30 b′ 30 , p′ 21 =a′ 21 b′ 21 , p′ 20 =a′ 20 b′ 20 , p′ 10 =a′ 10 b′ 10 ,

[0087] The above multiplication is performed by a first-level 64-bit Karatsuba multiplier, where p0, p1, p2, and p3 are performed by the first level-1 Karatsuba multiplier submodule. Since a... 32 a 31 a 30 a 21 a 20 a 10 b 32 b 31 b 30 b 21 b 20 b 10 The maximum bit width of the intermediate subtraction operation is 65 bits, which does not meet the multiplier bit width requirement of the first-stage 64-bit Karatsuba multiplier. Through sign preprocessing, the bit width impact of sign extension is ignored, reducing the maximum bit width of the intermediate multiplier to 64 bits, p′ 32 , p′ 31 , p′ 30 , p′ 21 , p′ 20 , p′ 10 This is performed by the second level-1 Karatsuba multiplier submodule. After the multiplication calculation is completed, it is based on a 32 a 31 a 30 a 21 a 20 a 10 b 32 b 31 b 30 b 21 b 20 b 10 Original symbols are extended to sign of the product:

[0088] p 32 =(a 32

[64] ^b 32

[64] )? p′ 32 :-p′ 32 ,

[0089] p 31 =(a 31

[64] ^b 31

[64] )? p′ 31 :-p′ 31 ,

[0090] p 30 =(a 30

[64] ^b 30

[64] )? p′ 30 :-p′ 30 ,

[0091] p 21 =(a 21

[64] ^b 21

[64] )? p′ 21 :-p′ 21 ,

[0092] p 20 =(a 20

[64] ^b 20

[64] )? p′ 20 :-p′ 20 ,

[0093] p 10 =(a 10

[64] ^b 10

[64] )? p′ 10 :-p′ 10 ,

[0094] The final calculation is s1 = p1 + p0 - p 10 s2 = p2 + p1 + p0 - p 20 s3 = p3 + p0 - p 30 +p2+p1-p 21 s4 = p3 + p2 + p1 - p 31 s5 = p3 + p2 - p 32 Q = p0 + {s1, 64′b0} + {s2, 128′b0} + {s3, 192′b0} + {s4, 256′b0} + {s5, 320′b0} + {p3, 384′b0}, where Q is the product of two 256-bit unsigned numbers.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application, and should all be covered within the scope of the claims of this application.

Claims

1. A Karatsuba large number multiplier based on FPGA for multiplying two unsigned numbers, characterized in that, include: Level-2 Karatsuba multiplier module; The level-2 Karatsuba multiplier module is used to perform multiplication of two mbit unsigned numbers using Karatsuba subtraction; it includes: The first decomposition unit is used to decompose the mbit multipliers A and B into k numbers, each with a maximum length of n bits. This represents rounding up, denoted as A0...A k-1 and B0...B k-1 The splitting results are output to the first level-1 Karatsuba multiplier submodule and the first subtraction unit; The first level-1 Karatsuba multiplier submodule is used to compute A. e ×B e Get p e (0≤e≤k-1), output the multiplication result to the first addition / subtraction unit; The first subtraction unit is used to calculate (A) e -A f ) and (B e -B f (0≤e≤k-1,0≤f≤k-1,e≠f), we get a ef and b ef The output is sent to the second level-1 Karatsuba multiplier submodule; The second level-1 Karatsuba multiplier submodule is used to calculate a. ef and b ef absolute value | a ef | and |b ef |, then calculate |a ef |×|b ef |, finally after a ef and b ef XORing the highest bit and then performing sign extension yields p. ef (0≤e≤k-1,0≤f≤k-1,e≠f), output the multiplication result to the first addition / subtraction unit; The first addition / subtraction unit is used to calculate the coefficients of each term in the multiplication result and output them to the first shift unit; The first shift unit is used to calculate the various terms of the multiplication result and output them to the first adder unit; and The first addition unit is used to add the terms of the multiplication result and output the multiplication result of two mbit unsigned numbers.

2. The FPGA-based Karatsuba large number multiplier according to claim 1, characterized in that, The first level-1 Karatsuba multiplier submodule and the second level-1 Karatsuba multiplier submodule are the same, both including: The second splitting unit is used to split the two input n-bit unsigned numbers into l numbers, each with a maximum length of r bits. This represents rounding up, denoted as C0…C l-1 and D0…D l-1 The output of each pair of split operation units is sent to the first DSP48E unit and the second subtraction unit. The first DSP48E unit is used to calculate C. i ×D i Get q i (0≤i≤l-1), output the multiplication result to the first addition / subtraction unit; The second subtraction unit is used to calculate (C) i -C j ) and (D i -D j (0≤i≤l-1,0≤j≤l-1,i≠j), thus obtaining c ij and d ij The output is sent to the second DSP48E unit; The second DSP48E unit is used to perform the multiplication of two signed numbers and calculate c. ij ×d ij , get q ij (0≤i≤l-1,0≤k≤l-1,i≠j), output the multiplication result to the second addition / subtraction unit; The second addition / subtraction unit is used to calculate the coefficients of each term in the multiplication result and output them to the second shift unit; The second shift unit is used to calculate the terms of the multiplication result and output them to the second adder unit; and The second addition unit is used to add the terms and output the multiplication result of two n-bit unsigned numbers.

3. The FPGA-based Karatsuba large number multiplier according to claim 1, characterized in that, The second splitting unit also supports asymmetric splitting.

Images