Online burning system of SPI FlashRom of SOC chip system

Abstract

The invention discloses an online burning system of an SPI FlashRom of an SOC chip system, and belongs to the technical field of SOC chip design, the system comprises an SPI controller IO control module, a physical connection module and a burner module; an IO control module of the SPI controller realizes state switching and latching of IO ports linked with reset signals, and signal driving of a chip to the SPI FlashRom is cut off during burning; the physical connection module builds mutually isolated native communication and burning links through double-path wiring, and realizes disassembly-free physical butt joint after SPI FlashRom welding; the burner module directly generates an SPI native burning protocol and signal, and bypasses a chip SPI controller to complete high-speed automatic burning. According to the method, high-speed online burning of the SPI FlashRom is achieved, non-invasive control is achieved, the original hardware architecture and working logic of the SOC chip are not changed, burning operation is convenient and fast, hardware safety is high, the method is suitable for laboratory debugging and production line batch burning scenes, burning efficiency is greatly improved, and operation cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of SOC chip design technology, and in particular to an in-circuit programming system for SPI FlashRom of an SOC chip system. Background Technology

[0002] As a non-volatile memory device, SPI FlashROM is the core storage carrier for firmware, programs, and key parameters in a System-on-a-Chip (SoC) chip system. Its programming performance directly affects the SoC chip's production efficiency, debugging convenience, and operational stability. Therefore, in-circuit programming of SPI FlashROM has become a crucial technical aspect in the SoC chip's R&D, production, and post-debugging processes. Currently, the industry mainly employs two methods for programming SPI FlashROM in SoC chip systems: one is offline programming followed by soldering, where a dedicated programmer is used to program the firmware on an independent SPI FlashROM, and then the SPI FlashROM is soldered onto the corresponding PCB board of the SoC chip; the other is in-circuit programming, where the SPI FlashROM is first soldered to the PCB board, and then the SoC chip's debug port calls the chip's internal SPI controller, which sends programming commands and data to the SPI FlashROM, achieving in-circuit firmware programming.

[0003] Existing SPI FlashROM programming methods all have significant technical flaws and are no longer suitable for the high-efficiency requirements of SOC chip R&D, debugging, and mass production. For offline programming followed by soldering, the process is cumbersome, with programming and soldering being two separate steps. If firmware modifications are needed during R&D or firmware programming errors occur during mass production, the soldered SPI FlashROM must be removed from the PCB board, reprogrammed, and then soldered again. This not only significantly increases the number of steps and time costs but also easily causes physical damage to the SPI FlashROM pins and PCB board pads due to repeated soldering, reducing overall hardware reliability. For online programming via the debug port to call the chip's SPI controller, the programming commands and data must undergo multiple conversions through the debug protocol, the SOC chip's internal bus protocol, and the SPI protocol. These multiple protocol conversions result in significant speed loss, making the actual programming speed far lower than the native transmission rate of the SPI FlashROM, leading to low programming efficiency. Furthermore, this method is highly dependent on the SOC chip's debug port resources; in some debugging scenarios, the programming operation may conflict with the chip's debug function, limiting the applicability of this programming method.

[0004] As SOC chips rapidly evolve towards high integration, miniaturization, and mass production, the industry has placed higher demands on SPI FlashRom programming technology. This requires both in-circuit programming of SPI FlashRom without disassembly or disconnection after soldering, simplifying the operation process, and increasing programming speed to fully utilize the native transmission characteristics of SPI FlashRom. Simultaneously, it must ensure that the programming process does not alter the SOC chip's native hardware architecture and operating logic, does not consume additional peripheral resources, balances hardware security and functional integrity, and adapts to various scenarios from small-batch debugging in the laboratory to large-scale batch programming on production lines. However, current technologies lack a programming solution that simultaneously meets all these requirements. Some suffer from cumbersome operation and hardware damage, while others exhibit slow programming speeds and resource conflicts, failing to effectively address the industry pain points of SPI FlashRom programming for SOC chip systems. Therefore, developing an efficient, convenient, and secure in-circuit programming system for SPI FlashRom of SOC chip systems has become an urgent technical challenge. Summary of the Invention

[0005] This invention provides an online programming system for SPI FlashRom of SOC chip system, which aims to solve the technical problems of existing SPI FlashRom programming methods being cumbersome to operate, slow to program, and prone to conflict with the chip's native functions.

[0006] This invention provides an in-circuit programming system for SPI FlashROM of a SOC chip system, comprising: The SPI controller IO control module is configured to switch all SPI controller IO ports to a pure input, undriven state and stop outputting level and control signals to the SPI FlashRom IO ports when a system reset signal is detected. A physical connection module, configured to establish physical and electrical connection channels between the programmer module and the SPI FlashROM, enabling in-circuit programming of the SPI FlashROM after it has been soldered to the PCB board; and The programmer module is configured to establish a direct physical and electrical connection with the SPI FlashRom's I / O port. When the SOC chip is in a reset state and the SPI FlashRom I / O port is not driven, it directly outputs control signals and programming data to the SPI FlashRom.

[0007] In one embodiment of the present invention, a reset signal linkage control module is further included, which is configured to switch between the burning mode and the normal operating mode of the system.

[0008] In one embodiment of the present invention, the SPI controller I / O control module includes: The SPI controller I / O port array is configured to provide a physical channel for SPI communication between the SOC chip's SPI controller and the SPI FlashROM; The reset signal detection and triggering unit is configured to immediately generate and output an IO state switching trigger signal when a reset signal is detected, and transmit it to the IO port state switching logic circuit. The IO port state switching logic circuit is configured to receive the IO state switching trigger signal output by the reset signal detection and trigger unit, execute the working state switching operation of the SPI controller IO port, and realize the switching of the IO port between the normal driving state and the pure input no-drive state.

[0009] In one embodiment of the present invention, the SPI controller I / O control module further includes: The state latch unit is configured to continuously latch the state after the IO port switches to a pure input undriven state.

[0010] In one embodiment of the present invention, the physical connection module includes: The SPI FlashRom soldering unit includes soldering pads and connection traces corresponding to the SPI FlashRom, providing a fixed soldering position for the SPI FlashRom on the PCB board; The programming physical interface unit consists of a programmer socket and a dedicated pin header, which connects to all I / O ports of the SPI FlashRom. Dual-path adapter unit: Each IO port of the SPI FlashROM is configured with an independent dual-path. One path is electrically connected to the SPI controller IO port of the SOC chip, and the other path is electrically connected to the programming physical interface unit.

[0011] In one embodiment of the present invention, the physical connection module further includes an electrical isolation protection unit, which is configured to suppress abnormal electrical signals generated during the insertion and removal of the programmer, and prevent abnormal signals from being transmitted to the SPI FlashRom and SOC chip.

[0012] In one embodiment of the present invention, the programmer module includes: The physical interface connects to a dedicated pin header in the physical connection module. The SPI native protocol generator is configured to generate native SPI control signals and standard programming protocol instructions required for SPI FlashROM programming. The programming instruction execution and control unit is configured to execute programming-related operations sequentially according to the programming instructions.

[0013] In one embodiment of the present invention, the programmer module further includes: The data transmission and caching unit is configured to cache and segment the data to be burned. The programming status detection and feedback unit is configured to collect the status feedback signal of the SPI FlashRom in real time through the physical interface, determine its programming status, and convert the programming status into an indication signal to feed back to the operator.

[0014] In one embodiment of the present invention, the reset signal linkage control module includes: A reset signal generation unit is configured to manually or automatically generate a reset signal that conforms to the SOC chip standard. The system power-on synchronization unit is configured to synchronize the system power-on operation with the occurrence of the reset signal. A reset state holding unit is configured to continuously latch and output the reset signal after the reset signal takes effect; The reset signal release unit is configured to receive a trigger signal and release the latch on the reset signal after the programming process is completed.

[0015] The present invention also provides a method for operating the system according to the above, comprising: The system reset signal is sent from the reset signal linkage control module to the SPI controller IO control module. When a system reset signal is detected, the SPI controller IO control module switches all SPI controller IO ports to a pure input, undriven state, stopping the output of level and control signals to the SPI FlashRom IO ports; Connect the programmer module to the programming physical docking unit in the physical connection module; The programmer module directly outputs control signals and programming data to the SPI FlashROM; After the programming is completed, the reset signal linkage control module controls the SPI controller IO control module to switch back to normal working mode.

[0016] The present invention has the following beneficial effects: (1) The IO port is intelligently switched between driven and undriven states by resetting the SPI controller IO control module. During programming, the chip’s signal drive to the FlashRom is cut off to avoid signal conflicts. The state latch function ensures the exclusivity of the programming channel. During normal operation, the original drive state is restored, and the original communication function between the SOC chip and the FlashRom is fully preserved without affecting the original working characteristics of the chip.

[0017] (2) Dual independent routing isolates the native communication and programming links, ensuring the signal integrity of the chip's native communication and enabling true online programming without disassembly or disconnection after FlashRom soldering; the standardized foolproof docking design enables quick plugging and unplugging of the programmer, and the electrical protection unit effectively avoids hardware damage caused by static electricity and surges, taking into account both ease of operation and hardware safety.

[0018] (3) Directly generate SPI native programming protocol and signal, bypass the chip SPI controller, eliminate the speed loss of multi-layer protocol conversion, and realize FlashRom native speed programming in conjunction with high-speed data cache. Attached Figure Description

[0019] Figure 1 A block diagram of an online programming system for an SOC chip system SPI FlashRom according to an embodiment of the present invention is shown. Detailed Implementation

[0020] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0021] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0022] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 A block diagram of an online programming system for an SOC chip system SPI FlashRom according to an embodiment of the present invention is shown.

[0025] like Figure 1As shown, this embodiment discloses an in-circuit programming system for SPI FlashROM of a SOC chip system. This system is integrated into the SOC chip and its supporting PCB board, and uses dedicated external programming hardware to achieve solderless, high-speed in-circuit programming of SPI FlashROM, effectively solving the technical problems of cumbersome operation and slow speed in traditional programming methods. This system mainly includes three core modules: an SPI controller I / O control module 100, a physical connection module 200, and a programmer module 300. These modules cooperate and are time-matched to achieve seamless switching between the programming mode and the normal working mode of the SOC chip system, without modifying the native hardware architecture or working logic of the SOC chip, thus ensuring the integrity of the system's native functions. The following provides a detailed description of the specific implementation methods, sub-module composition, working principles, and functional relationships of each module.

[0026] The SPI controller I / O control module 100 is integrated into the SPI controller subsystem within the SOC chip. Coupled with the SOC chip's reset pin signal, it forms the core hardware foundation for programming the SPI FlashROM bypassing the SOC chip's SPI controller. Its hardware circuitry consists of four electrically connected sub-modules: an SPI controller I / O port array, a reset signal detection and triggering unit, an I / O port state switching logic circuit, and a state latching unit. Each sub-module is a dedicated hardware circuit with no software protocol intermediaries, ensuring a response delay of ≤1μs and rapid linkage between the reset signal and the I / O port state. Each sub-module independently or collaboratively implements its corresponding core function, as detailed below: The SPI controller IO port array is a standard SPI communication IO port group natively integrated into the SOC chip. It is natively electrically connected to the corresponding IO ports of the SPI FlashROM through a physical connection module. It serves as the only hardware carrier for the SOC chip and the SPI FlashROM to perform regular data interaction and meets the SPI communication requirements for the normal operation of the SOC chip system.

[0027] The reset signal detection and triggering unit, when a valid reset signal is detected, the trigger signal generation circuit immediately generates a high-level trigger signal and outputs it to the IO port state switching logic circuit to establish the linkage triggering logic between the reset signal and the IO port state.

[0028] The IO port state switching logic circuit has its input terminal electrically connected to the output terminal of the reset signal detection and trigger unit, and its output terminal electrically connected to the control terminal of the SPI controller IO port array. This circuit pre-stores two working state logics: normal drive and pure input without drive. When a trigger signal is received from the reset signal detection and trigger unit, it immediately switches all ports of the SPI controller IO port array to the pure input without drive state, cutting off the level drive and signal output of the IO port inside the SOC chip. When no trigger signal is received, it maintains the normal drive state of the IO port array, supporting native communication between the SOC chip and the SPI FlashROM.

[0029] The state latch unit has its input terminal electrically connected to the output terminal of the IO port state switching logic circuit, and its output terminal electrically connected to the enable terminal of the SPI controller IO port array. When the IO port state switching logic circuit switches the IO port to a pure input undriven state, it immediately latches the state signal to keep the circuit continuously providing the operating voltage to the flip-flop. During the validity period of the reset signal, it continuously latches the state to prevent abnormal changes in the IO port state caused by factors such as system power-on surges and external electromagnetic interference, thus ensuring the stability and uniqueness of the state.

[0030] The physical connection module 200, deployed on the system PCB board where the SOC chip and SPI FlashROM reside, is the key physical and electrical carrier for in-circuit programming after SPI FlashROM soldering. It is an integrated design comprising four sub-modules: an SPI FlashROM soldering unit, a programming physical connection unit, a dual-path routing adapter unit, and an electrical isolation protection unit. Each sub-module is implemented at the PCB board level, adhering to high-speed SPI signal routing specifications to ensure signal integrity and transmission stability. Each sub-module independently or collaboratively implements its corresponding core function, as detailed below: The SPI FlashRom soldering unit is a standard surface mount pad group customized on the PCB board. The pad spacing and pin definitions are fully matched with the SPI FlashRom to be programmed, and it supports SPI FlashRom of various package types such as SOP / TSOP / WSON. The pad group and the pins of the SPI FlashRom are electrically connected through reflow soldering. The pads are grounded with copper pouring to reduce signal interference and provide a stable physical fixation and electrical connection foundation for the SPI FlashRom, ensuring mechanical strength and signal transmission reliability after soldering.

[0031] The programming physical interface unit is an integrated design of a programmer socket and a dedicated pin header. The number of pins on the dedicated pin header corresponds to the number of SPI FlashROM IO ports, and it features a foolproof design (missing pins / irregular pins) to prevent reverse insertion and removal of the programmer module. The programmer socket is a pin header that matches the dedicated pin header and is soldered onto the PCB board. The dedicated pin header is vertically soldered onto the programmer socket, enabling the SPI FlashROM IO port signals to be led out to the outside of the PCB board. It provides a standardized physical and electrical interface for the programmer module, supports rapid insertion and removal of the programmer module, with a insertion and removal cycle of ≥1000 times, meeting the needs of mass programming in production lines.

[0032] The dual-path adapter unit configures two independent high-speed traces for each I / O port of the SPI FlashRom. Both traces originate from the pads of the SPI FlashRom soldering unit and employ an equal-length routing design, with the length error controlled within 5mil. A certain physical spacing is maintained between the two traces, and a grounding isolation layer is added if necessary to avoid signal crosstalk between the two traces. The first trace is a native communication trace, electrically connected at one end to the SPI FlashRom soldering unit and at the other end to the SPI controller I / O port array of the SOC chip, dedicated to native communication between the SOC chip and the SPI FlashRom. The second trace is a dedicated programming trace, electrically connected at one end to the SPI FlashRom soldering unit and at the other end to the programming physical docking unit, dedicated to in-circuit programming communication between the programmer module and the SPI FlashRom. The two traces have no electrical connection and are completely isolated from each other.

[0033] The electrical isolation protection unit, located on the side of the dedicated programming trace closest to the programming physical interface unit, is used to suppress the instantaneous high current during the insertion and removal of the programmer module and to quickly discharge the electrostatic charge generated during the insertion and removal process to the ground plane, forming a complete electrical isolation and protection circuit. This prevents abnormal electrical signals from being conducted to the SPI FlashRom and SOC chip, protecting the hardware from damage caused by electrostatic discharge and surges.

[0034] In this embodiment, the dual-path routing adapter unit of the physical connection module consists of two independent hardware traces without electrical connection: the native communication traces and the dedicated programming traces configured for each IO port of the SPI FlashRom. This is a core and necessary design to enable online programming of the SPI FlashRom without disassembly after soldering and to ensure the integrity of the native working function of the SOC chip system.

[0035] If a single-path routing scheme with a mid-path outlet is adopted, it will cause signal bus contention between the SOC chip and the programmer module. This will not only easily lead to programming failures, but may even cause damage to the SOC chip, programmer module, and SPI FlashRom hardware due to high current generated by level disturbances. Furthermore, the mid-path outlet will disrupt the impedance matching, parasitic parameters, and other electrical characteristics of the original communication routing, resulting in a decrease in the native communication speed and an increase in the bit error rate between the SOC chip and SPI FlashRom. At the same time, the single-path routing requires an additional mechanical / electrical isolation switch to avoid signal conflicts, which increases the complexity of PCB design and hardware costs, introduces a switch operation step, reduces the convenience of programming, and the aging and poor contact of the switch will add new failure points. More importantly, the single-path routing and switch design requires disconnecting the physical connection between the SPI FlashRom and the SOC chip before programming, which cannot achieve the true solder-free online programming defined by this system.

[0036] The dual independent routing completely eliminates the risk of signal conflict at the hardware level. The native communication routing fully retains the native wiring design of the SOC chip system, ensuring the signal integrity and operational stability of native communication. No additional isolating switches are required, simplifying the hardware design and programming process. It also enables direct online programming through dedicated programming routing while maintaining the native connection between the SPI FlashRom and the SOC chip. This precisely matches the core design goals of this system: no soldering, no disassembly, high-speed online programming without changing the native hardware architecture and working logic of the SOC chip. At the same time, the two routings follow the anti-interference design principle, maintaining sufficient physical spacing and allowing for the addition of a grounding isolation layer to avoid crosstalk between routings, further ensuring the signal transmission stability of native communication and programming communication.

[0037] The programmer module 300 is an independent external dedicated hardware device. As the execution core for high-speed direct programming of SPI FlashROM, it establishes a direct physical and electrical connection with the SPI FlashROM via a physical connection module, bypassing the SPI controller of the SOC chip to achieve high-speed programming. This module adopts a portable design with a built-in rechargeable power supply, supporting offline programming. Its hardware circuit consists of five electrically connected sub-modules: a physical interface, an SPI native protocol generation unit, a programming instruction execution and control unit, a data transmission and buffering unit, and a programming status detection and feedback unit. These sub-modules work collaboratively to automate and speed up the entire programming process, achieving a programming speed up to the native maximum communication rate of the SPI FlashROM. Each sub-module and core function of this module has a one-to-one correspondence, as detailed below: The physical interface is a standard socket that is fully compatible with the dedicated pin header of the physical connection module. It has built-in spring-loaded contact terminals and is designed to prevent incorrect insertion, ensuring precise snap-fit ​​and electrical connection with the dedicated pin header. The interface integrates reverse connection protection circuitry, which immediately cuts off internal signal and power output in case of misinsertion, preventing damage to the programmer module and PCB board hardware. This interface is the only physical and electrical connection carrier between the programmer module and the physical connection module, providing a stable channel for the transmission of programming signals and data.

[0038] The native SPI protocol generator unit has built-in standard protocol logic for SPI FlashROM programming. It can independently generate native SPI control signals and standard programming protocol instructions required for SPI FlashROM programming, including but not limited to erase instructions, programming instructions, verification instructions, read status instructions, write enable instructions, and write disable instructions. The generated SPI control signals support adjustable clock frequency to match the programming rate requirements of different SPI FlashROM models, and there is no need to convert programming instructions to the SOC chip's bus protocol or debug protocol, reducing the speed loss caused by multi-layer protocol conversion.

[0039] The programming instruction execution and control unit is used to parse the control instructions of the programming process. The control circuit has built-in standard programming process logic of SPIFlashRom. It sends control instructions to each sub-module in the order of erase → read status → program → read status → verification, so as to realize the automated execution of the entire programming process without manual intervention.

[0040] The data transmission and caching unit performs high-speed caching and segmented transmission of the data to be burned. It divides large firmware files into fixed-length data segments (such as 4KB / 8KB) and transmits them sequentially to the SPI native protocol generation unit. This avoids burning stuttering caused by untimely data transmission, improves the data transmission rate, matches the high-speed transmission characteristics of the SPI native protocol, and ensures burning speed.

[0041] The programming status detection and feedback unit acquires the status signal fed back from the MISO pin of the SPI FlashROM in real time through the physical interface, and analyzes the status signal to determine the real-time working status of the SPI FlashROM, including but not limited to chip busy status, programming success status, programming failure status, verification failure status, and hardware connection abnormal status. In this embodiment, a dual audio-visual feedback design is implemented through a feedback component, including red, green, and blue LED indicators and a buzzer. A solid blue light indicates programming in progress, a solid green light plus a short buzzer sound indicates programming success, a solid red light plus three long buzzer sounds indicates programming failure, and a flashing red light indicates a hardware connection abnormality. This allows operators to quickly identify the programming status and handle abnormal situations promptly.

[0042] In one embodiment of the present invention, a reset signal linkage control module is further included, which is configured to switch between the programming mode and the normal operating mode of the system, including: A reset signal generation unit is configured to manually or automatically generate a reset signal that conforms to the SOC chip standard. The system power-on synchronization unit is configured to synchronize the system power-on operation with the occurrence of the reset signal. A reset state holding unit is configured to continuously latch and output the reset signal after the reset signal takes effect; The reset signal release unit is configured to receive a trigger signal and release the latch on the reset signal after the programming process is completed.

[0043] In this embodiment, all functional modules of the system are electrically connected, and the specific workflow is as follows: The system reset signal is sent from the reset signal linkage control module to the SPI controller IO control module. When a system reset signal is detected, the SPI controller IO control module switches all SPI controller IO ports to a pure input, undriven state, stopping the output of level and control signals to the SPI FlashRom IO ports; Connect the programmer module to the programming physical docking unit in the physical connection module; The programmer module directly outputs control signals and programming data to the SPI FlashROM; After the programming is completed, the reset signal linkage control module controls the SPI controller IO control module to switch back to normal working mode.

[0044] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. An in-circuit programming system for SPI FlashROM of a SOC chip system, characterized in that, include: The SPI controller IO control module is configured to switch all SPI controller IO ports to a pure input, undriven state and stop outputting level and control signals to the SPI FlashRom IO ports when a system reset signal is detected. The physical connection module is configured to establish physical and electrical connection channels between the programmer module and the SPI FlashRom to enable in-line programming of the SPI FlashRom after it is soldered to the PCB board. as well as The programmer module is configured to establish a direct physical and electrical connection with the SPI FlashRom's I / O port. When the SOC chip is in a reset state and the SPI FlashRom I / O port is not driven, it directly outputs control signals and programming data to the SPI FlashRom.

2. The system according to claim 1, characterized in that, It also includes a reset signal linkage control module, which is configured to switch between the burning mode and the normal system operation mode.

3. The system according to claim 1, characterized in that, The SPI controller I / O control module includes: The SPI controller I / O port array is configured to provide a physical channel for SPI communication between the SOC chip's SPI controller and the SPI FlashROM; The reset signal detection and triggering unit is configured to immediately generate and output an IO state switching trigger signal when a reset signal is detected, and transmit it to the IO port state switching logic circuit. The IO port state switching logic circuit is configured to receive the IO state switching trigger signal output by the reset signal detection and trigger unit, execute the working state switching operation of the SPI controller IO port, and realize the switching of the IO port between the normal driving state and the pure input no-drive state.

4. The system according to claim 3, characterized in that, The SPI controller I / O control module also includes: The state latch unit is configured to continuously latch the state after the IO port switches to a pure input undriven state.

5. The system according to claim 1, characterized in that, The physical connection module includes: The SPI FlashRom soldering unit includes soldering pads and connection traces corresponding to the SPI FlashRom, providing a fixed soldering position for the SPI FlashRom on the PCB board; The programming physical interface unit consists of a programmer socket and a dedicated pin header, which connects to all I / O ports of the SPI FlashRom. Dual-path adapter unit: Each IO port of the SPI FlashROM is configured with an independent dual-path. One path is electrically connected to the SPI controller IO port of the SOC chip, and the other path is electrically connected to the programming physical interface unit.

6. The system according to claim 5, characterized in that, The physical connection module also includes an electrical isolation protection unit, which is configured to suppress abnormal electrical signals generated during the insertion and removal of the programmer, and prevent abnormal signals from being transmitted to the SPIFlashRom and SOC chip.

7. The system according to claim 1, characterized in that, The programmer module includes: The physical interface connects to a dedicated pin header in the physical connection module. The SPI native protocol generator is configured to generate native SPI control signals and standard programming protocol instructions required for SPI FlashROM programming. The programming instruction execution and control unit is configured to execute programming-related operations sequentially according to the programming instructions.

8. The system according to claim 7, characterized in that, The programmer module also includes: The data transmission and caching unit is configured to cache and segment the data to be burned. The programming status detection and feedback unit is configured to acquire the status feedback signal of the SPI FlashRom in real time through the physical interface, determine its programming status, and convert the programming status into an indication signal to feed back to the operator.

9. The system according to claim 2, characterized in that, The reset signal linkage control module includes: A reset signal generation unit is configured to manually or automatically generate a reset signal that conforms to the SOC chip standard. The system power-on synchronization unit is configured to synchronize the system power-on operation with the occurrence of the reset signal. A reset state holding unit is configured to continuously latch and output the reset signal after the reset signal takes effect; The reset signal release unit is configured to receive a trigger signal and release the latch on the reset signal after the programming process is completed.

10. A method for operating the system according to any one of claims 1-9, characterized in that, include: The system reset signal is sent from the reset signal linkage control module to the SPI controller IO control module. When a system reset signal is detected, the SPI controller IO control module switches all SPI controller IO ports to a pure input, undriven state, stopping the output of level and control signals to the SPI FlashRom IO ports; Connect the programmer module to the programming physical docking unit in the physical connection module; The programmer module directly outputs control signals and programming data to the SPI FlashROM; After the programming is completed, the reset signal linkage control module controls the SPI controller IO control module to switch back to normal working mode.

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