High compatibility communication data processing method and system

Abstract

This invention discloses a highly compatible communication data processing method and system. The method establishes a mapping relationship between register byte addresses and double-byte buffers by unifying register addressing in double-byte units. It then calculates the index, modulus, and shift amount based on bitwise operations to achieve unified cross-boundary access operations for data that may cross buffer boundaries. This solves the problems of data processing incompatibility and code portability difficulties on microcontrollers (MCUs) with different unit address sizes when register lengths are mixed between single and double bytes in custom communication protocols. This invention achieves seamless compatibility between single-byte and double-byte MCUs, significantly improves code portability, and supports flexible access and processing of arbitrary starting addresses, lengths, and mixed-byte data. It is suitable for scenarios requiring highly compatible data packaging, such as CAN communication.

Description

Technical Field

[0001] This invention relates to communication data processing technology, and in particular to a highly compatible communication data processing method and system. Background Technology

[0002] In embedded system development, byte alignment is a core underlying mechanism that affects system performance, stability, and memory utilization. Different microcontrollers (MCUs) have different address sizes. For example, an 8-bit MCU has a one-byte address size, meaning it accesses one address at a time to read or write one byte of data; a 16-bit MCU accesses two addresses at a time to read or write two bytes of data. Therefore, when dealing with MCUs of different address lengths and address sizes, the differences in their hardware architecture, data bus width, and instruction sets transform the byte alignment problem from a simple programming convention into a series of complex and subtle development challenges.

[0003] In the field of communications development, the primary function is data exchange, which involves a large amount of data copying, parsing, and sending. Registers are used to store data and instructions for rapid processing. Registers act as temporary storage areas where data information can be quickly accessed and manipulated. The number and size of registers in a CPU are determined by the processor design. Different registers are distinguished by their addresses, and different registers have different addresses.

[0004] When defining communication protocol content, the storage area is divided into registers of different lengths to store different data contents within the protocol, enabling the computer to parse the data protocol and perform storage and retrieval operations. When defining a custom protocol, each register has a corresponding address, and the register members in consecutive segments should adhere to byte alignment principles, while also taking into account the differences in address sizes among different MCU units. For example, the industry standard for the Modbus protocol based on serial communication strictly defines a single register as 2 bytes in length. This satisfies byte alignment requirements and also provides good compatibility with mainstream embedded MCUs with different address sizes, including single-byte and double-byte registers.

[0005] However, since single-byte address MCUs are the mainstream in embedded development, especially in communication development, some engineers, limited by their understanding of platform development, fail to consider the overall picture when defining the length of a single register. Their considerations may only be the numerical range of the value assigned to the register; for example, small values ​​like temperature are defined as single bytes, while large values ​​like power generation are defined as double bytes. This results in a continuous register area containing protocol register members with inconsistent parity (single-byte and double-byte). While this makes the data more compact and saves space to some extent, it also causes significant problems for communication data processing in MCUs with double-byte address sizes (such as TI's C2000 series). Furthermore, once a protocol is mass-produced and used, considering product continuity, it is difficult to redefine the protocol; subsequent products on other MCU platforms must continue to use and follow this protocol.

[0006] It should be noted that the information disclosed in the background section above is only for understanding the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The main objective of this invention is to overcome the deficiencies in the aforementioned background technology and provide a highly compatible communication data processing method and system.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] In a first aspect of the present invention, a highly compatible communication data processing method is applied to microcontrollers (MCUs) with different unit address sizes, comprising:

[0010] A register addressing mode based on two-byte units is adopted, a two-byte pointer is declared as a two-byte buffer, and a mapping relationship between register byte address and buffer index is established based on the register addressing mode and the two-byte buffer.

[0011] Based on the mapping relationship, the register byte address of the data to be processed is mapped to the buffer index;

[0012] Based on the starting address of the register byte of the data to be processed, initialize the byte offset; calculate the buffer index by performing a right shift operation on the byte offset; calculate the byte position modulus by performing a bitwise AND operation on the byte offset to distinguish the high octets and low octets in the buffer; and obtain the data shift amount based on the byte position modulus by performing a left shift operation.

[0013] Based on the buffer index, byte position modulus, and data shift amount, cross-boundary data processing is performed: when a single register data crosses two double-byte buffer boundaries or is located within the same double-byte buffer, the current double-byte temporary data to be processed is moved by the shift operation according to the data shift amount, the corresponding position of the target buffer unit is cleared by AND operation, and the moved data is stored in the double-byte buffer to complete the data processing in a unified manner;

[0014] After processing is complete, update the byte offset and register byte start address to support continuous or arbitrary start and end of data block operations.

[0015] In a second aspect of the present invention, a slave response process data processing method includes:

[0016] Receive a read instruction sent by the host, the read instruction including the register start address and the length of the data to be read in bytes;

[0017] Using the register start address as the byte start address and the byte length of the data to be read as the data processing length boundary, the data is read from the register address space and stored in the double-byte buffer using the communication data processing method described above.

[0018] The data in the double-byte buffer is packaged into response data frames in sequence and sent to the host.

[0019] In a third aspect of the present invention, a slave receiving process data processing method includes:

[0020] Receive a write instruction sent by the host, the write instruction including the register start address, the byte length of the data to be written, and the content of the data to be written;

[0021] Using the register start address as the byte start address and the byte length of the data to be written as the length boundary of the data processing, the data to be written is processed and stored in the double-byte buffer using the communication data processing method.

[0022] Write the data in the double-byte buffer to the corresponding location in the register address space;

[0023] Return a success flag for the write operation to the host.

[0024] In a fourth aspect of the invention, a highly compatible communication data processing system is applied to a microcontroller (MCU) with different unit address sizes, including a processor and a memory.

[0025] The memory stores executable program instructions;

[0026] The processor is configured to execute the program instructions to implement the data processing method.

[0027] The present invention has the following beneficial effects:

[0028] This invention provides a highly compatible communication data processing method and system. Addressing the problems of complex data processing and poor platform compatibility caused by the mixed single and double byte lengths of protocol registers and the different address sizes (such as single byte or double byte) of different microcontrollers (MCUs), this invention proposes an innovative data processing method. Through a unified double-byte buffer design and corresponding address mapping and bit operation mechanism, it achieves seamless cross-platform compatibility and significantly improves code portability.

[0029] The technical solution of this invention effectively solves key difficulties in embedded communication development. Firstly, it can be directly applied to scenarios such as CAN communication, reliably packaging device register data into the communication frame buffer. Its core advantage lies in its excellent cross-platform compatibility. By employing a unified data processing path on MCUs with single-byte and double-byte address lengths, it avoids the hassle of writing different parsing code for different hardware, greatly simplifying development and maintenance. Simultaneously, this solution automatically maintains the correct byte order in little-endian systems. Furthermore, this method supports flexible access to data blocks, adapting to operations with arbitrary starting addresses and lengths, and can simultaneously process single-byte, double-byte, and multi-byte mixed register data, thereby meeting the needs of complex custom communication protocols and enhancing the system's adaptability and practicality.

[0030] Other beneficial effects of the embodiments of the present invention will be further described below. Attached Figure Description

[0031] Figure 1 This is a comparison diagram of the register storage architecture of MCUs with different unit address sizes in embodiments of the present invention.

[0032] Figure 2 This is a schematic diagram of the register reading process and the response "read instruction" array structure of a single-byte MCU in an embodiment of the present invention.

[0033] Figure 3 This is a schematic diagram of the response "read instruction" array structure of a two-byte MCU in an embodiment of the present invention, and the data that needs to be split and spliced ​​in the read register.

[0034] Figure 4 This is a diagram showing the mapping relationship between register byte addresses and double-byte buffers under the unified memory address addressing mode in this embodiment of the invention.

[0035] Figure 5This is a diagram illustrating the cross-boundary storage and displacement process of Buf buffer data when Mod=1 in an embodiment of the present invention.

[0036] Figure 6 This is a schematic diagram of buffer storage processing for different data reading lengths in an embodiment of the present invention.

[0037] Figure 7 This is a schematic diagram illustrating the specific process of shifting 2 bytes of data to be read, DataTemp, into the Buf[Index] and Buf[IndexNext] buffers through bitwise operations in an embodiment of the present invention.

[0038] Figure 8 This is a schematic diagram of the specific data processing flow for reading 2 bytes of data from offset address 3 in an embodiment of the present invention.

[0039] Figure 9 This is a schematic diagram illustrating the specific process of assigning 2 bytes of data to be read in the Buf buffer after obtaining Index, IndexNext, and Shift in an embodiment of the present invention.

[0040] Figure 10 This is a flowchart illustrating the overall process of the highly compatible communication data processing method of the present invention. Detailed Implementation

[0041] The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary and is not intended to limit the scope and application of the present invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] This invention aims to solve the problems of data processing incompatibility and portability caused by mixed single and double byte protocol register lengths and different address sizes of different MCU units in embedded communication. It proposes a data processing scheme based on double-byte unified addressing and bit operation mapping. By establishing an index mapping from register byte address to double-byte buffer and a cross-boundary processing mechanism, it achieves seamless compatibility and code portability on single-byte and double-byte MCUs, and supports flexible and correct access and packaging of mixed register data with arbitrary starting address and length.

[0044] See Figure 10This invention provides a highly compatible communication data processing method, comprising: employing a register address addressing mode based on two bytes, declaring a two-byte pointer as a two-byte buffer, and establishing a mapping relationship between register byte addresses and buffer indices based on the register address addressing mode and the two-byte buffer; based on the mapping relationship, Map the register byte address of the data to be processed to the buffer index; initialize the byte offset based on the register byte start address of the data to be processed; calculate the buffer index by performing a right shift operation on the byte offset, calculate the byte position modulus by performing a bitwise AND operation on the byte offset to distinguish the high octets and low octets in the buffer, and obtain the data shift amount based on the byte position modulus by performing a left shift operation; perform cross-boundary data processing based on the buffer index, byte position modulus, and data shift amount: when a single register data crosses two double-byte buffer boundaries or is located within the same double-byte buffer, the currently processed double-byte temporary data taken from the data to be processed is moved according to the data shift amount by a shift operation, the corresponding position of the target buffer unit is cleared by an AND operation, and the moved data is stored in the double-byte buffer to complete the data processing in a unified manner; after processing is completed, update the byte offset and register byte start address to support continuous or arbitrarily starting and ending data block operations.

[0045] In some embodiments, the process of performing right shift, bitwise AND, and left shift operations on the byte offset includes: initializing the byte offset to 0 to point to the starting position of the data to be processed; cyclically processing the data to be processed, and obtaining the current buffer index by shifting the current byte offset one bit to the right each time; performing a bitwise AND operation between the current byte offset and the value 1 to obtain the current byte position modulus; and shifting the current byte position modulus three bits to the left to obtain the current data shift amount.

[0046] In some embodiments, performing cross-boundary data processing includes: determining the current buffer index and the next buffer index based on the current buffer index and the byte position modulus; performing a corresponding shift operation on the two-byte temporary data to be processed according to the current data shift amount; generating a corresponding bitmask based on the current data shift amount; clearing the positions of the data to be stored in the two-byte buffers pointed to by the current buffer index and the next buffer index using bitwise AND operations; and storing the shifted two-byte temporary data into the corresponding position of the two-byte buffer that has been cleared.

[0047] In some embodiments, when the byte position modulus is 0, the data is stored in the lower eight bits of the double-byte buffer pointed to by the current buffer index, and the next buffer index is equal to the current buffer index; when the byte position modulus is 1, the data is stored in the higher eight bits of the double-byte buffer pointed to by the current buffer index, and the next buffer index is equal to the current buffer index plus 1.

[0048] In some embodiments, storing the shifted two-byte temporary data into the corresponding position of the two-byte buffer that has been cleared includes performing a bitwise OR operation between the shifted two-byte temporary data and the cleared buffer content.

[0049] In some embodiments, updating the byte offset and address information includes: after the current data processing is completed, increasing the byte offset by the length of the processed data, increasing the register start address by the same length, and determining whether the updated address exceeds the total length boundary of the data to be processed.

[0050] In some embodiments, if the starting address of the updated register byte does not exceed the total length boundary of the data to be processed, the next byte of data is processed in a loop; if the updated address exceeds the total length boundary, the current data operation is terminated.

[0051] This invention also provides a slave response process data processing method, including:

[0052] Receive a read instruction sent by the host, the read instruction including the register start address and the length of the data to be read in bytes;

[0053] Using the register start address as the byte start address and the byte length of the data to be read as the data processing length boundary, the data is read from the register address space and stored in the double-byte buffer using the communication data processing method described above.

[0054] The data in the double-byte buffer is packaged into response data frames in sequence and sent to the host.

[0055] This invention also provides a method for processing data during slave receiving, including:

[0056] Receive a write instruction sent by the host, the write instruction including the register start address, the byte length of the data to be written, and the content of the data to be written;

[0057] Using the register start address as the byte start address and the byte length of the data to be written as the length boundary of the data processing, the data to be written is processed and stored in the double-byte buffer using the communication data processing method.

[0058] Write the data in the double-byte buffer to the corresponding location in the register address space;

[0059] Return a success flag for the write operation to the host.

[0060] The communication data processing method proposed in this invention fundamentally solves the problems of data processing incompatibility and programming complexity caused by the mixed single and double byte register lengths in custom communication protocols and the differences in address sizes of different MCU units. This is achieved by unifying memory addressing in double-byte units and establishing an index mapping relationship between register byte addresses and double-byte buffers, combined with a cross-boundary data processing mechanism based on bit operations. This solution achieves seamless compatibility and highly portable code design between single-byte and double-byte MCU platforms, ensures the correct byte order including little-endian systems, and flexibly supports reliable access and efficient packaging of register data with arbitrary starting addresses, arbitrary lengths, and mixed single and double byte data. This significantly improves the stability, adaptability, and development efficiency of embedded communication systems when dealing with heterogeneous hardware and complex protocols.

[0061] The features, working principle and advantages of specific embodiments of the present invention are further described below.

[0062] The communication process in this invention is summarized as follows:

[0063] The communication process involved in this invention adopts a master-slave response method and uses data blocks as the basic format of the protocol content. Users can flexibly read or write registers in single or consecutive segments within the data block, where the size and address of the registers are defined by the user-defined protocol content. For simplicity, the underlying physical transmission medium (such as CAN or serial communication) is ignored; the core flow of the read and write process is summarized as follows:

[0064] Reading process: The master sends a read command, which includes the starting address of the register to be read and the length of the data to be read in bytes; the slave responds with a read command, and the response information includes the starting address of the register, the length of the data bytes, the corresponding register content, and the checksum.

[0065] Write process: The master sends a write command, which includes the starting address of the register to be written, the byte length of the data to be written, the content of the data to be written, and verification; the slave responds to the write command and provides a flag indicating whether the write was successful or not.

[0066] Different MCU platform architectures exhibit protocol differences when handling mixed single-byte and double-byte data. When the register length defined by the protocol is mixed between single and double bytes, its storage method differs on MCUs with different unit address sizes. For example... Figure 1As shown, in an MCU with a single-byte address length, each register occupies one or two integer multiples of the address space. However, in an MCU with a double-byte address length, a single-byte register occupies only half of a single address space, while a double-byte register may occupy one address space or span two address spaces.

[0067] The following example, using reading register n+2, illustrates the differences in parsing between the two MCU platform protocols:

[0068] The unit address space is a single-byte MCU: such as Figure 2 As shown, when a single-byte MCU reads the contents of a register, it directly points to the starting address of the corresponding register using a single-byte pointer, uses the starting address as the buffer index, and puts the data into the single-byte buffer buf array according to the length of the data bytes.

[0069] The unit address space is a two-byte MCU: such as Figure 3 As shown, when a double-byte MCU reads the contents of a register, it cannot directly access the starting address index of register n+2 when accessing the register address. When storing the data in the buffer, it is necessary to split and concatenate the data before the correct information can be obtained.

[0070] Depend on Figure 2 and Figure 3 It can be seen that in MCUs with a single-byte address length, since each register occupies one or two integer multiples of the address space, when the response protocol fills the register contents, all register contents can be easily copied to the buffer to be sent at once using address pointers. However, in MCUs with a double-byte address length, the data accessed by the address pointer may be a complete register content or only half a register content. For example, when... Figure 2 When reading the content at register position n+2, and filling the register with the response, it is necessary to retrieve the high octets and low octets of the two address spaces separately. Due to this difference, although the communication protocol content definition is the same, different data parsing and processing methods are required for MCUs with different unit address lengths to avoid parsing errors, resulting in higher implementation complexity.

[0071] To address the aforementioned issues and for protocols with mixed single-byte and double-byte misalignment, this invention proposes a data processing implementation method compatible with MCUs having single-byte or double-byte unit address spaces. The parameters used are shown in Table 1 below.

[0072] Table 1:

[0073]

[0074] 1. Unified memory address addressing mode:

[0075] To unify memory addressing to a two-byte unit, a two-byte pointer `Buf` is declared and defined as a data buffer. Register addresses are addressed byte-wise, and the two-byte buffer maps to address bytes. The specific relationship is as follows: Figure 4 As shown. This design choice is based on the fact that the double-byte unit can simultaneously cover the processing needs of both single-byte and double-byte MCUs.

[0076] Figure 4 The practical significance is that, assuming there is an 8-byte data segment with a starting address of 0, then after bytes 0 to 7 are mapped to the buffer, the specific location information that should be placed into the Buf buffer array is determined.

[0077] 2. Byte offset calculation mechanism:

[0078] Establish a mapping relationship between register byte addresses and buffer double-byte indices.

[0079] As we know from the first step, the data should be placed into the corresponding positions sequentially according to the address mapping method described above. One byte of data corresponds to 8 bits, which is 8 binary numbers, and the defined double-byte pointer Buf should be a 16-bit buffer. For example, the first data byte (byte 0) should be stored in the lower eight bits of the buffer Buf[0].

[0080] In terms of actual data, assuming the first byte (byte 0) actually represents temperature information with a value of 7, then 7 converted to binary is 0000 0111. Therefore, after storing byte 0 in Buf[0], it should be:

[0081] ;

[0082] The second byte (byte 1) contains voltage information, with a value of 6. Converted to binary, this should be 0000 0110. Therefore, it should be stored in the high eight bits of Buf[0]. After storage, Buf[0] should be:

[0083] ;

[0084] Subsequent data is then stored sequentially according to this rule.

[0085] The specific process for reading data once is as follows:

[0086] Determine the starting address RegAddr of the register data to be read and the length of the data to be read Len;

[0087] Initialize byte offset RegOffSet = 0;

[0088] The loop iterates through data and exits the loop once the read length exceeds the data length.

[0089] The buffer index Index is calculated by right-shifting the byte offset RegOffSet by 1 bit.

[0090] Index = RegOffSet >> 1;

[0091] Index is the index value of the buffer Buf, i.e., Buf[Index]. If Index is 0, it means that the current operation is on the data buffer Buf[0]. As can be seen from the above, Buf is a two-byte array, so Buf[0] consists of two bytes of data.

[0092] For Buf[0], when RegOffSet = 0 and RegOffSet = 1, the corresponding index should be 0. Therefore, RegOffSet needs to be right-shifted, and the cases of RegOffSet = 0 and RegOffSet = 1 should both be classified as Index = 0. In binary arithmetic, right shifting by one bit is equivalent to dividing by 2 (discarding the decimal part). For example, when RegOffSet = 1, the binary number is 0000 0001, and after right shifting by one bit, it becomes 0000 0000, which is 0.

[0093] By performing a bitwise AND operation between RegOffSet and 1, we obtain the byte position modulus Mod:

[0094] Mod = RegOffSet & 0x0001;

[0095] A Buf buffer contains two bytes of data, namely the high eight bits and the low eight bits mentioned above. Knowing only the Buf index value Index is equivalent to knowing that the operation is on Buf[0], but not knowing which byte is being operated on. Therefore, it is necessary to confirm the specific byte position in the buffer through AND operation.

[0096] The mathematical meaning of performing a bitwise AND operation between the byte offset RegOffSet and 1 is equivalent to taking the remainder of RegOffSet divided by 2. That is, when RegOffSet is even, Mod equals 0, and when RegOffSet is odd, Mod equals 1. It's important to note that the AND operation performs a bitwise operation on each bit of the two numbers; if not all bits are 1, then that bit equals 0.

[0097] The shift amount Shift is calculated by shifting the byte position modulus Mod three bits to the left.

[0098] Shift = Mod << 3.

[0099] The Shift value corresponds one-to-one with the Mod value. The mathematical meaning of shifting left by 3 bits is multiplying by 8. When Mod = 0, the shift amount Shift is also equal to 0. When Mod = 1, Shift is equal to 8.

[0100] The practical meaning of this value is that when Mod = 1, it represents the high eight bits of the data in the Buf buffer. The next byte of data should cross the current Buf buffer boundary and be stored in the next Buf index value. At this time, the data needs to be moved to the corresponding position according to the displacement, and the specific process is as follows: Figure 5 As shown.

[0101] The next index value, IndexNext, is obtained by adding the current index value (Index) and the byte position modulus (Mod).

[0102] IndexNext = Index + Mod.

[0103] All parameter contents are as follows: Figure 6 As shown.

[0104] Now that we know the current index value and the next index value, we need to discuss the specific data reading process in different cases. For example, when the data length is 1 byte, how should the data be processed and stored in the buffer? When the data is read across two buffers, how should it be stored?

[0105] 3. Cross-border data processing mechanism:

[0106] A single register data may span two double-byte boundaries, occupy a single double byte, or occupy only one byte; a unified index expansion mechanism is used for handling this. First, let's explain the specific read process:

[0107] Get the current index value Index and the next index value IndexNext of Buf, and assign values ​​to Buf[Index] and Buf[IndexNext]. The register data to be read is temporarily stored in a two-byte variable DataTemp.

[0108] Clear the original data in Buf[Indext] and Buf[IndexNext]. This step is necessary because the temporarily read data DataTemp is two bytes long, and to prevent incorrect readings from the Buf buffer, the buffer contents must be cleared before assigning data. During clearing, a binary bitwise AND operation is used to clear the data (high or low 8 bits) at the corresponding position in Buf, achieved by left-shifting or right-shifting 00FF or FF00, with the specific displacement being Shift.

[0109] Next, using binary bitwise operations, the data to be read, DataTemp, is shifted to the corresponding position in Buf. The specific process is as follows: Figure 7 As shown.

[0110] Depend on Figure 7 As we can see, since the size of the data to be read, DataTemp, is 2 bytes, there are two possibilities: either the data is read and stored exactly in a double-byte buffer, or the data crosses a buffer, with the first byte of data in the high eight bits of Buf[Index] and the second byte of data in the low eight bits of Buf[IndexNext].

[0111] In the first case, Index = IndexNext. The data is stored in the lower eight bits and the higher eight bits of the same Buf. The hexadecimal number 0x00FF is converted to binary as 0000 0000 1111 1111. Shifting 0x00FF left by the Shift bit and inverting it, and then performing a bitwise AND operation with the data in Buf, will clear the data at that position, ensuring that the position in Buf[Index] is empty before storing the data.

[0112] After clearing this bit in Buf[Index], shift the data to be read, DataTemp, left by Shift bits, and then perform a bitwise OR operation with the data in Buf[Index] to store the first data. For Buf[IndexNext], the above left shift operation needs to be changed to a right shift.

[0113] The second case is the same as the first case in terms of calculation process, but the displacement becomes 8. It should be noted that in the second case, Index and IndexNext are not equal, and the data is stored in the high eight bits of Index and the low eight bits of IndexNext.

[0114] 4. Address and displacement update:

[0115] After storing the data, it is also necessary to update the length of the read data and confirm the byte offset and address information.

[0116] If the register length to be read this time is 2, then the byte offset needs to be increased by 2, and the address also needs to be increased by 2, in order to determine whether the current time exceeds the end address (the total length of data to be read).

[0117] Finally, a practical example is used to demonstrate the process of reading 2 bytes of data (DataTemp = 0x1234) from offset address 3. The specific data processing flow is as follows: Figure 8 As shown.

[0118] After obtaining the Index, IndexNext, and shift value, you can begin assigning values ​​to the Buf buffer. The specific operation process is as follows: Figure 9 As shown.

[0119] In summary, this invention proposes a highly compatible communication data processing method and system. The important innovative contributions and outstanding features of this invention include: proposing and implementing a memory access framework with double bytes as the unified addressing unit, and establishing a dynamic mapping and bitwise operation mechanism from register byte address to double-byte buffer, thereby effectively solving the core problem of incompatibility in handling mixed single and double-byte register lengths on MCUs with different unit address sizes in custom communication protocols.

[0120] Compared with the prior art, the significant technical advantages of this invention are: it achieves seamless cross-platform compatibility and high code portability between single-byte and double-byte MCUs; it can automatically maintain the correct byte order in little-endian systems through a unified data processing path; and it provides flexible and reliable access and packaging capabilities for arbitrary starting addresses, arbitrary lengths, and mixed single- and double-byte register data, significantly enhancing the adaptability and processing efficiency of embedded communication systems to complex protocols and heterogeneous hardware.

[0121] The technical solution of this invention can be mainly used for:

[0122] CAN communication data packaging: Packs device register data into the CAN frame buffer;

[0123] Cross-platform compatibility: Through a unified double-byte buffer design, seamless compatibility is achieved on MCUs with single-byte and double-byte address lengths, greatly improving code portability while maintaining the correct byte order in little-endian systems;

[0124] Flexible data access: Supports data block operations with arbitrary starting address and byte length, and can flexibly adapt to register data of different lengths, enabling mixed processing of single-byte, double-byte and multi-byte data.

[0125] This invention also provides a storage medium for storing a computer program, which, when executed, performs at least the methods described above.

[0126] This invention also provides a control device, including a processor and a storage medium for storing a computer program; wherein the processor executes the computer program by performing at least the method described above.

[0127] This invention also provides a processor that executes a computer program, at least performing the methods described above.

[0128] The storage medium can be implemented by any type of non-volatile storage device, or a combination thereof. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc or CD-ROM; magnetic surface memory can be disk storage or magnetic tape storage. The storage media described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable types of memory.

[0129] In the several embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0130] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0131] In addition, in the various embodiments of the present invention, each functional unit can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0132] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0134] The methods disclosed in the several method embodiments provided by this invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0135] The features disclosed in the several product embodiments provided by this invention can be arbitrarily combined without conflict to obtain new product embodiments.

[0136] The features disclosed in the several method or device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0137] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various equivalent substitutions or obvious modifications can be made without departing from the concept of the present invention, and all such modifications, achieving the same performance or application, should be considered within the scope of protection of the present invention.

Claims

1. A high compatibility communication data processing method applied to microcontrollers with different cell address sizes, characterized in that, include: A register addressing mode based on two-byte units is adopted, a two-byte pointer is declared as a two-byte buffer, and a mapping relationship between register byte address and buffer index is established based on the register addressing mode and the two-byte buffer. Based on the mapping relationship, the register byte address of the data to be processed is mapped to the buffer index; Based on the starting address of the register byte of the data to be processed, initialize the byte offset; calculate the buffer index by performing a right shift operation on the byte offset; calculate the byte position modulus by performing a bitwise AND operation on the byte offset to distinguish the high octets and low octets in the buffer; and obtain the data shift amount based on the byte position modulus by performing a left shift operation. Based on the buffer index, byte position modulus, and data shift amount, cross-boundary data processing is performed: when a single register data crosses the boundaries of two double-byte buffers or is located within the same double-byte buffer, the current double-byte temporary data to be processed is taken from the data to be processed and moved according to the data shift amount through a shift operation. Then, the corresponding position of the target buffer unit is cleared through an AND operation, and the moved data is stored in the double-byte buffer to complete the data processing in a unified manner. After processing is complete, update the byte offset and register byte start address to support continuous or arbitrary start and end of data block operations; The process of performing right shift, bitwise AND, and left shift operations on the byte offset includes: Initialize the byte offset to 0 to point to the beginning of the data to be processed; The data to be processed is processed in a loop. Each time the data is processed, the current buffer index is obtained by shifting the current byte offset one bit to the right. Perform a bitwise AND operation between the current byte offset and the value 1 to obtain the modulus of the current byte position; Shift the current byte position left by three bits modulo to obtain the current data shift amount; The cross-boundary data processing includes: The current buffer index and the next buffer index are determined based on the current buffer index and the byte position modulus; The two-byte temporary data to be processed is shifted according to the current data shift amount. Generate a corresponding bitmask based on the current data shift amount, and use bitwise AND operation to clear the positions of the data to be stored in the double-byte buffers pointed to by the current buffer index and the next buffer index; The shifted two-byte temporary data is stored in the corresponding position of the two-byte buffer that has been cleared.

2. The method as described in claim 1, characterized in that: When the modulus of the byte position is 0, the data is stored in the lower eight bits of the double-byte buffer pointed to by the current buffer index, and the next buffer index is equal to the current buffer index. When the modulus of the byte position is 1, the data is stored in the high eight bits of the double-byte buffer pointed to by the current buffer index, and the next buffer index is equal to the current buffer index plus 1.

3. The method as described in claim 1, characterized in that, The step of storing the shifted two-byte temporary data into the corresponding position of the two-byte buffer that has been cleared includes: Perform a bitwise OR operation between the shifted two-byte temporary data and the cleared buffer contents.

4. The method as described in claim 1, characterized in that, The updated byte offset and register byte start address include: After the current data processing is completed, the byte offset is increased by the length of the processed data, the register byte starting address is increased by the same byte length, and it is determined whether the updated address exceeds the total length boundary of the data to be processed.

5. The method as described in claim 4, characterized in that, If the starting address of the updated register byte does not exceed the total length boundary of the data to be processed, the process continues to loop through the next byte of data; if the updated address exceeds the total length boundary, the current data operation ends.

6. A method for processing slave response data, characterized in that, include: Receive a read instruction sent by the host, the read instruction including the register start address and the length of the data to be read in bytes; Using the register start address as the byte start address and the byte length of the data to be read as the data processing length boundary, data is read from the register address space and stored in the double-byte buffer using the data processing method of any one of claims 1 to 5. The data in the double-byte buffer is packaged into response data frames in sequence and sent to the host.

7. A method for processing data during slave receiving process, characterized in that, include: Receive a write instruction sent by the host, the write instruction including the register start address, the byte length of the data to be written, and the content of the data to be written; Using the register start address as the byte start address and the byte length of the data to be written as the length boundary of the data processing, the data to be written is processed and stored in the double-byte buffer using the data processing method of any one of claims 1 to 5. Write the data in the double-byte buffer to the corresponding location in the register address space; Return a success flag for the write operation to the host.

8. A highly compatible communication data processing system, applied to microcontrollers (MCUs) with different unit address sizes, characterized in that, Including processor and memory; The memory stores executable program instructions; The processor is configured to execute the program instructions to implement the data processing method as described in any one of claims 1 to 7.

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