Control method and device based on inter-core communication, electronic equipment and chip

Abstract

The invention provides a control method and device based on inter-core communication, electronic equipment and a chip, and relates to the technical field of computers.The method comprises the steps that power-off is triggered in response to a first subsystem of the chip, and a second subsystem of the chip is prevented from sending data to the first subsystem; checking the first subsystem before power-off based on the first state information of the inter-core communication module of the first subsystem and the second state information of the inter-core communication module of the second subsystem; and determining whether the first subsystem is powered off or not according to the check result before power-off. According to the technical scheme provided by the invention, before the first subsystem is powered off, the data transmission of the opposite-end second subsystem is stopped, and the states of the first subsystem and the second subsystem are checked, so that the problems of unprocessed data loss caused by direct power-off of the first subsystem and chip bus hanging caused by bus access to an invalid address can be avoided, and the reliability of the system is improved. The power-on and power-off safety in a distributed inter-core communication scene is ensured, and the chip operation stability can be remarkably improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a control method, apparatus, electronic device and chip based on inter-core communication. Background Technology

[0002] A chip contains multiple subsystems, such as a protocol stack subsystem and a physical layer subsystem. The protocol stack subsystem is responsible for the logical processing of data, such as encapsulating communication protocols, managing data transmission and reception logic, and handling communication requests from upper-layer applications. The physical layer subsystem is responsible for the physical transmission of data, such as converting the digital signals processed by the protocol stack into radio frequency signals, and demodulating the received radio frequency signals back into digital signals. Summary of the Invention

[0003] This disclosure provides a control method, device, electronic device, and chip based on inter-core communication. The main purpose is to solve the problem of unprocessed data loss and chip bus hang-up caused by directly powering down a multi-subsystem with a distributed inter-core communication architecture in a chip when one subsystem is about to power down while the other subsystem is still powered on and has data transmission needs.

[0004] According to a first aspect of the present disclosure, a control method based on inter-core communication is provided, comprising: In response to a power-down trigger of the first subsystem of the chip, the second subsystem of the chip is prevented from sending data to the first subsystem. Obtain the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem; Perform a power-off check on the first subsystem based on the first status information and the second status information; Determine whether the first subsystem should be powered down based on the results of the pre-power-down inspection.

[0005] Optionally, preventing the second subsystem of the chip from sending data to the first subsystem includes: The blocking register in the normally open region of the chip prevents the second subsystem from sending data to the first subsystem. The blocking register is used to control the ability of the inter-core communication module of the second subsystem to distribute data to the first subsystem.

[0006] Optionally, the second status information of the inter-core communication module of the second subsystem is obtained, including: The second status information is obtained through the status register in the normally open region of the chip. The status register is used to collect and store the status information of the inter-core communication module of the second subsystem.

[0007] Optionally, the pre-power-down check of the first subsystem based on the first state information and the second state information includes: Determine whether the first state information meets the first preset condition; and, Determine whether the second state information meets the second preset condition; If the first status information satisfies the first preset condition and the second status information satisfies the second preset condition, then it is determined that the power-down check of the first subsystem has passed. If the first status information does not meet the first preset condition, and / or the second status information does not meet the second preset condition, then it is determined that the power-down check of the first subsystem has failed.

[0008] Optionally, the first status information satisfying the first preset condition includes at least one of the following: In the first subsystem, the read pointer and write pointer of the receiving component of the inter-core communication module are equal; In the first subsystem, the read pointer and write pointer of the sending component of the inter-core communication module are equal; The inter-core communication module of the first subsystem is in an idle state.

[0009] Optionally, the second status information satisfying the second preset condition includes: the inter-core communication module of the second subsystem is in an idle state.

[0010] Optionally, determining whether the first subsystem is powered down based on the pre-power-down check results includes: If the power-down check of the first subsystem passes, the read / write pointer information of the inter-core communication module of the first subsystem is saved, and the power-down operation of the first subsystem is executed. If the pre-power-down check of the first subsystem fails, the blockade on the second subsystem sending data to the first subsystem is lifted, and the power-down operation of the first subsystem is canceled.

[0011] Optionally, the method further includes: Before performing the power-down operation of the first subsystem, the wake-up source corresponding to the inter-core communication module of the first subsystem is cleared. The wake-up source is the wake-up interrupt signal generated by the power management module in the normally open area of ​​the chip. The wake-up interrupt signal is triggered by the power management module when it detects that the sending component of the inter-core communication module of the second subsystem is in a non-idle state.

[0012] Optionally, the method further includes: After the power-down operation of the first subsystem is performed, the power-on operation of the first subsystem is initiated when the power-on trigger condition of the first subsystem is met. After completing the hardware initialization of the first subsystem, restore the read / write pointer information of the inter-core communication module of the first subsystem; Remove the block on the second subsystem sending data to the first subsystem and restore inter-core communication with the second subsystem.

[0013] Optionally, restoring the read / write pointer information of the inter-core communication module of the first subsystem includes: Read the read / write pointer information of the inter-core communication module saved before the first subsystem is powered down; Based on the read and write pointer information, the read pointer value and write pointer value are synchronized to the register corresponding to the inter-core communication module of the first subsystem.

[0014] According to a second aspect of the present disclosure, a control device based on inter-core communication is provided, comprising: A blocking module is used to prevent the second subsystem of the chip from sending data to the first subsystem in response to a power-down trigger of the first subsystem of the chip. The acquisition module is used to acquire the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem. The inspection module is used to perform a pre-power-down inspection of the first subsystem based on the first status information and the second status information; The control module is used to determine whether the first subsystem should be powered down based on the results of the pre-power-down check.

[0015] Optionally, the blocking module is connected to a blocking register in the normally open region of the chip. The blocking module is used to prevent the second subsystem from sending data to the first subsystem through the blocking register. The blocking register is used to control the ability of the inter-core communication module of the second subsystem to distribute data to the first subsystem.

[0016] Optionally, the acquisition module is connected to a status register in the normally open region of the chip. The acquisition module is used to acquire the first status information and the second status information through the status register. The status register is used to collect and store the status information of the inter-core communication modules of different subsystems.

[0017] Optionally, the inspection module is used to determine whether the first status information meets a first preset condition; and to determine whether the second status information meets a second preset condition; if the first status information meets the first preset condition and the second status information meets the second preset condition, then it is determined that the power-off check of the first subsystem has passed; if the first status information does not meet the first preset condition, and / or the second status information does not meet the second preset condition, then it is determined that the power-off check of the first subsystem has failed.

[0018] Optionally, the control module is configured to, if the pre-power-down check of the first subsystem passes, save the read / write pointer information of the inter-core communication module of the first subsystem and execute the power-down operation of the first subsystem; if the pre-power-down check of the first subsystem fails, release the obstruction of the second subsystem from sending data to the first subsystem and cancel the power-down operation of the first subsystem.

[0019] According to a third aspect of the present disclosure, a chip is provided that includes the apparatus described in the second aspect, or is configured to perform the method described in the first aspect.

[0020] According to a fourth aspect of the present disclosure, an electronic device is provided, including the apparatus described in the second aspect or the chip described in the third aspect.

[0021] By employing the above technical solution, this disclosure provides a control method, apparatus, electronic device, and chip based on inter-core communication. In response to a power-down triggering by the first subsystem of the chip, the second subsystem of the chip is prevented from sending data to the first subsystem; first status information of the inter-core communication module of the first subsystem and second status information of the inter-core communication module of the second subsystem are acquired; then, a pre-power-down check of the first subsystem is performed based on the first and second status information; and finally, the power-down status of the first subsystem can be determined based on the pre-power-down check results. The technical solution provided by this disclosure, by preventing data transmission from the peer second subsystem before the first subsystem is powered down and by performing status checks on the first and second subsystems, can avoid the loss of unprocessed data and chip bus hang-up caused by direct power-down of the first subsystem, ensuring power-up and power-down safety in distributed inter-core communication scenarios and significantly improving chip operational stability.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram illustrating an example provided by an embodiment of this disclosure is shown; Figure 2 A flowchart illustrating a control method based on inter-core communication provided in an embodiment of this disclosure is shown. Figure 3 A flowchart illustrating another control method based on inter-core communication provided in an embodiment of this disclosure is shown; Figure 4 A schematic diagram of a control device based on inter-core communication provided in an embodiment of this disclosure is shown. Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure is shown. Detailed Implementation

[0026] Some embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, for clarity and brevity, descriptions of features known in the art may be omitted.

[0027] The embodiments described in the following examples of this disclosure do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0028] Multiple subsystems exist within a chip. As an inter-core communication scheme between subsystems, data is stored in the shared memory area of ​​DDR. Simultaneously, cross-subsystem communication is achieved through a communication module deployed in the Always-On (AON) area (a hardware module for inter-core notification, sending notifications to the target subsystem via interrupts). Since the AON area is always powered, this scheme eliminates the need for additional low-power control logic.

[0029] To achieve efficient communication between subsystems, the chip can adopt a distributed inter-core communication architecture, in which communication hardware instances are deployed peer-to-peer within both subsystems. For example... Figure 1 The diagram illustrates a distributed inter-core communication scheme between the first and second subsystems of a chip. For example, the first subsystem can be a protocol stack subsystem responsible for the logical processing of the communication protocol, and the second subsystem can be a physical layer subsystem responsible for the physical transmission of data. Each subsystem includes a processor, memory, and a distributed inter-core communication module. The processor is responsible for core computation and logic control. The memory can be static random access memory (SRAM), which can be used for temporary data storage within the subsystem. The distributed inter-core communication module can be a hardware component, specifically including a sending component and a receiving component to achieve bidirectional communication. For instance, the first subsystem passes the data to be transmitted to its own distributed inter-core communication module, which then sends the data to the receiving component of the second subsystem's distributed inter-core communication module via the sending component, thus achieving inter-core communication.

[0030] This approach avoids cross-subsystem software access and eliminates the need for software protocol negotiation, allowing data transmission directly through hardware links and significantly improving inter-core communication performance. However, due to the distributed peer-to-peer design—meaning the inter-core communication modules of the two subsystems have equal hardware status and no master-slave control relationship—if one subsystem is about to power down while the other subsystem remains powered on and requires data transmission, directly powering down can lead to the loss of unprocessed data in inter-core communication. Alternatively, it can cause the chip bus to hang due to the other subsystem continuously initiating bus accesses (accessing invalid addresses) to the powered-down subsystem, severely impacting chip reliability.

[0031] To address the aforementioned technical problems, this disclosure provides a control method based on inter-core communication. Figure 1 The distributed inter-core communication architecture shown provides a power-on / off control scheme based on distributed inter-core communication. This avoids the loss of unprocessed data and chip bus hang-ups caused by direct power-off of one subsystem, as well as issues such as invalid bus address access. Figure 2 As shown, the method includes the following steps: Step 101: In response to the first subsystem of the chip triggering power-down, prevent the second subsystem of the chip from sending data to the first subsystem.

[0032] The first subsystem and the second subsystem can be two subsystems in the same chip. Both the first subsystem and the second subsystem are equipped with a distributed inter-core communication module, which can be simply referred to as the inter-core communication module.

[0033] In some embodiments, the first subsystem can be powered down based on a power-down request. For example, the first subsystem may not be running any tasks and its own control logic may initiate a power-down request, or the chip's power management module may send a power-down request to the first subsystem based on the overall power consumption strategy, or the device's overall power consumption control module may send a power-down request to the first subsystem.

[0034] Preventing the second subsystem of a chip from sending data to the first subsystem can be considered as preventing the second subsystem from sending data to the first subsystem. For example, when the first subsystem of a chip is about to power down, the first step is to prevent the second subsystem from continuing to send data to the first subsystem. This is because the first subsystem is about to stop working, and if the second subsystem continues to send data at this time, subsequent situations such as data not being able to be sent and the first subsystem being unable to process data will occur. Therefore, new communication requests are cut off first to prepare for the first subsystem to power down.

[0035] Step 102: Obtain the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem.

[0036] In this embodiment, after preventing the second subsystem of the chip from sending data to the first subsystem, it is necessary to check the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem. The first status information can be used to determine whether there are any unfinished tasks in the inter-core communication module of the first subsystem, such as data to be received or data to be sent. The second status information can be used to determine whether there are any data requests for the first subsystem that have not yet been sent in the inter-core communication module of the second subsystem. Both the first and second status information can serve as the basis for pre-power-down checks of the first subsystem.

[0037] Step 103: Perform a pre-power-down check on the first subsystem based on the first and second state information.

[0038] This embodiment of the disclosure uses the first state information of the inter-core communication module of the first subsystem and the second state information of the inter-core communication module of the second subsystem as the basis for judgment to check whether the first subsystem meets the conditions for safe power-down.

[0039] For example, it can be determined whether there are any unprocessed communication tasks in the first subsystem and whether there are any pending communication tasks in the second subsystem targeting the first subsystem. If it is confirmed that there are no unprocessed communication tasks in the first subsystem and no pending communication tasks in the second subsystem targeting the first subsystem, it indicates that the pre-power-down check of the first subsystem has passed. If it is confirmed that there are unprocessed communication tasks in the first subsystem and / or that the second subsystem targets the first subsystem, it indicates that the pre-power-down check of the first subsystem has failed.

[0040] Step 104: Determine whether the first subsystem should be powered down based on the pre-power-down inspection results.

[0041] For example, if the pre-power-down check of the first subsystem passes, the first subsystem is allowed to perform the power-down; if the pre-power-down check of the first subsystem fails, the first subsystem is not allowed to perform the power-down.

[0042] The technical solution provided in this disclosure, by preventing the data transmission of the peer second subsystem before the first subsystem is powered down, and by checking the status of the first and second subsystems, can avoid the loss of unprocessed data and the chip bus hang-up caused by the direct power-down of the first subsystem, thus ensuring power-down safety in distributed inter-core communication scenarios and significantly improving chip operation stability.

[0043] Furthermore, to illustrate the specific implementation process of the above embodiments, as an optional approach, the following is provided: Figure 3 The specific implementation method shown includes the following steps: Step 201: In response to the power-down trigger of the first subsystem of the chip, clear the wake-up source corresponding to the inter-core communication module of the first subsystem, and prevent the second subsystem of the chip from sending data to the first subsystem through the blocking register in the normally open area of ​​the chip.

[0044] The always-on (AON) region is a region within the chip that is always powered. In this embodiment, a blocking register can be set in the AON region of the chip. This blocking register can be used to control the ability of the inter-core communication modules of each subsystem in the chip to distribute data to peer subsystems, including controlling the ability of the inter-core communication module of the second subsystem to distribute data to the first subsystem. For example, the blocking register can assign a dedicated control bit to the transmitting component of the inter-core communication module of each subsystem, such as one bit corresponding to the transmitting component of one subsystem's inter-core communication module. By associating the distribution capability enable signal of the transmitting component of the inter-core communication module with the blocking register, indirect control of the transmitting capability of the transmitting components of each subsystem's inter-core communication module can be achieved through the blocking register.

[0045] For example, in response to the power-down trigger of the first subsystem of the chip, the sending component of the inter-core communication module of the second subsystem is stopped from distributing new data descriptors (Desc) to the first subsystem through the blocking register in the normally open area of ​​the chip. The Direct Memory Access (DMA) data transfer that has already started will not be intercepted, ensuring that the ongoing communication task can be completed normally and avoiding abnormalities caused by data transfer interruption.

[0046] The wake-up source is a wake-up interrupt signal generated by the power management module in the normally open area of ​​the chip. This wake-up interrupt signal can be triggered by the power management module when it detects that the inter-core communication module of the second subsystem is in a non-idle state.

[0047] In some embodiments, the status signal of the transmitting component of the inter-core communication module of each subsystem is pulled out to a dedicated register in the AON region as a remote status register, and the status signal is also pulled out to the power management module in the AON region. If the power management module samples that the transmitting component of the inter-core communication module of the subsystem is in a non-idle state (such as a non-IDLE signal), it will trigger the wake-up interrupt signal of the peer subsystem of the subsystem. If the peer subsystem has been powered down, then the peer subsystem will be woken up according to the wake-up interrupt signal.

[0048] Before performing the power-down operation of the first subsystem, this embodiment needs to clear the wake-up source corresponding to the inter-core communication module of the first subsystem and disable the interrupt response and scheduling of the inter-core communication module of the first subsystem. All subsystems except the main CPU are in a low-power state. The wake-up source is used to trigger the current subsystem to wake up if there is a communication requirement (not idle) to a subsystem (such as the second subsystem) while the current subsystem (such as the first subsystem) is in a power-down state. Alternatively, if a sudden communication requirement arises for a subsystem during the power-down process of the current subsystem, a power-down reversal process can be triggered through a wake-up signal. If the power-down reversal is not intercepted in time (if the power-down process has progressed to a later stage), the current subsystem will restart the power-on process based on the wake-up signal after completing the power-down, ensuring that the communication requirement is responded to. It should be noted that when the current subsystem triggers power-down, it is already in a wake-up running state. At this time, the wake-up source is mostly an invalid signal remaining from normal communication (not a signal indicating an actual communication requirement to the subsystem). The wake-up signal is characterized by being pulled high when the inter-core communication module of the counterpart subsystem is not idle. As long as this signal is not cleared, even if the current subsystem has met the safe power-down conditions and completed power-down, the residual wake-up signal will still be interpreted as indicating a communication need, causing the current subsystem to immediately power on again after power-down, violating the low-power design goal. Therefore, clearing the wake-up source before the current subsystem performs a power-down operation aims to eliminate useless wake-up signals remaining from normal communication, preventing these residual signals from mistakenly triggering power-down reversal or abnormal power-on after power-down, ensuring the power-down process can proceed smoothly and complete stably, while not affecting the normal wake-up logic when there is a real communication need later.

[0049] Step 202: Obtain the first status information of the inter-core communication module of the first subsystem, and obtain the second status information of the inter-core communication module of the second subsystem through the status register in the normally open area of ​​the chip.

[0050] The first subsystem can obtain the first status information of the inter-core communication module locally, while the second status information of the inter-core communication module of the second subsystem can be obtained through the status register in the normally open area of ​​the chip.

[0051] This embodiment of the disclosure can set a status register in the AON region of the chip. This setting relies on the fact that the AON region does not lose power. The status register will collect and store the operating status of the inter-core communication modules of each subsystem in real time, without the need for cross-subsystem software negotiation, thus achieving hardware-level status synchronization. For example, the status signals of the transmitting components of the inter-core communication modules of each subsystem (such as the idle signal) are pulled out to a dedicated register in the AON region as a remote status register.

[0052] For example, the second status information of the inter-core communication module of the second subsystem is collected and stored through the status register within the AON area. The first subsystem can obtain the first status information of the inter-core communication module locally, while the second status information of the inter-core communication module of the second subsystem can be obtained through this status register. The first status information is used to determine the operating status of the inter-core communication module of the first subsystem, and the second status information is used to determine the communication status of the inter-core communication module of the second subsystem related to the first subsystem, providing an accurate basis for judgment during subsequent pre-power-down checks.

[0053] Step 203: Determine whether the first state information meets the first preset condition, and determine whether the second state information meets the second preset condition.

[0054] The first preset condition can be used to determine whether there are any unprocessed communication tasks in the first subsystem, and the second preset condition can be used to determine whether there are any pending communication requests from the second subsystem to the first subsystem.

[0055] In some embodiments, the first state information satisfying the first preset condition includes at least one of the following A1 to A3: A1. If the read pointer and write pointer of the receiving component of the inter-core communication module of the first subsystem are equal, it means that the receiving component of the inter-core communication module of the first subsystem has finished processing all the received data in the buffer and there is no residual data to be read.

[0056] A2. If the read pointer and write pointer of the sending component of the inter-core communication module of the first subsystem are equal, it means that the sending component of the inter-core communication module of the first subsystem has completed the distribution of all data to be sent and there are no residual tasks to be sent.

[0057] A3. The inter-core communication module of the first subsystem is in an idle state. This condition is a comprehensive verification of the status of the inter-core communication module of the first subsystem, indicating that the inter-core communication module of the first subsystem is not performing any communication operations.

[0058] In some examples, when A1, A2, and A3 are satisfied simultaneously, it can be determined that the first state information of the inter-core communication module of the first subsystem satisfies the first preset condition.

[0059] In some embodiments, the second state information satisfying the second preset condition includes: the inter-core communication module of the second subsystem is in an idle state. If this condition is satisfied, it indicates that the second subsystem has not initiated any communication operation and there is no behavior of sending data to the first subsystem.

[0060] In some examples, when both B1 and B2 above are met, it can be determined that the second state information of the inter-core communication module of the second subsystem meets the second preset condition.

[0061] Step 204a: If the first status information meets the first preset condition and the second status information meets the second preset condition, then the power-down check of the first subsystem is determined to be passed.

[0062] This pre-power-down check method ensures that the first subsystem has no communication residue and that the second subsystem has no communication requirements for the first subsystem. It avoids the loss of unprocessed data and the chip bus hang caused by accessing invalid addresses due to the first subsystem being powered down directly, ensuring power-down safety in distributed inter-core communication scenarios and significantly improving chip operation stability.

[0063] Step 205a: If the pre-power-down check of the first subsystem passes, save the read / write pointer information of the inter-core communication module of the first subsystem and execute the power-down operation of the first subsystem.

[0064] In this embodiment, it is necessary to save the read / write pointer information of the inter-core communication module of the first subsystem so as to quickly restore the communication state after power-on and ensure communication continuity.

[0065] In step 204b, which is parallel to step 204a, if the first state information does not meet the first preset condition, and / or the second state information does not meet the second preset condition, then it is determined that the power-down check of the first subsystem has failed.

[0066] For example, if the first state information does not meet the first preset condition, or the second state information does not meet the second preset condition, it is determined that the power-down check of the first subsystem has failed. For example, the first subsystem still has unprocessed data, or the second subsystem still has a data descriptor to be sent for the first subsystem. In this case, directly powering down will cause a fault, so it is necessary to start the power-down reversal process, that is, to execute the process shown in step 205b.

[0067] Step 205b: If the pre-power-down check of the first subsystem fails, then the block on the second subsystem sending data to the first subsystem is lifted, and the power-down operation of the first subsystem is cancelled.

[0068] For example, the blocking registers within the AON region can be released from preventing the second subsystem from sending data to the first subsystem, restoring normal communication between the two. Furthermore, the power-down operation of the first subsystem is canceled, allowing it to continue operating normally. This process ensures that the system can quickly revert to normal communication if the safe power-down conditions are not met, avoiding chip malfunctions caused by forced power-down. Additionally, if pending data descriptors appear in the second subsystem during or after the check, the power management module in the AON region will sample a non-IDLE signal, triggering a wake-up interrupt. This will also initiate a power-down reversal or power-on process, further ensuring system stability.

[0069] Furthermore, in some embodiments, after the power-down operation of the first subsystem is performed, when the power-on trigger condition of the first subsystem is met, the power-on operation of the first subsystem is initiated; after the hardware initialization of the first subsystem is completed, the read / write pointer information of the inter-core communication module of the first subsystem is restored; and the obstruction of the second subsystem sending data to the first subsystem is released, and inter-core communication with the second subsystem is restored.

[0070] The power-on triggering conditions may include any of the following: the power management module within the normally open area of ​​the chip detects a request from the second subsystem to send data to the first subsystem and sends a wake-up signal; or the first subsystem receives an external wake-up signal. For example, when the second subsystem has a pending data descriptor for the first subsystem, its inter-core communication module's sending component will be in a non-IDLE state. After the power management module detects this signal, it will trigger a wake-up interrupt to the first subsystem. If the first subsystem is already powered down, the power-on operation will be initiated directly. Alternatively, power-on can also be triggered by an external wake-up signal from the chip.

[0071] After the first subsystem is powered on, the hardware initialization of the first subsystem is performed first. The initialization scope covers the hardware components of the first subsystem, such as the basic circuits of the inter-core communication module, register configuration, etc., to ensure that the hardware is in a stable and usable initial state.

[0072] In some examples, restoring the read and write pointer information of the inter-core communication module of the first subsystem may specifically include: reading the read and write pointer information of the inter-core communication module saved before the first subsystem is powered down; and then, based on the read and write pointer information, synchronizing the read pointer value and the write pointer value to the register corresponding to the inter-core communication module of the first subsystem.

[0073] For example, after hardware initialization, it is necessary to accurately restore the read and write pointer information of the inter-core communication module of the first subsystem. This involves reading saved pointer data. The first subsystem retrieves the read and write pointer information of the receiving and transmitting components of the inter-core communication module stored before power-down. The read and write pointer values ​​are then accurately written into the dedicated register of the inter-core communication module of the first subsystem, achieving a complete restoration of the pointer state. This method allows the first subsystem to directly connect to the communication state before power-down upon power-up, avoiding problems such as unrecognizable cached data and incorrect new data transmission due to pointer loss, thus ensuring the continuity of data communication.

[0074] After the pointer is restored, the transmission restriction on the second subsystem needs to be lifted. This can be done by manipulating the blocking register in the AON region to clear the control instructions that previously prevented the second subsystem from sending data to the first subsystem (i.e., clear the blocking state of the corresponding bit). This allows the inter-core communication module of the second subsystem to resume its ability to distribute data descriptors to the first subsystem.

[0075] This disclosure provides a hardware-based low-power solution based on distributed inter-core communication. The hardware for this inter-core communication solution is distributed equally across the transceiver subsystems, and the master-slave relationship between the two subsystems cannot be defined from a business perspective. In this scenario, this disclosure can solve the power-on / off problem of distributed inter-core communication, ensuring safe power-on / off without data loss or chip bus crashes, without affecting the transceiver performance of distributed inter-core communication, significantly simplifying the low-power process, improving low-power performance, and solving the problem with a simpler low-power process from a chip architecture perspective.

[0076] Figure 4 This is a block diagram of a control device based on inter-core communication, illustrated according to some embodiments of the present disclosure. The device can be configured using an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), etc., and can be configured to execute... Figures 1 to 3 The method shown. Refer to... Figure 4 The device includes: a blocker 31, an acquisition module 32, an inspection module 33, and a control module 34.

[0077] The blocking module 31 is used to prevent the second subsystem of the chip from sending data to the first subsystem in response to the first subsystem of the chip being powered down. The acquisition module 32 is used to acquire the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem. Inspection module 33, which can be connected to acquisition module 32, is used to perform a pre-power-down inspection of the first subsystem based on first status information and second status information; The control module 34 can be connected to the inspection module 33 and is used to determine whether the first subsystem is powered down based on the inspection results before power-down.

[0078] In some embodiments of this disclosure, the blocking module 31 is used to prevent the second subsystem from sending data to the first subsystem via a blocking register, the blocking register being used to control the ability of the inter-core communication module of the second subsystem to distribute data to the first subsystem.

[0079] In some embodiments of this disclosure, the acquisition module 32 is connected to the status register in the normally open region of the chip. The acquisition module is used to acquire second status information through the status register. The status register is used to collect and store the status information of the inter-core communication module of the second subsystem.

[0080] In some embodiments of this disclosure, the inspection module 33 is used to determine whether the first state information meets the first preset condition; and to determine whether the second state information meets the second preset condition; if the first state information meets the first preset condition and the second state information meets the second preset condition, then it is determined that the power-off check of the first subsystem has passed; if the first state information does not meet the first preset condition and / or the second state information does not meet the second preset condition, then it is determined that the power-off check of the first subsystem has failed.

[0081] In some embodiments of this disclosure, the first state information satisfying the first preset condition includes at least one of the following: In the first subsystem, the read pointer and write pointer of the receiving component of the inter-core communication module are equal; In the first subsystem, the read pointer and write pointer of the inter-core communication module are equal. The inter-core communication module of the first subsystem is in an idle state.

[0082] In some embodiments of this disclosure, the second state information satisfying the second preset condition includes: the inter-core communication module of the second subsystem is in an idle state.

[0083] In some embodiments of this disclosure, the control module 34 is configured to, if the pre-power-down check of the first subsystem passes, save the read / write pointer information of the inter-core communication module of the first subsystem and execute the power-down operation of the first subsystem; if the pre-power-down check of the first subsystem fails, release the obstruction of the second subsystem from sending data to the first subsystem and cancel the power-down operation of the first subsystem.

[0084] In some embodiments of this disclosure, the control module 34 is used to clear the wake-up source corresponding to the inter-core communication module of the first subsystem before performing the power-down operation of the first subsystem. The wake-up source is a wake-up interrupt signal generated by the power management module in the normally open area of ​​the chip. The wake-up interrupt signal is triggered by the power management module when it detects that the sending component of the inter-core communication module of the second subsystem is in a non-idle state.

[0085] In some embodiments of this disclosure, the control module 34 is configured to, after performing the power-down operation of the first subsystem, initiate the power-on operation of the first subsystem when the first subsystem meets the power-on trigger condition; after completing the hardware initialization of the first subsystem, restore the read / write pointer information of the inter-core communication module of the first subsystem; release the obstruction of the second subsystem sending data to the first subsystem, and restore inter-core communication with the second subsystem.

[0086] In some embodiments of this disclosure, the control module 34 is used to read the read and write pointer information of the inter-core communication module saved before the first subsystem is powered off; based on the read and write pointer information, the read pointer value and the write pointer value are synchronized to the register corresponding to the inter-core communication module of the first subsystem.

[0087] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0088] Furthermore, embodiments of this disclosure provide a chip, which may include, for example... Figure 4 The control device shown is based on inter-core communication. Alternatively, the chip is configured to perform actions such as... Figures 1 to 3 The method shown is described above. By applying the chip of the embodiments of this disclosure, the power-on and power-off problems of distributed inter-core communication can be solved, ensuring safe power-on and power-off without data loss or chip bus hang-up, without affecting the transmission and reception performance of distributed inter-core communication, greatly simplifying the low-power process, improving low-power performance, and solving the problem with a simpler low-power process from the perspective of chip architecture.

[0089] In some embodiments, the chip may include one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, it causes the electronic device to perform the aforementioned actions. Figures 1 to 3 The method shown.

[0090] Furthermore, embodiments of this disclosure provide an electronic device, including as follows: Figure 4 The control device shown, based on inter-core communication, may include the aforementioned chip, wherein the chip includes, for example... Figure 4 The control device shown, based on inter-core communication, can be configured to perform actions such as Figures 1 to 3 The method shown.

[0091] like Figure 5 The above is a block diagram illustrating an electronic device 800 according to some embodiments of the present disclosure. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0092] Reference Figure 5The electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0093] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0094] Memory 804 is configured to store various types of data to support the operation of device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. Power component 806 provides power to various components of electronic device 800. Power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0095] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0096] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0097] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0098] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 may detect the on / off state of device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0099] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 3G, 4G, 5G, other communication standards, or combinations thereof. In some embodiments of this disclosure, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In some embodiments of this disclosure, communication component 816 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0100] In some embodiments of this disclosure, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0101] In some embodiments of this disclosure, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions that can be executed by a processor 820 of an electronic device 800 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0102] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0103] In the above detailed description, reference has been made to the accompanying drawings, which illustrate specific aspects of this disclosure by way of illustration. In this regard, terms indicating direction or positional relationship, such as “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” “counterclockwise,” “axial,” “radial,” and “circumferential,” are used with reference to the orientation of the described figures. Since components of the described device can be positioned in multiple different orientations, directional terms are used for illustrative purposes and not for limitation. It should be understood that other aspects can be utilized and structural or logical changes can be made without departing from the concept of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0104] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0105] It should be understood that, unless otherwise expressly specified and limited, the terms "joining," "attaching," "installing," "connecting," "linking," "fixing," etc., used in the embodiments of this disclosure should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms herein based on the specific circumstances.

[0106] Furthermore, the term "above" as used herein with respect to components, elements, or material layers formed or located "above" a surface may be used to indicate that the component, element, or material layer is "indirectly" positioned (e.g., placed, formed, deposited, etc.) on the surface such that one or more additional components, elements, or layers are arranged between the surface and the component, element, or material layer. However, the term "above" as used with respect to components, elements, or material layers formed or located "above" a surface may also optionally have a specific meaning: that the component, element, or material layer is "directly" positioned (e.g., placed, formed, deposited, etc.) on the surface, for example, in direct contact with the surface.

[0107] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0108] It should be understood that spatial relative terms, such as “above,” “upper,” “below,” and “lower,” are used herein to describe the relationship between one element and another shown in the figures. In addition to the orientation depicted in the figures, these spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “above” or “upper” relative to another element would be “below” or “lower” relative to that other element. Thus, depending on the spatial orientation of the device, the term “above” encompasses both above and below orientations. Devices may have other orientations (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly.

[0109] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0110] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0111] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0112] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A control method based on inter-core communication, characterized in that, include: In response to a power-down trigger of the first subsystem of the chip, the second subsystem of the chip is prevented from sending data to the first subsystem. Obtain the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem; Perform a power-off check on the first subsystem based on the first status information and the second status information; Determine whether the first subsystem should be powered down based on the results of the pre-power-down inspection.

2. The method according to claim 1, characterized in that, The step of preventing the second subsystem of the chip from sending data to the first subsystem includes: The blocking register in the normally open region of the chip prevents the second subsystem from sending data to the first subsystem. The blocking register is used to control the ability of the inter-core communication module of the second subsystem to distribute data to the first subsystem.

3. The method according to claim 1, characterized in that, Obtain the second status information of the inter-core communication module of the second subsystem, including: The second status information is obtained through the status register in the normally open region of the chip. The status register is used to collect and store the status information of the inter-core communication module of the second subsystem.

4. The method according to claim 1, characterized in that, The pre-power-down check of the first subsystem based on the first status information and the second status information includes: Determine whether the first state information meets the first preset condition; and, Determine whether the second state information meets the second preset condition; If the first status information satisfies the first preset condition and the second status information satisfies the second preset condition, then it is determined that the power-down check of the first subsystem has passed. If the first status information does not meet the first preset condition, and / or the second status information does not meet the second preset condition, then it is determined that the power-down check of the first subsystem has failed.

5. The method according to claim 4, characterized in that, The first status information satisfies the first preset condition, including at least one of the following: In the first subsystem, the read pointer and write pointer of the receiving component of the inter-core communication module are equal; In the first subsystem, the read pointer and write pointer of the sending component of the inter-core communication module are equal; The inter-core communication module of the first subsystem is in an idle state.

6. The method according to claim 4 or 5, characterized in that, The second status information satisfies the second preset condition, including: the inter-core communication module of the second subsystem is in an idle state.

7. The method according to claim 4, characterized in that, The step of determining whether the first subsystem is powered down based on the pre-power-down check results includes: If the power-down check of the first subsystem passes, the read / write pointer information of the inter-core communication module of the first subsystem is saved, and the power-down operation of the first subsystem is executed. If the pre-power-down check of the first subsystem fails, the blockade on the second subsystem sending data to the first subsystem is lifted, and the power-down operation of the first subsystem is canceled.

8. The method according to claim 7, characterized in that, The method further includes: Before performing the power-down operation of the first subsystem, the wake-up source corresponding to the inter-core communication module of the first subsystem is cleared. The wake-up source is the wake-up interrupt signal generated by the power management module in the normally open area of ​​the chip. The wake-up interrupt signal is triggered by the power management module when it detects that the sending component of the inter-core communication module of the second subsystem is in a non-idle state.

9. The method according to claim 7, characterized in that, The method further includes: After the power-down operation of the first subsystem is executed, the power-on operation of the first subsystem is initiated when the power-on trigger condition of the first subsystem is met. After completing the hardware initialization of the first subsystem, restore the read / write pointer information of the inter-core communication module of the first subsystem; Remove the block on the second subsystem sending data to the first subsystem and restore inter-core communication with the second subsystem.

10. The method according to claim 9, characterized in that, The process of restoring the read / write pointer information of the inter-core communication module of the first subsystem includes: Read the read / write pointer information of the inter-core communication module saved before the first subsystem is powered down; Based on the read and write pointer information, the read pointer value and write pointer value are synchronized to the register corresponding to the inter-core communication module of the first subsystem.

11. A control device based on inter-nuclear communication, characterized in that, include: A blocking module is used to prevent the second subsystem of the chip from sending data to the first subsystem in response to a power-down trigger of the first subsystem of the chip. The acquisition module is used to acquire the first status information of the inter-core communication module of the first subsystem and the second status information of the inter-core communication module of the second subsystem. The inspection module is used to perform a pre-power-down inspection of the first subsystem based on the first status information and the second status information; The control module is used to determine whether the first subsystem should be powered down based on the results of the pre-power-down check.

12. The apparatus according to claim 11, characterized in that, The blocking module is connected to a blocking register in the normally open region of the chip. The blocking module is used to prevent the second subsystem from sending data to the first subsystem through the blocking register. The blocking register is used to control the ability of the inter-core communication module of the second subsystem to distribute data to the first subsystem.

13. The apparatus according to claim 11, characterized in that, The acquisition module is connected to the status register in the normally open region of the chip. The acquisition module is used to acquire the second status information through the status register. The status register is used to collect and store the status information of the inter-core communication module of the second subsystem.

14. The apparatus according to claim 11, characterized in that, The inspection module is used to determine whether the first status information meets the first preset condition; and to determine whether the second status information meets the second preset condition; if the first status information meets the first preset condition and the second status information meets the second preset condition, then it is determined that the power-off check of the first subsystem has passed; if the first status information does not meet the first preset condition and / or the second status information does not meet the second preset condition, then it is determined that the power-off check of the first subsystem has failed.

15. The apparatus according to claim 14, characterized in that, The control module is configured to, if the pre-power-down check of the first subsystem passes, save the read / write pointer information of the inter-core communication module of the first subsystem and execute the power-down operation of the first subsystem; if the pre-power-down check of the first subsystem fails, release the obstruction of the second subsystem from sending data to the first subsystem and cancel the power-down operation of the first subsystem.

16. A chip, characterized in that, Includes the apparatus of any one of claims 11 to 15, or is configured to perform the method of any one of claims 1 to 10.

17. An electronic device, characterized in that, Includes the device according to any one of claims 11 to 15, or the chip according to claim 16.

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