Bandwidth expansion circuit applied to high-speed interface equalizer

Abstract

The technical scheme of the invention discloses a bandwidth expansion circuit applied to a high-speed interface equalizer. Aiming at the problem of insufficient compensation capability of the bandwidth expansion technology under the condition of relatively large input parasitic capacitance introduced by a load, an inductor is cascaded between a CTLE module and a VGA module, and the resonance effect of the series peaking inductor and the parasitic capacitance is utilized, so that the bandwidth expansion is realized; aiming at the bandwidth expansion requirement under the condition of high speed and large load, a series peaking inductor is combined with a parallel peaking inductor in the prior art, and the bandwidth of the CTLE module is pushed to higher frequency; in order to solve the problem that a passive inductor occupies a large area, an inverter composed of MOS tubes is designed to achieve an active inductor, the chip area is effectively reduced, and the system design requirement is met.

Description

Technical Field

[0001] This invention relates to a bandwidth extension circuit for high-speed interface equalizers, belonging to the field of integrated circuit design technology. Background Technology

[0002] In high-speed serial systems, analog equalizers are often used as the first-stage equalizer at the receiver to compensate for non-ideal characteristics in signal transmission and improve signal integrity. A common analog equalizer is the Continuous Time Linear Equalizer (CTLE), which compensates for high-frequency components more than low-frequency components to counteract the impact of frequency-selective fading on signal integrity. Because high-speed signal data transmission rates are relatively high, the CTLE module needs a sufficiently large bandwidth to ensure complete signal transmission and eliminate the impact of bandwidth limitations on signal integrity. However, to drive the subsequent Decision Feedback Equalizer (DFE), a Variable Gain Amplifier (VGA) is often cascaded between the CTLE and DFE modules. To improve driving capability, the VGA module typically uses large-sized driver transistors, resulting in a large input parasitic capacitance, which limits the bandwidth of the CTLE module.

[0003] To improve the bandwidth and high-frequency compensation capability of CTLE modules, parallel inductor peaking technology and negative capacitor technology are commonly used for bandwidth expansion. The following section introduces common CTLE structures and bandwidth expansion techniques.

[0004] 1. Continuous Time Linear Equalizer (CTLE) CTLE modules are often implemented using a source-degraded resistor-capacitor structure, such as... Figure 1 As shown. Input signal V in V ip M is the data signal transmitted through the channel. 10 M 20 For the input pair, the drain terminal is connected to the output signal V. out With load resistance R L Load capacitor C L The source terminal is connected to the source degradation resistor R. S Capacitor C S By setting an appropriate R L R S C S The value of ensures that the high-frequency compensation of the CTLE module meets the design requirements.

[0005] The transfer function of the CTLE module is shown in the following equation:

[0006] Among them, g m1 Indicates MOSFET M 10 M 20 Transconductance.

[0007] As shown in the above formula, the CTLE module contains one zero and two poles, namely: zero Principal pole: Secondary pole: Its amplitude-frequency response curve is as follows: Figure 2 As shown, because the zero is located before the dominant pole, the amplitude-frequency response curve of the CTLE module rises with a slope of +20dB / Dec at the zero. When it encounters the dominant pole, the curve flattens out due to the opposite characteristics of the zero and pole. When it encounters the secondary pole, the curve decreases with a slope of -20dB / Dec.

[0008] 2. Parallel inductor peaking technology As a common bandwidth expansion technique in CTLE modules, parallel inductor peaking technology cascades a passive inductor at the load resistor. This weakens the capacitive load in the original load network through the inductive load, causing the secondary pole to shift to a higher frequency, thus expanding bandwidth and improving the circuit's high-frequency gain. CTLE modules based on parallel inductor peaking technology include... Figure 3 As shown, its transfer function is as follows:

[0009] Where: load impedance Source degradation impedance .

[0010] Compared to the source-degraded resistor-capacitor CTLE structure, the CTLE structure based on parallel inductor peaking technology introduces an additional zero and two poles on top of the original zeros and poles, namely: zero ;pole By designing a suitable inductance value L, the additional zero point introduced can be eliminated. With the extreme point Adjacent elements cancel out the decrease in amplitude-frequency response curve at the poles, thereby achieving bandwidth expansion and gain enhancement.

[0011] 3. Negative capacitance technology Considering the source degradation resistor-capacitor CTLE structure, the secondary pole is affected by the load capacitance C. L The impact is significant, therefore, negative capacitance technology can be used to offset the load capacitance value, thereby shifting the secondary pole to a higher frequency and achieving the goal of expanding the bandwidth. The specific implementation structure is as follows: Figure 4 As shown, the capacitor C CIt is connected across the source terminals of M3 and M4; M3 and M4 are a cross-coupled pair, with the gate of M3 connected to the drain of M4, and cascaded across M... 12 The drain of M4; the gate of M4 is connected to the drain of M3, and cascaded in M... 22 The drain terminal. The output impedance of CTLE based on negative capacitance technology is shown in the following formula:

[0012] Among them, Z NC This represents the output impedance from the drain terminals of M3 and M4 in the negative capacitor structure, g. m2 For the transconductance of MOSFETs M3 and M4, C gs1 These are the gate-source capacitances of MOSFETs M3 and M4.

[0013] The transfer function of the CTLE structure based on negative capacitance technology can be expressed as follows:

[0014] In this case, the gate-source capacitance C of MOSFETs M3 and M4 is ignored. gs1 .

[0015] Parallel inductor peaking and negative capacitor techniques are common bandwidth-extending technologies in CTLE modules. Essentially, they introduce additional zeros and poles, which cancel each other out with the dominant poles. This allows the amplitude-frequency response curve to continue to improve under the influence of the original zeros, thus achieving bandwidth extension and high-frequency compensation enhancement. Since these two techniques use capacitors and inductors, their values ​​are typically quite large to meet design requirements, resulting in a significant chip area. Furthermore, when a large input parasitic capacitance is introduced by the downstream load, parallel inductor peaking and negative capacitor techniques require even larger inductors and capacitors to further increase bandwidth and meet system design requirements, necessitating an even larger chip area, which is unacceptable. Summary of the Invention

[0016] The technical problem this invention aims to solve is that bandwidth expansion technology has insufficient compensation capability when faced with large input parasitic capacitance introduced by the load; it cannot meet the bandwidth expansion requirements under high-speed load conditions; and passive inductors occupy a large area.

[0017] To solve the above-mentioned technical problems, the technical solution of the present invention discloses a bandwidth expansion circuit for a high-speed interface equalizer. The circuit is characterized in that a peaking inductor is connected in series between the output of the continuous-time linear equalizer and the input of the load of the subsequent variable gain amplifier. By setting an appropriate inductance value, the pole is pushed from a low frequency to an extremely high target frequency.

[0018] Preferably, the transistor M at the output of the continuous-time linear equalizer N The gate connection input signal VIN Load resistance R0, peaking inductance L0, drain parasitic capacitance C d Cascaded in transistor M N The drain terminal of the peaking inductor L0 is connected to the other side of the output signal V. OUT And the cascaded load input parasitic capacitance C in The parasitic capacitance C flowing to the load input is delayed by the series peaking inductor L0. in The current causes transistor M to, in the initial stage, […]. N Only for drain parasitic capacitance C d Charging reduces rise time.

[0019] Preferably, the series peaking inductor is combined with the parallel peaking inductor. The series peaking inductor is used to further expand the bandwidth based on the parallel inductor peaking technology. The resonant effect of multiple inductors and capacitors is used to compensate through three parallel resonances, pushing the bandwidth of the continuous-time linear equalizer to a higher frequency, so as to further expand the bandwidth to meet the design requirements.

[0020] Preferably, the input pair M of the continuous-time linear equalizer 13 M 23 The gate connection input signal V in V ip Source-terminal cascaded source degradation resistor R S With capacitor C S Drain-side cascaded load resistor R L and series peaked inductor L S Load resistance R L The other end is cascaded with a peaked inductor L. P Series peaked inductor L S The other end is connected in a cascaded load capacitor C L With output signal V out Among them, the parallel peaking inductor L P Series-connected peaked inductor L S All are implemented using active structures.

[0021] Preferably, at low frequencies, the input transistor M... 13 M 23 All the drain current flows into the load resistor R. L This generates an output voltage, and as the frequency begins to increase, the parallel peaking inductor L... P The increased impedance, through the effect of parallel peaking, improves the input impedance of transistor M. 13 M 23 The proportion of drain current flowing into the rest, and simultaneously, the series peaking inductor L S With input tube M 13 M 23The resonant frequency of the drain parasitic capacitance is In the series resonance, most of the shunt current flows into the peaking inductor L. S With input tube M 13 M 23 Drain parasitic capacitance; When the frequency is further increased, exceeding the series resonant frequency After that, the load capacitance C L With series peaked inductor L S The drain parasitic capacitance C forms a resonant frequency of The parallel resonant network exhibits capacitive characteristics and is equivalent to a capacitor C. e The capacitor C e With parallel peaking inductor L P To form another resonant frequency is Parallel resonant network.

[0022] Preferably, the parallel peaking inductor L P Or series peaked inductor L S This includes an inverter structure composed of MOSFETs M5 and M6. The gates of MOSFETs M5 and M6 are connected, as are the drains of MOSFETs M5 and M6. The source of MOSFET M5 is connected to the power supply, and the source of MOSFET M6 is grounded. Resistor R... N It is connected between the gate and drain of MOSFETs M5 and M6.

[0023] This invention addresses the problem of insufficient compensation capability of the aforementioned bandwidth expansion technologies when faced with large input parasitic capacitance introduced by the load. A novel bandwidth expansion technology is designed, which achieves bandwidth expansion by cascading an inductor between the CTLE module and the VGA module and utilizing the resonant effect of the series peaking inductor and the parasitic capacitance.

[0024] This invention addresses the bandwidth expansion requirements under high-speed load conditions. In cases where the downstream load has a large input parasitic capacitance, it combines a series peaking inductor with the parallel peaking inductor in existing technologies. By using a series peaking inductor to further expand the bandwidth based on the parallel inductor peaking technology, and utilizing the resonant effect of multiple inductors and capacitors, compensation is achieved through three parallel resonances, pushing the bandwidth of the CTLE module to a higher frequency to further expand the bandwidth and meet design requirements.

[0025] This invention addresses the issue of passive inductors occupying a large area by designing an active inductor using an inverter constructed from MOS transistors, effectively reducing chip area and meeting system design requirements. Attached Figure Description

[0026] Figure 1 The source degradation resistor-capacitor CTLE structure is illustrated. Figure 2 The amplitude-frequency response curve of the CTLE module is shown. Figure 3 The diagram illustrates the CTLE structure based on parallel inductor peaking technology; Figure 4 The diagram illustrates the CTLE structure based on negative capacitance technology; Figure 5 A simplified diagram illustrating the principle of series peaking inductor technology; Figure 6 The CTLE structure based on series-parallel peaked inductors is illustrated. Figure 7 The diagram illustrates the active inductor based on the inverter and its equivalent model. Detailed Implementation

[0027] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0028] This invention discloses a bandwidth expansion technology for high-speed interface equalizers, which specifically includes the following:

[0029] 1) Principle of Series Peaking Inductor Technology When the load after the CTLE module is large, the large parasitic capacitance of the load will cause the secondary pole of the CTLE module to shift to a lower frequency, reducing the bandwidth, as analyzed above. Therefore, in this invention, an inductor is connected in series between the output of the CTLE module and the input of the load, as shown in the simplified diagram below. Figure 5 As shown, the source degradation resistance R of the CTLE module is ignored. S With capacitor C s C d For MOSFET M N The parasitic capacitance of the drain, C in The load input parasitic capacitance. MOSFET M N The gate connection input signal V IN Load resistance R0, series peaking inductance L0, drain parasitic capacitance C d Cascaded in MOSFET M N The drain terminal of the inductor L0. The other side of the inductor L0 is connected to the output signal V. OUT And the cascaded load input parasitic capacitance C in At this point, the normalized transmission impedance can be expressed as:

[0030] in: ; ; .

[0031] The above equation shows that by introducing a series peaking inductor L0, the location of the poles can be changed. By setting an appropriate inductance value, the poles can be pushed from low frequencies to extremely high frequencies, thereby achieving bandwidth expansion. From a time-domain perspective, considering the amplifier's step response, the series peaking inductor L0 delays the flow to the load input parasitic capacitance C. in The current. This causes the transistor to only respond to the drain parasitic capacitance C in the initial stage. d Charging reduces rise time, thereby enabling bandwidth expansion.

[0032] (ii) CTLE design based on the combination of series peaking inductors and parallel peaking inductors In this invention, to address the bandwidth expansion requirements under high-speed load conditions, the designed series peaking inductor is combined with the existing parallel peaking inductor, and implemented using an active inductor based on an inverter structure. The specific structure is as follows: Figure 6 As shown. M 13 M 23 For the input pair transistors, the gate is connected to the input signal V. in V ip Source-terminal cascaded source degradation resistor R S With capacitor C S Drain-side cascaded load resistor R L and series peaked inductor L S Load resistance R L The other end is cascaded with a peaked inductor L. P Series peaking inductor L S The other end is connected in a cascaded load capacitor C L With output signal V out Among them, the parallel peaking inductor L P Series peaking inductor L S All are implemented using active structures, and the circuit structure is as follows: Figure 7 As shown. MOSFETs M5 and M6 form an inverter structure. The gates of M5 and M6 are connected, the drains of M5 and M6 are connected, the source of M5 is connected to the power supply, and the source of M6 is grounded. Resistor R... N It is connected between the gate and drain of MOSFETs M5 and M6. Figure 7 The right side of the middle section shows the equivalent diagram of an active inductor based on an inverter structure, where R... e Equivalent resistance, L e Equivalent inductance.

[0033] The working principle of the CTLE module based on a series-parallel peaked inductor is analyzed. At low frequencies, because the inductor impedance is very low, the input transistor M... 13M 23 All the drain current flows into the load resistor R. L This generates an output voltage. As the frequency begins to increase, due to the parallel peaking inductor L... P The increased impedance, through the effect of parallel peaking, improves the input impedance of transistor M. 13 M 23 The proportion of drain current flowing into the rest. Simultaneously, the series peaking inductor L... S With input tube M 13 M 23 The drain parasitic capacitance (let's say it's C) undergoes series resonance, and the resonant frequency at this point is shown in the following equation:

[0034] Therefore, most of the shunt current flows into the drain parasitic capacitance C. This bandwidth extension is essentially due to the inductance L. P and L S The resulting voltage increase offset the voltage drop caused by capacitor C.

[0035] When the frequency is further increased, exceeding the series resonant frequency After that, the load capacitance C L With series peaked inductor L S The drain parasitic capacitance C and the drain form a parallel resonant network, whose resonant frequency is shown in the following equation:

[0036] At this point, the resonant network exhibits capacitive characteristics, equivalent to a capacitor C. e The capacitor and the parallel peaking inductor L P This will form another parallel resonant network, with the resonant frequency as shown in the following equation:

[0037] in: ; ; .

[0038] Due to the effect of the parallel resonant network, the frequency increases to... , At any given time, there will be a boost in the response, thus pushing the bandwidth to higher frequencies. As the frequency continues to increase, due to the equivalent capacitance C... e Due to the effect of [something], the amplitude-frequency response curve will begin to drop rapidly.

Claims

1. A bandwidth extension circuit for use in high-speed interface equalizers, characterized in that, A peaking inductor is connected in series between the output of the continuous-time linear equalizer and the input of the load of the subsequent variable gain amplifier. By setting an appropriate inductance value, the poles can be pushed from low frequencies to extremely high target frequencies.

2. The bandwidth expansion circuit for a high-speed interface equalizer as described in claim 1, characterized in that, The transistor M at the output of the continuous-time linear equalizer N The gate connection input signal V IN Load resistance R0, peaking inductance L0, drain parasitic capacitance C d Cascaded in transistor M N The drain terminal of the peaking inductor L0 is connected to the other side of the output signal V. OUT And the cascaded load input parasitic capacitance C in The parasitic capacitance C flowing to the load input is delayed by the series peaking inductor L0. in The current causes transistor M to... N Only for drain parasitic capacitance C d Charging reduces rise time.

3. The bandwidth expansion circuit for a high-speed interface equalizer as described in claim 1, characterized in that, By combining the series peaking inductor with the parallel peaking inductor, the bandwidth is further extended based on the parallel inductor peaking technology. By utilizing the resonant effect of multiple inductors and capacitors, compensation is performed through three parallel resonances, pushing the bandwidth of the continuous-time linear equalizer to a higher frequency, thereby further expanding the bandwidth to meet design requirements.

4. The bandwidth expansion circuit for a high-speed interface equalizer as described in claim 3, characterized in that, The input pair M of the continuous-time linear equalizer 13 M 23 The gate connection input signal V in V ip Source-terminal cascaded source degradation resistor R S With capacitor C S Drain-side cascaded load resistor R L and series peaked inductor L S Load resistance R L The other end is cascaded with a peaked inductor L. P Series peaked inductor L S The other end is connected in a cascaded load capacitor C L With output signal V out Among them, the parallel peaking inductor L P Series-connected peaked inductor L S All are implemented using active structures.

5. The bandwidth extension circuit for a high-speed interface equalizer as described in claim 4, characterized in that, At low frequencies, the input transistor M 13 M 23 All the drain current flows into the load resistor R. L This generates an output voltage, and as the frequency begins to increase, the parallel peaking inductor L... P The increased impedance, through the effect of parallel peaking, improves the input impedance of transistor M. 13 M 23 The proportion of drain current flowing into the rest, and simultaneously, the series peaking inductor L S With input tube M 13 M 23 The resonant frequency of the drain parasitic capacitance is In the series resonance, most of the shunt current flows into the peaking inductor L. S With input tube M 13 M 23 Drain parasitic capacitance; When the frequency is further increased, exceeding the series resonant frequency After that, the load capacitance C L With series peaked inductor L S The drain parasitic capacitance C forms a resonant frequency of The parallel resonant network exhibits capacitive characteristics and is equivalent to a capacitor C. e The capacitor C e With parallel peaking inductor L P To form another resonant frequency is Parallel resonant network.

6. The bandwidth expansion circuit for a high-speed interface equalizer as described in claim 4, characterized in that, The parallel peaking inductor L P Or series peaked inductor L S This includes an inverter structure composed of MOSFETs M5 and M6. The gates of MOSFETs M5 and M6 are connected, as are the drains of MOSFETs M5 and M6. The source of MOSFET M5 is connected to the power supply, and the source of MOSFET M6 is grounded. Resistor R... N It is connected between the gate and drain of MOSFETs M5 and M6.

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