Architecture for heterogeneous inter-core communication and operation method and system of architecture

Abstract

The invention relates to an architecture for heterogeneous inter-core communication and an operation method and system of the architecture, and the method comprises the following steps: carrying out the identification distribution of different types of processor cores based on a preset inter-core mapping table, and obtaining a core identification code set; performing packaging processing on a to-be-transmitted sending data packet generated by a local processor core through the core identification code set to obtain a packaged data packet; performing cross-core transmission on the encapsulated data packet through a preset shared memory area to obtain transmission result data; and based on the transmission result data, performing de-encapsulation processing on the received encapsulation data packet to obtain the original sending data to be transmitted, thereby solving the technical problems of resource scrambling and data loss when a plurality of cores initiate data transmission requests at the same time.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to an architecture for heterogeneous inter-core communication, a method for operating the architecture, and a system. Background Technology

[0002] In heterogeneous core data transmission, traditional solutions either rely on dedicated buses or software-level multi-round handshake protocols, both of which have significant drawbacks. While dedicated buses offer higher transmission rates, they are costly and inflexible; any change in core type or number necessitates a redesign of the bus interface. Software handshake protocols, on the other hand, are constrained by the operating system's scheduling mechanism, leading to resource contention and data loss when multiple cores simultaneously initiate data transmission requests. More importantly, neither solution provides an efficient solution to the core issue of "data adaptation between different core types"—for example, some cores process data with 32-bit alignment while others use 64-bit alignment. Directly transmitting unprocessed raw data can cause parsing errors at the receiving end, requiring significant computational resources for data verification and correction, severely impacting overall computational efficiency. Summary of the Invention

[0003] The main technical problem addressed by this application is to provide an architecture, operating method, and system for communication between heterogeneous cores, which solves the technical problem of resource contention and data loss that easily occurs when multiple cores simultaneously initiate data transmission requests.

[0004] To address the aforementioned technical problems, this application employs an architecture and a method for operating the architecture for heterogeneous inter-core communication, comprising the following steps: Based on a preset inter-core mapping table, identifiers are assigned to different types of processor cores to obtain a set of core identifier codes; The data packets to be transmitted generated by the local processor core are encapsulated using the core identifier set to obtain encapsulated data packets. The encapsulated data packet is transmitted across cores through a preset shared memory region to obtain the transmission result data; Based on the transmission result data, the received encapsulated data packet is decapsulated to obtain the original data to be transmitted.

[0005] Furthermore, the process of assigning identifiers to different types of processor cores based on a preset inter-core mapping table yields a core identifier code set, including: The preset inter-core mapping table is read to obtain the core type and address correspondence information, and based on the core type and address correspondence information, the addresses of different types of processor cores are located to obtain the address of each core. The core location addresses are encoded according to the preset encoding rules to obtain core identification codes, and all core identification codes are integrated to obtain a core identification code set.

[0006] Furthermore, the process of encoding each core location address according to a preset encoding rule to obtain a core identifier code includes: The address format of each core location address is parsed to obtain the address segment start value and address segment length. Based on the address segment start value and address segment length, each core location address is segmented and extracted to obtain an address segment set. Based on preset encoding rules, each address segment in the address segment set is numerically converted to obtain the converted numerical code, and all numerical codes are concatenated in a preset order to obtain the core identifier code.

[0007] Furthermore, the process of encapsulating the data packet to be transmitted generated by the local processor core using the core identifier set to obtain an encapsulated data packet includes: The data format of the data packet to be transmitted generated by the local processor core is analyzed to obtain data format information. Based on the data format information, the data packet to be transmitted is converted according to a preset unified data format template to obtain a unified format data packet. Based on the core identifier set, the target core identifier and the source core identifier are added to the unified format data packet to obtain the encapsulated data packet.

[0008] Furthermore, the step of transmitting the encapsulated data packet across cores through a preset shared memory region to obtain transmission result data includes: The memory status of the preset shared memory region is detected to obtain free memory block information including the address and size of the free memory block. Based on the free memory block information, a free memory block of appropriate size is selected as the target memory block in the shared memory region. The source core's identification information and the target receiving core's identification information are associated and bound with the encapsulated data packet to generate a data combination to be transmitted that includes the source core identifier, the target core identifier, and the encapsulated data content. Based on a preset cross-core transmission protocol, the data to be transmitted is combined and transmitted to a selected target memory block in the shared memory region for writing operation. After the writing is completed, a write data packet is obtained. A data checksum generation operation is performed on the written data packet to generate a checksum, and the generated checksum is appended to the end of the written data packet to obtain the transmission result data.

[0009] Furthermore, the step of appending the generated checksum to the end of the data packet to obtain the transmission result data includes: The generated check code is converted into a specific format check code segment that is compatible with the data format of the data packet to obtain a format-adapted check code. The data length of the data packet to be written is detected to determine the remaining space size for appending data to the end of the data packet, and the remaining space information is obtained. Based on the remaining space information, the format adaptation check code is appended to the corresponding remaining space position at the end of the written data packet to obtain the appended check code data packet. Integrity markers are added to the additional checksum data packet. An integrity identifier field is added to the header of the additional checksum data packet to obtain the transmission result data.

[0010] Furthermore, based on the transmission result data, the received encapsulated data packet is decapsulated to obtain the original data to be transmitted, including: The transmitted result data is verified by a data check code. The check code of the received data packet is recalculated and compared with the additional check code to obtain the verification result. If the verification results are consistent, the data transmission is determined to be error-free and a valid data packet is obtained. If the verification results are inconsistent, the data transmission is determined to be error-free and a retransmission mechanism is triggered or the current data packet is discarded. The target core identifier and source core identifier in the valid data packet are identified and parsed to obtain the identifier parsing result. Based on the identifier parsing result, the data packet is restored according to a preset unified data format template to obtain the original data to be transmitted.

[0011] This invention also provides an architecture for heterogeneous inter-core communication and an operating system for that architecture, comprising: The allocation module is used to allocate identifiers to different types of processor cores based on a preset inter-core mapping table, thereby obtaining a set of core identifier codes. The encapsulation module is used to encapsulate the data packets to be transmitted generated by the local processor core using the core identifier code set, so as to obtain encapsulated data packets; The transmission module is used to perform cross-core transmission of the encapsulated data packet through a preset shared memory area to obtain transmission result data; The decapsulation module is used to decapsulate the received encapsulated data packet based on the transmission result data to obtain the original data to be transmitted.

[0012] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0013] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any of the above methods.

[0014] The above scheme assigns identifiers to different types of processor cores based on a preset inter-core mapping table to obtain a core identifier code set; encapsulates the data packets to be transmitted generated by the local processor core using the core identifier code set to obtain encapsulated data packets; transmits the encapsulated data packets across cores through a preset shared memory region to obtain transmission result data; and decapsulates the received encapsulated data packets based on the transmission result data to obtain the original data to be transmitted. This solves the technical problem of resource contention and data loss when multiple cores initiate data transmission requests simultaneously, avoids parsing errors that occur when the original data is transmitted directly, reduces data verification and correction steps at the receiving end, significantly reduces computing power consumption, and ensures the integrity and consistency of data transmitted between heterogeneous cores. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the steps of an architecture for heterogeneous inter-core communication and the method of operating the architecture in one embodiment of the present invention; Figure 2 This is a structural block diagram of an architecture for heterogeneous inter-core communication and the operating system of the architecture, according to one embodiment of the present invention. Figure 3 This is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0017] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Specifically, the architecture and operating method for heterogeneous inter-core communication in this embodiment include the following steps: like Figure 1 As shown, Figure 1 This invention provides an architecture and operating method for heterogeneous inter-core communication, comprising the following steps: Step S1: Based on the preset inter-core mapping table, assign identifiers to different types of processor cores to obtain a set of core identifier codes.

[0020] Specifically, this step requires a pre-defined inter-core mapping table. Then, based on this table, different types of processor cores are assigned unique identifiers, and finally, a set of core identifier codes is compiled. It's crucial that the inter-core mapping table clearly defines the type, functional parameters, and corresponding identifier rules for each core beforehand; otherwise, errors can easily occur during allocation. For example, in a heterogeneous architecture containing CPU, GPU, and NPU, the mapping table might specify that the CPU corresponds to identifier code "001," the GPU to "010," and the NPU to "011." Following this rule during allocation ensures that each core has a unique and unified identifier, allowing for precise matching during subsequent data transmission.

[0021] Step S2: The data packet to be transmitted generated by the local processor core is encapsulated using the core identifier code set to obtain an encapsulated data packet.

[0022] Specifically, the local processor core first generates a data packet to be transmitted. Then, it uses the previously obtained set of core identifiers to encapsulate this data packet, resulting in an encapsulated data packet. It's important to note that the corresponding core identifier must be embedded in the data packet header during encapsulation; it's not arbitrarily added. For example, if the local processor core is a CPU core and needs to transmit image data to the GPU, the generated data packet to be transmitted will embed the GPU's identifier "010" in the header. This way, during subsequent transmission, the header identifier tells the processor which core to send the data to, eliminating the need for additional matching.

[0023] Step S3: The encapsulated data packet is transmitted across cores through a preset shared memory region to obtain the transmission result data.

[0024] Specifically, first, the location of the predefined shared memory region is determined. Then, the encapsulated data packet obtained earlier is transmitted to this shared memory region to complete the cross-core transmission. After the transmission is complete, the transmission result data can be obtained. An important point to note is that the shared memory region must be pre-divided into dedicated storage blocks, with each storage block corresponding to a different target core. For example, if the CPU core transmits the encapsulated data packet to the NPU, the data packet is placed in the corresponding NPU storage block. When the NPU detects data in the block, it reads it, thus preventing data loss during the transmission process.

[0025] Step S4: Based on the transmission result data, decapsulate the received encapsulated data packet to obtain the original data to be transmitted.

[0026] Specifically, the first step is to examine the transmission result data. After confirming that the data transmission is successful, the received encapsulated data packets are decapsulated. Once this is complete, the original data to be transmitted can be obtained. It's important to note that decapsulation requires first extracting the core identifier from the data packet, and then unpacking it according to the format corresponding to the identifier. For example, in the case where the CPU transmits image data to the GPU, after receiving the encapsulated data packet, the GPU first extracts the "010" identifier, and then unpacks it according to a format that the GPU can recognize. This way, the original image data can be accurately obtained.

[0027] In a specific embodiment, the process of assigning identifiers to different types of processor cores based on a preset inter-core mapping table to obtain a core identifier code set includes: The preset inter-core mapping table is read to obtain the core type and address correspondence information, and based on the core type and address correspondence information, the addresses of different types of processor cores are located to obtain the address of each core. The core location addresses are encoded according to the preset encoding rules to obtain core identification codes, and all core identification codes are integrated to obtain a core identification code set.

[0028] Specifically, to complete the step of assigning identifiers to different types of processor cores based on a preset inter-core mapping table and obtaining a set of core identifier codes, the process must be carried out step by step. First, the preset inter-core mapping table must be read to obtain the information corresponding to the core type and its address. After obtaining this information, the addresses of different types of processor cores are located based on it, thus obtaining the address of each core. For example, in a heterogeneous architecture with CPU, GPU, and NPU cores, the inter-core mapping table will clearly state that the CPU corresponds to address "0x0001", the GPU to address "0x0002", and the NPU to address "0x0003". After reading this information, the actual location of each core, i.e., its address, can be accurately found.

[0029] Next, these core location addresses are encoded according to preset encoding rules to obtain individual core identifier codes. The final step is to integrate all the obtained core identifier codes together, thus forming a core identifier code set. It's important to note that the preset encoding rules must be defined in advance. For example, the last 8 bits of the core location address might be used as the main part of the identifier code, with two check bits added. For instance, the CPU's address "0x0001" might be encoded as "0100" according to this rule, and the GPU's "0x0002" would be encoded as "0200". By integrating these individual codes, the core identifier code set is formed.

[0030] In a specific embodiment, the process of encoding each core location address according to a preset encoding rule to obtain a core identifier code includes: The address format of each core location address is parsed to obtain the address segment start value and address segment length. Based on the address segment start value and address segment length, each core location address is segmented and extracted to obtain an address segment set. Based on preset encoding rules, each address segment in the address segment set is numerically converted to obtain the converted numerical code, and all numerical codes are concatenated in a preset order to obtain the core identifier code.

[0031] Specifically, to complete the step of encoding each core location address according to the preset encoding rules and obtaining the core identifier code, the process must proceed sequentially. The first step is to parse the address format of each core location address. After parsing, the starting value and length of the address segment can be obtained. With this information, the core location address is then segmented and extracted, resulting in a set of address segments. For example, suppose a core location address is "0x12345678". After parsing, the starting value of the address segment is found to be "0x12" with a length of 2, and the next segment starts with "0x34" with a length of 2. After segment extraction, the set of address segments is "0x12, 0x34, 0x56, 0x78".

[0032] Then, based on the preset encoding rules, each address segment in the address segment set is numerically converted to obtain the converted numerical code. Finally, all the numerical codes are concatenated in a preset order, and the core identifier code is obtained. It's important to note that the preset encoding rules must be clearly defined in advance. For example, if the rule specifies converting hexadecimal address segments to 8-bit binary, then "0x12" becomes "00010010", and "0x34" becomes "00110100". These converted numerical codes are then concatenated in the original address segment order, like "0001001000110100010101011001111000", which is the final core identifier code.

[0033] In a specific embodiment, the step of encapsulating the data packet to be transmitted generated by the local processor core using the core identifier code set to obtain an encapsulated data packet includes: The data format of the data packet to be transmitted generated by the local processor core is analyzed to obtain data format information. Based on the data format information, the data packet to be transmitted is converted according to a preset unified data format template to obtain a unified format data packet. Based on the core identifier set, the target core identifier and the source core identifier are added to the unified format data packet to obtain the encapsulated data packet.

[0034] Specifically, to complete the step of encapsulating the data packets generated by the local processor core using the core identifier set and obtaining the encapsulated data packets, we must proceed step by step. First, we need to analyze the data format of the data packets generated by the local processor core. After analysis, we can obtain the data format information. Once we understand this information, we then perform format conversion on the data packets according to a preset unified data format template, thus obtaining a unified format data packet. For example, if the local processor core is a CPU, and the generated data packets are 16-bit aligned image data, while the preset unified data format template requires 32-bit alignment, then during format conversion, bytes will be added according to the template rules to change the 16-bit aligned data to 32-bit aligned data, ultimately resulting in a unified format data packet.

[0035] Next, we operate based on the core identifier set. We add the target core identifier and the source core identifier to the unified format data packet we just obtained. This generates the encapsulated data packet. For example, if we want to send data to the GPU, and the GPU's identifier in the core identifier set is "010" and the CPU's identifier is "001", then we add "010" (target core identifier) ​​and "001" (source core identifier) ​​to the header of the unified format data packet, respectively. After adding these identifiers, this identifiable data packet is the final encapsulated data packet.

[0036] In a specific embodiment, the step of transmitting the encapsulated data packet across cores through a preset shared memory region to obtain transmission result data includes: The memory status of the preset shared memory region is detected to obtain free memory block information including the address and size of the free memory block. Based on the free memory block information, a free memory block of appropriate size is selected as the target memory block in the shared memory region. The source core's identification information and the target receiving core's identification information are associated and bound with the encapsulated data packet to generate a data combination to be transmitted that includes the source core identifier, the target core identifier, and the encapsulated data content. Based on a preset cross-core transmission protocol, the data to be transmitted is combined and transmitted to a selected target memory block in the shared memory region for writing operation. After the writing is completed, a write data packet is obtained. A data checksum generation operation is performed on the written data packet to generate a checksum, and the generated checksum is appended to the end of the written data packet to obtain the transmission result data.

[0037] Specifically, to complete the cross-core transmission of the encapsulated data packet through the preset shared memory region and obtain the transmission result data, the process must be carried out step by step. The first step is to perform a memory status check on the preset shared memory region. After the check, information about free memory blocks, including their addresses and sizes, can be obtained. Then, based on this information, a suitable free memory block is selected from the shared memory region as the target memory block. For example, if the encapsulated data packet size is 8KB, and there are free memory blocks of 6KB, 10KB, and 12KB, the 10KB block is selected as the target memory block to avoid memory waste or insufficient space.

[0038] After selecting the target memory block, the next step is to associate and bind the source core's identifier information, the target receiving core's identifier information, and the previously encapsulated data packet. This will generate a data combination to be transmitted that includes the source core identifier, the target core identifier, and the encapsulated data content. For example, if the source core is the CPU (identified by "001") and the target receiving core is the GPU (identified by "010"), then the data combination to be transmitted would be "001 (source core identifier) ​​+ 010 (target core identifier) ​​+ encapsulated data packet content".

[0039] Then, based on the preset cross-core transfer protocol, the data to be transferred is transmitted to the selected target memory block in the shared memory region for writing. Once the writing is complete, the write data packet is obtained. It is important to note that the preset cross-core transfer protocol must predefine the data transmission timing and format, such as specifying that data is transmitted every 1ms and in byte stream format, so that the writing process will not encounter problems.

[0040] The final step is to generate a data checksum from the obtained data packet. This checksum is then appended to the end of the data packet, resulting in the final transmission data. For example, if the checksum generated using the CRC32 algorithm is "1A3F5B7D", the final transmission data will be "data packet content + 1A3F5B7D (checksum)".

[0041] In a specific embodiment, appending the generated checksum to the end of the data packet to obtain the transmission result data includes: The generated check code is converted into a specific format check code segment that is compatible with the data format of the data packet to obtain a format-adapted check code. The data length of the data packet to be written is detected to determine the remaining space size for appending data to the end of the data packet, and the remaining space information is obtained. Based on the remaining space information, the format adaptation check code is appended to the corresponding remaining space position at the end of the written data packet to obtain the appended check code data packet. Integrity markers are added to the additional checksum data packet. An integrity identifier field is added to the header of the additional checksum data packet to obtain the transmission result data.

[0042] Specifically, to complete the step of appending the generated checksum to the end of the data packet and obtaining the transmission result data, the process must be carried out sequentially. The first step is to process the generated checksum, which requires data format conversion. The original checksum is converted into a specific format checksum segment that is compatible with the format of the data packet being written. This yields a format-adapted checksum. For example, if the data packet being written is in hexadecimal byte stream format, and the generated checksum is in 32-bit binary format, the conversion will transform the 32-bit binary into an 8-bit hexadecimal checksum segment, thus ensuring compatibility with the data packet format. This is the format-adapted checksum.

[0043] After the conversion is complete, the next step is to check the data length of the written data packet. We need to determine the amount of remaining space that can be appended to the end of the packet to obtain the remaining space information. For example, if the total length of the written data packet is 1024 bytes and 992 bytes have been used, then the remaining space at the end is 32 bytes, and the remaining space information obtained in this case is "32 bytes remaining".

[0044] Once the space situation is clear, based on this remaining space information, the previously obtained format adaptation checksum is appended to the corresponding remaining space position at the end of the data packet. After appending, the data packet with the appended checksum is obtained. Just like the case with 32 bytes remaining, if the format adaptation checksum is 16 bytes, then it is directly placed in the 16-byte space starting from byte 993 at the end. After placing it, this data packet is the data packet with the appended checksum.

[0045] The final step is to add an integrity flag to the additional checksum data packet. Specifically, this involves adding an integrity flag field to its header. After adding this, you will obtain the transmission result data. For example, if the integrity flag field is set to "0xAA", indicating that the data is complete after adding the checksum, then add the "0xAA" field at the very beginning of the additional checksum data packet header. At this point, the entire data packet contains the original data, the checksum, and the integrity flag, which is the final transmission result data.

[0046] In a specific embodiment, the step of decapsulating the received encapsulated data packet based on the transmission result data to obtain the original data to be transmitted includes: The transmitted result data is verified by a data check code. The check code of the received data packet is recalculated and compared with the additional check code to obtain the verification result. If the verification results are consistent, the data transmission is determined to be error-free and a valid data packet is obtained. If the verification results are inconsistent, the data transmission is determined to be error-free and a retransmission mechanism is triggered or the current data packet is discarded. The target core identifier and source core identifier in the valid data packet are identified and parsed to obtain the identifier parsing result. Based on the identifier parsing result, the data packet is restored according to a preset unified data format template to obtain the original data to be transmitted.

[0047] Specifically, to complete the step of decapsulating the received encapsulated data packet based on the transmission result data and obtaining the original data to be transmitted, the steps must be followed sequentially. The first step is to verify the data checksum of the transmission result data. Specifically, this involves recalculating the checksum of the received data packet and comparing it with the additional checksum in the transmission result data. This yields the verification result. It's important to note that the verification result will have two outcomes: if the two checksums match, it means the data transmission was error-free and a valid data packet can be obtained; if they don't match, there is a transmission problem. In this case, either a retransmission mechanism is triggered to retransmit the data, or the current data packet is simply discarded. For example, if the additional checksum in the transmission result data is "1A3F5B7D", and the checksum obtained after recalculating the received data packet is also "1A3F5B7D", then the verification results match, confirming that this is a valid data packet.

[0048] After confirming the data is correct, the next step is to identify and parse the target core identifier and source core identifier in the valid data packet. This parsing process yields the identifier resolution result. For example, if the target core identifier is "010" (corresponding to the GPU) and the source core identifier is "001" (corresponding to the CPU), this is the identifier resolution result. Based on this result, the data packet is then formatted according to a pre-defined unified data format template. Finally, the original data to be transmitted is obtained. Just as the 16-bit aligned image data was converted to 32-bit alignment during encapsulation, the restoration process involves converting the 32-bit alignment back to 16-bit alignment according to the template. The resulting image data is the original data to be transmitted.

[0049] Please see Figure 2 , Figure 2 This is a schematic diagram of a framework embodiment of the architecture and operating system for heterogeneous inter-core communication according to this application. Figure 2 As shown, the architecture for heterogeneous inter-core communication and its operating system include an allocation module 1, used to allocate identifiers to different types of processor cores based on a preset inter-core mapping table to obtain a core identifier code set; an encapsulation module 2, used to encapsulate the data packets to be transmitted generated by the local processor core using the core identifier code set to obtain encapsulated data packets; a transmission module 3, used to transmit the encapsulated data packets across cores through a preset shared memory region to obtain transmission result data; and a decapsulation module 4, used to decapsulate the received encapsulated data packets based on the transmission result data to obtain the original data to be transmitted.

[0050] Reference Figure 3 This invention also provides a computer device whose internal structure can be as follows: Figure 3 As shown, the computer device includes a processor, memory, display screen, input device, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores the data corresponding to this embodiment. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described method.

[0051] Those skilled in the art will understand that Figure 3 The structures shown are merely block diagrams of some structures related to the present invention and do not constitute a limitation on the computer devices on which the present invention is applied.

[0052] An embodiment of the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. It is understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0053] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the present invention and embodiments can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual-rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0054] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0055] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0056] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0057] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0058] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0059] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0060] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

Claims

1. An architecture for heterogeneous inter-core communication and a method for operating the architecture, characterized in that, Includes the following steps: Based on a preset inter-core mapping table, identifiers are assigned to different types of processor cores to obtain a set of core identifier codes; The data packets to be transmitted generated by the local processor core are encapsulated using the core identifier set to obtain encapsulated data packets. The encapsulated data packet is transmitted across cores through a preset shared memory region to obtain the transmission result data; Based on the transmission result data, the received encapsulated data packet is decapsulated to obtain the original data to be transmitted.

2. The architecture and operating method for heterogeneous inter-core communication according to claim 1, characterized in that, The process of assigning identifiers to different types of processor cores based on a preset inter-core mapping table yields a set of core identifier codes, including: The preset inter-core mapping table is read to obtain the core type and address correspondence information, and based on the core type and address correspondence information, the addresses of different types of processor cores are located to obtain the address of each core. The core location addresses are encoded according to the preset encoding rules to obtain core identification codes, and all core identification codes are integrated to obtain a core identification code set.

3. The architecture and operating method for heterogeneous inter-core communication according to claim 2, characterized in that, The process of encoding each core location address according to a preset encoding rule to obtain a core identifier code includes: The address format of each core location address is parsed to obtain the address segment start value and address segment length. Based on the address segment start value and address segment length, each core location address is segmented and extracted to obtain an address segment set. Based on preset encoding rules, each address segment in the address segment set is numerically converted to obtain the converted numerical code, and all numerical codes are concatenated in a preset order to obtain the core identifier code.

4. The architecture and operating method for heterogeneous inter-core communication according to claim 1, characterized in that, The process of encapsulating the data packet to be transmitted generated by the local processor core using the core identifier code set to obtain the encapsulated data packet includes: The data format of the data packet to be transmitted generated by the local processor core is analyzed to obtain data format information. Based on the data format information, the data packet to be transmitted is converted according to a preset unified data format template to obtain a unified format data packet. Based on the core identifier set, the target core identifier and the source core identifier are added to the unified format data packet to obtain the encapsulated data packet.

5. The architecture and operating method for heterogeneous inter-core communication according to claim 1, characterized in that, The step of transmitting the encapsulated data packet across cores through a preset shared memory region to obtain transmission result data includes: The memory status of the preset shared memory region is detected to obtain free memory block information including the address and size of the free memory block. Based on the free memory block information, a free memory block of appropriate size is selected as the target memory block in the shared memory region. The source core's identification information and the target receiving core's identification information are associated and bound with the encapsulated data packet to generate a data combination to be transmitted that includes the source core identifier, the target core identifier, and the encapsulated data content. Based on a preset cross-core transmission protocol, the data to be transmitted is combined and transmitted to a selected target memory block in the shared memory region for writing operation. After the writing is completed, a write data packet is obtained. A data checksum generation operation is performed on the written data packet to generate a checksum, and the generated checksum is appended to the end of the written data packet to obtain the transmission result data.

6. The architecture and operating method for heterogeneous inter-core communication according to claim 5, characterized in that, The step of appending the generated checksum to the end of the data packet to obtain the transmission result data includes: The generated check code is converted into a specific format check code segment that is compatible with the data format of the data packet to obtain a format-adapted check code. The data length of the data packet to be written is detected to determine the remaining space size for appending data to the end of the data packet, and the remaining space information is obtained. Based on the remaining space information, the format adaptation check code is appended to the corresponding remaining space position at the end of the written data packet to obtain the appended check code data packet. Integrity markers are added to the additional checksum data packet, and an integrity identifier field is added to the header of the additional checksum data packet to obtain the transmission result data.

7. The architecture and operating method for heterogeneous inter-core communication according to claim 1, characterized in that, The step of decapsulating the received encapsulated data packet based on the transmission result data to obtain the original data to be transmitted includes: The transmitted result data is verified by a data check code. The check code of the received data packet is recalculated and compared with the additional check code to obtain the verification result. If the verification results are consistent, the data transmission is determined to be error-free and a valid data packet is obtained. If the verification results are inconsistent, the data transmission is determined to be error-free and a retransmission mechanism is triggered or the current data packet is discarded. The target core identifier and source core identifier in the valid data packet are identified and parsed to obtain the identifier parsing result. Based on the identifier parsing result, the data packet is restored according to the preset unified data format template to obtain the original data to be transmitted.

8. An architecture for heterogeneous inter-core communication and an operating system thereof, characterized in that, include: The allocation module is used to allocate identifiers to different types of processor cores based on a preset inter-core mapping table, thereby obtaining a set of core identifier codes. The encapsulation module is used to encapsulate the data packets to be transmitted generated by the local processor core using the core identifier code set, so as to obtain encapsulated data packets; The transmission module is used to perform cross-core transmission of the encapsulated data packet through a preset shared memory area to obtain the transmission result data; The decapsulation module is used to decapsulate the received encapsulated data packet based on the transmission result data to obtain the original data to be transmitted.

9. A computer device, characterized in that, It includes a memory and a processor that are coupled to each other, the memory storing program instructions, and the processor executing the program instructions to implement the architecture and method of operating the architecture for heterogeneous inter-core communication as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The system stores program instructions that can be executed by a processor, the program instructions being used to implement the architecture for heterogeneous inter-core communication and the method of operating the architecture as described in any one of claims 1 to 7.

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