Method and network equipment for realizing FPGA (Field Programmable Gate Array) loading configuration data

Abstract

The invention provides a method for loading configuration data by an FPGA (Field Programmable Gate Array) and network equipment, and the method comprises the following steps: the FPGA receives a bit stream instruction for loading the configuration data, obtains a first bit stream switch and a first bit stream jump program corresponding to the bit stream instruction from a storage medium connected with the FPGA according to the bit stream instruction, closes the first bit stream switch, and sends the first bit stream jump program to the FPGA; and acquiring a corresponding first application bit stream according to the first bit stream jump program, and loading first configuration data for the FPGA according to the first application bit stream. By means of the method, the external storage medium can be subjected to physical partition to store a plurality of Bit files, and configuration data loading is carried out according to needs.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a method and network device for loading configuration data into an FPGA. Background Technology

[0002] FPGA (Field-Programmable Gate Array) is an integrated circuit built on configurable logic units, interconnect resources, and I / O modules. Its core feature is that its hardware functions can be dynamically reconfigured through software programming. It has the advantages of high performance and low latency of ASIC (Application-Specific Integrated Circuit) while retaining the flexibility of general-purpose processors. It is currently widely used in industrial control, communication systems, medical devices, and consumer electronics.

[0003] Each FPGA's internal logic resources (such as LUTs and Block RAM) have a physical limit. When new functions exceed the current resource capacity, traditional solutions require replacing them with higher-model chips, leading to increased hardware costs, PCB redesign, and interruptions in mass production. However, if functional modules are mutually exclusive in the time dimension (such as communication protocol switching or AI algorithm rotation), different functions can be compiled into independent bit files and loaded on demand through a time-sharing multiplexing strategy. This allows for the superposition of functions without changing the hardware. For example, an industrial controller can run motion control algorithm A during the day and switch to data encryption module B at night, enabling a single FPGA to support 140% of its functional capacity.

[0004] FPGA AS loading (Active Serial) refers to the FPGA actively reading configuration data from external non-volatile memory (such as Flash memory) to complete self-booting. Compared to other FPGA loading methods such as PS (Passive Serial) and JTAG mode, this method has advantages such as fast boot speed, simple system design, and high reliability. However, in standard AS mode, the FPGA can only read a fixed bitstream file from external Flash memory, resulting in the inability to dynamically adjust functionality. If the design needs to be modified, the Flash memory must be reprogrammed. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this specification provides a method and network device for loading configuration data into an FPGA.

[0006] According to a first aspect of the embodiments of this specification, a method for loading configuration data into an FPGA is provided, the method comprising: The FPGA receives a bitstream command to load configuration data. According to the bit stream instruction, the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction are obtained from the storage medium connected to the FPGA. Close the first stream switch and obtain the corresponding first application bit stream according to the first stream jump procedure; The first configuration data is loaded for the FPGA based on the first application bitstream.

[0007] The first bitstream instruction carries a bitstream identifier that enables the first bitstream.

[0008] The step of retrieving the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction from the storage medium connected to the FPGA according to the bit stream instruction includes: According to the bit stream command, open or close the closed bit stream switch in the storage medium; Based on the first stream identifier carried by the bit stream instruction, the first stream switch and the first stream jump program corresponding to the first stream identifier are retrieved from the storage medium.

[0009] The method further includes: When the FPGA is powered on for the first time, the default bit stream switch and default bit stream jump program are retrieved from the storage medium connected to the FPGA. Close the default bitstream switch and obtain the corresponding default application bitstream according to the default bitstream jump procedure; The default configuration data is loaded for the FPGA based on the default application bitstream.

[0010] The method further includes: The configuration data of the bit stream switches, bit stream jumpers and application bit streams corresponding to different configuration data are stored in the storage medium in sequence.

[0011] As can be seen from the above embodiments, by storing configuration data of each version of AS in the storage medium and by using bit stream switches and bit stream jump programs, it is possible to store multiple bit files (multiple versions of AS configuration data) by physically partitioning the external storage medium, and design dynamic switching logic to achieve on-demand loading, thereby expanding the functional capacity without replacing the hardware, realizing the loading and startup of multiple versions of AS on the FPGA, and promoting the evolution of FPGA towards "reconfigurability".

[0012] According to a second aspect of the embodiments of this specification, a network device is provided, the network device comprising: an FPGA and a storage medium connected to the FPGA, the FPGA comprising: The receiving module is used to receive bitstream instructions for loading configuration data; The acquisition module is used to acquire the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction from the storage medium connected to the FPGA according to the bit stream instruction; The processing module is used to close the first bit stream switch, obtain the corresponding first application bit stream according to the first bit stream jump program, and load the first configuration data for the FPGA according to the first application bit stream.

[0013] The first bitstream instruction carries a bitstream identifier that enables the first bitstream.

[0014] Specifically, the acquisition module is used to open and close the closed bit stream switch in the storage medium according to the bit stream instruction, and to acquire the first stream switch and the first stream jump program corresponding to the first stream identifier from the storage medium according to the first stream identifier carried by the bit stream instruction.

[0015] The acquisition module is further configured to acquire a default bit stream switch and a default bit stream jump program from the storage medium connected to the FPGA when the FPGA is powered on for the first time, and to close the default bit stream switch and acquire the corresponding default application bit stream according to the default bit stream jump program. The processing module is used to load default configuration data for the FPGA based on the default application bitstream.

[0016] Specifically, the configuration data of bit stream switches, bit stream jump programs, and application bit streams corresponding to different configuration data are stored sequentially in the storage medium.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0019] Figure 1 This is a flowchart illustrating a method for loading configuration data onto an FPGA according to an exemplary embodiment.

[0020] Figure 2 This is a schematic diagram of the architecture of a storage medium illustrated in this specification according to an exemplary embodiment.

[0021] Figure 3 This is a flowchart illustrating a method for loading configuration data onto an FPGA according to an exemplary embodiment.

[0022] Figure 4This is a schematic diagram illustrating a framework for loading and starting a system configuration according to an exemplary embodiment. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0024] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0025] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0026] Currently, one implementation primarily utilizes a multi-FPGA configuration loading and reconfiguration system that uses multiple FLASH (storage media) chips for hybrid multiplexing. This system consists of N SRAM-type FPGAs, M SPI FLASH chips, and a general-purpose reconfiguration controller. The general-purpose reconfiguration controller is connected to the FLASH chips via a four-wire SPI bus and to the FPGA via a set of GPIO interfaces, supporting both Slave Serial and Slave SelectMAP configuration modes. The signal connection between the general-purpose reconfiguration controller and the FLASH chips supports both serial and parallel read / write modes, as does the signal connection between the general-purpose reconfiguration controller and the FPGA. Any program stream can be stored using either a single FLASH chip or with redundant storage across three FLASH chips. Each FPGA supports both loading the original program stream and loading the reconfigured program stream.

[0027] However, the above method essentially uses multiple Flash chips to physically pull down the chip select signal to load multiple versions of the FPGA's AS (Autowired Substrate). However, this multi-Flash solution requires independent memory chip configuration for each version (e.g., 4 Flash chips for 4 versions), directly increasing PCB layout area and Bill of Materials (BOM) costs. Furthermore, the chip select pins consume FPGA I / O resources (e.g., using 4 Flash chips requires 4 CS pins + a shared data bus). In addition, when physically pulling down the CS signal to trigger loading, it is necessary to ensure the target Flash is active upon power-up, posing a timing conflict risk (e.g., loading begins before CS is fully pulled low, leading to bitstream read errors). Moreover, the switching delay is affected by mechanical operations (e.g., relay switching) (potentially reaching tens of milliseconds).

[0028] To address the aforementioned technical problems, this disclosure provides a method for loading configuration data onto an FPGA, such as... Figure 1 As shown, the method includes: The S101FPGA receives a bitstream command to load configuration data. S102 retrieves the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction from the storage medium connected to the FPGA according to the bit stream instruction; S103 closes the first stream switch and obtains the corresponding first application bit stream according to the first stream jump program; S104 loads the first configuration data for the FPGA based on the first application bitstream.

[0029] In this embodiment, in order to implement the technical solution of this disclosure, the storage method of multi-version configuration data in the storage medium is pre-set by loading multi-version configuration data through a storage medium. The multi-version bitstream file mainly consists of application bitstream switch program, application bitstream jump program, golden bitstream and application bitstream. Each application bitstream has a switch program and a jump program. All of these files can be finally merged into a merged bitstream file by the CDT_CFG tool.

[0030] The merged bitstream file is stored in FLASH in 4KB (one subsector) blocks. The first 4KB is the switch routine, consisting of 1023 32'hffff_ffff characters + 1 synchronization code (32'h0133_2d94). The second 4KB is the application bitstream jump routine. The golden bitstream can be set after the last jump routine, with any portion less than 4KB padded with 32'hffff_ffff. The starting positions of the golden bitstream and the application bitstream can be set when generating the merged bitstream file. The golden bitstream precedes the application bitstream, ensuring that there is no address overlap between the bitstreams.

[0031] For example, assuming a merged bitstream including 3 application bitstreams, the bitstream size of the PG3T500 device is 24,668,112 bytes, approximately 24,090KB. Since the FLASH storage is 4KB aligned, it occupies 6,023 4KB bytes.

[0032] The switch and jump routines each occupy 4KB, and the three application bitstreams require a total of 24KB of space. Therefore, the default starting address of the gold bitstream is 0x6000 (6×4KB, 24KB). The starting address of application bitstream 1 is 0x0178d00 ((6+6023)×4KB, 24116KB) by default; The starting address of application bitstream 2 is 0x02f14000 ((6+6023+6023)×4KB, 48208KB) by default; The starting address of application bitstream 3 is 0x0469b000 ((6+6023+6023+6023)×4KB,72300KB); The starting address of each bit stream can also be set to an address aligned to 4KB after the default address. For example, if the starting address of the gold bit stream is set to 0x7000 (28KB), then the default address of applied bit stream 1 becomes 0x0178e000 ((6+1+6023)×4KB, 12624KB), and the addresses of applied bit streams 2 and 3 follow the same pattern.

[0033] exist Figure 2 In one example shown, when there is one application bitstream, the switching routine is enabled by default, meaning the application bitstream is started by default. When there are multiple application bitstreams, switching routine 1 is enabled by default, and the other switching routines are disabled, meaning the first application bitstream is started by default. After a normal boot into user mode, the system determines whether to perform a bitstream switch based on the instructions issued by the master controller. If a bitstream switch is required, the master controller needs to issue an erase switch enable instruction via the control bus to erase the switch enable of all bitstreams, then re-enable the switch enable of the target application bitstream, and finally issue a hot boot enable to load the target application bitstream. If an error or timeout occurs during the loading of the application bitstream, the system will automatically fall back to the golden bitstream to prevent the system from becoming unusable.

[0034] In step S101, the bit stream instruction for loading configuration data received by the FPGA may include an initial bit stream instruction (i.e., a bit stream instruction received after the device is powered on) and a switching bit stream instruction for switching configuration data.

[0035] In this embodiment, when the device is powered on for the first time, the FPGA receives the initial bit stream instruction for loading configuration data. When distinguishing between the initial bit stream instruction and the bit stream switching instruction, it can be determined whether the bit stream identifier carried in the bit stream instruction is the default value. If it is the default value, it can be determined that the FPGA receives the initial bit stream instruction for loading configuration data; otherwise, it is the bit stream switching identifier.

[0036] In step S102, when the bit stream instruction is identified to carry the first bit stream identifier corresponding to the first bit stream, the FPGA control puts all bit stream switches in the storage medium into the open state (i.e., disconnects all bit stream switches), finds the corresponding first bit stream switch and first bit stream jump program according to the first bit stream identifier, closes the first bit stream switch (i.e. enables the first bit stream), and loads the first configuration data for the FPGA according to the first application bit stream corresponding to the first bit stream jump program.

[0037] like Figure 3 One example flow is as follows: When the chip is powered on (i.e., the device is powered on for the first time), the FPGA loads the default configuration data from the storage medium. When the user needs to switch bit streams, the storage medium receives the bit stream switching command sent by the FPGA. The storage medium obtains the first bit stream identifier from the bit stream switching command. When it is determined that the first bit stream identifier is inconsistent with the currently loaded configuration data, all bit stream switches are opened or closed. The corresponding first bit stream switch and first bit stream jump program are found according to the first bit stream identifier. The first bit stream switch is closed, and the first bit stream application is found according to the first bit stream jump program. The configuration data is loaded according to the first bit stream application.

[0038] During the above process, errors or timeouts may occur. If an error or timeout occurs during the loading of the application bitstream, the system will automatically revert to the gold bitstream to prevent the system from becoming unusable.

[0039] Based on the above-described method embodiments, this disclosure provides a configuration diagram for loading and booting a multi-version AS system to implement the technology of this disclosure, such as... Figure 4As shown, the FPGA is configured in AS loading mode, that is, MODE[2:1] is connected to ground through pull-down resistors, and MODE[0] is connected to the VCC power supply through pull-up resistors. The FPGA's reset pin RSTN, initialization completion flag pin INIT_FLAG_N, and configuration completion pin CFG_DONE are connected to the CPLD. The master controller and the CPLD communicate through the LVDS bus, and the CPLD and the FPGA communicate through the Local Bus. When the FPGA version needs to be switched, the master controller sends a command to the FPGA through the CPLD. Then, the FPGA startup process can be judged by monitoring the FPGA's INIT_FLAG_N and CFG_DONE. When an abnormality occurs, the FPGA can be reset through RSTN to restore it to normal.

[0040] As can be seen from the above embodiments, by sequentially deploying multiple functional versions (multiple configuration data) in a storage medium and constructing a standardized loading index through switching and jumping programs, it is possible to expand the functional capacity without replacing the hardware, realize the loading and startup of multiple versions of FPGA AS, and promote the evolution of FPGA towards "reconfigurability".

[0041] Based on the above method embodiments, this disclosure also provides a network device, the network device comprising: an FPGA and a storage medium connected to the FPGA, wherein the FPGA comprises: The receiving module is used to receive bitstream instructions for loading configuration data; The acquisition module is used to acquire the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction from the storage medium connected to the FPGA according to the bit stream instruction; The processing module is used to close the first bit stream switch, obtain the corresponding first application bit stream according to the first bit stream jump program, and load the first configuration data for the FPGA according to the first application bit stream.

[0042] The first bitstream instruction carries a bitstream flag that enables the first bitstream.

[0043] Specifically, the acquisition module is used to open and close the closed bit stream switch in the storage medium according to the bit stream instruction, and to acquire the first stream switch and the first stream jump program corresponding to the first stream identifier from the storage medium according to the first stream identifier carried by the bit stream instruction.

[0044] The acquisition module is further configured to acquire a default bit stream switch and a default bit stream jump program from the storage medium connected to the FPGA when the FPGA is powered on for the first time, and to close the default bit stream switch and acquire the corresponding default application bit stream according to the default bit stream jump program. The processing module is used to load default configuration data for the FPGA based on the default application bitstream.

[0045] Specifically, the configuration data of bit stream switches, bit stream jump programs, and application bit streams corresponding to different configuration data are stored sequentially in the storage medium.

[0046] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0047] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0048] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0049] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0050] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A method for loading configuration data into an FPGA, characterized in that, The method includes: The FPGA receives a bitstream command to load configuration data. According to the bit stream instruction, the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction are obtained from the storage medium connected to the FPGA. Close the first stream switch and obtain the corresponding first application bit stream according to the first stream jump procedure; The first configuration data is loaded for the FPGA based on the first application bitstream.

2. The method according to claim 1, characterized in that, The first bitstream instruction carries a bitstream flag that enables the first bitstream.

3. The method according to claim 2, characterized in that, The step of retrieving the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction from the storage medium connected to the FPGA according to the bit stream instruction includes: According to the bit stream command, open or close the closed bit stream switch in the storage medium; Based on the first stream identifier carried by the bit stream instruction, the first stream switch and the first stream jump program corresponding to the first stream identifier are retrieved from the storage medium.

4. The method according to claim 1, characterized in that, The method further includes: When the FPGA is powered on for the first time, the default bit stream switch and default bit stream jump program are retrieved from the storage medium connected to the FPGA. Close the default bitstream switch and obtain the corresponding default application bitstream according to the default bitstream jump procedure; The default configuration data is loaded for the FPGA based on the default application bitstream.

5. The method according to claim 1, characterized in that, The method further includes: The configuration data of the bit stream switches, bit stream jumpers and application bit streams corresponding to different configuration data are stored in the storage medium in sequence.

6. A network device, characterized in that, The network device includes: an FPGA and a storage medium connected to the FPGA, wherein the FPGA includes: The receiving module is used to receive bitstream instructions for loading configuration data; The acquisition module is used to acquire the first bit stream switch and the first bit stream jump program corresponding to the bit stream instruction from the storage medium connected to the FPGA according to the bit stream instruction; The processing module is used to close the first bit stream switch, obtain the corresponding first application bit stream according to the first bit stream jump program, and load the first configuration data for the FPGA according to the first application bit stream.

7. The network device according to claim 6, characterized in that, The first bitstream instruction carries a bitstream flag that enables the first bitstream.

8. The network device according to claim 7, characterized in that, The acquisition module is specifically used to open and close the closed bit stream switch in the storage medium according to the bit stream instruction, and to acquire the first stream switch and the first stream jump program corresponding to the first stream identifier from the storage medium according to the first stream identifier carried by the bit stream instruction.

9. The network device according to claim 6, characterized in that, The acquisition module is also used to acquire a default bit stream switch and a default bit stream jump program from the storage medium connected to the FPGA when the FPGA is powered on for the first time, and to close the default bit stream switch and acquire the corresponding default application bit stream according to the default bit stream jump program. The processing module is used to load default configuration data for the FPGA based on the default application bitstream.

10. The network device according to claim 6, characterized in that, The configuration data of the bit stream switches, bit stream jumpers and application bit streams corresponding to different configuration data are stored in the storage medium in sequence.

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