Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes: a display panel including pixels arranged in a first direction; a timing controller for generating output data based on the input image data; a data driver for converting the output data into a data signal and outputting the data signal to at least one output line; a data distributor for supplying a data signal to a data line connected to the display panel based on one of the first control signal and the second control signal supplied from the timing controller; and a luminance corrector for generating compensation data for correcting a pixel to which the data signal is supplied relatively late among the pixels.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0144342, filed with the Korean Intellectual Property Office on October 21, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to display devices and electronic devices including display devices. Background Technology

[0004] With the development of information technology, display devices have become increasingly important as a connection medium between users and information. Therefore, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0005] The display device's data driver supplies data signals to pixels, and the pixels emit light with brightness based on the data signals, thereby displaying an image. The data driver can supply data signals to the pixels via a data distributor. When the data distributor is included in the display device, the data driver can use fewer channels than the number of pixels relative to the horizontal line to supply data signals. When the emitted brightness of some pixels decreases according to the order in which data signals are supplied to multiple pixels, the quality of the image displayed by the display device may degrade.

[0006] The information disclosed in this related technology section is only intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art known to a person skilled in the art in this country. Summary of the Invention

[0007] The embodiments provide a display device and an electronic device in which the quality of an image displayed by the display device can be improved by compensating for brightness differences that unexpectedly occur due to charging deviations of data signals between multiple pixels.

[0008] According to an aspect of this disclosure, a display device is provided, comprising: a display panel including a plurality of pixels arranged in a first direction; a timing controller configured to generate output data based on input image data; a data driver configured to convert the output data into a data signal and output the data signal to at least one output line; a data distributor configured to supply the data signal to a data line connected to the display panel based on one of a first control signal and a second control signal supplied from the timing controller; and a brightness corrector configured to generate compensation data for correcting pixels among the plurality of pixels that are supplied with the data signal relatively late.

[0009] The pixel may include a first pixel, which includes a first_1 pixel configured to be supplied with a data signal corresponding to a first control signal and a first_2 pixel configured to be supplied with a data signal corresponding to a second control signal different from the first control signal.

[0010] The first and second pixels may include a pixel that is supplied with data signals relatively later than the first and second pixels.

[0011] The pixel may also include a second pixel arranged sequentially in the first direction, wherein, in a frame, the second pixel is configured to be supplied with data signals in the same direction as the direction in which the first pixel is configured to be supplied with data signals sequentially.

[0012] The second pixel may include: a second pixel 2_1, which is configured to be supplied with a data signal corresponding to the first control signal; and a second pixel 2_2, which is configured to be supplied with a data signal corresponding to the second control signal relatively later than the second pixel 2_1.

[0013] Pixel 1_1 and Pixel 2_1 can be adjacent to each other in a second direction that intersects with the first direction, wherein Pixel 1_2 and Pixel 2_2 are adjacent to each other in the second direction.

[0014] In the next frame after one frame, the first pixel and the second pixel can be configured to be supplied with data signals sequentially in the opposite direction to the direction in which the first pixel and the second pixel were configured to be supplied with data signals in that frame.

[0015] In the first mode, pixels 1_2 and 2_2 can be configured to be off, while in the second mode, which is different from the first mode, pixels 1_1 and 2_1 are configured to be off.

[0016] The brightness corrector can be configured to control the brightness of the light emitted by the pixel in the first mode to be substantially the same as that in the second mode.

[0017] The pixel may also include a second pixel arranged sequentially in the first direction, wherein, in a frame, the second pixel is configured to be supplied with data signals in a direction opposite to the direction in which the first pixel is configured to be supplied with data signals sequentially.

[0018] The second pixel may include: a 2_2 pixel configured to receive a data signal corresponding to a second control signal; and a 2_1 pixel configured to receive a data signal corresponding to a first control signal relatively later than the 2_2 pixel.

[0019] Pixel 1_1 and Pixel 2_1 can be adjacent to each other in a second direction that intersects with the first direction, wherein Pixel 1_2 and Pixel 2_2 are adjacent to each other in the second direction.

[0020] In the next frame after one frame, the first pixel and the second pixel can be configured to be supplied with data signals sequentially in the opposite direction to the direction in which the first pixel and the second pixel were configured to be supplied with data signals in that frame.

[0021] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor configured to provide input image data; and a display device configured to display an image based on the input image data and comprising: a display panel including a plurality of pixels arranged in a first direction; a timing controller configured to generate output data based on the input image data; a data driver configured to convert the output data into a data signal and output the data signal to at least one output line; a data distributor configured to supply the data signal to a data line connected to the display panel based on one of a first control signal and a second control signal supplied from the timing controller; and a brightness corrector configured to generate compensation data for correcting pixels among the plurality of pixels that are supplied with the data signal relatively late.

[0022] The pixel may include a first pixel, which includes a first_1 pixel configured to be supplied with a data signal corresponding to a first control signal, and a first_2 pixel configured to be supplied with a data signal corresponding to a second control signal different from the first control signal.

[0023] Pixel 1_2 can be configured to receive data signals relatively later than pixel 1_1.

[0024] The plurality of pixels may also include second pixels arranged sequentially in the first direction, and in a frame, the second pixels are configured to be supplied with data signals sequentially in the same direction as the direction in which the first pixels are configured to be supplied with data signals.

[0025] The second pixel may include: a 2_1 pixel configured to receive a data signal corresponding to the first control signal; and a 2_2 pixel configured to receive a data signal corresponding to the second control signal relatively later than the 2_1 pixel.

[0026] In the next frame after one frame, the first pixel and the second pixel can be configured to be supplied with data signals sequentially in the opposite direction to the direction in which the first pixel and the second pixel were configured to be supplied with data signals in that frame. Attached Figure Description

[0027] Embodiments will now be described more fully below with reference to the accompanying drawings. However, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being located “between” two elements, it can be the only element between those two elements, or there may be one or more intervening elements. The same reference numerals always refer to the same element.

[0029] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0030] Figure 2 This is a diagram illustrating pixels according to one or more embodiments of the present disclosure.

[0031] Figure 3 This is a diagram illustrating the arrangement structure of pixels according to one or more embodiments of the present disclosure.

[0032] Figure 4 This is a diagram illustrating a scan driver according to one or more embodiments of the present disclosure.

[0033] Figure 5 It is a diagram illustrating the sequence in which data signals are applied to pixels in a first region according to one or more embodiments of the present disclosure, and the waveforms of signals exchanged between the display panel and the data distributor.

[0034] Figure 6 This is a graph showing the brightness of the light output for each driving mode in the first region according to the comparative example.

[0035] Figure 7 This is a diagram showing the brightness of light output from a first region for each driving mode according to one or more embodiments of the present disclosure.

[0036] Figure 8 This is a diagram illustrating the sequence in which data signals are applied to pixels of a first region for each frame according to one or more embodiments of the present disclosure, and the first region as viewed by a user of a display device.

[0037] Figure 9 It is a diagram illustrating the sequence in which data signals are applied to pixels in a first region according to one or more embodiments of the present disclosure, and the waveforms of signals exchanged between the display panel and the data distributor.

[0038] Figure 10This is a graph showing the brightness of the light output for each driving mode in the first region according to the comparative example.

[0039] Figure 11 This is a diagram showing the brightness of light output from a first region for each driving mode according to one or more embodiments of the present disclosure.

[0040] Figure 12 This is a diagram illustrating the sequence in which data signals are applied to pixels of a first region for each frame according to one or more embodiments of the present disclosure, and the first region as viewed by a user of a display device.

[0041] Figure 13 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0042] Figure 14 It is shown that Figure 13 The electronic device shown is an example view of a smartphone.

[0043] Figure 15 It is shown that Figure 13 The electronic device shown is an example view of a tablet PC. Detailed Implementation

[0044] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey the aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or unnecessary for those skilled in the art to fully understand the aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their repeated description may be omitted.

[0045] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The use of the words “can,” “may,” or “may not” in describing embodiments corresponds to one or more embodiments of this disclosure.

[0046] Those skilled in the art will understand, in consideration of the full contents of this disclosure, that, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be technically associated and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0047] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description. The embodiments disclosed herein should not be construed as limited to the shapes of the elements, layers, or regions shown, but will include deviations in shape caused, for example, by manufacturing processes.

[0048] It should be understood that when a component, layer, area, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed" on, "connected to," or "(operationally, functionally, or communicatively) coupled to" another component, layer, area, or assembly, it can be directly formed on, directly connected to, or coupled to another component, layer, area, or assembly, or indirectly formed on, indirectly connected to, or coupled to another component, layer, area, or assembly, such that one or more intermediary components, layers, areas, or assemblies may exist. Furthermore, this can collectively mean direct or indirect connection or coupling, as well as integral or non-integral connection or coupling.

[0049] For example, when a layer, area, or component is referred to as "electrically connected" or "electrically coupled" to another layer, area, or component, it can be directly electrically connected or coupled to the other layer, area, or component, or one or more intermediary layers, areas, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, diodes, and / or the like. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, but may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression "connection" refers to an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component or directly on another component without any intermediate components.

[0050] Similarly, other expressions describing relationships between components, such as "between," "directly between," or "adjacent to" and "directly adjacent to," can be interpreted in a similar way. It should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between those two elements or layers, or there can be one or more intervening elements or layers.

[0051] For the purposes of this disclosure, expressions such as “at least one of…”, “any one of…”, or “one or more of…”, when following a list of elements, modify the entire list of elements, rather than individual elements within that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more items in the relevant list. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “a plurality of…”, “one of…”, and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements, rather than individual elements within that list. When “C to D” is recorded, unless otherwise specified, it means C or greater and D or less.

[0052] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, area, layer, segment, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, area, layer, or segment described below may be referred to as a second element, component, area, layer, or segment. The description of an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or sets. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first set),” “second category (or second set),” etc.

[0053] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0054] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It should also be understood that the terms “comprising,” “including,” “having,” “having,” “containing,” and “comprise”, when used in this specification, designate the presence of the recorded features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0055] When one or more embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description.

[0056] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation rather than as terms of degree and are intended to explain inherent deviations in measured or calculated values ​​as recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. “About” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of “may” in describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable by one of ordinary skill in the art. Other expressions may also be derived from those that omit “substantially.”

[0057] In some embodiments, well-known structures and arrangements may be described in conjunction with one or more functional blocks (e.g., block diagrams), units, and / or modules in the accompanying drawings to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, line connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein; alternatively, blocks, units, and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. Furthermore, each block, unit, and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing functions different from those functions of the dedicated hardware. Additionally, in some embodiments, blocks, units, and / or modules may be physically divided into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules without departing from the scope of this disclosure.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0059] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0060] refer to Figure 1 The display device 100 according to one or more embodiments of the present disclosure may include a display panel 110, a scan driver 120, a data driver 130, a timing controller 140, a data distributor 150, and a brightness corrector 160.

[0061] The timing controller 140 can control the overall operation of the display device 100. The timing controller 140 can receive input image data and control signals for each frame from an external processor. The timing controller 140 can generate output data by correcting the input image data and can supply the output data to the data driver 130. Furthermore, the timing controller 140 can control the scan driver 120, the data driver 130, and the data distributor 150 in response to control signals.

[0062] Data driver 130 can generate data signals corresponding to the output data and can provide these data signals to output lines OL1, OL2, ..., OLp (where p is a natural number of 3 or greater and m or less). For example, data driver 130 can sample the output data using a clock signal and supply data signals corresponding to the output data to output lines OL1 through OLp. Data driver 130 can supply multiple data signals to each of the output lines OL1 through OLp during one horizontal cycle.

[0063] Data distributor 150 can be connected to data driver 130 via output lines OL1 to OLp. Data distributor 150 can be connected to pixel PXij via data lines DL1, DL2, DL3, ... and DLm (m is a natural number of 4 or greater). Data distributor 150 may include multiple demultiplexers (or multiplexers).

[0064] Data distributor 150 can selectively connect output lines OL1 to OLp to data lines DL1 to DLm. In this example, under the control of timing controller 140, data distributor 150 can electrically connect each of output lines OL1 to OLp to two or more data lines (two or more of data lines DL1 to DLm) during one horizontal cycle. During one horizontal cycle, each of data lines DL1 to DLm can receive a data signal from the corresponding output line (one of output lines OL1 to OLp) to which it is connected.

[0065] A clock signal and a scan start signal from the timing controller 140 can be supplied to the scan driver 120. The scan driver 120 can, in response to the clock signal, supply enable scan signals (where n is a natural number greater than or equal to 4) to the scan lines SL1, SL2, SL3, ..., SLn while shifting the scan start signal. The enable scan signals can correspond to the gate on-state voltage of the transistors. In the example, when the enable scan signal is supplied to a P-type transistor, the enable scan signal can be set to a logic low voltage.

[0066] The display panel 110 may include pixels PXij connected to scan lines SL1 to SLn and data lines DL1 to DLm. Each pixel PXij may be connected to the corresponding data line and the corresponding scan line (i is a natural number greater than or equal to 1 and less than or equal to n, and j is a natural number greater than or equal to 1 and less than or equal to m). Pixel PXij may mean a pixel connected to the i-th scan line and the j-th data line.

[0067] A brightness corrector 160 can be connected to a data driver 130. The brightness corrector 160 can transmit compensation data CD to the data driver 130. The compensation data CD can be a signal used to control the brightness of at least one pixel PXij among a plurality of pixels PXij. For example, the data driver 130 can increase the brightness of at least one pixel PXij among a plurality of pixels PXij based on the transmitted compensation data CD. (See later...) Figures 5 to 7 This will be described in detail.

[0068] Figure 2 This is a diagram illustrating pixels according to one or more embodiments of the present disclosure. The present disclosure is not limited to... Figure 2 The pixel PXij shown is displayed on the display panel 110 (see [reference]). Figure 1 The () may include pixels having various circuit configurations known in the art.

[0069] refer to Figure 2 Display panel 110 (see) Figure 1 Pixel PXij can be publicly connected to a first power line VDDL and a second power line VSSL. A first drive power supply VDD can be supplied to the first power line VDDL, and a second drive power supply VSS can be supplied to the second power line VSSL. When pixel PXij is set to emit state, the first drive power supply VDD can be set to a voltage higher than the voltage of the second drive power supply VSS.

[0070] Pixel PXij according to one or more embodiments of this disclosure may be a pixel for emitting light of a first color. Pixels emitting light of a second or third color may be configured to be substantially the same as pixel PXij except for the light-emitting element LD, and therefore, repeated descriptions will be omitted.

[0071] For example, the first color can be one of red, green, and blue. The second color can be one of red, green, and blue that is not the first color, and the third color can be one of red, green, and blue that is not the first color or the second color. Alternatively, magenta, cyan, and yellow can be used instead of red, green, and blue as the first to third colors.

[0072] A pixel PXij may include multiple transistors T1 and T2, a storage capacitor Cst, and a light-emitting element LD.

[0073] The transistor is implemented using a P-type transistor (e.g., a PMOS transistor). However, those skilled in the art can use an N-type transistor (e.g., an NMOS transistor) to design pixel circuits with the same function.

[0074] The first electrode of the first transistor T1 can be connected to the first power line VDDL, and the second electrode of the first transistor T1 can be connected to the first electrode (or anode electrode) of the light-emitting element LD. Furthermore, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current supplied from the first power line VDDL to the second power line VSSL via the light-emitting element LD in response to the voltage of the first node N1. For example, a gate voltage Vgs can be applied to the gate electrode of the first transistor T1 through the first node N1. Therefore, the first transistor T1 can supply a current of a selected magnitude to the first electrode of the light-emitting element LD based on the magnitude of the gate voltage Vgs.

[0075] The first electrode of the second transistor T2 can be connected to the data line DLj, and the second electrode of the second transistor T2 can be connected to the first node N1. Furthermore, the gate electrode of the second transistor T2 can be connected to the scan line SLi. When an enable scan signal is supplied to the scan line SLi, the second transistor T2 can be turned on to electrically connect the data line DLj and the first node N1 to each other.

[0076] The first transistor T1 and the second transistor T2 can be implemented using P-type transistors and / or N-type transistors. In an embodiment, the first transistor T1 and the second transistor T2 can include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the first transistor T1 and the second transistor T2 can include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like.

[0077] A storage capacitor Cst can be connected between the first power line VDDL and the first node N1. The storage capacitor Cst can store the voltage of the first node N1.

[0078] The first electrode (or anode electrode) of the light-emitting element LD can be connected to the second electrode of the first transistor T1, and the second electrode (or cathode electrode) of the light-emitting element LD can be connected to the second power line VSSL. The light-emitting element LD can emit light of a first color with a selected brightness corresponding to the amount of current supplied from the first transistor T1.

[0079] In some embodiments, the gate voltage Vgs can be supplied via data lines DLj. The gate voltage Vgs may vary unintentionally depending on the order in which it is supplied to data lines DLj among the multiple data lines DL1 to DLm. Therefore, the amount of current supplied from the first transistor T1 may vary, and the emission brightness of the light-emitting element LD may vary. That is, correcting the emission brightness of the light-emitting element LD may be appropriate.

[0080] The light-emitting element (LD) can be configured as an organic light-emitting diode (OLED) or an inorganic light-emitting diode, such as a microLED (light-emitting diode) or a quantum dot LED. Furthermore, the LD can also be a device composed of a combination of organic and inorganic materials. Only one LD is shown. However, multiple sub-light-emitting elements can be connected in series, parallel, or series-parallel, and thus can replace the LD.

[0081] Figure 3 This is a diagram illustrating the arrangement structure of pixels according to one or more embodiments of the present disclosure.

[0082] refer to Figure 3 The display panel 110 may include multiple pixels. For example, the display panel 110 may include a first region A1, in which a first pixel PX1 and a second pixel PX2 are located on a first direction DR1. For ease of description, the pixels located in the first region A1 will be described primarily.

[0083] The first pixel PX1 may include a first pixel PX1_1 and a first pixel PX1_2 arranged sequentially in the first direction DR1. The second pixel PX2 may include a second pixel PX2_1 and a second pixel PX2_2 arranged sequentially in the first direction DR1. The first pixel PX1_1 and the second pixel PX2_1 may be adjacent to each other in the second direction DR2, which intersects with the first direction DR1, and the first pixel PX1_2 and the second pixel PX2_2 may be adjacent to each other in the second direction DR2. The third direction DR3 may be perpendicular to the plane defined by the first direction DR1 and the second direction DR2.

[0084] Each of the first pixel PX1 and the second pixel PX2 may include a red pixel PR, a green pixel PG, and a blue pixel PB. In some embodiments, the pixels may be arranged in a PenTile configuration. ® PenTile ® and Pentile ® (This is a registered trademark of Samsung Display Co., Ltd. of South Korea), but this disclosure is not limited thereto.

[0085] The red pixel PR, green pixel PG, and blue pixel PB can be arranged sequentially in the first direction DR1. For example, the red pixel PR, green pixel PG, and blue pixel PB can be arranged along scan lines SL1 to SL3 (or along the direction of the scan lines).

[0086] Each of the first pixel PX1 and the second pixel PX2 may include a single red pixel PR, a single green pixel PG, and a single blue pixel PB. For example, the first pixel PX1_1 may include the red pixel PR, the green pixel PG, and the blue pixel PB located between the first scan line SL1 and the second scan line SL2. The second pixel PX2_1 may include the red pixel PR, the green pixel PG, and the blue pixel PB located between the second scan line SL2 and the third scan line SL3.

[0087] Furthermore, the first and second pixels PX1_2 may include a red pixel PR, a green pixel PG, and a blue pixel PB located between the first scan line SL1 and the second scan line SL2. The second and second pixels PX2_2 may include a red pixel PR, a green pixel PG, and a blue pixel PB located between the second scan line SL2 and the third scan line SL3.

[0088] Pixels in the red pixel PR, green pixel PG, and blue pixel PB that are located on the same vertical line (e.g., in the same column) can be connected to the same data line. In the example, the red pixel PR of pixel 1_1 PX1_1 and the red pixel PR of pixel 2_1 PX2_1 that are located on the same vertical line can be connected to the same first data line DL1. However, this is merely illustrative and the present disclosure is not limited thereto. For example, any pixel in the red pixel PR, green pixel PG, and blue pixel PB that is located on the same vertical line can be connected to different data lines alternately.

[0089] Pixels in the red pixel PR, green pixel PG, and blue pixel PB that are on the same horizontal line (e.g., in the same row) can be connected to the same scan line. For example, the red pixel PR and the green pixel PG of pixel 1_1 PX1_1 can be connected to the same second scan line SL2. However, this is merely illustrative and the present disclosure is not limited thereto. For example, any pixel in the red pixel PR, green pixel PG, and blue pixel PB that are on the same horizontal line can be connected to different scan lines alternately.

[0090] Data distributor 150 may include a plurality of demultiplexers 152a, 152b, and 152c. Each of demultiplexers 152a, 152b, and 152c may transmit two data signals supplied to a corresponding line of a plurality of output lines OL to two data lines (e.g., two of data lines DL1 to DL6). That is, each of demultiplexers 152a, 152b, and 152c may be a 1:2 multiplexer. In some embodiments, this is merely illustrative and the disclosure is not limited thereto. For example, each of demultiplexers 152a, 152b, and 152c may transmit three data signals supplied to a corresponding line of a plurality of output lines OL to three data lines. That is, each of demultiplexers 152a, 152b, and 152c may be a 1:3 multiplexer. However, for ease of description, it will be described that each of demultiplexers 152a, 152b, and 152c is a 1:2 multiplexer. However, the following description also applies even when each of the demultiplexers 152a, 152b and 152c is a 1:3 multiplexer.

[0091] The first demultiplexer 152a can time-divide the data signal from the first output line OL1 and supply the time-divided data signal to the first data line DL1 and the second data line DL2. The second demultiplexer 152b can time-divide the data signal from the second output line OL2 and supply the time-divided data signal to the third data line DL3 and the fourth data line DL4. The third demultiplexer 152c can time-divide the data signal from the third output line OL3 and supply the time-divided data signal to the fifth data line DL5 and the sixth data line DL6.

[0092] Each of demultiplexers 152a, 152b, and 152c may include a first transistor M1 and a second transistor M2. The first transistor M1 of demultiplexers 152a, 152b, and 152c may be connected to output lines OL1 to OL3 and to first data lines DL1 to third data lines DL3, respectively. The first transistor M1 can be connected via timing controller 140 (see...). Figure 1 The first control signal CLA enables the transistor M1 to conduct. The first control signal CLA may have a gate on-state voltage, enabling the first transistor M1 to conduct. In the example, when the first transistor M1 is a P-type transistor, the first control signal CLA may have a logic low level.

[0093] The second transistor M2 of demultiplexers 152a, 152b, and 152c can be connected to output lines OL1 to OL3 and to the fourth data lines DL4 to the sixth data lines DL6, respectively. The second transistor M2 can be connected via timing controller 140 (see...). Figure 1 The second control signal CLB enables the transistor M2 to conduct. The second control signal CLB can have a gate on-state voltage, enabling the second transistor M2 to conduct. In the example, when the second transistor M2 is a P-type transistor, the second control signal CLB can have a logic low level.

[0094] Figure 4 This is a diagram illustrating a scan driver according to one or more embodiments of the present disclosure.

[0095] refer to Figure 4 The scan driver 120 according to one or more embodiments of the present disclosure may include stage circuits ST1, ST2, ST3, ST4, ST5, ...

[0096] Each of stage circuits ST1 to ST5 can be electrically connected to a scan line (one of scan lines SL1, SL2, SL3, SL4, and SL5). Each of stage circuits ST1 to ST5 can supply a scan signal GW (one of scan signals GW1, GW2, GW3, GW4, and GW5) to the scan line (one of scan lines SL1 to SL5) to which it is connected.

[0097] Clock signals CLK1 and CLK2 can be supplied to stage circuits ST1 to ST5. Each of the odd-numbered stage circuits ST1, ST3, ST5, ... can be supplied with the first clock signal CLK1 through the first input terminal and with the second clock signal CLK2 through the second input terminal. Each of the even-numbered stage circuits ST2, ST4, ... can be supplied with the second clock signal CLK2 through the first input terminal and with the first clock signal CLK1 through the second input terminal.

[0098] The first-stage circuit ST1 can be supplied with a start signal FLM and, in response to clock signals CLK1 and CLK2, can output a scan signal GW1 while shifting the start signal FLM. The carry signal (or scan signal GW1) output from the first-stage circuit ST1 can be supplied to the third-stage circuit ST3. That is, each of the odd-numbered stage circuits ST3, ST5, ... can receive a carry signal input from the previous odd-numbered stage circuit. However, this is merely illustrative, and the present disclosure is not limited thereto. For example, each of the odd-numbered stage circuits ST3, ST5, ... can receive a carry signal input from the previous stage circuit.

[0099] The second-stage circuit ST2 can be supplied with a start signal FLM and, in response to clock signals CLK1 and CLK2, can output a scan signal GW2 while shifting the start signal FLM. The carry signal (or scan signal GW2) output from the second-stage circuit ST2 can be supplied to the fourth-stage circuit ST4. That is, each of the even-numbered stage circuits ST4, ... can receive a carry signal input from the previous even-numbered stage circuit. However, this is merely illustrative, and the present disclosure is not limited thereto. For example, each of the even-numbered stage circuits ST4, ... can receive a carry signal input from the previous stage circuit.

[0100] Figure 5 It is a diagram illustrating the sequence in which data signals are applied to pixels in a first region according to one or more embodiments of the present disclosure, and the waveforms of signals exchanged between the display panel and the data distributor. Figure 6 This is a graph showing the brightness of the light output for each driving mode in the first region according to the comparative example. Figure 7 This is a diagram showing the brightness of light output from a first region for each driving mode according to one or more embodiments of the present disclosure.

[0101] refer to Figure 5 When a pixel located on the nth horizontal line is driven, each of the first control signal CLA and the second control signal CLB can supply a signal with the same waveform as when a pixel located on the (n+1)th horizontal line is driven. For example, when a pixel located on the nth horizontal line is driven, the first control signal CLA can have a high level during the first half of the first time interval 1H and a low level during the other half of the first time interval 1H. The first control signal CLA when a pixel located on the (n+1)th horizontal line is driven can have the same waveform as the first control signal CLA when a pixel located on the nth horizontal line is driven.

[0102] When a pixel located on the nth horizontal line is driven, the second control signal CLB may have a low level during the first half of the first time interval 1H and a high level during the other half of the first time interval 1H. The second control signal CLB when a pixel located on the (n+1)th horizontal line is driven may have the same waveform as the second control signal CLB when a pixel located on the nth horizontal line is driven.

[0103] Data signals can be supplied to a first pixel PX1 located on the nth horizontal line of the first region A1, and then to a second pixel PX2 located on the (n+1)th horizontal line. The first pixel PX1 can be configured to... (See...) Figure 3The data signals are received sequentially according to the order in which they are arranged on the surface. For example, after supplying a data signal to pixel 1_1 PX1_1, a data signal can be supplied to pixel 1_2 PX1_2.

[0104] Each of the first pixel PX1 and the second pixel PX2 can receive at least one of the multiple output lines OL1 to the third output line OL3 (see [link]). Figure 3 The data signal is transmitted. For example, depending on the grayscale level to be represented, the selected data signal can be transmitted through the first output line OL1 to the third output line OL3 (see...). Figure 3 The data is transmitted to pixels 1_1 (PX1_1) and 1_2 (PX1_2). As described above... Figure 2 As described in [the document], the first transistor T1 supplied to the 1_1 pixel PX1_1 (see [reference]). Figure 2 The gate voltage Vgs (see) Figure 2 The gate voltage Vgs supplied to the first transistor T1 of pixel 1_2 PX1_2 may differ from the gate voltage Vgs supplied to the first transistor T1 of pixel 1_2. In other words, the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 1_2 PX1_2 and the reference voltage Vref may be smaller than the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 1_1 PX1_1 and the reference voltage Vref. Therefore, the light-emitting element LD of pixel 1_2 PX1_2 (see...) Figure 2 It may emit light with a relatively low gray level (or brightness).

[0105] The second pixel PX2 located on the (n+1)th horizontal line can be determined according to the second pixel PX2 in the first direction DR1 (see...). Figure 3 The pixels are arranged in a specific order, and data signals are supplied sequentially. For example, pixel 2_1 PX2_1 can be driven by the first control signal CLA, and then pixel 2_2 PX2_2 can be driven by the second control signal CLB.

[0106] Each of the 2_1 pixel PX2_1 and the 2_2 pixel PX2_2 can receive at least one of the multiple output lines OL, from the first output line OL1 to the third output line OL3 (see...). Figure 3 The data signal is transmitted through the first output line OL1 to the third output line OL3, depending on the desired grayscale level. Figure 3 The data is transmitted to pixels 2_1 (PX2_1) and 2_2 (PX2_2). As described above... Figure 2As described above, the gate voltage Vgs supplied to the first transistor T1 of pixel 2_1 PX2_1 may differ from the gate voltage Vgs supplied to the first transistor T1 of pixel 2_2 PX2_2. In other words, the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 2_2 PX2_2 and the reference voltage Vref may be smaller than the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 2_1 PX2_1 and the reference voltage Vref. Therefore, the light-emitting element LD of pixel 2_2 PX2_2 may emit light with a relatively low grayscale level (or brightness).

[0107] refer to Figure 6 The pixels of the first region A1 can be driven in a first mode and a second mode. In the first mode, only the pixels in the column direction of the first region A1 can be driven. For example, in the first mode, pixel 1_1 PX1_1 and pixel 2_1 PX2_1 can be driven, while pixel 1_2 PX1_2 and pixel 2_2 PX2_2 can be de-driven (e.g., turned off).

[0108] Additionally, in the second mode, only the pixels in the column direction of the first region A1 can be driven. For example, in the second mode, the first pixel PX1_1 and the second pixel PX2_1 can be de-driven (e.g., turned off), while the first pixel PX1_2 and the second pixel PX2_2 can be driven.

[0109] According to the comparative example, the brightness of the first region A1 in the first mode and the brightness of the first region A1 in the second mode may be different from each other. For example, the brightness of the first region A1 in the first mode may be higher than the brightness of the first region A1 in the second mode. Therefore, the brightness of the first region A1 in the display panel 110 (see...) Figure 1 The quality of the displayed image may be degraded.

[0110] In some embodiments, the first region A1 can be driven using a full white mode FW. In other words, all pixels located in the first region A1 can be driven to represent white. Suitable for driving the first region A1 (or display panel 110 (see...) Figure 1 The power consumption may increase relatively. On the other hand, when driving the pixels located in the first region A1 in the first mode (or the second mode), the power consumption suitable for driving the first region A1 (or the display panel 110) may decrease relatively.

[0111] refer to Figure 7 The brightness of the first region A1 in the first mode can be the same as the brightness of the first region A1 in the second mode. For example, brightness corrector 160 (see...) Figure 1This can correct pixels 1_2 (PX1_2) and 2_2 (PX2_2). In other words, the luminance corrector 160 can generate compensation data CD (see...). Figure 1 ), which enables data drive 130 or data distributor 150 (see Figure 1 The brightness of the light represented by the first and second pixels PX1_2 and the second and second pixels PX2_2 can be increased, and the brightness of the light represented by the first and second pixels PX1_2 and the second and second pixels PX2_2 of the display panel 110 can also be increased. Therefore, the brightness of the first region A1 in the first mode is the same as the brightness of the first region A1 in the second mode, and the brightness of the light represented by the display panel 110 (see...) can be increased. Figure 1 The quality of the displayed image can be relatively improved.

[0112] Figure 8 This is a diagram illustrating the sequence in which data signals are applied to pixels of a first region for each frame according to one or more embodiments of the present disclosure, and the first region as viewed by a user of a display device.

[0113] refer to Figure 8 In the nth frame, which is a selected frame, a data signal can be applied to the first pixel PX1 located on the nth horizontal line, and then to the second pixel PX2 located on the (n+1)th horizontal line. In the nth frame, the brightness of the light output from the first pixel PX1_2 and the second pixel PX2_2 can be relatively low.

[0114] Data distributor 150 (see Figure 3 In the (n+1)th frame, the data distributor 150 can supply data signals to the first pixel PX1 and the second pixel PX2 in the opposite direction to the direction in which the data distributor 150 supplies data signals to the first pixel PX1 and the second pixel PX2 in the nth frame. For example, the data distributor 150 is based on the timing controller 140 (see...). Figure 1 The control signal can change the timing of the data signal supply and the order in which the data signals are supplied. Therefore, the data distributor 150 can change the direction in which it supplies data signals to the first pixel PX1 and the second pixel PX2 in the (n+1)th frame, and the brightness of the light output from the first pixel PX1_1 and the second pixel PX2_1 can be reduced.

[0115] Output from the first pixel PX1 and the second pixel PX2 and by the display device 100 (see...) Figure 1The brightness of the image viewed by the user can be uniform. For example, the data distributor 150 can alternately change the direction in which it supplies data signals to the first pixel PX1 and the second pixel PX2 for each frame. Therefore, it is possible to reduce or prevent the risk that the image quality will be degraded due to the difference in brightness between the light represented by one pixel of the first region A1 (e.g., pixel PX1_1 in the nth frame) and another pixel of the first region A1 (e.g., pixel PX1_2 in the nth frame), and to display the best image to the user of the display device 100.

[0116] Data distributor 150 can alternately change the direction in which it supplies data signals to the first pixel PX1 and the second pixel PX2 for each frame, and the emission brightness of at least one of the first pixel PX1 and the second pixel PX2 can be adjusted according to the brightness corrector 160 (see [link]). Figure 1 The brightness corrector 160 can correct the emitted brightness of pixels PX1_2 and PX2_2 in the nth frame, and can also correct the emitted brightness of pixels PX1_1 and PX2_1 in the (n+1)th frame. Therefore, the display device 100 (see [reference]) can correct the emitted brightness of pixels PX1_1 and PX2_1 in the (n+1)th frame. Figure 1 It can display images with relatively further improved quality.

[0117] Figure 9 It is a diagram illustrating the sequence in which data signals are applied to pixels in a first region according to one or more embodiments of the present disclosure, and the waveforms of signals exchanged between the display panel and the data distributor. Figure 10 This is a graph showing the brightness of the light output for each driving mode in the first region according to the comparative example. Figure 11 This is a diagram showing the brightness of light output from a first region for each driving mode according to one or more embodiments of the present disclosure.

[0118] refer to Figure 9 When a pixel located on the nth horizontal line is driven, and when a pixel located on the (n+1)th horizontal line is driven, each of the first control signal CLA and the second control signal CLB can supply a signal with a different waveform. For example, when a pixel located on the nth horizontal line is driven, the first control signal CLA can have a high level during the first half of the first time interval 1H and a low level during the other half of the first time interval 1H. On the other hand, when a pixel located on the (n+1)th horizontal line is driven, the first control signal CLA can have a low level during the first half of the first time interval 1H and a high level during the other half of the first time interval 1H.

[0119] When a pixel located on the nth horizontal line is driven, the second control signal CLB can be low during the first half of the first time interval 1H and high during the other half of the first time interval 1H. On the other hand, when a pixel located on the (n+1)th horizontal line is driven, the second control signal CLB can be high during the first half of the first time interval 1H and low during the other half of the first time interval 1H.

[0120] Data signals can be supplied to a first pixel PX1 located on the nth horizontal line of the first region A1', and then to a second pixel PX2 located on the (n+1)th horizontal line of the first region A1'. The first pixel PX1 can be used as a reference in the first direction DR1 (see...). Figure 3 The data signal is supplied to the first pixel PX1 sequentially according to the order in which the second pixel PX2 is arranged, and the data signal is supplied to the second pixel PX2 sequentially according to the order in which the second pixel PX2 is arranged in the opposite direction to the first direction DR1. For example, after the first pixel PX1_1 is supplied with a data signal, the first pixel PX1_2 can be supplied with a data signal. Thereafter, a data signal can be supplied to the second pixel PX2_2, and then a data signal can be supplied to the second pixel PX2_1.

[0121] Each of the first pixel PX1 and the second pixel PX2 can receive at least one of the multiple output lines OL1 to the third output line OL3 (see [link]). Figure 3 The data signal is transmitted. For example, depending on the grayscale level to be represented, the selected data signal can be transmitted through the first output line OL1 to the third output line OL3 (see...). Figure 3 The data is transmitted to pixels 1_1 (PX1_1) and 1_2 (PX1_2). As described above... Figure 2 As described in [the document], the first transistor T1 supplied to the 1_1 pixel PX1_1 (see [reference]). Figure 2 The gate voltage Vgs (see) Figure 2 The gate voltage Vgs supplied to the first transistor T1 of pixel 1_2 PX1_2 may differ from the gate voltage Vgs supplied to the first transistor T1 of pixel 1_2. In other words, the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 1_2 PX1_2 and the reference voltage Vref may be smaller than the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 1_1 PX1_1 and the reference voltage Vref. Therefore, the light-emitting element LD of pixel 1_2 PX1_2 (see...) Figure 2The light-emitting element (LD) of pixel 2_2 may emit light with a relatively low gray level (or brightness). Furthermore, the gate voltage Vgs supplied to the first transistor T1 of pixel 2_2 PX2_2 may differ from the gate voltage Vgs supplied to the first transistor T1 of pixel 2_1 PX2_1. In other words, the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 2_1 PX2_1 and the reference voltage Vref can be smaller than the absolute difference between the gate voltage Vgs of the first transistor T1 of pixel 2_2 PX2_2 and the reference voltage Vref. Therefore, the light-emitting element LD of pixel 2_1 PX2_1 (see...) Figure 2 It may emit light with a relatively low gray level (or brightness).

[0122] refer to Figure 10 The pixels of the first region A1' can be driven in a first mode and a second mode. In the first mode, pixels 1_1 PX1_1 and 2_2 PX2_2 can be driven, while pixels 1_2 PX1_2 and 2_1 PX2_1 can be de-driven. In the second mode, pixels 1_2 PX1_2 and 2_1 PX2_1 can be driven, while pixels 1_1 PX1_1 and 2_2 PX2_2 can be de-driven. According to a comparative example, the brightness of the first region A1' in the first mode and the brightness of the first region A1' in the second mode may be different from each other. For example, the brightness of the first region A1' in the first mode may be higher than the brightness of the first region A1' in the second mode. Therefore, the brightness of the first region A1' in the display panel 110 (see...) Figure 1 The quality of the displayed image may be relatively degraded.

[0123] refer to Figure 11 The brightness of the first region A1' in the first mode can be the same as the brightness of the first region A1' in the second mode. For example, brightness corrector 160 (see...) Figure 1 This can correct pixels 1_2 (PX1_2) and 2_1 (PX2_1). In other words, the luminance corrector 160 can generate compensation data CD, allowing the data driver 130 or data distributor 150 (see...) to... Figure 1 The brightness of the light represented by the first and second pixels PX1_2 and the second and first pixels PX2_1 of the display panel 110 can be increased. Therefore, the brightness of the first region A1' in the first mode is the same as the brightness of the first region A1' in the second mode, and the quality of the image displayed by the display panel 110 can be relatively improved.

[0124] Figure 12This is a diagram illustrating the sequence in which data signals are applied to pixels of a first region for each frame according to one or more embodiments of the present disclosure, and the first region as viewed by a user of a display device.

[0125] refer to Figure 12 In the nth frame, which is a selected frame, a data signal can be applied to the first pixel PX1 located on the nth horizontal line, and then to the second pixel PX2 located on the (n+1)th horizontal line. In the nth frame, the brightness of the light output from the first pixel PX1_2 and the second pixel PX2_1 may be relatively low.

[0126] Data distributor 150 (see Figure 3 In the (n+1)th frame, the data distributor 150 can supply data signals to the first pixel PX1 and the second pixel PX2 in the opposite direction to the direction in which the data distributor 150 supplies data signals to the first pixel PX1 and the second pixel PX2 in the nth frame. For example, the data distributor 150 is based on the timing controller 140 (see...). Figure 1 The control signal can change the timing of the data signal supply and the order in which the data signals are supplied. Therefore, in the (n+1)th frame, the data distributor 150 can change the direction in which it supplies data signals to the first pixel PX1 and the second pixel PX2, and the brightness of the light output from the first pixel PX1_1 and the second pixel PX2_2 can be reduced.

[0127] Output from the first pixel PX1 and the second pixel PX2 and by the display device 100 (see...) Figure 1 The brightness of the image viewed by the user can be uniform. For example, the data distributor 150 can alternately change the direction in which it supplies data signals to the first pixel PX1 and the second pixel PX2 for each frame. Therefore, it is possible to reduce or prevent the risk that the image quality will be degraded due to the difference in brightness between the light represented by one pixel of the first region A1' (e.g., the 1_1 pixel PX1_1 in the nth frame) and another pixel of the first region A1' (e.g., the 1_2 pixel PX1_2 in the nth frame), and to display the best image to the user of the display device 100.

[0128] The data distributor 150 can alternately change the direction in which it supplies data signals to the first pixel PX1 and the second pixel PX2 for each frame, and the emission brightness of at least one of the first pixel PX1 and the second pixel PX2 can be corrected by the brightness corrector 160. In other words, the brightness corrector 160 can correct the emission brightness of the first-second pixel PX1_2 and the second-first pixel PX2_1 in the nth frame, and can correct the emission brightness of the first-first pixel PX1_1 and the second-second pixel PX2_2 in the (n+1)th frame. Therefore, the display device 100 is able to display an image with a relatively further improved quality.

[0129] Figure 13 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Figure 14 It is shown that Figure 13 The electronic device shown is an example view of a smartphone. Figure 15 It is shown that Figure 13 The electronic device shown is an example view of a tablet PC.

[0130] Reference Figures 13 to 15 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 100 is shown. Furthermore, the electronic device 1000 may also include several ports capable of communicating with video cards, sound cards, memory cards, USB devices, and the like, or with other systems. In one or more embodiments, as... Figure 14 As shown, the electronic device 1000 can be implemented as a smartphone. In one or more embodiments, as Figure 15 As shown, the electronic device 1000 can be implemented as a tablet PC. However, this is merely illustrative, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smartpad, smartwatch, vehicle navigation system, computer monitor, laptop computer, head-mounted display device, or the like.

[0131] Processor 1010 can perform specific calculations or tasks. In some embodiments, processor 1010 can be a microprocessor, a central processing unit, an application processor, or the like. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, and the like. In some embodiments, processor 1010 can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0132] The memory device 1020 can store data suitable for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices, such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nanofloating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, or ferroelectric random access memory (FRAM) devices; and / or volatile memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, or mobile DRAM devices.

[0133] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), optical disc read-only memories (CD-ROMs), and the like.

[0134] I / O device 1040 may include input components (such as a keyboard, keypad, touchscreen, or mouse) and output components (such as a speaker or printer). In some embodiments, display device 1060 may be included in I / O device 1040.

[0135] The power supply 1050 can supply power suitable for the operation of the electronic device 1000. For example, the power supply 1050 can be a power management integrated circuit (PMIC).

[0136] The display device 1060 can display images corresponding to the visual information of the electronic device 1000. The display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but this disclosure is not limited thereto. The display device 1060 can be connected to other components via a bus or other communication links. Figure 13 The display device 1060 shown can be like Figure 1 The same as the display device 100 shown is described.

[0137] In the display device and electronic device according to the present disclosure, the quality of the image displayed by the display device can be improved by compensating for the brightness difference that occurs unexpectedly due to the charging deviation of the data signals between multiple pixels.

[0138] Embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, aspects described in connection with some embodiments may be used alone or in combination with aspects described in connection with other embodiments, unless expressly indicated otherwise, since the filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims, the functional equivalents of which are included therein.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels arranged in a first direction; The timing controller is configured to generate output data based on the input image data; A data driver is configured to convert the output data into a data signal and output the data signal to at least one output line; A data distributor is configured to supply the data signal to a data line connected to the display panel based on one of a first control signal and a second control signal supplied from the timing controller. as well as A brightness corrector is configured to generate compensation data for correcting pixels that are supplied with the data signal relatively late among the plurality of pixels.

2. The display device according to claim 1, wherein, The plurality of pixels includes a first pixel, and the first pixel includes: Pixel 1_1 is configured to be supplied with the data signal corresponding to the first control signal; and The first and second pixels are configured to be supplied with the data signal corresponding to the second control signal, which is different from the first control signal.

3. The display device according to claim 2, wherein, The first 1_2 pixel includes the pixel among the plurality of pixels that was supplied with the data signal relatively later than the first 1_1 pixel.

4. The display device according to claim 3, wherein, The plurality of pixels also includes second pixels arranged sequentially in the first direction, and In one frame, the second pixel is configured to be supplied with the data signal in the same direction as the first pixel is configured to be supplied with the data signal sequentially.

5. The display device according to claim 4, wherein, The second pixel includes: Pixel 2_1 is configured to be supplied with the data signal corresponding to the first control signal; and The 2_2 pixel is configured to be supplied with the data signal corresponding to the second control signal relatively later than the 2_1 pixel.

6. The display device according to claim 5, wherein, The first pixel and the second pixel are adjacent to each other in a second direction that intersects with the first direction, and Wherein, the first pixel and the second pixel are adjacent to each other in the second direction.

7. The display device according to claim 6, wherein, In the next frame following the first frame, the first pixel and the second pixel are configured to be supplied with the data signal sequentially in a direction opposite to the direction in which the first pixel and the second pixel were configured to be supplied with the data signal in the first frame.

8. The display device according to claim 6, wherein, In the first mode, the first and second pixels are configured to be off, and In a second mode, which differs from the first mode, the first pixel and the second pixel are configured to be off.

9. The display device according to claim 8, wherein, The brightness corrector is configured to control the brightness of the light emitted by the plurality of pixels in the first mode and in the second mode to be the same.

10. The display device according to claim 3, wherein, The plurality of pixels also includes second pixels arranged sequentially in the first direction, and In one frame, the second pixel is configured to be supplied with the data signal in the opposite direction to the direction in which the first pixel is configured to be supplied with the data signal sequentially.

11. The display device according to claim 10, wherein, The second pixel includes: Pixel 2_2 is configured to receive the data signal corresponding to the second control signal; and The 2_1 pixel is configured to receive the data signal corresponding to the first control signal relatively later than the 2_2 pixel.

12. The display device according to claim 11, wherein, The first pixel and the second pixel are adjacent to each other in a second direction that intersects with the first direction, and Wherein, the first pixel and the second pixel are adjacent to each other in the second direction.

13. The display device according to claim 12, wherein, In the next frame following the first frame, the first pixel and the second pixel are configured to be supplied with the data signal sequentially in a direction opposite to the direction in which the first pixel and the second pixel were configured to be supplied with the data signal in the first frame.

14. Electronic devices, including: The processor is configured to provide input image data; as well as A display device configured to display an image based on the input image, and includes: The display panel includes a plurality of pixels arranged in a first direction; A timing controller is configured to generate output data based on the input image data; A data driver is configured to convert the output data into a data signal and output the data signal to at least one output line; A data distributor is configured to supply the data signal to a data line connected to the display panel based on one of a first control signal and a second control signal supplied from the timing controller; and A brightness corrector is configured to generate compensation data for correcting pixels that are supplied with the data signal relatively late among the plurality of pixels.

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