Memory device, memory system, and method of manufacturing memory system

Abstract

The invention relates to a memory device, a memory system and a method of manufacturing the memory system. A memory device includes a two-transistor zero capacitor gain cell that is back-end-process compatible and includes a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

Description

Technical Field

[0001] This invention relates to memory devices, memory systems, and methods for manufacturing memory systems. Background Technology

[0002] The advantages of artificial intelligence (AI) in modern society enable a wide range of transformative new applications, from natural language processing to cancer diagnosis. However, today's AI algorithms are highly memory-constrained. Limited main memory capacity and bandwidth are bottlenecks, and moving data from DRAM is expensive.

[0003] High-speed, high-density, and energy-efficient memories are needed to help alleviate the current energy-intensive architectures used in AI accelerators. High-density and high-capacity on-chip memory can alleviate main memory capacity and bandwidth bottlenecks. Summary of the Invention

[0004] On the one hand, it provides a highly reliable, back-end process (BEOL) compatible dual-transistor zero-capacitor (2T0C) gain unit implementation for high-density embedded dynamic random access memory (eDRAM).

[0005] According to one or more embodiments, an apparatus is provided comprising a dual-transistor zero-capacitor gain unit in a back-end fabrication structure, the dual-transistor zero-capacitor gain unit including a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

[0006] According to another aspect of one or more embodiments, a system is provided, the system comprising: a front-end fabrication structure including a logic chip; and a back-end fabrication structure on the front-end fabrication structure, the back-end fabrication structure including a layer. The layer includes a dual-transistor zero-capacitor gain unit, the dual-transistor zero-capacitor gain unit including a read transistor and a write transistor electrically connected to the read transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

[0007] According to another aspect of one or more embodiments, a method is provided, the method comprising: fabricating a first structure including a logic chip using a front-end process; fabricating a first tier including a read transistor with a dual-transistor zero-capacitor gain unit using a back-end process; and fabricating a second tier on the first tier including a write transistor with a dual-transistor zero-capacitor gain unit using the back-end process. Attached Figure Description

[0008] The above and / or other aspects will become apparent and more readily understood from the following description of various embodiments in conjunction with the accompanying drawings, wherein:

[0009] Figure 1 A dual-transistor zero-capacitor (2T0C) gain unit according to some embodiments is shown;

[0010] Figure 2 Examples of semiconductor memory devices according to some embodiments are shown;

[0011] Figure 3 and Figure 4 The following are illustrated according to some embodiments. Figure 1 A hierarchical plan view of an exemplary layout of the 2T0C gain unit;

[0012] Figure 5 The following are illustrated according to some embodiments. Figure 1 A plan view of an exemplary composite layout of the 2T0C gain units;

[0013] Figures 6 to 9 The respective paths according to some embodiments are shown. Figure 5 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D' in the diagram;

[0014] Figure 10 and Figure 11 The following are illustrated according to some embodiments. Figure 1 A hierarchical plan view of an exemplary layout of the 2T0C gain unit;

[0015] Figure 12 and Figure 13 A cross-sectional view of an example of embedded dynamic random access memory (eDRAM) according to some embodiments is shown;

[0016] Figure 14 A cross-sectional view of an example of a semiconductor memory device according to some embodiments is shown;

[0017] Figure 15 A three-dimensional (3D) eDRAM with monolithic integration is shown according to some embodiments;

[0018] Figure 16 A 3D eDRAM with heterogeneous integration according to some embodiments is shown;

[0019] Figure 17 A flowchart is shown illustrating a method for manufacturing embedded dynamic random access memory (eDRAM) according to some embodiments; and

[0020] Figure 18A flowchart is shown illustrating a method for manufacturing embedded dynamic random access memory (eDRAM) according to some implementations. Detailed Implementation

[0021] As used herein, the phrase "at least one of A, B, or C" includes, within its scope, "A only," "B only," "C only," "A and B," "B and C," "A and C," and "A, B, and C." It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion, and do not indicate any particular order unless the order is specifically described. Therefore, without departing from the spirit and scope of this disclosure, the "first" element, component, region, layer, or portion described below may be referred to as a "second" element, component, region, layer, or portion. Note that the components in the accompanying drawings are not necessarily drawn to scale, and some components may be exaggerated for clarity of description.

[0022] This disclosure relates to a hybrid dual-transistor zero-capacitor (2T0C) gain unit, and more specifically, to an embedded dynamic random access memory (eDRAM) using the hybrid dual-transistor zero-capacitor (2T0C) gain unit.

[0023] 2T0C gain cell eDRAM is an on-chip memory option where transistors serve as both memory elements and amplification sources to provide gain. A 2T0C gain cell can be a cell used for data storage that uses two transistors and zero capacitors. Unlike single-transistor single-capacitor (1T1C) DRAM cells that rely on capacitors to store charge, 2T0C gain cells use the gate capacitance of the read transistor to store data. The advantages offered by 2T0C gain cells include suitability for 3D stacked memory architectures, lower power consumption, and easier manufacturing because no capacitors are required.

[0024] The write transistor in a 2T0C gain cell can use low off-state current, which can be achieved by oxide semiconductor (OS) based transistors. However, OS-based transistors may have reliability issues such as negative bias temperature instability (NBTI) and / or positive bias temperature instability (PBTI). NBTI can include mechanisms in which the p-channel degrades over time due to the application of a negative gate voltage at high temperatures. This degradation causes a shift in the transistor's threshold voltage and a reduction in drain current, which can lead to circuit failure. NBTI is affected by temperature, gate voltage, time, gate oxide thickness, device area, and geometry, and is primarily caused by interface traps generated at the silicon-oxide interface. Interface traps are generated when Si-H bonds break due to the applied electric field and the presence of holes. PBTI occurs when a positive voltage is applied to the transistor's gate at high temperatures. PBTI can cause a shift in the transistor's threshold voltage. This shift in threshold voltage can reduce the transistor's drive current and can increase leakage. PBTI is caused by electron trapping within the gate dielectric material. The trapped electrons generate a negative charge, which degrades the transistor's performance. Some OS-based transistor-based gain cell eDRAMs may degrade due to NBTI and PBTI stability issues.

[0025] To address the stability issues of OS-based transistors, a 2T0C gain unit can be implemented, using both OS-based and silicon-based transistors. However, high-temperature processing is used to fabricate the silicon-based transistors, making them not back-end process (BEOL) compatible but rather implemented in a front-end process (FEOL) structure that allows for high-temperature processing. The silicon-based transistors occupy additional FEOL area, resulting in area loss, which may be detrimental for high-density memories.

[0026] The various implementations described herein provide BEOL-compliant hybrid 2T0C gain cell implementations suitable for high-density eDRAM. The hybrid 2T0C gain cell comprises an OS-based write transistor and a polysilicon-based read transistor, wherein both the OS-based write transistor and the polysilicon-based read transistor suppress reliability issues and are fully BEOL-compliant. In some implementations, a polysilicon channel material can be used for the read transistor in the 2T0C gain cell to address reliability concerns. OS has some NBTI but significant PBTI. Compared to OS, polysilicon offers improved NBTI and PBTI performance. The write transistor in the 2T0C gain cell is less susceptible to PBTI, and due to its low leakage, it can be OS-based. The read transistor in the 2T0C gain cell is more susceptible to both NBTI and PBTI; therefore, using polysilicon for the read transistor can provide better performance than using OS, since high leakage is not a major concern for the read transistor. In some implementations, OS-based write transistors can be stacked with polysilicon-based transistors to form a stacked structure for 2TOC gain cells, wherein the stacked structure is a BEOL stacked structure compatible with BEOL technology. In some implementations, 2TOC gain cells can be stacked to form 3D embedded DRAM. Various implementations provide a high-density memory that is fully BEOL compatible and has improved reliability compared to memories using OS-based transistors and polysilicon-based transistors, thanks to the improved NBTI and PBTI performance of polysilicon.

[0027] Figure 1 An example of a 2TOC gain unit according to some embodiments is shown. In one embodiment, the 2TOC gain unit 1 may include a write transistor Tw and a read transistor Tr. The write transistor Tw has a gate electrically connected to a write word line (WWL), a first source / drain electrically connected to a write bit line (WBL), and a second source / drain electrically connected to a memory node (SN). The read transistor Tr has a gate electrically connected to the memory node SN, a first source / drain electrically connected to a read bit line (RBL), and a second source / drain electrically connected to a read write line (RWL). In one embodiment, the gate of the write transistor Tw may be directly connected to the WWL, the first source / drain of the write transistor Tw may be directly connected to the WBL, the second source / drain of the write transistor Tw may be directly connected to the memory node SN, the gate of the read transistor Tr may be directly connected to the memory node SN, the first source / drain of the read transistor Tr may be directly connected to the RBL, and the second source / drain of the read transistor Tr may be directly connected to the RWL.

[0028] In an implementation, the write transistor Tw can be an OS-based transistor. In another implementation, the OS-based transistor can also have an oxide semiconductor channel. For example, the oxide semiconductor can be selected from, but is not limited to, IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, or ZrZnSnO or combinations thereof.

[0029] In one implementation, the readout transistor Tr can be a polysilicon (poly-Si) based transistor that is BEOL compatible. In another implementation, the polysilicon-based transistor can have a polysilicon channel. In some implementations, the polysilicon-based transistor can be formed using low-temperature polysilicon (LTPS) compatible with BEOL processes, which use temperatures lower than the relatively high temperatures (e.g., greater than 1000°C) used in FEOL processes (e.g., less than about 400°C).

[0030] In an embodiment, the 2T0C gain unit 1 can be formed as part of a stacked structure. In an embodiment, the stacked structure can be a monolithically integrated BEOL stacked structure compatible with BEOL technology. For example, the write transistor Tw can be formed in a different tier from the read transistor Tr in the BEOL structure of the semiconductor memory device, as will be described in more detail below. For example, in the BEOL structure of the semiconductor memory device, multiple tiers can be formed using a low-temperature process (e.g., processing at temperatures below approximately 400°C). As used herein, a tier can represent a stacked functional block or active device plane, such as a transistor tier. In some contexts, a tier can correspond to a level or metal interconnect layer in the BEOL stacked structure. In an embodiment, the read transistor Tr can be formed in a first tier of multiple tiers, and the write transistor Tw can be formed in a second tier of multiple tiers. In an embodiment, the first tier can be co-bonded to the second tier. In an embodiment, the second tier including the write transistor Tw can be disposed on top of the first tier including the read transistor Tr. However, this is merely an example; in some implementations, the layer including the read transistor Tr can be positioned on top of the layer including the write transistor Tw. In one implementation, the read transistor Tr in the first layer can be electrically connected to the write transistor Tw in the second layer via a vertical electrical connection (such as a path) formed between the first and second layers. In another implementation, the storage node SN of the 2TOC gain unit 1 can be provided by the parasitic capacitance of the path between the first and second layers. A description of various layout structures of the 2TOC gain unit 1 is provided below in more detail.

[0031] In this implementation, during the write operation, the voltages on RWL and RBL can be zero, and the read transistor Tr can be turned off. A high potential can be applied to WWL, and the write transistor Tw can be turned on. A voltage can be applied to WBL, and the voltage can be written to SN. For example, in this implementation, if WBL is high, SN can be charged to a voltage close to the supply voltage (VDD), and if WBL is low, SN can be discharged to ground (VSS). The voltage at SN determines the gate voltage of the read transistor Tr. After the voltage is written to SN, a low potential can be applied to WWL to turn off the write transistor Tw. Therefore, charge remains at SN due to parasitic capacitance, and the voltage potential is stored by SN.

[0032] In one implementation, during a read operation, the WWL can be supplied with a low potential and the write transistor Tw can be turned off. In another implementation, a voltage such as VDD or VSS can be applied to the RBL to precharge it to that voltage (e.g., VDD or VSS), and the voltage potential in the SN can be read on the RWL. For example, if the SN stores a high voltage potential, the read transistor Tr is turned on and a first level can be sensed on the RWL; if the SN stores a low voltage potential, the read transistor remains off and a second level can be sensed on the RWL. While the above write and read operations are described with reference to a high potential used to turn on the write transistor Tw and the read transistor Tr, this description is merely illustrative, and in some implementations, a low potential can be used to turn on the write transistor Tw and the read transistor Tr.

[0033] Figure 2 A semiconductor memory device according to some embodiments is illustrated. According to one embodiment, the semiconductor memory device 100 may include a memory cell array (MCA), control logic 10, an RWL decoder 20, a WWL decoder 30, a precharger and write driver 40, multiple sense amplifiers (SAs) 50, and a column decoder 60. The MCA may include multiple memory cells (MCs) arranged in a grid structure. In one embodiment, each MC may be as follows: Figure 1 The 2T0C gain unit 1 is shown. In an embodiment, each MC can be disposed in a BEOL stack structure as described herein. Each MC can be electrically connected to the RWL decoder 20 via a corresponding RWL, to the WWL decoder 30 via a corresponding WWL, to the precharger and write driver 40 via a corresponding RBL and a corresponding WBL, and to a corresponding sense amplifier among the plurality of sense amplifiers 50 via a corresponding RBL. The plurality of sense amplifiers 50 can be electrically connected to the column decoder 60.

[0034] Control logic 10 can control each of the RWL decoder 20, WWL decoder 30, precharger and write driver 40, multiple SA 50 and column decoder 60 based on one or more control signals received from outside the semiconductor memory device 100.

[0035] RWL decoder 20 can receive read word line control signals from control logic 10, and based on the read word line control signals, can apply a voltage potential to one of the multiple RWLs.

[0036] The WWL decoder 30 can receive write word line control signals from the control logic 10, and based on the write word line control signals, can apply a voltage potential to one of the multiple WWLs.

[0037] The precharger and write driver 40 can receive a precharge control signal from the control logic 10, and based on the precharge control signal, can precharge one or more of the RBLs. The precharger and write driver 40 can also receive a write control signal from the control logic 10, and based on the write control signal, can enable or disable one of the WBLs.

[0038] Multiple SAs 50 can sense stored data from one of the SNs of the MC under the control of control logic 10, amplify the data, and output the data to column decoder 60. Column decoder 60 can receive column control signals from control logic 10 and can output data (DATA) to the outside of semiconductor memory device 100.

[0039] In this implementation, during the write operation of the memory cell (MC), control logic 10 can control the RWL decoder 20, as well as the precharger and write driver 40, to apply a low potential to the RWL and RBL of one of the MCs to turn off the read transistor Tr of the memory cell MC. Control logic 10 can control the WWL decoder 30 to apply a high potential to the WWL of the MC to turn on the write transistor Tw of the MC. Control logic 10 can control the precharger and write driver 40 to provide a high or low potential to the WBL of the MC according to the data to be written, and the voltage corresponding to the data to be written is stored in the storage node (SN). For example, in this implementation, if control logic 10 controls the precharger and write driver 40 to enable the WBL of the MC, the storage node SN of the memory cell MC is charged to VDD; if control logic 10 controls the precharger and write driver 40 to apply a low potential to the WBL, the SN of the MC is discharged to VSS. After writing the voltage to the SN of the MC, control logic 10 controls the WWL decoder 30 to apply a low potential to the WWL of the write transistor Tw of the MC. Therefore, the charge is retained at the SN of the MC due to the parasitic capacitance at the SN, and the voltage potential is stored at the SN of the MC. A write operation is described for one of the multiple MCs. However, the write operation for the remaining parts of the MC is the same, and its repeated description is omitted for brevity.

[0040] In this implementation, during the read operation of the MC, control logic 10 controls WWL decoder 30 to apply a low potential to the WWL of the MC, thereby turning off the write transistor Tw of the MC. Control logic 10 can also control RWL decoder 20 to apply VDD or VSS to the RWL of the MC, thereby pre-charging the RWL to VDD or VSS, and the data stored in the SN of the MC can be read from the RBL of the MC by the corresponding sense amplifier 50. For example, if the SN of the MC stores a high potential, the read transistor Tr is turned on and a first level can be sensed on the RBL by the sense amplifier 50; if the SN stores a low potential, the read transistor remains off and a second level can be sensed on the RBL by the sense amplifier 50. The read operation is described for one of the multiple MCs. However, the read operations for the remaining parts of the MC are the same, and for the sake of brevity, their repeated description is omitted.

[0041] Figure 3 and Figure 4 The following are illustrated according to some embodiments. Figure 1 A hierarchical plan view of an exemplary layout of the 2T0C gain unit. Figure 5 The following are illustrated according to some embodiments. Figure 1 A plan view of an exemplary composite layout of 2T0C gain units. For example, Figure 5 The combination is shown Figure 3 and Figure 4 The plan view shows the hierarchical composite layout. Figures 6 to 9 The respective paths according to some embodiments are shown. Figure 5 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'. (Refer to...) Figure 1 and Figure 6 In an embodiment, the 2T0C gain unit 1 can be formed as a stacked structure. In an embodiment, the stacked structure can be a BEOL stacked structure compatible with BEOL technology. For example, as described above, multiple layers can be formed in the BEOL structure of a semiconductor memory device. In an embodiment, each of the multiple layers can include an insulating layer and a transistor formed in the insulating layer. Each layer can be a transistor layer formed using a low-temperature process (e.g., using a BEOL process with a temperature below approximately 400°C).

[0042] In an implementation, multiple tiers may include a first tier (Tier 1) and a second tier (Tier 2). In an implementation, such as... Figure 3 and Figure 6As shown, Tier 1 may include an insulating layer 210, a gate line 220, a gate insulating layer 225, a first source / drain region 230, a second source / drain region 240, and a channel region 280. In an embodiment, the gate line 220, the first source / drain region 230, and the second source / drain region 240 may respectively correspond to Figure 1 The gate, first source / drain, and second source / drain of the read transistor Tr are shown.

[0043] In one embodiment, the gate line 220, the gate insulating layer 225, the first source / drain region 230, the second source / drain region 240, and the channel region 280 may be disposed in the insulating layer 210. In another embodiment, as... Figure 6 As shown, the channel region 280 can be disposed in the first direction D1 between the first source / drain region 230 and the second source / drain region 240. In an embodiment, as... Figure 7 As shown, the sidewalls of the channel region 280 in the second direction D2 may be surrounded by an insulating layer 210. As used in this specification, the first direction D1 may intersect the second direction D2, and the third direction D3 may be orthogonal to each of the first direction D1 and the second direction D2. The third direction D3 may also be referred to as the vertical direction.

[0044] In the implementation method, such as Figure 6 and Figure 7 As shown, gate line 220 can be disposed on channel region 280 in the third direction D3. In an embodiment, gate line 220 can completely cover channel region 280 in the third direction D3. Gate line 220 can be disposed above channel region 280, wherein gate insulating layer 225 is located between gate line 220 and channel region 280 in the third direction D3. In an embodiment, gate line 220 can contact gate insulating layer 225, and gate insulating layer 225 can contact channel region 280. Gate line 220, gate insulating layer 225, first source / drain region 230, second source / drain region 240, and channel region 280 can each extend in the second direction D2. In an embodiment, the top surfaces of gate line 220, first source / drain region 230, and second source / drain region 240 can be covered by insulating layer 210.

[0045] In the implementation method, such as Figure 8 As shown, the path 290 can extend through the insulating layer 210 to connect the second source / drain region 240 to the RBL. In some embodiments, the RBL can be directly connected to the second source / drain region 240 via the path 290. In some embodiments, a wiring pattern can be connected to the path 290 to connect to the RBL.

[0046] In one embodiment, the channel region 280 may be the region between the first source / drain 230 and the second source / drain 240, and may include an active region in which the gate line 220 of the read transistor Tr and the first and second source / drains 230 and 240 are formed. In another embodiment, the channel region 280 may include polysilicon. For example, the polysilicon may be low-temperature polysilicon compatible with a BEOL process, which uses a low temperature (e.g., less than about 400°C) lower than the relatively high temperatures (e.g., greater than 1000°C) used in a FEOL process.

[0047] Continue to refer to Figure 1 , Figure 4 and Figure 6 In this embodiment, Tier 2 can be disposed on Tier 1. For example, Tier 2 can be disposed on the insulating layer 210 of Tier 1. In this embodiment, Tier 2 can overlap Tier 1 on a third direction D3. In this embodiment, as... Figure 6 As shown, Tier 2 may include an insulating layer 310, a gate line 320, a gate insulating layer 325, a first source / drain region 330, a second source / drain region 340, and a channel region 380.

[0048] In the implementation, the gate line 320, the first source / drain region 330, and the second source / drain region 340 can respectively correspond to Figure 1 The gate, first source / drain, and second source / drain of the write transistor Tw are shown.

[0049] In one embodiment, the gate line 320, the gate insulating layer 325, the first source / drain region 330, the second source / drain region 340, and the channel region 380 may be disposed within the insulating layer 310. In another embodiment, as... Figure 7 As shown, the channel region 380 can be disposed in the second direction D2 between the first source / drain region 330 and the second source / drain region 340.

[0050] In the implementation method, such as Figure 7As shown, the gate line 320 can be disposed on the channel region 380 in the third direction D3. In an embodiment, the gate line 320 can completely cover the channel region 380 in the third direction D3. The gate line 320 can be disposed above the channel region 380, wherein the gate insulating layer 325 is disposed between the gate line 320 and the channel region 380 in the third direction D3. In an embodiment, the gate line 320 can contact the gate insulating layer 325, and the gate insulating layer 325 can contact the channel region 380. The gate line 320, the gate insulating layer 325, the first source / drain region 330, the second source / drain region 340, and the channel region 380 can each extend in the first direction D1. In an embodiment, as... Figure 7 As shown, the top surfaces of the gate line 320, the first source / drain region 330, and the second source / drain region 340 can be covered by the insulating layer 310. In an embodiment, as... Figure 7 As shown, the passage 360 ​​can extend through the insulating layer 310 to electrically connect the WWL to the gate line 320. In an embodiment, the WWL can be directly connected to the gate line 320 via the passage 360. Figure 7 As shown, the second source / drain region 340 of the write transistor Tw can be electrically connected to the gate line 220 of the read transistor Tr via a path 250. In an embodiment, the path 250 can be directly connected to the second source / drain region 340 of the write transistor Tw and directly connected to the gate line 220 of the read transistor Tr.

[0051] In the implementation method, such as Figure 9 As shown, the path 390 can extend through the insulating layer 310 to connect the first source / drain region 330 to the WBL. In some embodiments, the WBL can be directly connected to the first source / drain region 330 via the path 390. In some embodiments, a wiring pattern can be connected to the path 390 to connect to the WBL.

[0052] In an embodiment, the channel region 380 may include an oxide semiconductor. For example, the oxide semiconductor may be selected from, but is not limited to, IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, or ZrZnSnO or combinations thereof.

[0053] In one embodiment, the channel region 380 may be the region between the first source / drain 330 and the second source / drain 340, and may be included in the active region where the gate line 320 of the write transistor Tw is formed, as well as the first source / drain 330 and the second source / drain 340. In another embodiment, the channel region 380 may be perpendicular to the channel region 280 in a plan view, as shown in... Figure 3-5 The best one to see.

[0054] Figure 10 The following is illustrated according to some embodiments. Figure 5 The A-A' cut-off Figure 1 A hierarchical plan view of an exemplary layout of the 2T0C gain unit. Figure 11 It shows along Figure 5 The B-B' cut in Figure 1 A hierarchical plan view of an exemplary layout of the 2T0C gain unit. Figure 10 and Figure 11 Corresponding to Figure 6 and Figure 7 The cross-sectional view shown illustrates that, except for the component for the read transistor Tr being implemented in Tier 2 and the component for the write transistor Tw being implemented in Tier 1, in this implementation, Tier 2 may vertically overlap with Tier 1 on the third direction D3. Figure 10 In the same figures, the same reference numerals refer to Figure 6 The same components in Figure 11 In the same figures, the same reference numerals refer to Figure 7 The same components are used, and for the sake of brevity, repeated descriptions have been omitted.

[0055] like Figure 10 and Figure 11 As shown, the first source / drain region 230, the channel region 280, and the second source / drain region 240 of the read transistor Tr can be disposed on the insulating layer 310. Figure 6 Unlike the stacked structure, the path 250 can extend from the bottom of the gate line 220 of the read transistor Tr to the top of the second source / drain region 340 of the write transistor Tw.

[0056] In one implementation, multiple read transistors Tr can be arranged in Tier 1 and spaced apart from each other in both the first direction D1 and the second direction D2, and multiple write transistors Tw can be arranged in Tier 2 and spaced apart from each other in both the first direction D1 and the second direction D2, and stacked on top of the read transistors Tr, to achieve the arrangement. Figure 2The MC represents the mesh structure of the MCA. In other words, the read transistor Tr of Tier 1 and the write transistor Tw of Tier 2 can each be repeated in both the first direction D1 and the second direction D2 to achieve... Figure 2 The MCA shown.

[0057] Figure 12 The following is illustrated according to some embodiments. Figure 5 A cross-sectional view of an example eDRAM taken from A-A'. Figure 13 The following is illustrated according to some embodiments. Figure 5 A cross-sectional view of an example eDRAM taken from B-B'. Figure 12 and Figure 13 Corresponding to Figure 6 and Figure 7 The cross-sectional view shown in the figure. Figure 12 In the same figures, the same reference numerals refer to Figure 6 The same components in Figure 13 In the figures, the same reference numerals correspond to Figure 7 The same components are used, and for the sake of brevity, repeated descriptions are omitted. In an implementation, eDRAM may include multiple eDRAM layers stacked on the third-direction D3. For example, the multiple eDRAM layers may include a first eDRAM layer (eDRAM layer 1), a second eDRAM layer (eDRAM layer 2), ..., up to the Xth eDRAM layer (eDRAM layer X) stacked on the third-direction D3. Each of eDRAM layer 1, eDRAM layer 2, ... up to eDRAM layer X may include Figure 6-9 The BEOL stack structure is shown in the figure. For example, in an implementation, eDRAM layer 1 may include an implementation of... Figure 1 The Tier 1 implementation of the read transistor Tr shown Figure 1 The diagram shows Tier 2 of the write transistor Tw, and Tier 2 can be stacked on top of Tier 1 on third-direction D3, as shown. Figure 6 As shown. eDRAM layer 2 may include implementations Figure 1 The Tier 1 implementation of the read transistor Tr shown. Figure 1 The diagram shows Tier 2 of the write transistor Tw, and Tier 2 can be stacked on top of Tier 1, as shown. Figure 6 As shown. The eDRAM layer X may include implementations Figure 1 The Tier 1 implementation of the read transistor Tr shown Figure 1 The diagram shows Tier 2 of the write transistor Tw, and Tier 2 can be stacked on top of Tier 1, as shown. Figure 6As shown in the diagram. In some implementations, one or more of the multiple layers may have a BEOL stack structure, where Tier 1 is implemented. Figure 1 The write transistor Tw shown is implemented in Tier 2. Figure 1 The read transistor Tr shown is stacked on top of Tier 1, as follows. Figure 10 As shown in the diagram. In some implementations, each of the multiple eDRAM layers may have a BEOL stack structure, where Tier 1 implements the write transistor Tw and Tier 2 implements the read transistor Tr, with Tier 2 stacked on top of Tier 1, as shown in the diagram. Figure 10 As shown in the image.

[0058] In one implementation, multiple read transistors Tr can be arranged in Tier 1 and spaced apart from each other in both the first direction D1 and the second direction D2, and multiple write transistors Tw can be arranged in Tier 2 and spaced apart from each other in both the first direction D1 and the second direction D2, and stacked on top of the read transistors Tr, respectively, to achieve... Figure 2 The MCA shown.

[0059] In the implementation, each of eDRAM layer 1, eDRAM layer 2, ... to eDRAM layer X may respectively include a plurality of read transistors Tr arranged in Tier 1 and spaced apart from each other in both the first direction D1 and the second direction D2, and a plurality of write transistors Tw arranged in Tier 2 and spaced apart from each other in both the first direction D1 and the second direction D2 and stacked on top of the read transistors Tr, in order to achieve Figure 2 The 3D arrangement of memory cells MC in the MCA is shown.

[0060] Figure 14 A cross-sectional view of an example of a semiconductor memory device according to some embodiments is shown.

[0061] In one embodiment, the semiconductor memory device 1000 may include a first structure 500 and a second structure 600. The first structure 500 may have a top surface (SF), and the second structure 600 may be disposed on the top surface (SF) of the first structure 500. In one embodiment, the first structure 500 may be FEOL compatible, such that the first structure 500 can be manufactured using FEOL processes at temperatures, for example, greater than 1000°C. In another embodiment, the second structure 600 may be BEOL compatible, such that the second structure 600 can be manufactured using BEOL processes at temperatures, for example, less than about 400°C.

[0062] In one embodiment, the first structure 500 may include a substrate 510 and an upper dielectric layer 560 on top of the substrate 510. The substrate 510 may be a silicon substrate and may include a plurality of PMOS transistors 515 separated by shallow trench isolation (STI) structures 520 within the substrate 510. Each PMOS transistor 515 may include a P-well 530. The P-well may have N-doped regions 535 and 540 therein as the source and drain of the PMOS transistor 515. A gate 550 may be disposed on the P-well 530. A plurality of channels 570 may be disposed on the gate 550 and the N-doped well 535 to extend to the top surface SF of the FEOL structure 500. However, the first structure 500 is merely an example, and in some embodiments, the first structure 500 may be configured differently, as long as the first structure includes one or more transistors. In some embodiments, the one or more transistors may be included in one or more logic chips.

[0063] The second structure 600 may include a plurality of connection layers 610. One or more of the plurality of connection layers 610 may include an insulating layer 620, one or more wiring patterns 630, and one or more vias 640. The plurality of connection layers 610 may include a BEOL-compatible stacking structure as described above. For example, according to the above... Figure 1 and Figure 6 In this implementation, one of the multiple connection layers 610 may be included in Tier 1. Figure 1 The read transistor Tr is shown, and another of the multiple connection layers 610 can be included in Tier 2. Figure 1 The write transistor Tw is shown. In some embodiments, according to the above description... Figure 1 and Figure 10 In this implementation, one of the multiple connection layers 610 may be included in Tier 1. Figure 1 The write transistor Tw shown, and another of the multiple interconnect layers 610 may be included in Tier 2. Figure 1 The read transistor Tr is shown in the diagram.

[0064] According to various embodiments, a hybrid 2TOC gain cell may include an OS-based write transistor stacked with polysilicon-based read transistors to form a stacked structure, wherein the stacked structure is compatible with BEOL technology. In some embodiments, multiple hybrid 2TOC gain cells may be repeatedly stacked to form a monolithically integrated 3D embedded DRAM. These various embodiments provide high-density memory that is fully BEOL compatible and offers improved reliability.

[0065] Figure 15A system with monolithic integration according to some embodiments is illustrated. In one embodiment, system 1510 can implement 3D eDRAM. In another embodiment, system 1500 can be implemented as a single chip. In one embodiment, system 1500 may include a first structure 1510 and a second structure 1520. In another embodiment, the second structure 1520 may include, as per [the relevant information]... Figure 1 and Figure 6 Multiple 2T0C gain units are shown and described. For example, in some embodiments, the second structure 1520 may include information about... Figure 12 and Figure 13 A plurality of eDRAM structures spaced apart in a direction parallel to the first structure 1510 are shown and described. In an embodiment, the second structure 1520 may include a first eDRAM layer 1530 and a second eDRAM layer 1540. Although Figure 15 The diagram shows two eDRAM layers, but the implementation is not limited to two eDRAM layers. In some implementations, multiple eDRAM layers may be provided, such as... Figure 15 As shown by the dashed line in the image.

[0066] In one embodiment, the first structure 1510 may be an FEOL-compatible FEOL structure, such that the first structure 1510 can be manufactured using FEOL processes at temperatures, for example, greater than about 1000°C. The first structure 1510 may include one or more transistors. In another embodiment, the first structure 1510 may include one or more logic chips. For example, one or more logic chips may include one or more transistors.

[0067] In one embodiment, the second structure 1520 may be a BEOL-compatible BEOL structure, such that the second structure 1520 can be manufactured using a BEOL process at a temperature, for example, less than about 400°C. A first eDRAM layer 1530 may be on the top surface of the first structure 1510, and a second eDRAM layer 1540 may be on the top surface of the first eDRAM layer 1530. In another embodiment, the first eDRAM layer 1530 may be formed on the first structure 1510, and the second eDRAM layer 1540 may be formed on the first eDRAM layer 1530. In some embodiments, the first eDRAM layer 1530 may be co-bonded to the first structure 1510, and the second eDRAM layer 1540 may be co-bonded to the first eDRAM layer 1530.

[0068] In one embodiment, the first eDRAM layer 1530 may include a first layer 1533 on the first structure 1510 and a second layer 1536 on the first layer 1533. In another embodiment, as... Figure 15As shown, the first layer 1533 may be on the top surface of the first structure 1510. In an embodiment, the first layer 1533 may include a plurality of Tier 1s. For example, each Tier 1 may include approximately... Figure 1 and Figure 6 The readout transistor Tr is shown and described. In an embodiment, the plurality of Tier 1s of the first layer 1533 may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown below. Figure 15 As shown. In an embodiment, the second layer 1536 may include multiple Tier 2s on top of multiple Tier 1s of the first layer 1533. For example, each Tier 2 may include... Figure 1 and Figure 6 The write transistor Tw is shown and described. In an embodiment, multiple Tier 2s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, such as... Figure 15 As shown. In an embodiment, a combination of one of the plurality of Tier 1s in the first layer 1533 and one of the plurality of Tier 2s in the second layer 1536 can correspond to the formation in Figure 6 The stacked structure shown Figure 1 The first eDRAM layer 1530 may include a plurality of 2TOC gain units 1 spaced apart from each other in a direction parallel to the top surface of the first structure 1510. Although Figure 15 The 2T0C gain unit 1 of the first eDRAM layer 1530 is shown to have according to Figure 6 The stacked structure is merely an example; in some implementations, the system may include... Figure 10 The 2T0C gain unit 1 in the stacked structure shown and described.

[0069] The second eDRAM layer 1540 may include a first layer 1543 and a second layer 1546. The first layer 1543 of the second eDRAM layer 1540 may be on top of the second layer 1536 of the first eDRAM layer 1530. In an embodiment, as shown... Figure 15 As shown, the first layer 1543 of the second eDRAM layer 1540 may be on the top surface of the second layer 1536 of the first eDRAM layer 1530. In an embodiment, the first layer 1543 may include a plurality of Tier 1s. For example, each Tier 1 may include approximately... Figure 1 and Figure 6 The readout transistor Tr is shown and described. In an embodiment, the plurality of Tier 1s of the first layer 1543 may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, as shown below. Figure 15As shown. In an embodiment, the second layer 1546 may include multiple Tier 2s on top of multiple Tier 1s of the first layer 1543. For example, each Tier 2 may include... Figure 1 and Figure 6 The write transistor Tw is shown and described. In an embodiment, multiple Tier 2s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, such as... Figure 15 As shown. In an embodiment, a combination of one of the Tier 1 components of the first layer 1543 and one of the plurality of Tier 2 components of the second layer 1546 can correspond to the components formed in... Figure 6 The stacked structure shown Figure 1 The second eDRAM layer 1540 may include a plurality of 2TOC gain units 1 spaced apart from each other in a direction parallel to the top surface of the first structure 1510. Although Figure 15 The 2T0C gain unit 1 in the second eDRAM layer 1540 is shown to have according to Figure 6 The stacked structure is merely an example; in some implementations, the system may include... Figure 10 The 2T0C gain unit 1 in the stacked structure shown and described.

[0070] As described above, in one embodiment, the first eDRAM layer 1530 may be co-bonded to the first structure 1510, such that the first layer 1533 is co-bonded to the first structure 1510. In another embodiment, the second eDRAM layer 1540 may be co-bonded to the first eDRAM layer 1530, such that the first layer 1543 of the second eDRAM layer 1540 is co-bonded to the second layer 1536 of the first eDRAM layer 1530.

[0071] Figure 16 A system with heterogeneous integration according to some embodiments is illustrated. In one embodiment, system 1600 may be a 3D eDRAM and may include a first chip (Chiplet-1) 1610 and a plurality of second chips (Chiplet-2) 1620. In one embodiment, Chiplet-1 1610 may be a FEOL structure fabricated in a FEOL process. In one embodiment, Chiplet-1 1610 may include one or more transistors. In one embodiment, Chiplet-1 1610 may include one or more logic chips. For example, one or more logic chips may include one or more transistors.

[0072] In one embodiment, the plurality of Chiplet-2 1620s may be manufactured separately from the Chiplet-1 1610. In another embodiment, each of the plurality of Chiplet-2 1620s may be a BEOL structure manufactured in a BEOL process. In yet another embodiment, each of the plurality of Chiplet-2 1620s may be manufactured separately from the Chiplet-1 1610. In yet another embodiment, each of the plurality of Chiplet-2 1620s may be manufactured separately from each other.

[0073] In one embodiment, a plurality of Chiplet-2 1620s may be arranged on Chiplet-1 1610 in a first row 1624 and may be spaced apart in a first direction parallel to the top surface of Chiplet-1 1610. In another embodiment, the plurality of Chiplet-2 1620s may be further arranged in a second direction parallel to the top surface of Chiplet-1 1610 and intersecting the first direction, and may be spaced apart from each other in the second direction. In yet another embodiment, each of the plurality of Chiplet-2 1620s in the first row 1624 may have a hybrid engagement 1630 with Chiplet-1 1610.

[0074] In some implementations, multiple Chiplet-2 1620s may be arranged in the second row 1627 to correspond respectively to multiple Chiplet-2 1620s in the first row 1624, and may be spaced apart in a first direction and / or a second direction. In other words, multiple Chiplet-2 1620s may be stacked upwards in a third direction orthogonal to the first and second directions to form a 3D eDRAM structure. In an implementation, multiple Chiplet-2s in the second row 1627 may each have a hybrid bonding 1630 with their counterparts in the multiple Chiplet-2 1620s in the first row 1624, thereby forming a 3D eDRAM with heterogeneous integration.

[0075] In an implementation, each of the plurality of Chiplet-2 1620s may include Figure 1 and Figure 6 The 2T0C gain unit 1 shown can therefore include Tier 1 with a read transistor Tr and Tier 2 with a write transistor Tw on Tier 1. Although Figure 16 A Chiplet-2 1620 with a 2T0C gain unit 1 is shown, which has about Figure 6The stacked structure shown and described is merely an example; in some embodiments, the Chiplet-21620 may include a 2TOC gain unit 1, which has regarding Figure 10 The stacked structure is shown and described.

[0076] Figure 17 A flowchart illustrating a method for manufacturing eDRAM according to some embodiments is shown. In one embodiment, the method for manufacturing eDRAM may include operations S10 to S30. In another embodiment, the method for manufacturing eDRAM may be used to manufacture... Figure 15 The example shown is a monolithically integrated 3D eDRAM.

[0077] In operation S10, the first structure can be manufactured. For example, in one embodiment, the first structure can be manufactured using the FEOL process. The FEOL process can be performed at a temperature greater than approximately 1000°C. The first structure can correspond to... Figure 14 The first structure 500 shown Figure 15 The first structure 1510 shown or Figure 16 The Chiplet-1. In an embodiment, the first structure may include one or more transistors. In an embodiment, the first structure may include one or more logic chips. For example, one or more logic chips may include one or more transistors.

[0078] In operation S20, Tier 1 can be manufactured on the first structure. In this embodiment, Tier 1 can be manufactured using the BEOL process. The BEOL process can be performed at a temperature below approximately 400°C. For example, Tier 1 can be related to... Figure 1 and Figure 6 The Tier 1 shown and described or about Figure 1 and Figure 10 Tier 1 is shown and described. In some implementations, Tier 1 may correspond to... Figure 15 The first layer 1533 shown may include multiple Tier 1s, and the manufacture of Tier 1s may include... Figure 15 A plurality of Tier 1s of a first layer 1533 are formed on the top surface of the first structure 1510. In an embodiment, the plurality of Tier 1s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, such as... Figure 15 As shown.

[0079] In operation S30, Tier 2 can be manufactured on Tier 1. In this embodiment, Tier 2 can be manufactured using the BEOL process. The BEOL process can be performed at temperatures below approximately 400°C. For example, Tier 2 can be related to... Figure 1 and Figure 6 The Tier 2 shown and described or about Figure 1 and Figure 10 Tier 2 is shown and described. In some implementations, Tier 2 may correspond to... Figure 15 The second layer 1536 shown includes multiple Tier 2s respectively on multiple Tier 1s of the first layer 1533, and manufacturing Tier 2s may include manufacturing multiple Tier 2s respectively on multiple Tier 1s, such as... Figure 15 As shown. In an embodiment, multiple Tier 2s may be spaced apart from each other in a direction parallel to the top surface of the first structure 1510, such as... Figure 15 As shown.

[0080] Figure 18 A flowchart illustrating a method for manufacturing eDRAM according to some embodiments is shown. In some embodiments, the method for manufacturing eDRAM may include operations S110 to S130.

[0081] In operation S110, a first core can be manufactured. In an embodiment, the first core may correspond to... Figure 16 Chiplet-1 in the process. The first chip can be manufactured using the FEOL process. The FEOL process can be performed at temperatures above approximately 1000°C.

[0082] In operation S120, a second core can be manufactured. In an embodiment, the second core can correspond to... Figure 16 The second chip, Chiplet-2, can be manufactured as a separate chip from the first chip. In embodiments, the second chip can be manufactured in a BEOL process. The BEOL process can be performed at temperatures below approximately 400°C. For example, in some embodiments, the second chip may include a Tier 1 with a read transistor Tr and a Tier 2 with a write transistor Tw, and may correspond, for example, to... Figure 16 The Chiplet-2 is shown and described. In some embodiments, the manufacture of the second chip may include manufacturing multiple Chiplet-2 chips, as described above. Figure 16 The subject of discussion.

[0083] In operation S130, the first and second chips can be bonded together by hybrid bonding to form a 3D eDRAM with heterogeneous integration.

[0084] Exemplary Implementation

[0085] Refer to the following numbered clauses for descriptions of various exemplary implementations.

[0086] Clause 1, a hybrid 2T0C gain cell eDRAM comprising a layer stack including a first layer and a second layer, wherein one of the first and second layers in the hybrid 2T0C gain cell eDRAM includes an oxide semiconductor as a write transistor and the other of the first and second layers includes polysilicon as a read transistor.

[0087] Clause 2, a hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the first and second layers are repeated to form a 3D 2T0C gain cell eDRAM.

[0088] Clause 3, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the first layer comprises oxide semiconductor as write transistors and the second layer comprises polysilicon as read transistors.

[0089] Clause 4, a hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the first layer comprises polysilicon as read transistors and the second layer comprises oxide semiconductors as write transistors.

[0090] Clause 5, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes indium oxide.

[0091] Clause 6, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes indium tin oxide.

[0092] Clause 7, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes indium gallium zinc oxide.

[0093] Clause 8, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes tin oxide.

[0094] Clause 9, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes zinc oxide.

[0095] Clause 10, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes Si-doped indium oxide.

[0096] Clause 11, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes Ge-doped indium oxide.

[0097] Clause 12, the hybrid 2T0C gain cell eDRAM as described in Clause 1, wherein the oxide semiconductor includes W-doped indium oxide.

[0098] Clause 13, a structure comprising a first layer and a second layer, wherein the second layer is stacked on top of the first layer and connected to a memory node, the first layer comprising read word lines, read bit lines, a memory node, gate metal, and transistor channels, and the second layer comprising write word lines, write bit lines, a memory node, gate metal, and transistor channels, the transistor channels in the first layer comprising polysilicon, the transistor channels in the second layer comprising oxide semiconductor, and the first layer and the second layer transistor channels being perpendicular to each other.

[0099] Clause 14, the structure as described in Clause 13, wherein the first and second levels are repeated to form 3D 2TOCeDRAM.

[0100] Clause 15, a logic chip including a BEOL, the BEOL comprising the structure described in Clause 13, wherein both the first level and the second level are manufactured and repeated.

[0101] Clause 16, a logic chip comprising the structure described in Clause 13, wherein both the first and second layers are manufactured as separate dies and integrated with the logic chip via 3D heterogeneous integration.

[0102] Clause 17, a structure comprising a first layer and a second layer, wherein the second layer is stacked on top of the first layer and connected to a memory node, wherein the first layer includes write word lines, write bit lines, a memory node, gate metal, and transistor channels, wherein the second layer includes read word lines, read bit lines, a memory node, gate metal, and transistor channels, wherein the transistor channels in the first layer comprise oxide semiconductors, wherein the transistor channels in the second layer comprise polysilicon, and wherein the transistor channels of the first and second layers are perpendicular to each other.

[0103] Clause 18, the structure as described in Clause 17, wherein the first and second levels are repeated to form 3D 2TOCeDRAM.

[0104] Clause 19, a logic chip including a BEOL, the BEOL comprising the structure described in Clause 17, wherein both the first level and the second level are manufactured and repeated.

[0105] Clause 20, a logic chip comprising the structure described in Clause 17, wherein both the first and second layers are manufactured as separate dies and integrated with the logic chip via 3D heterogeneous integration.

[0106] Clause 21, a hybrid 2T0C gain cell eDRAM, comprising a stack of layers including a first layer and a second layer, wherein one of the first layer and the second layer comprises an oxide semiconductor, and the other of the first layer and the second layer comprises polysilicon.

[0107] Clause 22, a hybrid 2T0C gain cell eDRAM as described in Clause 21, wherein the first and second layers are repeated to form a 3D 2T0C gain cell eDRAM.

[0108] Clause 23, a structure comprising a first layer and a second layer, wherein the second layer is stacked on top of the first layer and connected to a memory node, wherein the first layer includes read word lines, read bit lines, a memory node, gate metal, and a transistor channel, and wherein the second layer includes write word lines, write bit lines, a memory node, gate metal, and a transistor channel, wherein the transistor channel in the first layer comprises polysilicon, wherein the transistor channel in the second layer comprises oxide semiconductor, and wherein the components of the first layer and the second layer are perpendicular to each other.

[0109] Clause 24, the structure as described in Clause 23, wherein the first and second levels are repeated to form 3D 2TOCeDRAM.

[0110] Clause 25, the structure described in Clause 23 or 24, wherein both the first level and the second level are manufactured and repeated in the BEOL of the logic chip.

[0111] Clause 26, the structure of any one of Clauses 23-25, wherein both the first and second tiers are manufactured as separate chips and integrated with the logic chip via 3D heterogeneous integration.

[0112] Clause 27, a hybrid dual-transistor zero-capacitor 2T0C gain unit, includes a back-end process (BEOL) stack structure comprising a first level and a second level stacked on the first level, wherein one of the first and second levels includes a write transistor having an oxide semiconductor channel, and the other of the first and second levels includes a read transistor having a polysilicon channel.

[0113] Clause 28, the hybrid 2T0C gain unit as described in Clause 27, wherein the oxide semiconductor channel is perpendicular to the polysilicon channel in a plan view.

[0114] Clause 29, the hybrid 2T0C gain unit according to Clause 27 or 28, wherein the write transistor in one of the first and second levels is connected via a storage node to the read transistor in the other of the first and second levels.

[0115] Clause 30, a hybrid 2T0C gain unit according to any one of Clauses 27 to 29, wherein the second level overlaps perpendicularly with the first level.

[0116] Clause 31, a hybrid 2T0C gain unit according to any one of Clauses 27 to 30, wherein the first level includes a write transistor and the second level includes a read transistor.

[0117] Clause 32, a hybrid 2T0C gain unit according to any one of Clauses 27 to 31, wherein the first level includes a read transistor and the second level includes a write transistor.

[0118] Clause 33, a hybrid 2T0C gain cell according to any one of Clauses 27 to 32, wherein the read transistor includes a gate, a first source / drain and a second source / drain, and the write transistor includes a gate, a first source / drain and a second source / drain, wherein the gate of the read transistor is electrically connected to the second source / drain of the write transistor.

[0119] Clause 34, a hybrid 2T0C gain cell according to any one of Clauses 27 to 33, wherein the gate line of the read transistor is connected via a path to the second source / drain region of the write transistor.

[0120] Clause 35, a hybrid 2T0C gain cell according to any one of Clauses 27 to 34, wherein a portion of the gate line of the read transistor in the first level vertically overlaps with a portion of the second source / drain region of the write transistor in the second level, and a path vertically connects said portion of the gate line of the read transistor to said portion of the second source / drain region of the write transistor.

[0121] Clause 36, a hybrid 2T0C gain cell according to any one of Clauses 27 to 35, wherein the gate of the write transistor is electrically connected to the write word line, the first source / drain of the write transistor is electrically connected to the write bit line, the first source / drain of the read transistor is electrically connected to the read word line, and the second source / drain of the read transistor is electrically connected to the read bit line.

[0122] Clause 37, a hybrid 2T0C gain cell according to any one of Clauses 27 to 36, wherein the hybrid 2T0C gain cell stores data at a storage node, the storage node being the gate of the read transistor and the second source / drain of the write transistor.

[0123] Clause 38, a hybrid 2T0C gain unit according to any one of Clauses 27 to 37, wherein the first level is a first core and the second level is a second core, the first core being hybridly bonded to the second core.

[0124] Clause 39, a hybrid 2T0C gain unit according to any one of Clauses 27 to 38, wherein the oxide semiconductor channel comprises at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.

[0125] Item 40, an embedded dynamic random access memory (eDRAM) including a back-end process (BEOL) structure, the BEOL structure including multiple layers, wherein each layer includes a first level and a second level stacked on the first level to vertically overlap the first level, wherein one of the first level and the second level includes a write transistor having an oxide semiconductor channel, and the other of the first level and the second level includes a read transistor having a polysilicon channel.

[0126] Clause 41, the eDRAM as described in Clause 40, further includes a front-end process (FEOL) structure, the front-end process (FEOL) structure including a logic chip, wherein the logic chip is electrically connected to a write transistor and a read transistor.

[0127] Clause 42, eDRAM according to any one of Clauses 40 to 41, wherein the oxide semiconductor channel is perpendicular to the polysilicon channel in the plan view.

[0128] Clause 43, eDRAM according to any one of Clauses 40 to 42, wherein the second level includes a read transistor and the first level includes a write transistor.

[0129] Clause 44, eDRAM according to any one of Clauses 40 to 43, wherein the first level includes a read transistor and the second level includes a write transistor.

[0130] Clause 45, an embedded dynamic random access memory (eDRAM) comprising: a front-end process (FEOL) structure including one or more transistors formed on a substrate; a back-end process (BEOL) structure disposed on the top surface of the FEOL structure, the BEOL structure including a first level, a second level stacked on the first level to perpendicularly overlap the first level, and a path connecting the first level and the second level, wherein the first level includes a first insulating layer and a read transistor of a dual-transistor zero-capacitance (2T0C) gain unit disposed in the first insulating layer, the read transistor including a first source disposed in a first direction. The second layer includes a drain region, a polysilicon channel region, a second source / drain region, and a gate line disposed on top of the polysilicon channel region and extending in a second direction perpendicular to the first direction. The second layer includes a second insulating layer and a write transistor of a 2TOC gain unit disposed in the second insulating layer. The write transistor includes a first source / drain region, an oxide semiconductor channel region, and a second source / drain region disposed in the second direction, and a gate line disposed on the oxide semiconductor channel region and extending in the first direction. The path electrically connects the gate line of the read transistor in the first layer to the second source / drain region of the write transistor in the second layer.

[0131] Clause 46, the eDRAM according to Clause 45, wherein the first source / drain region of the read transistor in the first level is electrically connected to the read bit line, the second source / drain region of the read transistor in the first level is electrically connected to the read word line, and wherein the first source / drain region of the write transistor in the second level is electrically connected to the write bit line, and the gate line of the write transistor in the second level is electrically connected to the write word line.

[0132] Clause 47, a method of manufacturing embedded dynamic random access memory (eDRAM), the method comprising manufacturing a front-end process (FEOL) structure including one or more logic chips, manufacturing a first layer on the FEOL structure, and manufacturing a second layer on the first layer to form eDRAM.

[0133] Clause 48, the method according to Clause 47, wherein manufacturing the first layer includes manufacturing a plurality of first layers on the top surface of the FEOL structure, each of the plurality of first layers being spaced apart from each other in a first direction parallel to the top surface of the FEOL structure.

[0134] Clause 49, the method described in Clause 48, wherein manufacturing the second layer includes manufacturing a plurality of second layers on a plurality of first layers respectively.

[0135] Clause 50, a method of manufacturing embedded dynamic random access memory (eDRAM), the method comprising: manufacturing a first die including a FEOL structure, the FEOL structure including one or more logic chips; manufacturing a second die including a first level and a second level on the first level; and mixing and bonding the first die and the second die together to form a 3D eDRAM with heterogeneous integration.

[0136] Clause 51, the method according to Clause 50, wherein manufacturing the second core includes manufacturing a first plurality of second cores, each second core including a first layer and a second layer on the first layer, and wherein hybrid bonding includes hybrid bonding each of the first plurality of second cores to the first core.

[0137] Clause 52, the method according to Clause 51, wherein manufacturing the second core includes further manufacturing a second plurality of second cores, each second core including a first layer and a second layer on the first layer, and wherein the hybrid bonding further includes hybrid bonding the second plurality of cores to the first plurality of second cores respectively.

[0138] Clause 53, an apparatus including a dual-transistor zero-capacitor (2T0C) gain unit in a back-end process architecture, the 2T0C gain unit including a write transistor and a read transistor electrically connected to the write transistor, wherein the write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

[0139] Clause 54, the apparatus described in Clause 53, wherein an oxide semiconductor channel is stacked on a polysilicon channel.

[0140] Clause 55 of the apparatus according to claim 53 or 54, wherein the read transistor is in the first layer and the write transistor is in the second layer, and the second layer is stacked on the first layer.

[0141] Clause 56, the apparatus according to any one of Clauses 53 to 55, wherein the write transistor overlaps with the read transistor.

[0142] Clause 57, the apparatus according to any one of Clauses 53 to 56, wherein the read transistor is connected to the write transistor via a path, and wherein the 2T0C gain unit uses the parasitic capacitance of the path to store data.

[0143] Clause 58, the apparatus according to any one of Clauses 53 to 57, wherein the read transistor includes a gate, a source, and a drain, and the write transistor includes a gate, a source, and a drain, wherein the gate of the read transistor is electrically connected to the drain of the write transistor.

[0144] Clause 59, the apparatus according to any one of Clauses 53 to 58, wherein the gate line of the read transistor is connected via a path to the drain region of the write transistor.

[0145] Clause 60, the apparatus according to any one of Clauses 53 to 59, wherein a portion of the gate line of the read transistor overlaps with a portion of the drain region of the write transistor, and a path connects said portion of the gate line of the read transistor to said portion of the drain region of the write transistor.

[0146] Clause 61, the apparatus according to any one of Clauses 53 to 60, wherein the read transistor includes a gate, a source, and a drain, and the write transistor includes a gate, a source, and a drain, wherein the gate of the read transistor is electrically connected to the drain of the write transistor, and wherein the gate of the write transistor is electrically connected to a write word line, the source of the write transistor is electrically connected to a write bit line, the source of the read transistor is electrically connected to a read word line, and the drain of the read transistor is electrically connected to a read bit line.

[0147] Clause 62, the apparatus according to any one of Clauses 53 to 61, wherein the gate of the read transistor is electrically connected to the drain of the write transistor, and wherein the 2T0C gain unit uses the parasitic capacitance at the gate of the read transistor to store data.

[0148] Clause 63, the apparatus according to any one of Clauses 53 to 62, wherein a read transistor is included in a first die and a write transistor is included in a second die, and the first die is co-bonded to the second die.

[0149] Clause 64, the apparatus according to any one of Clauses 53 to 63, wherein the oxide semiconductor channel comprises at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.

[0150] Clause 65, a system comprising: a front-end process (FEOL) structure including a logic chip; and a back-end process (BEOL) structure on the FEOL structure, the BEOL structure including a layer, wherein the layer includes a dual-transistor zero-capacitor (2T0C) gain unit, the dual-transistor zero-capacitor (2T0C) gain unit including a read transistor and a write transistor electrically connected to the read transistor, and wherein the write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

[0151] Clause 66, the system described in Clause 65, wherein the logic chip is electrically connected to a write transistor and a read transistor.

[0152] Clause 67, the system described in Clause 65 or 66, wherein an oxide semiconductor channel is stacked on a polysilicon channel.

[0153] Clause 68, a system according to any one of Clauses 65 to 67, wherein the read transistor is in a first layer and the write transistor is in a second layer, and the second layer is stacked on the first layer.

[0154] Clause 69, the system according to any one of Clauses 65 to 68, wherein the read transistor is connected to the write transistor via a path, and wherein the 2T0C gain unit uses the parasitic capacitance of the path to store data.

[0155] Clause 70, a method comprising: fabricating a first structure using a front-end process (process), the first structure including a logic chip; fabricating a first level using a back-end process (BEOL) process, the first level including a read transistor of a dual-transistor zero-capacitor gain unit; and fabricating a second level on the first level using the BEOL process, the second level including a write transistor of a 2T0C gain unit.

[0156] Clause 71, the method described in Clause 70, wherein the first layer is created on the first structure.

[0157] Clause 72, the method described in Clause 70, wherein the first layer is joined to the first structure by a hybrid joining.

[0158] It should be understood that the implementation methods are not limited to the various implementation methods described above, but various other changes and modifications may be made therein without departing from the spirit and scope set forth in the appended claims.

[0159] Cross-references to related applications

[0160] This application is based on and claims priority to U.S. Provisional Application No. 63 / 709,875, filed October 21, 2024, with the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: In the back-end process architecture, a dual-transistor zero-capacitor gain unit includes a write transistor and a read transistor electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

2. The memory device according to claim 1, wherein, The oxide semiconductor channel is stacked on the polysilicon channel.

3. The memory device according to claim 1, wherein, The read transistor is in a first layer, and the write transistor is in a second layer, with the second layer stacked on top of the first layer.

4. The memory device according to claim 1, wherein, The write transistor overlaps with the read transistor.

5. The memory device according to claim 1, wherein, The read transistor is connected to the write transistor via a path, and The dual-transistor zero-capacitor gain unit uses the parasitic capacitance of the path to store data.

6. The memory device according to claim 1, wherein, The read transistor includes a gate, a source, and a drain, and the write transistor includes a gate, a source, and a drain. The gate of the read transistor is electrically connected to the drain of the write transistor.

7. The memory device according to claim 1, wherein, The gate line of the read transistor is connected to the drain region of the write transistor via a path.

8. The memory device according to claim 1, wherein, A portion of the gate line of the read transistor overlaps with a portion of the drain region of the write transistor, and a path connects the portion of the gate line of the read transistor to the portion of the drain region of the write transistor.

9. The memory device according to claim 1, wherein, The read transistor includes a gate, a source, and a drain, and the write transistor includes a gate, a source, and a drain. Wherein, the gate of the read transistor is electrically connected to the drain of the write transistor, and The gate of the write transistor is electrically connected to the write word line, the source of the write transistor is electrically connected to the write bit line, the source of the read transistor is electrically connected to the read word line, and the drain of the read transistor is electrically connected to the read bit line.

10. The memory device according to claim 1, wherein, The gate of the read transistor is electrically connected to the drain of the write transistor, and The dual-transistor zero-capacitor gain unit uses the parasitic capacitance at the gate of the read transistor to store data.

11. The memory device according to claim 1, wherein, The read transistor is included in a first die, and the write transistor is included in a second die, and the first die is co-bonded to the second die.

12. The memory device according to claim 1, wherein, The oxide semiconductor channel includes at least one of indium oxide, indium tin oxide, indium gallium zinc oxide, tin oxide, zinc oxide, Ge-doped indium oxide, or W-doped indium oxide.

13. A memory system, comprising: Front-end manufacturing structure, including logic chips; as well as A back-end process structure on the front-end process structure, the back-end process structure comprising layers. The layer includes a dual-transistor zero-capacitor gain unit, which includes a read transistor and a write transistor electrically connected to the read transistor. The write transistor includes an oxide semiconductor channel, and the read transistor includes a polysilicon channel.

14. The memory system according to claim 13, wherein, The logic chip is electrically connected to the write transistor and the read transistor.

15. The memory system according to claim 13, wherein, The oxide semiconductor channel is stacked on the polysilicon channel.

16. The memory system according to claim 13, wherein, The read transistor is in a first layer, and the write transistor is in a second layer, with the second layer stacked on top of the first layer.

17. The memory system according to claim 13, wherein, The read transistor is connected to the write transistor via a path, and The dual-transistor zero-capacitor gain unit uses the parasitic capacitance of the path to store data.

18. A method of manufacturing a memory system, comprising: The first structure is manufactured using a front-end process technology, and the first structure includes a logic chip. The first layer is manufactured using a back-end process technology, and the first layer includes a readout transistor of a dual-transistor zero-capacitor-gain unit. as well as A second layer is fabricated on the first layer using the back-end process technology, the second layer including the write transistor of the dual-transistor zero-capacitor-gain unit.

19. The method according to claim 18, wherein, The first layer is manufactured on the first structure.

20. The method according to claim 18, wherein, The first layer is joined to the first structure by a hybrid bonding process.

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