IMC layer applied to fuse fusing and thickness control method

Abstract

The invention discloses an IMC layer applied to fuse fusing and a thickness control method thereof, a fuse is a Cu base material circuit etched on a substrate, solder containing Sn is welded on the surface of a Cu base material to form the IMC layer at least comprising a Cu-Sn compound layer, the thickness of the IMC layer is 1-3 microns, and the IMC layer is located between the Cu base material and a surface layer formed by the Sn material. The thickness control method is used for completing fusing of the fuse in millisecond-level unit time when the cutoff current value is exceeded, and the thickness control method is used for thickness control of the IMC layer.

Description

Technical Field

[0001] This invention relates to the field of circuit protection technology, and in particular to an IMC layer and a method for controlling its thickness when a fuse is blown. Background Technology

[0002] The lines on an FPC are very narrow. If a short circuit occurs between the voltage sampling lines or with the module housing due to external compression, metal debris, improper assembly, or damage to the insulation layer, a huge short-circuit current will be generated. When designing protection schemes, engineers rely entirely on the time-current curves provided by the fuse manufacturer for fusing.

[0003] A battery pack in a new energy electric vehicle may contain dozens of modules and hundreds of FPCs, or a battery factory may produce millions or even tens of millions of battery cell modules annually. Existing fuse designs that rely on time-current curves for blowing have a problem of poor blowing consistency. This means that if a fuse fails to blow in time under the set fault current, the short-circuit current will persist, which may eventually lead to FPC burnout, BMS damage, or even thermal runaway and failure of safety protection. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide an IMC layer for fuse breaking that can ensure consistent fuse breaking performance.

[0005] This invention discloses an IMC layer for fuse melting. The fuse is a Cu substrate circuit etched on a substrate. An IMC layer including at least a Cu-Sn compound layer is formed by soldering a solder containing Sn on the surface of the Cu substrate. The thickness of the IMC layer is 1 to 3 μm and it is located between the Cu substrate and the surface layer formed by the Sn material, so that the fuse can melt in milliseconds when the interruption current value is exceeded.

[0006] Furthermore, the Cu-Sn compound layer includes at least a Cu6Sn5 layer.

[0007] Furthermore, the Cu6Sn5 layer accounts for more than 80% of the IMC layer.

[0008] Furthermore, the Cu-Sn compound layer also includes a Cu3Sn layer, which is located between the Cu6Sn5 layer and the Cu substrate.

[0009] Furthermore, the Cu3Sn layer accounts for less than 20% of the IMC layer.

[0010] Furthermore, the solder may also include Ni components and form a Sn-Ni compound layer during the soldering process. The Sn-Ni compound layer includes at least a Ni3Sn4 layer, which is located on the side close to the Cu substrate.

[0011] A method for controlling the thickness of an IMC layer used in fuse blowing, wherein the Cu substrate of the substrate is soldered to the solder via a reflow soldering process, and the thickness of the IMC layer is controlled by the following formula:

[0012] Where X: thickness of the IMC layer; K0: pre-exponential factor / rate constant; t: time above the liquidus line; Q: activation energy for IMC layer growth; R: ideal gas constant; T: peak temperature.

[0013] Furthermore, the thickness of the IMC layer increases by 2 μm for every 10°C increase in peak temperature.

[0014] Furthermore, the thickness of the IMC layer increases by 1 μm for every 30 seconds the time above the liquidus line is extended.

[0015] Furthermore, when the solder contains Ni and the Ni content in the solder is 0.1%, the thickness of the IMC layer is reduced by 20%.

[0016] The IMC layer for fuse fusing provided by this invention is formed by welding a solder containing Sn to the surface of a Cu substrate, creating an IMC layer comprising at least a Cu-Sn compound layer. The thickness of the IMC layer is 1–3 μm. This ensures that fuses on different FPCs can fuse within milliseconds when the breaking current exceeds the threshold value, achieving consistent fusing and preventing problems such as FPC burnout, BMS damage, or even thermal runaway and safety protection failure. The thickness control method for the IMC layer for fuse fusing provided by this invention controls the thickness of the IMC layer to 1–3 μm, thereby ensuring that fuses on different FPCs can fuse within milliseconds when the breaking current exceeds the threshold value, ultimately achieving consistent fusing. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of the fuse on the substrate of the present invention without solder.

[0019] Figure 2 This is a schematic diagram of the fuse on the substrate of the present invention having been soldered.

[0020] Figure 3 This is a schematic diagram of the fuse with solder applied according to the present invention being blown.

[0021] Figure 4 This is a cross-sectional schematic diagram of a solder-coated fuse according to the present invention.

[0022] Figure 5 This is a schematic diagram of the fusing time of Group A of the fuses of the present invention when no solder is applied.

[0023] Figure 6 This is a schematic diagram of the B-group fusing time of the fuse of the present invention when no solder is applied.

[0024] Figure 7 This is a schematic diagram of the melting time of Group A of the fuse with solder applied according to the present invention.

[0025] Figure 8 This is a schematic diagram of the B-group fusing time of the fuse with solder applied according to the present invention.

[0026] Figure 9 This is a schematic diagram of the time-current curve of the fuse. Detailed Implementation

[0027] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. Based on the description of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0028] The terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use. They are used only for the convenience of description and simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the invention.

[0029] The terms “include,” “comprising,” or any other variation thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0030] Please see Figures 1-9This invention discloses an IMC layer for fuse melting. The fuse 20 is a Cu substrate circuit etched on a substrate 10. A solder 30 containing Sn is soldered on the surface of the Cu substrate to form an IMC layer including at least a Cu-Sn compound layer. The thickness of the IMC layer is 1 to 3 μm and it is located between the Cu substrate and the surface layer formed by the Sn material, so that the fuse 20 can complete melting in milliseconds when the interruption current value is exceeded.

[0031] Please see Figure 9 This represents the current-time curve of an existing fuse during a short circuit. During the first time period on the t-axis, the fuse does not melt. During the second time period, the fuse begins to melt and generates an arc. The fuse completely melts only after the second time period ends. At this point, the breaking current on the I-axis is close to the peak current. However, in typical designs, the fault current setting of the fuse must be less than the peak current. This means that when the fuse 20 is between the fault current and the peak current, a large short-circuit current usually persists, causing the FPC to burn out or even the BMS to be damaged.

[0032] Please see Figures 1-4 In this invention, a fuse 20 with Cu-based material circuitry is etched onto a substrate 10, and pads 21 are provided on the fuse 20. An IMC (Intermetallic Compounds) layer is formed by soldering solder onto the pads 21. In this embodiment, liquid lead-free solder (such as SAC305) is used. The solder is soldered onto the pads 21 via a reflow soldering process, forming the Cu-Sn compound layer between the surface of the Cu substrate of the substrate 10 and the Sn surface layer of the solder. The Cu-Sn compound layer includes a Cu6Sn5 layer and a Cu3Sn layer. The Cu6Sn5 layer is located near the Sn surface layer, and the Cu3Sn layer is located between the Cu6Sn5 layer and the Cu substrate.

[0033] The resistivity of the IMC layer directly affects the current. Generally, the resistivity of the IMC layer is higher than that of pure metal solder (e.g., Sn) and substrate (e.g., Cu), as is common knowledge. The resistivity of pure tin (Sn) is 11.5 μΩ·cm; the resistivity of pure copper (Cu) is 1.7 μΩ·cm; while the resistivity of Cu6Sn5 in the IMC layer of this invention is 17.5 μΩ·cm, and the resistivity of Cu3Sn is 8.9 μΩ·cm. It should be noted that Cu3Sn is more brittle and prone to problems. Therefore, in this embodiment, the Cu6Sn5 layer needs to account for more than 80% of the IMC layer to ensure connection reliability, while the Cu3Sn layer needs to account for less than 20%. This ensures that the fuse 20 melts quickly when the cutoff current value is exceeded, rather than melting prematurely before reaching the cutoff current value, thus preventing misjudgment.

[0034] In a specific embodiment of the present invention, the Cu6Sn5 layer accounts for approximately 85% of the IMC layer to ensure sufficient adhesion, and the Cu3Sn layer accounts for approximately 15% of the IMC layer to ensure that the IMC layer melts when the fusing current is reached. When the Cu3Sn layer accounts for more than 20% of the IMC layer, the IMC layer becomes extremely brittle and may even crack during thermal cycling, leading to decreased reliability and misjudgment.

[0035] The current-breaking mechanism of the IMC layer is mostly indirectly triggered by mechanical properties, specifically manifested in the brittleness and cracks of the IMC layer leading to the interruption of the current path. The IMC layer is inherently brittle and its CTE (coefficient of thermal expansion) is mismatched with the surrounding materials. Under thermal cycling or mechanical stress, microcracks are most likely to form and propagate within the IMC layer or at the interface between the IMC layer and the solder, physically cutting off the current conduction path. Initially, the crack is small, and current can still pass through the unbroken portion. At this time, the resistance increases slowly, and the equipment may function normally. In the later stages, the crack continues to propagate, the effective conductive cross-sectional area becomes smaller and smaller, and the local current density increases sharply, leading to increased Joule heating, further accelerating crack propagation. Eventually, the crack penetrates the entire interface, causing the solder joint to be completely open (see [link to relevant documentation]). Figure 3 The circuit failed.

[0036] Please see Figures 5-8 The present invention uses data verification of fuses in groups A and B with and without solder to statistically analyze the difference in fusing time, so as to verify the fusing consistency when the IMC layer is 1 to 3 μm thick.

[0037] Please see Figure 5 The experimental parameters were: copper thickness: 0.035mm, fuse length: 11mm, fuse treatment: partial non-tinning, current: 5A, voltage: DC5V.

[0038] Based on the above data, the longest time is 4.02 seconds and the shortest time is 1.64 seconds. The calculated limit difference in fuse breaking time is 2.38 seconds.

[0039] Please see Figure 6 The experimental parameters were: copper thickness: 0.035mm, fuse length: 11mm, fuse treatment: local tinning, current: 5A, voltage: DC5V.

[0040] Based on the above data, the longest time is 2.16 seconds and the shortest time is 1.74 seconds. The calculated limit difference in fuse interruption time is 0.42 seconds.

[0041] Please see Figure 7 The experimental parameters were: copper thickness: 0.035mm, fuse length: 11mm, fuse treatment: partial non-tinning, current: 5A, voltage: DC5V.

[0042] Based on the above data, the longest time is 3.28 seconds and the shortest time is 1.46 seconds. The calculated limit difference in fuse interruption time is 1.82 seconds.

[0043] Please see Figure 8 The experimental parameters were: copper thickness: 0.035mm, fuse length: 11mm, fuse treatment: local tinning, current: 5A, voltage: DC5V.

[0044] Based on the above data, the longest time is 2.08 seconds and the shortest time is 1.54 seconds. The calculated limit difference in fuse interruption time is 0.54 seconds.

[0045] The above four sets of data show that the melting time limit difference of the fuse 20 with partial tinning is more than 3 times higher than that with partial undilution. This results confirm that the fuse 20 with partial tinning and the IMC layer thickness maintained at 1-3 μm can quickly complete melting when the set cutoff current is reached. In contrast, the fuse 20 with partial undilution will maintain high current operation at or above the cutoff current without completing melting, which will inevitably cause the FPC to burn out or even the BMS to be damaged.

[0046] In another embodiment of the present invention, the solder may further include Ni components and form a Sn-Ni compound layer during the soldering process. The Sn-Ni compound layer includes a Ni3Sn4 layer and a Ni3Sn layer. The Ni3Sn4 layer is located on the side closer to the Cu substrate to strengthen the connection strength between the IMC layer and the Cu substrate. The Ni3Sn layer is located on the side of the Ni3Sn4 layer away from the Cu substrate. The Sn-Ni compound layer can suppress the formation rate of the IMC layer. By adding Ni components to the solder, the formation thickness of the IMC layer can be reduced under the same conditions in the reflow soldering process. Specifically, since it is difficult to control the thickness of the IMC layer to 1-3 μm, this embodiment improves this by adding Ni components to the solder. When 0.1% Ni components are added, it has been verified that the thickness of the IMC layer can be reduced by about 20%, which has a very significant effect on controlling the thickness of the IMC layer from 1 to 3 μm.

[0047] This invention also discloses a method for controlling the thickness of an IMC layer used in fuse blowing, wherein the Cu substrate of the substrate is soldered to the solder via a reflow soldering process, and the thickness of the IMC layer is controlled by the following formula:

[0048] Where X: thickness of the IMC layer; K0: pre-exponential factor / rate constant; t: time above the liquidus line; Q: activation energy for IMC layer growth; R: ideal gas constant; T: peak temperature.

[0049] In reflow soldering, the following factors influence the thickness of the IMC layer:

[0050] Referring to the table above, specifically, when the peak temperature increases by 10°C, the thickness of the IMC layer increases by 2μm; when the time above the liquidus line is extended by 30s, the thickness of the IMC layer increases by 1μm; when the cooling rate is greater than 2°C / s, excessive growth can be suppressed, which is beneficial for controlling the thickness of the IMC layer; when the solder contains Ni and the Ni content in the solder is 0.1%, the thickness of the IMC layer decreases by 20%.

[0051] In actual SMT production, we indirectly control the thickness of the IMC layer by strictly controlling process parameters, material selection, and on-site monitoring, wherein: 1. Precise control of the reflow soldering temperature profile is the most direct and important control method. The key parameters of the profile directly correspond to T and t in the IMC growth formula.

[0052] Peak temperature T: controls the growth rate of the IMC layer; Target: Must be higher than the solder melting point to ensure good soldering, but never too high; Control value: Usually set 20-35°C higher than the solder liquidus line. For lead-free solder (SAC305, melting point 217°C), the peak temperature is generally controlled at 240-250°C.

[0053] Time above the liquidus line (t): Controls the duration of IMC growth; Objective: To provide sufficient time for the solder paste to fully wet and form solder joints, but not too long. Control value: For lead-free soldering, typically controlled between 60-90 seconds.

[0054] Heating rate and cooling rate: Heating rate: typically controlled at 1.0-3.0°C / second. Excessive heating may cause thermal shock to components and solder splatter. Cooling rate: typically controlled at -2 to -4°C / second. This ensures a refined solder joint microstructure, making it more uniform, and suppresses excessive growth and coarsening of the IMC layer, reducing the precipitation of lead-rich phases in the eutectic solder.

[0055] More specifically, this invention is based on SAC305 solder and Cu substrate pad 21. Experiments show that by measuring the peak temperature (Tp) and time above the liquidus line (TAL) during reflow soldering, and then fitting K0 and Q values, the thickness range of the IMC layer can be determined. In this embodiment, the peak temperature and liquidus line time during reflow soldering are TAL: 60-90s, and Tp: 240-245℃ to achieve a thickness of 1-3μm for the IMC layer. This ensures that melting occurs within milliseconds under a cutoff current of 5A, thus preventing FPC burnout and even BMS damage. Further verification data shows that when Tp rises above 250℃ or TAL exceeds 120s, the IMC layer thickness increases to 4-6μm or even thicker, increasing the risk of brittleness, i.e., premature melting before reaching the cutoff current value, leading to misjudgment.

[0056] 2. The impact of multiple reflows and repairs on the thickness of the IMC layer Each reflow is equivalent to a "heat treatment" for the growth of the IMC layer, and the thickness of the IMC layer will increase cumulatively, whereby the thickness is calculated as follows:

[0057] For boards requiring double-sided mounting or rework, the impact of the first reflow on the second must be considered. The profile for the second reflow should be optimized by using a lower peak temperature or a shorter TAL to reduce the overall thickness of the IMC layer.

[0058] The IMC layer for fuse fusing provided by this invention is formed by welding a solder containing Sn to the surface of a Cu substrate, creating an IMC layer comprising at least a Cu-Sn compound layer. The thickness of the IMC layer is 1–3 μm. This ensures that fuses on different FPCs can fuse within milliseconds when the breaking current exceeds the threshold value, achieving consistent fusing and preventing problems such as FPC burnout, BMS damage, or even thermal runaway and safety protection failure. The thickness control method for the IMC layer for fuse fusing provided by this invention controls the thickness of the IMC layer to 1–3 μm, thereby ensuring that fuses on different FPCs can fuse within milliseconds when the breaking current exceeds the threshold value, ultimately achieving consistent fusing.

[0059] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An IMC layer for fuse breaking, wherein the fuse is a Cu substrate circuit etched on a substrate, characterized in that, An IMC layer comprising at least a Cu-Sn compound layer is formed by soldering a Sn-containing solder onto the surface of a Cu substrate. The IMC layer has a thickness of 1–3 μm and is located between the Cu substrate and the surface layer formed by the Sn material, so as to enable the fuse to complete melting in milliseconds when the cutting-off current value is exceeded.

2. The IMC layer applied to fuse blowing as described in claim 1, characterized in that, The Cu-Sn compound layer includes at least a Cu6Sn5 layer.

3. The IMC layer applied to fuse blowing as described in claim 2, characterized in that, The Cu6Sn5 layer accounts for more than 80% of the IMC layer.

4. The IMC layer applied to fuse blowing as described in claim 2, characterized in that, The Cu-Sn compound layer further includes a Cu3Sn layer, which is located between the Cu6Sn5 layer and the Cu substrate.

5. The IMC layer applied to fuse blowing as described in claim 4, characterized in that, The Cu3Sn layer accounts for less than 20% of the total IMC layer.

6. The IMC layer applied to fuse blowing as described in claim 1, characterized in that, The solder may also include Ni components and form a Sn-Ni compound layer during the soldering process. The Sn-Ni compound layer includes at least a Ni3Sn4 layer, which is located on the side close to the Cu substrate.

7. A method for controlling the thickness of an IMC layer applied to fuse melting as described in any one of claims 1-6, wherein the Cu substrate of the substrate is welded to the solder via a reflow soldering process, characterized in that... The thickness of the IMC layer is controlled by the following formula: Where X: thickness of the IMC layer; K0: pre-exponential factor / rate constant; t: time above the liquidus line; Q: activation energy for IMC layer growth; R: ideal gas constant; T: peak temperature.

8. The thickness control method as described in claim 7, characterized in that, The thickness of the IMC layer increases by 2 μm for every 10°C increase in peak temperature.

9. The thickness control method as described in claim 7, characterized in that, For every 30 seconds the time above the liquidus line is extended, the thickness of the IMC layer increases by 1 μm.

10. The thickness control method as described in claim 7, characterized in that, When the solder contains Ni and the Ni content in the solder is 0.1%, the thickness of the IMC layer is reduced by 20%.

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