Detection comparison circuit, detection comparison method and electronic device
By introducing an input clamping circuit into the signal input detection and comparison circuit, the delay problem caused by the parasitic capacitance at the positive input terminal of the comparator is solved, achieving high-precision and high-speed voltage signal detection and improving the robustness of the comparison circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI NAXI MICROELECTRONICS CO LTD
- Filing Date
- 2025-12-16
- Publication Date
- 2026-04-21
AI Technical Summary
In existing signal input detection and comparison circuits, the parasitic capacitance at the positive input terminal of the comparator causes a delay, which slows down the comparison and transmission speed of the comparator.
An input clamping circuit is used to compare the difference between the input first voltage and the reference voltage. When the difference is greater than a preset threshold, the first voltage is clamped to generate a second voltage within the range of the reference voltage, so that the first voltage does not exceed the limit, reducing the delay of the series resistor and achieving high-precision signal detection.
It achieves high-speed voltage signal comparison and detection, reduces delay caused by parasitic capacitance, and improves the robustness of the comparison circuit.
Smart Images
Figure CN121907205A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of input signal detection circuit technology, and in particular to a detection comparison circuit, a detection comparison method, and an electronic device. Background Technology
[0002] With the continuous development of electronic technology, the importance of signal input detection and comparison circuits in various electronic devices is becoming increasingly prominent.
[0003] In existing signal input detection and comparison circuits, parasitic capacitance is generated at the positive input terminal of the comparator, which may cause a delay, thereby slowing down the comparison speed and transmission speed of the comparator, and thus slowing down the signal detection speed of the signal input detection and comparison circuit. Summary of the Invention
[0004] The main objective of this invention is to provide a detection comparison circuit and an electronic device, which aim to achieve high-speed voltage signal comparison and detection.
[0005] To achieve the above objectives, the present invention proposes a detection and comparison circuit, comprising: an input clamping circuit for receiving a first voltage and a reference voltage, the input clamping circuit being configured to: output the first voltage when the difference between the first voltage and the reference voltage is less than a preset threshold; and output a second voltage when the difference between the first voltage and the reference voltage is greater than the preset threshold, the second voltage being within a preset range, the preset range being a voltage range including the reference voltage; and a comparison circuit for receiving the reference voltage and either the first voltage or the second voltage, and outputting a comparison result.
[0006] Optionally, the input clamping circuit includes: a clamping output terminal coupled to the comparator circuit; a first NMOS transistor, the drain of which is used to input the first voltage; a second NMOS transistor, the source of which is coupled to the source of the first NMOS transistor, and the drain of which is coupled to the clamping output terminal; a first diode having a first anode and a first cathode, the first anode being coupled to the gate of the first NMOS transistor and the gate of the second NMOS transistor, and the first cathode being coupled to the drain of the first NMOS transistor; and a third NMOS transistor, the gate of which is coupled to the reference power supply input terminal. The drain of the third NMOS transistor is coupled to the power supply, and the source of the third NMOS transistor is coupled to the clamping output terminal; the gate of the third PMOS transistor is coupled to the reference power supply input terminal, the source of the third PMOS transistor is grounded, and the drain of the third PMOS transistor is coupled to the clamping output terminal; the gate of the first PMOS transistor is grounded, the drain of the first PMOS transistor is coupled to the drain of the second PMOS transistor and the power supply respectively, and the source of the first PMOS transistor is coupled to the first anode terminal; the gate of the second PMOS transistor is coupled to the power supply, and the source of the second PMOS transistor is grounded.
[0007] Optionally, the difference between the source voltage of the second PMOS transistor and the reference voltage is twice the first voltage difference, where the first voltage difference is the voltage difference between the source voltage and the gate voltage of the second PMOS transistor.
[0008] Optionally, the input clamping circuit is configured such that: when the first voltage is greater than the reference voltage, the first PMOS transistor is turned on, the gate voltage of the first PMOS transistor is equal to the source voltage of the first PMOS transistor, the first NMOS transistor is in the saturation region, the second NMOS transistor is in the linear region, the third NMOS transistor is turned off, and the third PMOS transistor clamps the voltage output from the drain of the second NMOS transistor to the second voltage, wherein the difference between the second voltage and the reference voltage is within one first voltage difference; when the first voltage is equal to the reference voltage, the first NMOS transistor and the second NMOS transistor are in the linear region, the third NMOS transistor and the third PMOS transistor are turned off, and the drain of the second NMOS transistor outputs the first voltage; when the first voltage is less than the reference voltage, the first diode is turned on, the first NMOS transistor is between the linear region and the saturation region, the second NMOS transistor and the third PMOS transistor are turned off, and the third NMOS transistor clamps the voltage output from the clamping output terminal to the second voltage, wherein the difference between the second voltage and the reference voltage is within one first voltage difference.
[0009] Optionally, the input clamping circuit includes: a clamping output terminal coupled to the comparator circuit; a first PMOS transistor, the source of which is used to input the first voltage; a second PMOS transistor, the drain of which is coupled to the clamping output terminal, and the source of which is coupled to the drain of the first PMOS transistor; a first diode having a first anode and a first cathode, the first anode being coupled to the source of the first PMOS transistor, and the first cathode being coupled to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor; and a third PMOS transistor, the gate of which is coupled to the reference power supply input terminal. The source of the third PMOS transistor is grounded, and its drain is coupled to the clamp output terminal; the gate of the third NMOS transistor is coupled to the reference power input terminal, its drain is coupled to the power supply, and its source is coupled to the clamp output terminal; the gate of the first NMOS transistor is coupled to the power supply, its source is coupled to the source and power supply of the second NMOS transistor, and its drain is coupled to the first anode terminal; the gate of the second NMOS transistor is coupled to the reference power input terminal, and its drain is coupled to the power supply.
[0010] Optionally, the source voltage of the second NMOS transistor is less than twice the reference voltage by a second voltage difference; wherein, the second voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor.
[0011] Optionally, the input clamping circuit is configured such that: when the first voltage is less than the reference voltage, the first NMOS transistor is turned on, the gate voltage of the first NMOS transistor is equal to the source voltage of the first NMOS transistor, the first PMOS transistor is in the saturation region, the second PMOS transistor is in the linear region, the third PMOS transistor is turned off, and the third NMOS transistor clamps the source voltage of the second PMOS transistor to be the second voltage, wherein the difference between the second voltage and the reference voltage is within one second voltage difference; when the first voltage is equal to the reference voltage, the first PMOS transistor and the second PMOS transistor are in the linear region, the third NMOS transistor and the third PMOS transistor are turned off, and the source of the second PMOS transistor outputs the first voltage; when the first voltage is greater than the reference voltage, the first diode is turned on, the first PMOS transistor is between the linear region and the saturation region, the second PMOS transistor and the third NMOS transistor are turned off, and the third PMOS transistor clamps the source voltage of the second PMOS transistor to be the second voltage, wherein the difference between the second voltage and the reference voltage is within one second voltage difference.
[0012] Optionally, the input clamping circuit includes: a clamping output terminal coupled to the comparator circuit; a first PMOS transistor, the source of which is used to input the first voltage; a second PMOS transistor, the gate of which is coupled to the reference power supply input terminal, and the drain of which is grounded; a third PMOS transistor, the gate of which is coupled to the source of which is grounded, and the drain of which is coupled to the clamping output terminal; a first NMOS transistor, the gate of which is coupled to the gate of which is coupled to the gate of which is coupled to the gate of which is coupled to the gate of which is coupled to the gate of which is coupled to the gate of which is coupled to the gate of which is grounded; and a second NMOS transistor, the source of which is coupled to the first PMOS transistor. The clamping output terminal is coupled, the drain of the second NMOS transistor is coupled to the drain of the first PMOS transistor, and the gate of the second NMOS transistor is coupled to the source of the second PMOS transistor; a second diode has a second anode and a second cathode, the second anode is coupled to the drain of the first PMOS transistor and the drain of the second NMOS transistor, and the second cathode is coupled to the gate of the first PMOS transistor and the drain of the first NMOS transistor; a third NMOS transistor has its gate grounded, its source coupled to the clamping output terminal, and its drain coupled to the power supply; a fourth NMOS transistor has its gate coupled to the reference power supply input terminal, its source grounded, and its drain coupled to the power supply.
[0013] Optionally, the difference between the source voltage of the second NMOS transistor and the reference voltage is a third voltage difference; the third voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor; the second diode is a Zener diode.
[0014] Optionally, the input clamping circuit is configured such that: when the first voltage is less than the reference voltage, the first NMOS transistor is turned on, the gate voltage of the first NMOS transistor is equal to the source voltage of the first NMOS transistor, the first PMOS transistor is in the saturation region, the second NMOS transistor is in the linear region, the third PMOS transistor is turned off, and the third NMOS transistor clamps the source voltage of the second NMOS transistor to the second voltage, which is less than twice the third voltage difference of the reference voltage; when the first voltage is equal to the reference voltage, the first PMOS transistor and the second NMOS transistor are in the linear region, the third NMOS transistor and the third PMOS transistor are turned off, and the source of the second NMOS transistor outputs the first voltage; when the first voltage is greater than the reference voltage, the first PMOS transistor is between the linear region and the saturation region, the second diode is in the reverse breakdown voltage conduction state, the first NMOS transistor and the second NMOS transistor are in the saturation region, the third NMOS transistor is turned off, and the third PMOS transistor clamps the source voltage of the second NMOS transistor to the second voltage, which is greater than twice the third voltage difference of the reference voltage.
[0015] The present invention also proposes an electronic device comprising the detection and comparison circuit shown above.
[0016] The present invention also proposes a detection comparison method, which is applied to the detection comparison circuit described above. The method includes: receiving a first voltage and a reference voltage; selecting a target input clamping circuit according to the reference voltage; comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting a comparison result.
[0017] Optionally, when the reference voltage is low VREF or medium VREF, the target input clamping circuit is a first input clamping circuit. The step of comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting the comparison result specifically includes: when the difference between the first voltage and the reference voltage is within one first voltage difference, the first input clamping circuit outputs a second voltage based on the first voltage, compares the second voltage with the reference voltage, and outputs the result; when the first voltage is equal to the reference voltage, the first input clamping circuit outputs the first voltage, compares the first voltage with the reference voltage, and outputs the result; wherein, the first voltage difference is the voltage difference between the source voltage and the gate voltage of the second PMOS transistor in the first input clamping circuit.
[0018] Optionally, when the reference voltage is medium VREF or high VREF, the target input clamping circuit is a second input clamping circuit. The step of comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting the comparison result specifically includes: when the difference between the first voltage and the reference voltage is within one second voltage difference, the second input clamping circuit outputs a second voltage and compares the second voltage with the reference voltage before outputting the result; when the first voltage is equal to the reference voltage, the second input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage before outputting the result; wherein, the second voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor in the second input clamping circuit.
[0019] Optionally, when the reference voltage is VREF, the target input clamping circuit is a third input clamping circuit. The step of comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting the comparison result specifically includes: when the difference between the first voltage and the reference voltage is within twice the third voltage difference, the third input clamping circuit outputs a second voltage and compares the second voltage with the reference voltage before outputting the result; when the first voltage is equal to the reference voltage, the third input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage before outputting the result; wherein, the third voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor in the third input clamping circuit.
[0020] This invention employs an input clamping circuit. This circuit compares the difference between an input first voltage and a reference voltage. When the difference exceeds a preset threshold (i.e., the first voltage is high or low relative to the reference voltage), the input clamping circuit clamps the first voltage and generates a second voltage within a certain range near the reference voltage, preventing the first voltage from becoming too high and thus enabling high-precision signal detection. When the difference is less than the preset threshold (i.e., the first voltage is close to the threshold value of the reference voltage), there is no series resistance between the input first voltage and the comparison circuit, resulting in minimal delay and enabling high-speed voltage signal comparison and detection. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0022] Figure 1 This is a detection and comparison circuit in the prior art; Figure 2 This is a schematic diagram of the detection and comparison circuit of the present invention; Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the detection and comparison circuit of the present invention; Figure 4 This is a schematic diagram of the circuit structure of another embodiment of the detection and comparison circuit of the present invention; Figure 5 This is a schematic diagram of the circuit structure of another embodiment of the detection and comparison circuit of the present invention; Figure 6 This is a schematic flowchart of the detection and comparison method of the present invention.
[0023] Figure 7 for Figure 6 The diagram shows a specific process flow diagram for step S603.
[0024] Figure 8 for Figure 6 The diagram shows another specific process flow for step S603.
[0025] Figure 9 for Figure 6 The diagram shows another specific process flow for step S603.
[0026] Explanation of icon numbers: 10. Detection and comparison circuit; 100. Input clamping circuit; 200. Comparison circuit; VIN: First power input terminal; VOUT: Comparator output terminal; VREF: Reference power input terminal; VIN_CLAMP: Clamp output terminal; VDD: Power supply; PM0: First PMOS transistor; PM1: Second PMOS transistor; PM2: Third PMOS transistor; NM0: First NMOS transistor; NM1: Second NMOS transistor; NM2: Third NMOS transistor; NM3: Fourth NMOS transistor; D0: First diode; DZ: Second diode; VG: Gate voltage; VS: Source voltage.
[0027] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0029] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.
[0030] See Figure 1 As shown, Figure 1 A detection and comparison circuit is shown. In this circuit, the input of the comparator is equipped with an NMOS high-voltage transistor NM0, a resistor R0, and a diode D0. The high-voltage transistor NM0 is used to accept the high voltage (a potential higher than the reference voltage) at the input, while the resistor R0 and D0 are used to accept the negative voltage (a point lower than the reference voltage). This limits the voltage at the positive input of the comparator from being too high or too low, preventing it from affecting the comparison result. However, the resistor R0 and the parasitic capacitance at the positive input of the comparator constitute an RC delay, slowing down the comparison speed of the comparator. Furthermore, when the reference threshold VREF of the comparator is high (close to the VDD voltage), the high-voltage transistor NM0 cannot turn on properly. This invention, through the inclusion of an input clamping circuit 100, compares the difference between an input first voltage and a reference voltage. When the difference exceeds a preset threshold (i.e., the first voltage is high or low relative to the reference voltage), the clamping circuit clamps the first voltage and generates a second voltage within a certain range near the reference voltage. This prevents the first voltage from becoming too high and reduces transistor threshold voltage shifts caused by NBTI (Negative Bias Temperature Instability) and PBTI (Positive Bias Temperature Instability), achieving high-precision signal detection. When the difference between the first voltage and the reference voltage is less than the preset threshold (i.e., the first voltage is close to the threshold of the reference voltage), there is no series resistance between the input first voltage and the comparison circuit, resulting in minimal delay and enabling high-speed voltage signal comparison and detection.
[0031] This invention proposes a detection and comparison circuit 10.
[0032] Reference Figure 2 , Figure 2This is a schematic diagram of the structure of an embodiment of the detection and comparison circuit of the present invention.
[0033] In this embodiment of the invention, the detection comparison circuit includes an input clamping circuit 100 and a comparison circuit 200.
[0034] Specifically, the input clamping circuit 100 is used to receive a first voltage and a reference voltage, wherein the first voltage is the voltage output from the first power input terminal VIN, and the reference voltage is the voltage output from VREF.
[0035] The input clamping circuit 100 is configured to: output the first voltage when the difference between the first voltage and the reference voltage is less than a preset threshold; and output a second voltage when the difference between the first voltage and the reference voltage is greater than the preset threshold. The second voltage is within a preset range, which includes the reference voltage. Specifically, the preset threshold may be, for example, a range of 0.1 to 0.5. When the difference between the first voltage and the reference voltage is less than the preset threshold, it can be determined that the input first voltage is close to the reference voltage, and the input clamping circuit 100 does not need to clamp the first voltage; the input clamping circuit 100 can directly output the first voltage to the comparator circuit. When the difference between the first voltage and the reference voltage is greater than the preset threshold, that is, the voltage value of the first voltage is high or low compared to the reference voltage, the input clamping circuit 100 needs to clamp the first voltage and generate a second voltage output to the comparator circuit 200 to prevent the second voltage at the input terminal of the comparator circuit 200 from becoming overvoltage. This ensures that the input first voltage is clamped by the input clamping circuit 100 so that the voltage does not become overvoltage. The preset range may be, for example, a voltage range of ±1 of the reference voltage.
[0036] The comparator circuit 200 is used to receive the reference voltage and the first voltage or the second voltage, and output the comparison result to the comparator circuit output terminal VOUT. The comparator circuit 200 may be, for example, a comparator in the prior art.
[0037] Further, see Figure 3 The input clamping circuit 100 may include: a first PMOS transistor PM0, a second PMOS transistor PM1, a third PMOS transistor PM2, a first NMOS transistor NM0, a second NMOS transistor NM1, a third NMOS transistor NM2, a first diode D0, and a clamping output terminal VIN_CLAMP.
[0038] Specifically, the clamp output terminal VIN_CLAMP is coupled to the comparator circuit 200. The drain of the first NMOS transistor NM0 is used to input the first voltage. The source of the second NMOS transistor NM1 is coupled to the source of the first NMOS transistor NM0, and the drain of the second NMOS transistor NM1 is coupled to the clamp output terminal VIN_CLAMP. The first diode D0 has a first anode and a first cathode. The first anode is coupled to the gate of the first NMOS transistor NM0 and the gate of the second NMOS transistor NM1, and the first cathode is coupled to the drain of the first NMOS transistor NM0. Wherein, as... Figure 3 As shown, the first anode terminal of the first diode D0 can be, for example, a... Figure 3 At the upper end of D0, the first cathode end may be, for example, Figure 3 The lower end of D0. The gate of the third NMOS transistor NM2 is coupled to the reference power input terminal VREF, the drain of the third NMOS transistor NM2 is coupled to the power supply VDD, and the source of the third NMOS transistor NM2 is coupled to the clamp output terminal VIN_CLAMP; the gate of the third PMOS transistor PM2 is coupled to the reference power input terminal VREF, the source of the third PMOS transistor PM2 is grounded, and the drain of the third PMOS transistor PM2 is coupled to the clamp output terminal VIN_CLAMP; the gate of the first PMOS transistor PM0 is grounded, the drain of the first PMOS transistor PM0 is coupled to the drain of the second PMOS transistor PM1 and the power supply VDD, and the source of the first PMOS transistor PM0 is coupled to the first anode of D0; the gate of the second PMOS transistor PM1 is coupled to the power supply VDD, and the source of the second PMOS transistor PM1 is grounded. Among them, PM0, PM1 and PM2 are used for the control and clamping of high-level signals, NM0, NM1 and NM2 are used for the control and clamping of low-level signals, and D0 can be turned on when the first voltage is lower than the reference voltage, that is, when the first voltage is negative, D0 can provide a low-impedance path.
[0039] Furthermore, the difference between the source voltage of the second PMOS transistor and the reference voltage is twice the first voltage difference, which is the difference between the source voltage VS and the gate voltage VG of the second PMOS transistor. Figure 3 The input clamping circuit 100 shown is suitable for applications where the reference voltage is low or medium.
[0040] In application scenarios where the reference voltage is low or medium: 1. Overvoltage Protection: When the first voltage is greater than the reference voltage and the first voltage is high, the first PMOS transistor PM0 is turned on, forming a low-impedance path. The gate voltage VG of the first PMOS transistor PM0 is equal to the source voltage VS of the first PMOS transistor PM0. The first NMOS transistor NM0 is in the saturation region, meaning NM0 can act as a constant current source. The second NMOS transistor NM1 is in the linear region, meaning NM1 can be equivalent to a small resistor. The third NMOS transistor NM2 is turned off, and no current flows through NM2. The third PMOS transistor PM2 clamps the drain output voltage of the second NMOS transistor NM1 to the second voltage. The difference between the second voltage and the reference voltage is within one first voltage difference. By clamping the NM1 output voltage with PM2, the source output voltage of NM1 is clamped to be greater than the reference voltage by one first voltage difference, preventing the input first voltage from being used as high voltage and damaging the comparator circuit.
[0041] 2. Normal Transmission: When the first voltage equals the reference voltage, the first NMOS transistor NM0 and the second NMOS transistor NM1 are in the linear region. NM0 and NM1 can both be considered equivalent to resistors, connected in series and dividing the first voltage. This causes the voltage output from the input clamping circuit's clamping output terminal VIN_CLAMP to be close to the first voltage. The third NMOS transistor NM2 and the third PMOS transistor PM2 are cut off, and NM2 and PM2 have no clamping effect, allowing direct signal transmission. The drain of the second NMOS transistor NM1 outputs the first voltage. The transmission path is: VIN → linear resistor network (NM0 / NM1) → VIN_CLAMP, ensuring distortion-free signal transmission. Of course, in other embodiments, the first voltage can also be close to the reference voltage, which also constitutes normal transmission.
[0042] 3. Negative Voltage Protection: When the first voltage is less than the reference voltage, and the first voltage is negative, the first diode D0 conducts. D0 conduction provides a low-impedance path, preventing negative voltage surges. The first NMOS transistor NM0 is between the linear and saturation regions, i.e., NM0 is in diode mode. The source and drain of NM0 are short-circuited, allowing NM0 to function as a diode. The second NMOS transistor NM1 and the third PMOS transistor PM2 are cut off. NM1 is cut off to block current, and PM2 is cut off and has no action. The third NMOS transistor NM2 clamps the voltage output from the clamped output terminal VIN_CLAMP to the second voltage. The difference between the second voltage and the reference voltage is within one first voltage difference. NM2 limits the voltage output from VIN_CLAMP to within one first voltage difference of the reference voltage, preventing negative voltage damage to the comparator circuit 200.
[0043] By precisely controlling the operating state of each MOSFET, in applications where the reference voltage is low or medium, and the source voltage VS of PM2 is twice the reference voltage, when the first voltage is high and in an overvoltage state, PM2 is turned on to limit the first voltage from high level clamping to a difference greater than the reference voltage within one first voltage difference. This prevents high-level damage to the comparator circuit 200. When the first voltage is close to the reference voltage, there is no intervention. When the first voltage is negative (i.e., low level), the first voltage is less than the reference voltage and in an undervoltage state. By turning on NM2, the low-level damage to the comparator circuit 200 is limited. This allows for intelligent clamping of the input first voltage, constructing a reliable and adaptive input protection front end, and significantly improving the robustness of the comparator circuit 200.
[0044] Figure 4 Another circuit configuration of the input clamping circuit 100 is shown.
[0045] Specifically, such as Figure 4 As shown, the input clamping circuit 100 may include: a first PMOS transistor PM0, a second PMOS transistor PM1, a third PMOS transistor PM2, a first NMOS transistor NM0, a second NMOS transistor NM1, a third NMOS transistor NM2, a first diode D0, and a clamping output terminal VIN_CLAMP.
[0046] The clamp output terminal VIN_CLAMP is coupled to the comparator circuit 200; the source of the first PMOS transistor PM0 is used to input the first voltage. The drain of the second PMOS transistor PM1 is coupled to the clamp output terminal VIN_CLAMP, and the source of the second PMOS transistor PM1 is coupled to the drain of the first PMOS transistor PM0. The first diode D0 has a first anode and a first cathode; the first anode is coupled to the source of the first PMOS transistor PM0, and the first cathode is coupled to the gate of the first PMOS transistor PM0 and the gate of the second PMOS transistor PM1; wherein, as... Figure 4 As shown, the first anode terminal of the first diode D0 can be, for example, a... Figure 4 At the upper end of D0, the first cathode end may be, for example, Figure 4The lower end of D0. The gate of the third PMOS transistor PM2 is coupled to the reference power input terminal VREF, the source of the third PMOS transistor PM2 is grounded, and the drain of the third PMOS transistor PM2 is coupled to the clamp output terminal VIN_CLAMP. The gate of the third NMOS transistor NM2 is coupled to the reference power input terminal VREF, the drain of the third NMOS transistor NM2 is coupled to the power supply VDD, and the source of the third NMOS transistor NM2 is coupled to the clamp output terminal VIN_CLAMP. The gate of the first NMOS transistor NM0 is coupled to the power supply VDD, the source of the first NMOS transistor NM0 is coupled to the power supply VDD, and the drain of the first NMOS transistor NM0 is coupled to the first anode terminal. The gate of the second NMOS transistor NM1 is coupled to the reference power input terminal VREF, the drain of the second NMOS transistor NM1 is coupled to the power supply VDD, and the source of the second NMOS transistor NM1 is coupled to the source of the first NMOS transistor NM0. NM0, NM1, and NM2 are used for signal detection, conduction control, and clamping. PM0, PM1, and PM2 are used to form the current path and clamping switch. D0 can be used to turn on the circuit and guide the current path when there is a high voltage input.
[0047] Furthermore, the source voltage VS of the second NMOS transistor NM1 is less than the reference voltage by a second voltage difference that is twice the difference; wherein, the second voltage difference is the voltage difference between the source voltage VS and the gate voltage VG of the second NMOS transistor NM1. Figure 4 The input clamping circuit shown is suitable for applications where the reference voltage is medium or high.
[0048] In application scenarios where the reference voltage is medium or high voltage: 1. Negative Voltage Protection: When the first voltage is less than the reference voltage, and the first voltage is negative (i.e., low level), the first NMOS transistor NM0 is turned on, and the gate voltage VG of the first NMOS transistor NM0 is equal to the source voltage VS of the first NMOS transistor NM0. The first PMOS transistor PM0 is in the saturation region and can be used as a constant current source. The second PMOS transistor PM1 is in the linear region and can be considered as a small resistor. The third PMOS transistor PM2 is turned off, and no current flows through PM2. The third NMOS transistor NM2 clamps the source output voltage of the second PMOS transistor PM1 to the second voltage, and the difference between the second voltage and the reference voltage is within one second voltage difference. By clamping the output voltage of PM1 with NM2, the source output voltage of PM1 is clamped to be less than the reference voltage by one second voltage difference, which can prevent damage to the comparator circuit when the input first voltage is a negative voltage.
[0049] 2. Normal Transmission: When the first voltage equals the reference voltage, the first PMOS transistor PM0 and the second PMOS transistor PM1 are in the linear region, meaning PM0 and PM1 are in a variable resistance state, adjustable through the channel resistance to achieve dynamic balance. The third NMOS transistor NM2 and the third PMOS transistor PM2 are cut off, and NM2 and PM2 have no clamping effect, allowing the signal to be directly transmitted to the clamped output terminal VIN_CLAMP. The source of the second PMOS transistor PM1 outputs the first voltage. When the first voltage equals the reference voltage, the input clamping circuit 100 will not interfere with the original signal, ensuring that the comparator circuit 200 can accurately detect the slight difference between the first voltage and the reference voltage. Of course, in other embodiments, the first voltage can also be close to the reference voltage, which is also considered a normal transmission state.
[0050] 3. Overvoltage Protection: When the first voltage is greater than the reference voltage, the first voltage is in a high-level state, the first diode D0 is turned on, and D0 can be forcibly shunt when the first voltage is used as a high-voltage input to prevent PM0 from being damaged due to overvoltage. At the same time, PM2 is triggered to clamp. The first PMOS transistor PM0 is in the linear region and saturation region, that is, the source and drain of PM0 are short-circuited. At this time, PM0 can be connected and filled similarly to a diode, which is equivalent to entering the working state of a diode. The second PMOS transistor PM1 and the third NMOS transistor NM2 are cut off. PM1 is cut off to block current, and NM2 is cut off and has no action. The third PMOS transistor PM2 clamps the voltage output from the source of the second PMOS transistor PM1 to the second voltage. The difference between the second voltage and the reference voltage is within one second voltage difference. PM2 limits the voltage output of VIN_CLAMP to within one second voltage difference greater than the reference voltage to prevent high voltage from damaging the comparator circuit 200.
[0051] By precisely controlling the operating state of each MOSFET, in applications where the reference voltage is medium or high, and the source voltage VS of PM1 is twice the reference voltage, when the first voltage is low and in a negative state, NM2 is turned on to limit the first voltage from being clamped off from the low level. That is, the first voltage is clamped to within one second voltage difference less than the reference voltage, which can prevent the low level from damaging the comparator circuit 200. When the first voltage is close to the reference voltage, there is no intervention. When the first voltage is high (i.e., high level), the first voltage is greater than the reference voltage and in an overvoltage state. By turning on PM2, the high level is limited to prevent the comparator circuit 200 from being damaged. The first voltage input can be intelligently clamped, constructing a reliable and adaptive input protection front end, which significantly improves the robustness of the comparator circuit 200.
[0052] Figure 5Another circuit configuration of the input clamping circuit 100 is shown.
[0053] like Figure 5 As shown, the input clamping circuit 100 may include: a first PMOS transistor PM0, a second PMOS transistor PM1, a third PMOS transistor PM2, a first NMOS transistor NM0, a second NMOS transistor NM1, a third NMOS transistor NM2, a fourth NMOS transistor NM3, a second diode DZ, and a clamping output terminal VIN_CLAMP.
[0054] Specifically, the clamp output terminal VIN_CLAMP is coupled to the comparator circuit 200. The source of the first PMOS transistor PM0 is used to input the first voltage. The gate of the second PMOS transistor PM1 is coupled to the reference power input terminal VREF, and the drain of the second PMOS transistor PM1 is grounded. The gate of the third PMOS transistor PM2 is coupled to the source of the second PMOS transistor PM1, the source of the third PMOS transistor PM2 is grounded, and the drain of the third PMOS transistor PM2 is coupled to the clamp output terminal VIN_CLAMP. The gate of the first NMOS transistor NM0 is coupled to the gate of the second PMOS transistor PM1, the drain of the first NMOS transistor NM0 is coupled to the gate of the first PMOS transistor PM0, and the source of the first NMOS transistor NM0 is grounded. The source of the second NMOS transistor NM1 is coupled to the clamped output terminal VIN_CLAMP, the drain of the second NMOS transistor NM1 is coupled to the drain of the first PMOS transistor PM0, and the gate of the second NMOS transistor NM1 is coupled to the source of the second PMOS transistor PM1. The second diode DZ has a second anode and a second cathode. The second anode is coupled to the drain of the first PMOS transistor PM0 and the drain of the second NMOS transistor NM1, and the second cathode is coupled to the gate of the first PMOS transistor PM0 and the drain of the first NMOS transistor NM0. Wherein, as... Figure 5 As shown, the second anode of the second diode DZ can be, for example, a... Figure 5 At the upper end of DZ, the second cathode end can be, for example, Figure 5 The lower end of DZ. The gate of the third NMOS transistor NM2 is grounded, the source of the third NMOS transistor is coupled to the clamp output terminal VIN_CLAMP, and the drain of the third NMOS transistor NM2 is coupled to the power supply VDD. The gate of the fourth NMOS transistor NM3 is coupled to the reference power supply input terminal VREF, the source of the fourth NMOS transistor NM3 is grounded, and the drain of the fourth NMOS transistor NM3 is coupled to the power supply VDD.
[0055] Furthermore, the difference between the source voltage VS of the second NMOS transistor NM1 and the reference voltage is a third voltage difference; the third voltage difference is the voltage difference between the source voltage VS and the gate voltage VG of the second NMOS transistor NM1; the second diode DZ is a Zener diode. Figure 5 The input clamping circuit 100 shown is suitable for applications where the reference voltage is a medium voltage.
[0056] In application scenarios where the reference voltage is a medium voltage: 1. Negative Voltage Protection: When the first voltage is less than the reference voltage and the first voltage is in a low-level state, the first NMOS transistor NM0 is turned on, and the gate voltage VG of the first NMOS transistor NM0 is equal to the source voltage VS of the first NMOS transistor NM0. The first PMOS transistor PM0 is in the saturation region, and PM0 acts as a constant current source to stabilize the current. The second NMOS transistor PM1 is in the linear region, and PM1 can be equivalent to a small resistor. The third PMOS transistor PM2 is turned off, PM2 does not operate, and the fourth NMOS transistor is in the linear region. The third NMOS transistor NM2 clamps the source output voltage of the second NMOS transistor NM1 to the second voltage, which is less than twice the reference voltage difference and within the third voltage difference. NM2 turns on to clamp the output voltage of NM1. By clamping the output voltage of NM1 with NM2, the source output voltage of NM1 is clamped to a third voltage difference less than twice the reference voltage, which can prevent damage to the comparator circuit 200 when the input first voltage is used as a negative voltage.
[0057] 2. Normal Transmission: When the first voltage equals the reference voltage, the first PMOS transistor PM0 and the second NMOS transistor NM1 are in the linear region, and the fourth NMOS transistor is also in the linear region. PM0 and NM1 are in a variable resistance state, adjustable through the channel resistance to form a dynamic balance. The third NMOS transistor NM2 and the third PMOS transistor PM2 are cut off, and NM2 and PM2 have no clamping effect. The source of the second NMOS transistor PM1 outputs the first voltage. When the first voltage equals the reference voltage, the input clamping circuit 100 will not interfere with the original signal, ensuring that the comparator circuit 200 can accurately detect the slight difference between the first voltage and the reference voltage. Of course, in other embodiments, the first voltage can also be close to the reference voltage, which is also considered a normal transmission state.
[0058] 3. Overvoltage Protection: When the first voltage is greater than the reference voltage and the first voltage is high, the first PMOS transistor PM0 is between the linear and saturation regions, and the source and drain of PM0 are short-circuited, making PM0 equivalent to a diode. The second diode DZ is in the reverse breakdown voltage conduction state. DZ can absorb transient energy when the first voltage is high, preventing PM0 from breaking down and providing a stable voltage drop. The first NMOS transistor NM0 and the second NMOS transistor NM1 are in the saturation region, and NM0 and NM1 can be in a constant current source state. At the same time, the fourth NMOS transistor is also in the saturation region. The third NMOS transistor NM2 is cut off and does not operate. The third PMOS transistor PM2 clamps the voltage output from the source of the second NMOS transistor NM2 to the second voltage, and the difference between the second voltage and the reference voltage is within twice the third voltage difference. PM2 limits the voltage output of VIN_CLAMP to within twice the third voltage difference of the reference voltage, avoiding high voltage damage to the comparator circuit 200.
[0059] By precisely controlling the operating state of each MOSFET, in applications with a medium reference voltage and where the source voltage VS of NM1 is lower than the reference voltage by one third voltage difference, when the first voltage is low and in a negative state, NM2 is turned on to limit the first voltage from being clamped off from the low level. That is, the first voltage is clamped to within the third voltage difference, which is less than twice the reference voltage. This prevents the low level from damaging the comparator circuit 200. When the first voltage is close to the reference voltage, there is no intervention. When the first voltage is high (i.e., high level), the first voltage is greater than the reference voltage and in an overvoltage state. By turning on PM2 and using DZ for voltage regulation, the high level is limited from damaging the comparator circuit 200. The first input voltage can be intelligently clamped, constructing a reliable and adaptive input protection front end, which significantly improves the robustness of the comparator circuit 200.
[0060] By using the circuit configurations of the three different input clamping circuits 100 described above, it is possible to meet the requirements of any voltage application with a reference voltage threshold range between GND and VDD.
[0061] This invention also proposes an electronic device including the detection and comparison circuit described in the above embodiments. The detection and comparison circuit can be incorporated into various types of electronic devices that require multiple power inputs or dynamic power switching, such as computer power supplies, server power supplies, control devices, or communication devices. It is suitable for detecting and comparing high-voltage and negative-voltage inputs, intelligently clamping the input voltage. The input clamping circuit limits the detected voltage to a certain range, reducing transistor threshold voltage offset caused by NBTI and PBTI, significantly improving the robustness of the comparison circuit, and making it suitable for high-voltage, high-precision, and high-speed detection applications.
[0062] This invention also proposes a detection comparison method, such as... Figure 6 As shown, the detection comparison method can be applied to the detection comparison circuit described above, wherein the detection comparison method includes: S601, Receive the first voltage and the reference voltage; S602. Select the target input clamping circuit based on the reference voltage; S603: Compare the difference between the first voltage and the reference voltage through the target input clamping circuit, and output the comparison result.
[0063] Specifically, this detection comparison method can be applied to, for example... Figure 2 The detection and comparison circuit shown above can be referred to for details. Figure 2 The details of the detection and comparison circuit will not be elaborated here.
[0064] Furthermore, such as Figure 7 As shown, when the reference voltage is low or medium, the target input clamping circuit is the first input clamping circuit, which is as follows: Figure 3 The input clamping circuit shown is... Step S603 specifically includes: S6031. When the difference between the first voltage and the reference voltage is within one first voltage difference, the first input clamping circuit outputs the second voltage according to the first voltage, and outputs the result after comparing the second voltage with the reference voltage. S6032. When the first voltage equals the reference voltage, the first input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage before outputting the result; wherein, the first voltage difference is the voltage difference between the source voltage and the gate voltage of the second PMOS transistor in the first input clamping circuit.
[0065] Specifically, in application scenarios where the reference voltage is low or medium, the specific determination process of the first voltage and the reference voltage, as well as the specific composition and working principle of the input clamping circuit, can be referred to as above. Figure 3The specific details of the input clamping circuit will not be elaborated here.
[0066] Furthermore, such as Figure 8 As shown, when the reference voltage is a medium or high voltage, the target input clamping circuit is a second input clamping circuit, which is as follows: Figure 4 The input clamping circuit shown, step S603 specifically includes: S6033. When the difference between the first voltage and the reference voltage is within one second voltage difference, the second input clamping circuit outputs the second voltage and compares the second voltage with the reference voltage before outputting the result. S6034. When the first voltage equals the reference voltage, the second input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage before outputting the result; wherein, the second voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor in the second input clamping circuit.
[0067] Specifically, in application scenarios where the reference voltage is a medium or high voltage, the specific determination process of the first voltage and the reference voltage, as well as the specific composition and working principle of the input clamping circuit, can be referred to the above. Figure 4 The specific details of the input clamping circuit will not be elaborated here.
[0068] Furthermore, such as Figure 9 As shown, when the reference voltage is a medium voltage, the target input clamping circuit is a third input clamping circuit. Figure 5 The input clamping circuit shown, step S603 specifically includes: S6035. When the difference between the first voltage and the reference voltage is within twice the difference of the third voltage, the third input clamping circuit outputs the second voltage and compares the second voltage with the reference voltage before outputting the result. S6036. When the first voltage equals the reference voltage, the third input clamping circuit outputs the first voltage and compares it with the reference voltage before outputting the result. The third voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor in the third input clamping circuit.
[0069] Specifically, in application scenarios where the reference voltage is a medium voltage, the specific determination process of the first voltage and the reference voltage, as well as the specific composition and working principle of the input clamping circuit, can be referred to as above. Figure 5 The specific details of the input clamping circuit will not be elaborated here.
[0070] The specific working principle and beneficial effects of the detection and comparison method in this embodiment can be referred to the specific working elements and beneficial effects of the detection and comparison circuit described above, which will not be repeated here.
[0071] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A detection and comparison circuit, characterized in that, include: An input clamping circuit, used to receive a first voltage and a reference voltage, is configured as follows: When the difference between the first voltage and the reference voltage is less than a preset threshold, the first voltage is output; When the difference between the first voltage and the reference voltage is greater than a preset threshold, a second voltage is output. The second voltage is within a preset range, which is a voltage range that includes the reference voltage. A comparison circuit is used to receive the reference voltage and the first voltage or the second voltage, and output a comparison result.
2. The detection and comparison circuit as described in claim 1, characterized in that, The input clamping circuit includes: The clamp output terminal is coupled to the comparator circuit. The first NMOS transistor, the drain of the first NMOS transistor is used to input the first voltage; The second NMOS transistor has its source coupled to the source of the first NMOS transistor, and its drain coupled to the clamp output terminal. The first diode has a first anode and a first cathode. The first anode is coupled to the gate of the first NMOS transistor and the gate of the second NMOS transistor, and the first cathode is coupled to the drain of the first NMOS transistor. The third NMOS transistor has its gate coupled to the reference power input terminal, its drain coupled to the power supply, and its source coupled to the clamp output terminal. The third PMOS transistor has its gate coupled to the reference power input terminal, its source grounded, and its drain coupled to the clamp output terminal. The second PMOS transistor has its gate coupled to the power supply and its source grounded. The first PMOS transistor has its gate grounded, its drain coupled to the drain of the second PMOS transistor and the power supply, and its source coupled to the first anode.
3. The detection and comparison circuit as described in claim 2, characterized in that, The difference between the source voltage of the second PMOS transistor and the reference voltage is twice the first voltage difference, which is the voltage difference between the source voltage and the gate voltage of the second PMOS transistor.
4. The detection and comparison circuit as described in claim 3, characterized in that, The input clamping circuit is configured as follows: When the first voltage is greater than the reference voltage, the first PMOS transistor is turned on, the gate voltage of the first PMOS transistor is equal to the source voltage of the first PMOS transistor, the first NMOS transistor is in the saturation region, the second NMOS transistor is in the linear region, the third NMOS transistor is turned off, and the voltage output from the drain of the second NMOS transistor by the third PMOS transistor is the second voltage. The difference between the second voltage and the reference voltage is within one first voltage difference. When the first voltage is equal to the reference voltage, the first NMOS transistor and the second NMOS transistor are in the linear region, the third NMOS transistor and the third PMOS transistor are cut off, and the drain of the second NMOS transistor outputs the first voltage. When the first voltage is less than the reference voltage, the first diode is turned on, the first NMOS transistor is between the linear region and the saturation region, the second NMOS transistor and the third PMOS transistor are turned off, and the third NMOS transistor clamps the voltage output by the clamping output terminal to be the second voltage. The difference between the second voltage and the reference voltage is within one first voltage difference.
5. The detection and comparison circuit as described in claim 1, characterized in that, The input clamping circuit includes: The clamp output terminal is coupled to the comparator circuit. The first PMOS transistor, the source of which is used to input the first voltage; The second PMOS transistor has its drain coupled to the clamp output terminal and its source coupled to the drain of the first PMOS transistor. The first diode has a first anode and a first cathode, the first anode being coupled to the source of the first PMOS transistor, and the first cathode being coupled to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The third PMOS transistor has its gate coupled to the reference power input terminal, its source grounded, and its drain coupled to the clamp output terminal. The third NMOS transistor has its gate coupled to the reference power input terminal, its drain coupled to the power supply, and its source coupled to the clamp output terminal. The first NMOS transistor has its gate coupled to the power supply, its source coupled to the power supply, and its drain coupled to the first cathode. The second NMOS transistor has its gate coupled to the reference power input terminal, its drain coupled to the power supply, and its source coupled to the source of the first NMOS transistor.
6. The detection and comparison circuit as described in claim 5, characterized in that, The source voltage of the second NMOS transistor is less than the reference voltage by a second voltage difference that is twice the reference voltage; wherein, the second voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor.
7. The detection and comparison circuit as described in claim 6, characterized in that, The input clamping circuit is configured as follows: When the first voltage is less than the reference voltage, the first NMOS transistor is turned on, the gate voltage of the first NMOS transistor is equal to the source voltage of the first NMOS transistor, the first PMOS transistor is in the saturation region, the second PMOS transistor is in the linear region, the third PMOS transistor is turned off, and the voltage output from the source of the second PMOS transistor by the third NMOS transistor is the second voltage. The difference between the second voltage and the reference voltage is within one second voltage difference. When the first voltage is equal to the reference voltage, the first PMOS transistor and the second PMOS transistor are in the linear region, the third NMOS transistor and the third PMOS transistor are cut off, and the source of the second PMOS transistor outputs the first voltage. When the first voltage is greater than the reference voltage, the first diode is turned on, the first PMOS transistor is between the linear region and the saturation region, the second PMOS transistor and the third NMOS transistor are turned off, and the third PMOS transistor clamps the source output voltage of the second PMOS transistor to be the second voltage. The difference between the second voltage and the reference voltage is within one second voltage difference.
8. The detection and comparison circuit as described in claim 1, characterized in that, The input clamping circuit includes: The clamp output terminal is coupled to the comparator circuit. The first PMOS transistor, the source of which is used to input the first voltage; The second PMOS transistor has its gate coupled to the reference power input terminal and its drain grounded. The third PMOS transistor has its gate coupled to the source of the second PMOS transistor, its source grounded, and its drain coupled to the clamp output terminal. The first NMOS transistor has its gate coupled to the gate of the second PMOS transistor, its drain coupled to the gate of the first PMOS transistor, and its source grounded. The second NMOS transistor has its source coupled to the clamp output terminal, its drain coupled to the drain of the first PMOS transistor, and its gate coupled to the source of the second PMOS transistor. The second diode has a second anode and a second cathode. The second anode is coupled to the drain of the first PMOS transistor and the drain of the second NMOS transistor, and the second cathode is coupled to the gate of the first PMOS transistor and the drain of the first NMOS transistor. The third NMOS transistor has its gate grounded, its source coupled to the clamp output terminal, and its drain coupled to the power supply. The fourth NMOS transistor has its gate coupled to the reference power input terminal, its source grounded, and its drain coupled to the power supply.
9. The detection and comparison circuit as described in claim 8, characterized in that, The difference between the source voltage of the second NMOS transistor and the reference voltage is a third voltage difference; the third voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor; the second diode is a Zener diode.
10. The detection and comparison circuit as described in claim 9, characterized in that, The input clamping circuit is configured as follows: When the first voltage is less than the reference voltage, the first NMOS transistor is turned on, the gate voltage of the first NMOS transistor is equal to the source voltage of the first NMOS transistor, the first PMOS transistor is in the saturation region, the second NMOS transistor is in the linear region, the third PMOS transistor is turned off, and the third NMOS transistor clamps the source output voltage of the second NMOS transistor to the second voltage, which is less than twice the third voltage difference of the reference voltage difference. When the first voltage is equal to the reference voltage, the first PMOS transistor and the second NMOS transistor are in the linear region, the third NMOS transistor and the third PMOS transistor are cut off, and the source of the second NMOS transistor outputs the first voltage. When the first voltage is greater than the reference voltage, the first PMOS transistor is between the linear region and the saturation region, the second diode is in the reverse breakdown voltage conduction state, the first NMOS transistor and the second NMOS transistor are in the saturation region, the third NMOS transistor is cut off, and the third PMOS transistor clamps the source output voltage of the second NMOS transistor to the second voltage. The difference between the second voltage and the reference voltage is within twice the difference of the third voltage.
11. An electronic device, characterized in that, The electronic device includes the detection and comparison circuit as described in any one of claims 1-10.
12. A detection and comparison method, characterized in that, The method is applied to the detection comparison circuit as described in any one of claims 1-10, wherein the method comprises: Receive the first voltage and the reference voltage; Select the target input clamping circuit based on the reference voltage; The target input clamping circuit compares the difference between the first voltage and the reference voltage and outputs the comparison result.
13. The detection and comparison method as described in claim 12, characterized in that, When the reference voltage is low VREF or medium VREF, the target input clamping circuit is a first input clamping circuit, which is the input clamping circuit as described in claim 2 above. The step of comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting the comparison result specifically includes: When the difference between the first voltage and the reference voltage is within one first voltage difference, the first input clamping circuit outputs a second voltage based on the first voltage, and compares the second voltage with the reference voltage to output the result. When the first voltage is equal to the reference voltage, the first input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage to output the result. Wherein, the first voltage difference is the voltage difference between the source voltage and the gate voltage of the second PMOS transistor in the first input clamping circuit.
14. The detection and comparison method as described in claim 12, characterized in that, When the reference voltage is medium VREF or high VREF, the target input clamping circuit is a second input clamping circuit, which is the input clamping circuit as described in claim 5 above. The step of comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting the comparison result specifically includes: When the difference between the first voltage and the reference voltage is within one second voltage difference, the second input clamping circuit outputs the second voltage and compares the second voltage with the reference voltage to output the result. When the first voltage is equal to the reference voltage, the second input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage to output the result; The second voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor in the second input clamping circuit.
15. The detection and comparison method as described in claim 12, characterized in that, When the reference voltage is at VREF, the target input clamping circuit is a third input clamping circuit, which is the input clamping circuit as described in claim 5 above. The step of comparing the difference between the first voltage and the reference voltage through the target input clamping circuit and outputting the comparison result specifically includes: When the difference between the first voltage and the reference voltage is within twice the difference of the third voltage, the third input clamping circuit outputs a second voltage and compares the second voltage with the reference voltage to output the result. When the first voltage is equal to the reference voltage, the third input clamping circuit outputs the first voltage and compares the first voltage with the reference voltage to output the result. The third voltage difference is the voltage difference between the source voltage and the gate voltage of the second NMOS transistor in the third input clamping circuit.