High-frequency switching circuit, high-frequency module, and communication device

Abstract

The invention provides a high-frequency switching circuit, a high-frequency module and a communication device, which can reduce the generation of reflected waves of high-frequency signals entering from an external terminal when a charge pump is in a stopped state. The high-frequency switching circuit includes a common terminal, a first input / output terminal, a first series FET, a first parallel FET, a charge pump, a voltage supply path, a first switch, and a second switch. The first series FET is connected to the common terminal and the first input / output terminal in a first signal path. The first parallel FET is connected between the signal path and ground. The voltage supply path is connected to a connection node to which the output of the charge pump 11 and the control electrode of the first series FET are connected. The first switch is provided in a first path connecting a first output portion of the charge pump and a connection node. The second switch is provided in the voltage supply path.

Description

Technical Field

[0001] This invention generally relates to high-frequency switching circuits, high-frequency modules, and communication devices; more specifically, it relates to a high-frequency switching circuit having a common terminal and input / output terminals, a high-frequency module having the above-mentioned high-frequency switching circuit, and a communication device having the above-mentioned high-frequency module. Background Technology

[0002] The positive and negative potential generation circuit described in Patent Document 1 includes multiple FETs and a power supply circuit that supplies voltage to the multiple FETs. The power supply circuit includes a charge pump. When a specified FET among the multiple FETs is turned on, the charge pump applies a positive voltage to the specified FET; when the specified FET is turned off, the charge pump applies a negative voltage to the specified FET.

[0003] Patent documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2016-9938 Summary of the Invention

[0005] The problem the invention aims to solve

[0006] In the positive and negative potential generation circuit described in Patent Document 1, when the charge pump is stopped, a voltage near 0V is applied to each FET, so the on-resistance of each FET does not become sufficiently small. Therefore, when a high-frequency signal from an external terminal enters and passes through each FET while the charge pump is stopped, a reflected wave is generated due to the on-resistance of each FET. The reflected wave returns to the external terminal, thereby degrading the receiving sensitivity of the external terminal due to the reflected wave.

[0007] In view of the above-mentioned problems, the present invention aims to provide a high-frequency switching circuit, a high-frequency module, and a communication device that can reduce the generation of reflected waves from high-frequency signals coming from external terminals when the charge pump is stopped.

[0008] Solution for solving the problem

[0009] One aspect of the present invention relates to a high-frequency switching circuit comprising a common terminal, a first input / output terminal, a first series FET, a first parallel FET, a charge pump, a voltage source, a voltage supply path, a first switch, and a second switch. The first input / output terminal is connected to the common terminal via a first signal path. The first series FET is connected to both the common terminal and the first input / output terminal in the first signal path. The first parallel FET is connected between the signal path between the first input / output terminal and the first series FET and ground. The charge pump has an output section from which control voltages for controlling the first series FET and for controlling the first parallel FET are supplied. The voltage source has a first output section and a second output section, respectively supplying voltages. The voltage source supplies the voltages to the charge pump from the second output section. The voltage supply path connects the first output section of the voltage source to a connection node connected to the control electrode of the first series FET. The first switch is disposed in the first path connecting the output section of the charge pump to the connection node, and is used to turn the first path on and off. The second switch is disposed in the voltage supply path, and is used to turn the voltage supply path on and off.

[0010] One embodiment of the present invention includes a high-frequency module comprising the high-frequency switching circuit and electronic components. The electronic components are connected between the first input / output terminal and an external terminal of the high-frequency switching circuit.

[0011] One embodiment of the present invention relates to a communication device comprising the aforementioned high-frequency module and signal processing circuitry. The signal processing circuitry is connected to the high-frequency module and performs signal processing on the high-frequency signals.

[0012] Invention Effects

[0013] The high-frequency switching circuit, high-frequency module, and communication device according to the present invention have the advantage of reducing the generation of reflected waves from high-frequency signals coming from external terminals when the charge pump is stopped. Attached Figure Description

[0014] Figure 1 This is a structural diagram of the high-frequency module and communication device involved in Implementation Method 1.

[0015] Figure 2 This is a structural diagram of the high-frequency switching circuit of the aforementioned high-frequency module.

[0016] Figure 3 This is a structural diagram of the high-frequency switching circuit involved in Implementation Method 2.

[0017] Figure 4 This is a structural diagram of the high-frequency switching circuit involved in Implementation Method 3. Detailed Implementation

[0018] (1) Implementation method 1

[0019] The high-frequency switching circuit 1 according to Embodiment 1 will be described in detail with reference to the accompanying drawings.

[0020] (1-1)Overview

[0021] like Figure 2 As shown, the high-frequency switching circuit 1 according to Embodiment 1 includes a common terminal 2, a first input / output terminal 3, a first series FET (Field Effect Transistor) 5, a first parallel FET 6, a charge pump 11, a voltage source 10, a voltage supply path 12, a first switch SW1, and a second switch SW2. The first input / output terminal 3 is connected to the common terminal 2 via a first signal path L1. The first series FET 5 is connected to both the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET 5 and ground. The charge pump 11 has a first output section 11b (output section). The charge pump 11 supplies control voltages for controlling the first series FET 5 and control voltages for controlling the first parallel FET 6 from the first output section 11b. The voltage source 10 has a first output section 10a and a second output section 10b that respectively supply voltages. The voltage source 10 supplies the aforementioned voltages to the charge pump 11 from the second output section 10b. Voltage supply path 12 connects the first output 10a of voltage source 10 to connection node N1, which is connected to the control electrode of the first series FET 5. A first switch SW1 is disposed on the first path M1 connecting the first output 11b of charge pump 11 to connection node N1, and is used to turn the first path M1 on and off. A second switch SW2 is disposed on voltage supply path 12, and is used to turn the voltage supply path 12 on and off.

[0022] According to this structure, when the charge pump 11 is stopped, the first path M1 is disconnected by the first switch SW1 and the voltage supply path 12 is turned on by the second switch SW2. This allows the voltage (power supply voltage) applied to the voltage supply path 12 to be applied to the control electrode of the first series FET 5, thereby switching the first series FET 5 to an on-state with sufficiently low on-resistance. Therefore, when the charge pump 11 is stopped, the reflection of the high-frequency signal entering the common terminal 2 from the external terminal due to the on-resistance of the first series FET 5 can be reduced. Consequently, the degradation of the receiving sensitivity of the external terminal due to the reflected wave returning to the external terminal can be reduced.

[0023] (1-2) Communication device

[0024] Reference Figure 1 An example of the structure of a communication device 30 having a high-frequency module 31 including a high-frequency switching circuit 1 will be described.

[0025] like Figure 1 As shown, the communication device 30 is a communication device equipped with a high-frequency module 31. The communication device 30 is, for example, a portable terminal (e.g., a smartphone), but is not limited to portable terminals; it could also be a wearable terminal (e.g., a smartwatch). The high-frequency module 31 is, for example, a module capable of supporting both 4G (fourth-generation mobile communication) and 5G (fifth-generation mobile communication) standards. The 4G standard is, for example, 3GPP (Third Generation Partnership Project) or LTE standards. The 5G standard is, for example, 5G NR (New Radio).

[0026] In addition to the high-frequency module 31, the communication device 30 also has a signal processing circuit 32 and an antenna 33.

[0027] The high-frequency module 31 is configured to amplify the received signal (high-frequency signal) received by the antenna 33 and output it to the signal processing circuit 32. Additionally, the high-frequency module 31 is configured to amplify the transmitted signal (high-frequency signal) output from the signal processing circuit 32 and transmit it from the antenna 33. The high-frequency module 31 is, for example, controlled by the signal processing circuit 32.

[0028] The signal processing circuit 32 is connected to the high-frequency module 31 and is configured to process the received signal output from the high-frequency module 31. Additionally, the signal processing circuit 32 is configured to process the transmitted signal output to the high-frequency module 31. The signal processing circuit 32 includes an RF (Radio Frequency) signal processing circuit 35 and a baseband signal processing circuit 34.

[0029] The RF signal processing circuit 35 is, for example, an RFIC (Radio Frequency Integrated Circuit) used to process high-frequency signals (transmit and receive signals). The RF signal processing circuit 35 performs down-conversion and other signal processing on the received signal output from the high-frequency module 31 and outputs the processed received signal to the baseband signal processing circuit 34. Additionally, the RF signal processing circuit 35 performs up-conversion and other signal processing on the transmitted signal output from the baseband signal processing circuit 34 and outputs the processed transmitted signal to the high-frequency module 31.

[0030] The baseband signal processing circuit 34 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 34 outputs the received signal from the RF signal processing circuit 35 to the outside. This output signal (received signal) can be used as an image signal for image display or as an audio signal for communication. Additionally, the baseband signal processing circuit 34 generates a transmit signal based on the baseband signal (e.g., audio and image signals) input from the outside, and outputs the generated transmit signal to the RF signal processing circuit 35.

[0031] (1-3) Example of the structure of a high-frequency module

[0032] like Figure 1 As shown, the high-frequency module 31 includes: a high-frequency switching circuit 1, and one or more (in Figure 1 In the example, there are two) receiving components 50 (electronic components), and one or more (in Figure 1 In the example, there are two) transmitting components 51 (electronic components) and multiple external terminals 40a~40c.

[0033] The receiving component 50 is an electronic component used to process the received signal. Figure 1 In this example, one or more receiving components 50 are receiving filters 36 and low-noise amplifiers 38. One or more receiving components 50 are connected between the first input / output terminal 3 and the external terminal 40b.

[0034] The transmitting component 51 is an electronic component used to process the transmitted signal. Figure 1 In this example, one or more transmitting components 51 are transmitting filter 37 and power amplifier 39. One or more transmitting components 51 are connected between the second input / output terminal 4 and the external terminal 40c.

[0035] External terminal 40a is an antenna terminal for connecting antenna 33. External terminal 40b is an output terminal connected to the input section (not shown) of signal processing circuit 32, used to output the received signal processed by high-frequency module 31 to the input section of signal processing circuit 32. External terminal 40c is an output terminal connected to the output section (not shown) of signal processing circuit 32, used to input the transmitted signal processed by signal processing circuit 32 to the input section of high-frequency module 31.

[0036] The high-frequency switching circuit 1 is, for example, an antenna switch. The high-frequency switching circuit 1 has a common terminal 2, and multiple (in...) Figure 2In this example, there are two input / output terminals (first input / output terminal 3 and second input / output terminal 4). Furthermore, input / output terminals are also called selection terminals. The common terminal 2 can be selectively connected to either the first input / output terminal 3 or the second input / output terminal 4. The common terminal 2 is connected to the external terminal 40a (antenna terminal). The first input / output terminal 3 is connected to the external terminal 40b via one or more receiving components 50. The second input / output terminal 4 is connected to the external terminal 40c via one or more transmitting components 51.

[0037] The receiving filter 36 has an input section 36a and an output section 36b. The input section 36a is connected to the first input / output terminal 3 of the high-frequency switching circuit 1. The output section 36b is connected to the input section 38a of the low-noise amplifier 38. The receiving filter 36 receives a signal (received signal) from the input section 36a, limits the input signal to the receiving frequency band of the first communication frequency band, allows it to pass through, and outputs the passed signal from the output section 36b.

[0038] The transmitting filter 37 has an input section 37a and an output section 37b. The input section 37a is connected to the output section 39b of the power amplifier 39. The output section 37b is connected to the second input / output terminal 4 of the high-frequency switching circuit 1. The transmitting filter 37 receives a signal (transmit signal) from the input section 37a, restricts the input signal to the transmission frequency band of the second communication band, allows it to pass through, and outputs the passed signal from the output section 37b. Furthermore, the second communication band can be either the same as the first communication band or a different communication band.

[0039] The low-noise amplifier 38 has an input section 38a and an output section 38b. The input section 38a is connected to the output section 36b of the receiving filter 36. The output section 38b is connected to an external terminal 40b. The low-noise amplifier 38 amplifies the signal (received signal) input to the input section 38a and outputs the amplified signal from the output section 38b.

[0040] The power amplifier 39 has an input section 39a and an output section 39b. The input section 39a is connected to an external terminal 40c. The output section 39b is connected to the input section 37a of the transmit filter 37. The power amplifier 39 amplifies the signal (transmit signal) input to the input section 39a and outputs the amplified signal from the output section 39b.

[0041] (1-4) Structure of high-frequency switching circuit

[0042] Reference Figure 2 The structure of high-frequency switching circuit 1 is described in detail. For example... Figure 2As shown, in addition to the aforementioned common terminal 2, first input / output terminal 3, and second input / output terminal 4, the high-frequency switching circuit 1 also includes a first series FET 5, a first parallel FET 6, a second series FET 7, a second parallel FET 8, a third parallel FET 9 (parallel FET), a voltage source 10, a charge pump 11, a voltage supply path 12, first to fifth level shifters 13 to 17, resistors R1 to R5, a first switch SW1, and a second switch SW2. Furthermore, the voltage source 10 may not be included in the structure of the high-frequency switching circuit 1.

[0043] As described above, common terminal 2 and external terminal 40a (refer to...) Figure 1 )connect.

[0044] As described above, the first input / output terminal 3 is connected via one or more receiving components 50 (see reference 50). Figure 1 ) to connect with external terminal 40b (refer to Figure 1 The first input / output terminal 3 is connected to the common terminal 2 via the first signal path L1.

[0045] As described above, the second input / output terminal 4 is connected to the external terminal 40c (see reference) via one or more transmitting components 51 (see reference). Figure 1 The second input / output terminal 4 is connected to the common terminal 2 via the second signal path L2.

[0046] The first series FET 5 is, for example, an N-channel enhancement-mode MOSFET. The first series FET 5 is connected in series with the first signal path L1. That is, the first series FET 5 is connected to the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first series FET 5 turns the first signal path L1 on and off by switching the first series FET 5 on and off. The first series FET 5 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first signal path L1 has signal paths L11 and L12. The first main electrode of the first series FET 5 is connected to the common terminal 2 via signal path L11. The second main electrode of the first series FET 5 is connected to the first input / output terminal 3 via signal path L12. The control electrode of the first series FET 5 is indirectly connected to the connection node N1 via resistor R1 and the first level shifter 13.

[0047] The first parallel FET 6 is, for example, an N-channel enhancement-mode MOSFET. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET 5 and ground. Switching the first parallel FET 6 on and off connects the signal path L12 to ground. The first parallel FET 6 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first main electrode of the first parallel FET 6 is connected to a connection node N2 located on the signal path L12. The second main electrode of the first parallel FET 6 is connected to ground. The control electrode of the first parallel FET 6 is indirectly connected to the connection node N1 via a resistor R2 and a second level shifter 14.

[0048] The second series FET 7 is, for example, an N-channel enhancement-mode MOSFET. The second series FET 7 is connected in series with the second signal path L2. That is, the second series FET 7 is connected to the common terminal 2 and the second input / output terminal 4 in the second signal path L2. The second series FET 7 turns the second signal path L2 on and off by switching the second series FET 7 on and off. The second series FET 7 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The second signal path L2 has signal paths L21 and L12. The first main electrode of the second series FET 7 is connected to the common terminal 2 via signal path L21. The second main electrode of the second series FET 7 is connected to the second input / output terminal 4 via signal path L22. The control electrode of the second series FET 7 is indirectly connected to the connection node N1 via resistor R3 and the first level shifter 15.

[0049] The second parallel FET 8 is, for example, an N-channel enhancement-mode MOSFET. The second parallel FET 8 is connected between the signal path L22 between the second input / output terminal 4 and the second series FET 7 and ground. Switching the second parallel FET 8 on and off connects the signal path L22 to ground. The second parallel FET 8 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first main electrode of the second parallel FET 8 is connected to a connection node N3 located in the signal path L22. The second main electrode of the second parallel FET 8 is connected to ground. The control electrode of the second parallel FET 8 is indirectly connected to the connection node N1 via a resistor R4 and a fourth level shifter 16.

[0050] The third parallel FET 9 is, for example, an N-channel enhancement-mode MOSFET. The third parallel FET 9 is connected to a common terminal 2, and switching the third parallel FET 9 on and off connects and disconnects the common terminal 2 from ground. The third parallel FET 9 has a control electrode (e.g., gate), a first main electrode (e.g., drain), and a second main electrode (e.g., source). The first main electrode of the third parallel FET 9 is connected to a connection node N5 located in signal path L3. Figure 1 In the example, signal path L3 between common terminal 2 in signal path L11 and connection node N4, and signal path L3 between common terminal 2 in signal path L21 and connection node N4 constitute a common signal path. The second main electrode of the third parallel FET 9 is connected to ground. The control electrode of the third parallel FET 9 is indirectly connected to connection node N1 via resistor R5 and fifth level shifter 17.

[0051] In the following description, without distinguishing between the first series FET 5, the first parallel FET 6, the second series FET 7, the second parallel FET 8, and the third parallel FET 9, these FETs are sometimes referred to as FET 5~9.

[0052] Voltage source 10 outputs a constant power supply voltage. Voltage source 10 outputs the power supply voltage based on a power supply voltage from a power supply circuit (not shown). Voltage source 10 has a first output section 10a and a second output section 10b. The first output section 10a is connected to one end of the voltage supply path 12. The second output section 10b is connected to the input section 11a of the charge pump 11. Voltage source 10 applies the power supply voltage output from the first output section 10a to the voltage supply path 12. Additionally, voltage source 10 inputs the power supply voltage output from the second output section 10b to the input section 11a of the charge pump 11.

[0053] The charge pump 11 supplies positive and negative voltages based on the power supply voltage input from the voltage source 10, serving as the control electrode for controlling each of the FETs in FETs 5-9. Figure 2 In this example, charge pump 11 supplies control voltage to the first input sections 13a-17a of the first to fifth level shifters 13-17. Here, the positive voltage is the control voltage used to switch FETs 5-9 to the ON position. Conversely, the negative voltage is the control voltage used to switch FETs 5-9 to the OFF position.

[0054] More specifically, the charge pump 11 has an input section 11a, a first output section 11b, and a second output section 11c.

[0055] The input section 11a is connected to the second output section 10b of the voltage source 10 and is input with the power supply voltage from the voltage source 10.

[0056] The first output unit 11b is connected to the connection node N1 via the first path M1. A first switch SW1 (described later) is provided in the first path M1. The connection node N1 is connected to the first input units 13a-17a of each of the first to fifth level shifters 13-17. Therefore, the first output unit 11b is connected to the first input units 13a-17a of each of the first to fifth level shifters 13-17 via the first switch SW1. Furthermore, the first to fifth level shifters 13-17 correspond one-to-one with FETs 5-9. Specifically, the first level shifter 13 corresponds to the first series FET 5, the second level shifter 14 corresponds to the first parallel FET 6, the third level shifter 15 corresponds to the second series FET 7, the fourth level shifter 16 corresponds to the second parallel FET 8, and the fifth level shifter 17 corresponds to the parallel FET 9. Furthermore, the outputs 13c to 17c of each of the first to fifth level shifters 13 to 17 are connected to the control electrodes of the corresponding FETs 5 to 9. Therefore, the first output 11b is indirectly connected to the control electrodes of the corresponding FETs 5 to 9 via the first switch SW1 and the corresponding level shifter among the first to fifth level shifters 13 to 17. The second output 11c is connected to the second inputs 13b to 17b of each of the first to fifth level shifters 13 to 17. The charge pump 11 boosts the power supply voltage input to the input section 11a to generate a positive voltage and outputs the generated positive voltage from the first output section 11b. Alternatively, the charge pump 11 can, for example, multiply the generated positive voltage by a negative factor to generate a negative voltage and output the generated negative voltage from the second output section 11c.

[0057] Voltage supply path 12 connects the first output 10a of voltage source 10 to connection node N1. The power supply voltage output from the first output 10a of voltage source 10 is applied to voltage supply path 12. A second switch SW2 (described later) is provided in voltage supply path 12. Furthermore, as described above, connection node N1 is connected to the first inputs 13a-17a of each of the first to fifth level shifters 13-17. Therefore, voltage supply path 12 supplies the power supply voltage to the first inputs 13a-17a of each of the first to fifth level shifters 13-17 via the second switch SW2.

[0058] A first switch SW1 is disposed on the first path M1 and is used to turn the first path M1 on and off. The first switch SW1 can selectively switch between on and off according to a control signal from a control unit (not shown). The first switch SW1 turns the first path M1 on by switching on and turns the first path M1 off by switching off. By turning the first path M1 on and off by the first switch SW1, the supply and cessation of the positive voltage from the first output 11b of the charge pump 11 to the first inputs 13a to 17a of the first to fifth level shifters 13 to 17 are selectively switched.

[0059] The second switch SW2 is disposed in the voltage supply path 12 and is used to turn the voltage supply path 12 on and off. The second switch SW2 can selectively switch between on and off according to a control signal from a control unit (not shown). The second switch SW2 turns on the voltage supply path 12 by switching to on and turns off the voltage supply path 12 by switching to off. By turning the voltage supply path 12 on and off by the second switch SW2, the supply and cessation of the positive voltage from the first output 10a of the voltage source 10 to the first inputs 13a to 17a of the first level shifters 13 to 17 are switched.

[0060] The high-frequency switching circuit 1 has multiple operating modes, including a transmit / receive mode and a low-power mode. The transmit / receive mode is the mode in which the communication device 30 equipped with the high-frequency switching circuit 1 performs transmit and receive operations. The low-power mode is the mode in which the communication device 30 does not perform transmit or receive operations and remains in standby mode. In the low-power mode, the charge pump stops. In the transmit / receive mode, the output voltage of the first output section 11b of the charge pump 11 is applied to the connection node N1 by switching the first switch SW1 to the on position and the second switch SW2 to the off position. In the low-power mode, the power supply voltage applied to the voltage supply path 12 is applied to the connection node N1 by switching the first switch SW1 to the off position and the second switch SW2 to the on position.

[0061] The first level shifter 13 has a first input section 13a, a second input section 13b, an output section 13c (first output section), and a control signal input section 13d. The first input section 13a is connected to a connection node N1 and is input with a voltage (positive voltage or power supply voltage) applied to the connection node N1. The second input section 13b is connected to the second output section 11c of the charge pump 11 and is input with the output voltage (negative voltage) of the second output section 11c. The control signal input section 13d is selectively input with either a high-level signal or a low-level signal as a control signal from a control section (not shown). The output section 13c is connected to the control electrode of the first series FET 5 via a resistor R1. The first level shifter 13 selectively outputs from the output section 13c either the voltage (positive voltage or power supply voltage) input to the first input section 13a or the voltage (negative voltage) input to the second input section 13b, depending on the control signal input to the control signal input section 13d. For example, when a high-level signal is input to the control signal input unit 13d, the first level shifter 13 outputs a voltage from the output unit 13c that is input to the first input unit 13a; when a low-level signal is input to the control signal input unit 13d, the first level shifter 13 outputs a voltage from the output unit 13c that is input to the second input unit 13b. The output voltage of the output unit 13c is applied to the control electrode of the first series FET 5, thereby switching the first series FET 5 on and off.

[0062] The second level shifter 14 has a first input section 14a (third input section), a second input section 14b (fourth input section), an output section 14c (second output section), and a control signal input section 14d. The first input section 14a (third input section) is connected to a connection node N1 and is input with a voltage (positive voltage or power supply voltage) applied to the connection node N1. The second input section 14b (fourth input section) is connected to the second output section 11c of the charge pump 11 and is input with the output voltage (negative voltage) of the second output section 11c. The control signal input section 14d is selectively input with either a high-level signal or a low-level signal as a control signal from a control section (not shown). The output section 14c is connected to the control electrode of the first parallel FET 6 via a resistor R2. The second level shifter 14, based on the control signal input to the control signal input section 14d, selectively outputs from the output section 14c either the voltage (positive voltage or power supply voltage) input to the first input section 14a or the voltage (negative voltage) input to the second input section 14b. For example, when a high-level signal is input to the control signal input unit 14d, the second level shifter 14 outputs a voltage from the output unit 14c that is input to the first input unit 14a; when a low-level signal is input to the control signal input unit 14d, the second level shifter 14 outputs a voltage from the output unit 14c that is input to the second input unit 14b. The output voltage of the output unit 14c is applied to the control electrode of the first parallel FET 6, thereby switching the first parallel FET 6 on and off.

[0063] The third level shifter 15 has a first input section 15a, a second input section 15b, an output section 15c, and a control signal input section 15d. The first input section 15a is connected to a connection node N1 and is input with a voltage (positive voltage or power supply voltage) applied to the connection node N1. The second input section 15b is connected to the second output section 11c of the charge pump 11 and is input with the output voltage (negative voltage) of the second output section 11c. The control signal input section 15d is selectively input with either a high-level signal or a low-level signal as a control signal from a control section (not shown). The output section 15c is connected to the control electrode of the second series FET 7 via a resistor R3. The third level shifter 15, based on the control signal input to the control signal input section 15d, selectively outputs from the output section 15c either the voltage (positive voltage or power supply voltage) input to the first input section 15a or the voltage (negative voltage) input to the second input section 15b. For example, when a high-level signal is input to the control signal input unit 15d, the third level shifter 15 outputs a voltage from the output unit 15c that is input to the first input unit 14a; when a low-level signal is input to the control signal input unit 15d, the third level shifter 15 outputs a voltage from the output unit 15c that is input to the second input unit 14b. The output voltage of the output unit 15c is applied to the control electrode of the second series FET 7, thereby switching the second series FET 7 on and off.

[0064] The fourth level shifter 16 has a first input section 16a, a second input section 16b, an output section 16c, and a control signal input section 16d. The first input section 16a is connected to a connection node N1 and receives a voltage (positive voltage or power supply voltage) applied to the connection node N1. The second input section 16b is connected to the second output section 11c of the charge pump 11 and receives the output voltage (negative voltage) of the second output section 11c. The control signal input section 16d is selectively input with either a high-level signal or a low-level signal as a control signal from a control section (not shown). The output section 16c is connected to the control electrode of the second parallel FET 8 via a resistor R4. The fourth level shifter 16, based on the control signal input to the control signal input section 16d, selectively outputs from the output section 16c either the voltage (positive voltage or power supply voltage) input to the first input section 16a or the voltage (negative voltage) input to the second input section 16b. For example, when a high-level signal is input to the control signal input unit 16d, the fourth level shifter 16 outputs a voltage from the output unit 16c that is input to the first input unit 16a; when a low-level signal is input to the control signal input unit 16d, the fourth level shifter 16 outputs a voltage from the output unit 16c that is input to the second input unit 16b. The output voltage of the output unit 16c is applied to the control electrode of the second parallel FET 8, thereby switching the second parallel FET 8 on and off.

[0065] The fifth level shifter 17 has a first input section 17a, a second input section 17b, an output section 17c, and a control signal input section 17d. The first input section 17a is connected to a connection node N1 and receives a voltage (positive voltage or power supply voltage) applied to the connection node N1. The second input section 17b is connected to the second output section 11c of the charge pump 11 and receives the output voltage (negative voltage) of the second output section 11c. The control signal input section 17d is selectively input with either a high-level signal or a low-level signal as a control signal from a control section (not shown). The output section 17c is connected to the control electrode of the third parallel FET 9 via a resistor R5. The fifth level shifter 17, based on the control signal input to the control signal input section 17d, selectively outputs from the output section 17c either the voltage (positive voltage or power supply voltage) input to the first input section 17a or the voltage (negative voltage) input to the second input section 17b. For example, when a high-level signal is input to the control signal input unit 17d, the fifth level shifter 17 outputs a voltage from the output unit 17c that is input to the first input unit 17a; when a low-level signal is input to the control signal input unit 17d, the fifth level shifter 17 outputs a voltage from the output unit 17c that is input to the second input unit 17b. The output voltage of the output unit 17c is applied to the control electrode of the third parallel FET 9, thereby switching the third parallel FET 9 on and off.

[0066] (1-5) Operation of high-frequency switching circuit

[0067] Reference Figure 2 This will explain the operation of the high-frequency switching circuit 1.

[0068] (1-5-1) Actions in Sending Mode

[0069] In transmit / receive mode, charge pump 11 operates to generate positive and negative voltages. The generated positive voltage is output from the first output unit 11b, and the generated negative voltage is output from the second output unit 11c. Furthermore, in transmit / receive mode, the first switch SW1 is switched on, and the second switch SW2 is switched off. Therefore, the output voltage (power supply voltage) of the first output unit 10a of voltage source 10 is not applied to connection node N1, and the output voltage (positive voltage) of the first output unit 11b of charge pump 11 is applied to connection node N1. Consequently, the output voltage (positive voltage) of the first output unit 11b of charge pump 11 is input to the first input units 13a-17a of the first to fifth level shifters 13-17. Additionally, the output voltage (negative voltage) of the second output unit 11c of charge pump 11 is input to the second input units 13b-17b of the first to fifth level shifters 13-17.

[0070] Furthermore, when the common terminal 2 is selectively connected to the first input / output terminal 3, the first series FET 5 among FETs 5-9 is switched on, and the remaining FETs 6-9 are switched off. That is, a high-level signal is input to the control signal input section 13d of the first level shifter 13, and a low-level signal is input to the control signal input sections 14d-17d of the second to fifth level shifters 14-17. Consequently, the first series FET 5 is switched on, and the remaining FETs 6-9 are switched off. As a result, the common terminal 2 is selectively connected to the first input / output terminal 3. That is, the first signal path L1 between the common terminal 2 and the first input / output terminal 3 is turned on, and the second signal path L2 between the common terminal 2 and the second input / output terminal 4 is turned off.

[0071] Furthermore, when the common terminal 2 is selectively connected to the second input / output terminal 4, the second series FET 7 among FETs 5-9 is switched on, while the remaining FETs 5, 6, 8-9 are switched off. That is, a high-level signal is input to the control signal input section 15d of the third level shifter 15, and low-level signals are input to the control signal input sections 13d, 14d, 16d, and 17d of the first, second, and fourth-to-fifth level shifters 13, 14, 16, and 17d. Consequently, the second series FET 7 is switched on, while the remaining FETs 5, 6, 8, and 9 are switched off. As a result, the common terminal 2 is selectively connected to the second input / output terminal 4. That is, the second signal path L2 between the common terminal 2 and the second input / output terminal 4 is turned on, and the first signal path L1 between the common terminal 2 and the first input / output terminal 3 is cut off.

[0072] (1-5-2) Operation in low power mode

[0073] In low-power mode, charge pump 11 stops generating neither positive nor negative voltage, and outputs a voltage near 0V from the first output 11b and the second output 11c. Additionally, in low-power mode, the first switch SW1 is switched off, and the second switch SW2 is switched on. Therefore, the output voltage (voltage near 0V) of the first output 11b of charge pump 11 is not applied to connection node N1, and the output voltage (power supply voltage) of the first output 10a of voltage source 10 is applied to connection node N1. Consequently, the output voltage (power supply voltage) of the first output 10a of voltage source 10 is input to the first inputs 13a-17a of the first to fifth level shifters 13-17. Furthermore, the output voltage (voltage near 0V) of the second output 11c of charge pump 11 is input to the second inputs 13b-17b of the first to fifth level shifters 13-17.

[0074] Furthermore, in low-power mode, all FETs 5-9 are switched on. That is, high-level signals are input to the control signal input sections 13d-15d of the first to fifth level shifters 13-17. Consequently, the output voltage (power supply voltage) of the voltage source 10 applied to the voltage supply path 12 is applied to the control electrodes of FETs 5-9, thereby switching FETs 5-9 on. In this on-state, FETs 5-9 are switched on by the power supply voltage, so the on-resistance of FETs 5-9 in the on-state is sufficiently small. Therefore, in low-power mode, it is possible to reduce the occurrence of high-frequency signal reflections within the high-frequency switching circuit 1 when a high-frequency signal transmitted from a nearby external terminal enters the high-frequency switching circuit 1. As a result, it is possible to reduce the occurrence of reflected waves returning to the external terminal.

[0075] (1-5-3) Explanation on reducing high-frequency signal reflections in high-frequency switching circuits

[0076] When an external terminal is present near the communication device 30 equipped with the high-frequency switching circuit 1, high-frequency signals transmitted from the external terminal may sometimes enter the interior of the communication device 30 (i.e., the interior of the high-frequency switching circuit 1) through the antenna 33 of the communication device 30. Consider the following case: when the communication device 30 is in low-power mode, high-frequency signals transmitted from the external terminal enter the interior of the high-frequency switching circuit 1. In this case, as described above, in low-power mode, by applying a power supply voltage to the control electrodes of FETs 5-9, the on-resistance of FETs 5-9 in the on state is sufficiently small. It can be considered as having virtually no on-resistance. Therefore, in low-power mode, when the high-frequency signal entering from the aforementioned external terminal passes through each FET 5-9, almost no distortion (reflected wave) is generated due to the on-resistance of each FET 5-9. That is, since the on-resistance of FETs 5-9 is sufficiently small, almost no reflected wave of the high-frequency signal is generated.

[0077] Furthermore, most of the high-frequency signal entering the high-frequency switching circuit 1 flows to ground from the common terminal 2 through the third parallel FET 9, so the strength of the remaining high-frequency signal is sufficiently small. Therefore, even if the remaining high-frequency signal generates a reflected wave, the intensity of the reflected wave is sufficiently small. Additionally, the high-frequency signal flowing in the first signal path L1 flows to ground through the first series FET 5 and the first parallel FET 6, so almost no reflected wave is generated from the high-frequency signal. Similarly, the high-frequency signal flowing in the second signal path L2 flows to ground through the second series FET 7 and the second parallel FET 8, so almost no reflected wave is generated from the high-frequency signal. Therefore, in low-power mode, the reflected wave of the high-frequency signal is reduced in the high-frequency switching circuit 1. As a result, the degradation of the receiving sensitivity of the external terminal due to the reflected wave returning to the external terminal can be reduced.

[0078] (1-6) Comparative Examples

[0079] The high-frequency switching circuit of the comparative example (hereinafter referred to as the "comparative example") will be described. The comparative example differs from the high-frequency switching circuit 1 of Embodiment 1 in that the voltage supply path 12, the first switch SW1, and the second switch SW2 are omitted. Therefore, in the comparative example, regardless of the transmit / receive mode or the low-power mode, the output voltage of the first output section 11b of the charge pump 11 is input to the first input sections 13a to 17a of the first to fifth level shifters 13 to 17. In the low-power mode, since the charge pump 11 stops, no positive or negative voltage is generated, and the output voltages of the first output section 11b and the second output section 11c of the charge pump 11 become voltages near 0V. In the comparative example, in the low-power mode, FETs 5 to 9 are all switched on due to the output voltage of the first output section 11b of the charge pump 11.

[0080] However, in the comparative example, in low-power mode, a voltage near 0V is applied to the control electrodes of FETs 5-9 from the outputs 13c-17c of the first to fifth level shifters 13-17 instead of a positive voltage. Therefore, FETs 5-9 in the comparative example cannot be sufficiently switched on, resulting in a sufficiently high on-resistance when on. In this state, if a high-frequency signal sent from an external terminal enters the high-frequency switching circuit of the comparative example, distortion (i.e., reflected waves) caused by the sufficiently high on-resistance occurs as the incoming high-frequency signal flows through each FET 5-9. The resulting reflected waves return to the external terminal, thereby degrading the receiving sensitivity of the external terminal. In contrast, the high-frequency switching circuit 1 of Embodiment 1, as described above, can reduce the reflected waves, thus reducing the degradation of the receiving sensitivity of the external terminal.

[0081] (1-7) Effects

[0082] The high-frequency switching circuit 1 according to Embodiment 1 includes a common terminal 2, a first input / output terminal 3, a first series FET 5, a first parallel FET 6, a charge pump 11, a voltage source 10, a voltage supply path 12, a first switch SW1, and a second switch SW2. The first input / output terminal 3 is connected to the common terminal 2 via a first signal path L1. The first series FET 5 is connected to both the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET 5 and ground. The charge pump 11 has a first output section 11b (output section). The charge pump 11 supplies control voltages for controlling the first series FET 5 and control voltages for controlling the first parallel FET 6 from the first output section 11b. The voltage source 10 has a first output section 10a and a second output section 10b that respectively supply voltages. The voltage source 10 supplies the aforementioned voltages to the charge pump 11 from the second output section 10b. Voltage supply path 12 connects the first output 10a of voltage source 10 to connection node N1, which is connected to the control electrode of the first series FET 5. A first switch SW1 is disposed on the first path M1 connecting the first output 11b of charge pump 11 to connection node N1, and is used to turn the first path M1 on and off. A second switch SW2 is disposed on voltage supply path 12, and is used to turn the voltage supply path 12 on and off.

[0083] According to this structure, when the charge pump 11 is stopped, the first path M1 is disconnected by the first switch SW1 and the voltage supply path 12 is turned on by the second switch SW2. This allows the voltage applied to the voltage supply path 12 (e.g., the power supply voltage) to be applied to the control electrode of the first series FET 5, thereby switching the first series FET 5 to an on-state with sufficiently low on-resistance. Therefore, when the charge pump 11 is stopped, the reflection of the high-frequency signal entering the common terminal 2 from the external terminal due to the on-resistance of the first series FET 5 can be reduced. Consequently, the degradation of the receiving sensitivity of the external terminal due to the reflected wave returning to the external terminal can be reduced.

[0084] Furthermore, in the high-frequency switching circuit 1 according to Embodiment 1, the control electrode of the first parallel FET 6 is connected to the path that connects the connection node N1 to the control electrode of the first series FET 5 (in Figure 2 In the example, it is the connection node N1).

[0085] According to this structure, when the charge pump 11 is stopped, the first path M1 is disconnected by the first switch SW1 and the voltage supply path 12 is turned on by the second switch SW2. This allows the voltage applied to the voltage supply path 12 (e.g., the power supply voltage) to still be applied to the control electrode of the first parallel FET 6, thereby switching the first parallel FET 6 to an on-state with sufficiently low on-resistance. Therefore, when the charge pump 11 is stopped, the generation of reflected waves caused by the on-resistance of the first parallel FET 6 when it passes through the common terminal 2 from the external terminal can be reduced, and the high-frequency signal can be directed to ground. As a result, the degradation of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be further reduced.

[0086] Furthermore, the high-frequency switching circuit 1 according to Embodiment 1 also includes a second input / output terminal 4, a second series FET 7, and a second parallel FET 8. The second input / output terminal 4 is connected to the common terminal 2 via a second signal path L2. The second series FET 7 is connected to both the common terminal 2 and the second input / output terminal 4 in the second signal path L2. The second parallel FET 8 is connected between the signal path L22 between the second input / output terminal 4 and the second series FET 7 and ground. The connection node N1 is also connected to the control electrode of the second series FET 7.

[0087] According to this structure, the second series FET 7, located in the second signal path L2, similarly to the first series FET 5, can reduce the generation of reflected waves caused by the on-resistance of the second series FET 7 when a high-frequency signal entering the common terminal 2 from the external terminal passes through the second series FET 7 while the charge pump 11 is in a stopped state. As a result, the degradation of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal can be further reduced.

[0088] Furthermore, in the high-frequency switching circuit 1 according to Embodiment 1, the charge pump 11 supplies control voltages for controlling each of the FETs 5-9 based on voltages from the voltage source 10 (e.g., power supply voltage). According to this structure, the voltage source 10 used for the voltage supply path 12 can also be used as the voltage source for the charge pump 11. As a result, the high-frequency switching circuit 1 can be miniaturized.

[0089] In addition, the high-frequency switching circuit 1 according to Embodiment 1 also includes a third parallel FET 9 (parallel FET). The third parallel FET 9 is connected between the common terminal 2 and ground.

[0090] According to this structure, the third parallel FET 9, connected between the common terminal 2 and ground, similarly to the first series FET 5, can reduce the generation of reflected waves caused by the on-resistance of the third parallel FET 9 when a high-frequency signal entering the common terminal 2 from an external terminal passes through the third parallel FET 9 while the charge pump 11 is stopped, and can also allow the high-frequency signal to flow to ground. As a result, the degradation of the receiving sensitivity of the external terminal due to the reflected wave returning to the external terminal can be further reduced.

[0091] Furthermore, the high-frequency switching circuit 1 according to Embodiment 1 also includes a first level shifter 13 and a second level shifter 14. The first level shifter 13 controls a first series FET 5. The second level shifter 14 controls a first parallel FET 6. The first level shifter 13 has a first input section 13a, a second input section 13b, and an output section 13c (first output section). The first input section 13a is connected to a connection node N1. The second input section 13b is connected to a charge pump 11 (negative voltage supply circuit). The output section 13c is connected to the control electrode of the first series FET 5, thereby selectively outputting the voltage input to the first input section 13a and the voltage input to the second input section 13b. The second level shifter 14 has a first input section 14a (third input section), a second input section 14b (fourth input section), and an output section 14c (second output section). The first input section 14a is connected to a path M1a or a connection node N1 (connection node N1 in Embodiment 1). Path M1a is the path between the first output section 11b (output section) of charge pump 11 and the first switch SW1. The second input section 14b is connected to charge pump 11 (negative voltage supply circuit). The output section 14c is connected to the control electrode of the first parallel FET 6, thereby selectively outputting the voltage input to the first input section 14a and the voltage input to the second input section 14b.

[0092] According to this structure, even with the first level shifter 13 and the second level shifter 14, it is possible to reduce the generation of reflected waves caused by the on-resistance of the FETs when a high-frequency signal entering the common terminal 2 from the external terminal passes through the FETs (at least the first series FET 5 among the first series FET 5 and the first parallel FET 6 (in Embodiment 1, the first series FET 5 and the first parallel FET 6)) when the charge pump 11 is stopped. As a result, it is possible to reduce the degradation of the receiving sensitivity of the external terminal due to the reflected waves returning to the external terminal.

[0093] Furthermore, the high-frequency module 31 according to Embodiment 1 includes a high-frequency switching circuit 1 and an electronic component 50. The electronic component 50 is connected between the first input / output terminal 3 of the high-frequency switching circuit 1 and the external terminal 40b. According to this structure, a high-frequency module 31 that functions as the high-frequency switching circuit 1 can be provided.

[0094] Furthermore, the communication device 30 according to Embodiment 1 includes a high-frequency module 31 and a signal processing circuit 32. The signal processing circuit 32 is connected to the high-frequency module 31 to perform signal processing on the high-frequency signal. According to this structure, a communication device 30 that functions as a high-frequency switching circuit 1 can be provided.

[0095] (1-8) Variations

[0096] A variation of Implementation 1 will be described.

[0097] In Embodiment 1, the following example illustrates a situation where one or more receiving components 50 are connected between the first input / output terminal 3 and the external terminal 40b, and one or more transmitting components 51 are connected between the second input / output terminal 4 and the external terminal 40c. However, it is also possible for one or more transmitting components 51 to be connected between the first input / output terminal 3 and the external terminal 40b, and for one or more receiving components 50 to be connected between the second input / output terminal 4 and the external terminal 40c. In this case, the external terminal 40b becomes an input terminal for inputting the transmitted signal processed by the signal processing circuit 32 to the high-frequency module 31, and the external terminal 40c becomes an output terminal for outputting the received signal processed by the high-frequency module 31 to the input section of the signal processing circuit 32.

[0098] (2) Implementation Method 2

[0099] Reference Figure 3 The high-frequency switching circuit 1 according to Embodiment 2 will be described below. In the following description, the same reference numerals are sometimes used for structures that are the same as those in Embodiment 1, and the description is omitted.

[0100] (2-1) Structure

[0101] In Embodiment 1, the case where the control electrodes of FETs 5-9 are all connected to connection node N1 is illustrated. More specifically, in Embodiment 1, the case where the first input sections 13a-17a of the first to fifth level shifters 13-17 are all connected to connection node N1 is illustrated. In contrast, as... Figure 3As shown, in Embodiment 2, similarly to Embodiment 1, the control electrodes of the first series FET 5 and the second series FET 7 among FETs 5-9 are each connected to the connection node N1. Furthermore, the control electrodes of the remaining first to third parallel FETs 6, 8, and 9 are connected to the connection node N6 located in path M1a. Here, path M1a is the portion of the first path M1 between the first output section 11b of the charge pump 11 and the connection node N1, between the first output section 11b of the charge pump 11 and the first switch SW1.

[0102] More specifically, in Embodiment 2, the first input portions 13a and 15a of the first level shifter 13 and the third level shifter 15, corresponding to the first series FET 5 and the second series FET 7, are connected to the connection node N1. On the other hand, the first input portions 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17, corresponding to the remaining first to third parallel FETs 6, 8, and 9, are connected to the connection node N6 provided in path M1a.

[0103] That is, in Embodiment 2, depending on whether the first switch SW1 and the second switch SW2 are turned on or off, one of the output voltage of the first output section 11b of the charge pump 11 and the output voltage of the first output section 10a of the voltage source 10 is selectively applied to the first input sections 13a and 15a of the first level shifter 13 and the third level shifter 15. However, regardless of whether the first switch and the second switch are turned on or off, the output voltage of the first output section 11b of the charge pump 11 is always applied to the first input sections 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17.

[0104] (2-2) Actions

[0105] In the transmit / receive mode of Embodiment 2, similarly to Embodiment 1, the first switch SW1 is switched on, and the second switch SW2 is switched off. Therefore, in Embodiment 2, also similarly to Embodiment 1, the output voltage (positive voltage) of the first output section 11b of the charge pump 11 is applied to the first input sections 13a-17a of the first to fifth level shifters 13-17, and the output voltage (negative voltage) of the second output section 11c of the charge pump 11 is applied to the second input sections 13b-17b of the first to fifth level shifters 13-17. Furthermore, similarly to Embodiment 1, the on / off state of FETs 5-9 is switched according to the control signal input sections 13d-17d of the first to fifth level shifters 13-17.

[0106] In the low-power mode of Embodiment 2, similarly to Embodiment 1, the first switch SW1 is switched off, and the second switch SW2 is switched on. As a result, the output voltage (power supply voltage) of the first output section 10a of the voltage source 10 is applied to the first input sections 13a and 15a of the first level shifter 13 and the third level shifter 15. On the other hand, in the low-power mode, since the charge pump 11 stops, the output voltages of the first output section 11b and the second output section 11c of the charge pump 11 become voltages near 0V. Therefore, in the low-power mode, the output voltage of the first output section 11b of the charge pump 11, i.e., a voltage near 0V, is applied to the first input sections 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17a. The output voltage (a voltage near 0V) of the second output section 11c of the charge pump 11 is applied to the second input sections 13b to 17b of the first to fifth level shifters 13 to 17.

[0107] In Embodiment 2, similarly to Embodiment 1, in low-power mode, all FETs 5-9 are switched on by the first to fifth level shifters 13-17. More specifically, in low-power mode, as described above, similarly to Embodiment 1, the output voltage (power supply voltage) of the first output section 10a of the voltage source 10 is applied to the first input sections 13a and 15a of the first and third level shifters 13 and 15. Therefore, the first series FET 5 and the second series FET 7 are switched on by a sufficiently high voltage (power supply voltage). Thus, similarly to Embodiment 1, even if a high-frequency signal from an external terminal enters the high-frequency switching circuit 1, the generation of reflected waves of the high-frequency signal can be reduced when the high-frequency signal passes through the first series FET 5 and the second series FET 7.

[0108] Furthermore, in low-power mode, as described above, the output voltage (a voltage near 0V) of the first output section 11b of the charge pump 11 is applied to the first input sections 14a, 16a, and 17a of the second, fourth, and fifth level shifters 14, 16, and 17. Therefore, the first to third parallel FETs 6, 8, and 9 are switched on by the voltage near 0V. That is, the first to third parallel FETs 6, 8, and 9 are not sufficiently switched on, and the on-resistance in the on-state becomes a resistance that is high enough. Therefore, when a high-frequency signal from an external terminal enters the high-frequency switching circuit 1 and passes through the first to third parallel FETs 6, 8, and 9, a reflection wave of the aforementioned high-frequency signal may sometimes be generated. However, in Embodiment 2, in low-power mode, since the reflection wave of the aforementioned high-frequency signal is reduced in the first series FET 5 and the second series FET 7, although the effect is weaker compared to Embodiment 1, the overall reflection wave of the aforementioned high-frequency signal can be reduced.

[0109] (2-3) Effects

[0110] Similar to Embodiment 1, the high-frequency switching circuit 1 in Embodiment 2 includes a common terminal 2, a first input / output terminal 3, a first series FET 5, a first parallel FET 6, a charge pump 11, a voltage supply path 12, a first switch SW1, and a second switch SW2. The first input / output terminal 3 is connected to the common terminal 2 via a first signal path L1. The first series FET 5 is connected to both the common terminal 2 and the first input / output terminal 3 in the first signal path L1. The first parallel FET 6 is connected between the signal path L12 between the first input / output terminal 3 and the first series FET and ground. The charge pump 11 supplies control voltages for controlling the first series FET 5 and the first parallel FET 6. The voltage supply path 12 is connected to a connection node N1 that connects the first output section 11b (output section) of the charge pump 11 and the control electrode of the first series FET 5. The first switch SW1 is disposed in the first path M1 that connects the first output section 11b of the charge pump 11 to the connection node N1, and is used to turn the first path M1 on and off. The second switch SW2 is located in the voltage supply path 12 and is used to turn the voltage supply path 12 on and off.

[0111] According to this structure, similarly to Embodiment 1, when the charge pump 11 is stopped, the first path M1 is disconnected by the first switch SW1 and the voltage supply path 12 is turned on by the second switch SW2. This allows the power supply voltage applied to the voltage supply path 12 to be applied to the control electrode of the first series FET 5, thereby switching the first series FET 5 to an on-state with sufficiently low on-resistance. Therefore, when the charge pump 11 is stopped, the reflection of the high-frequency signal entering the common terminal 2 from the external terminal due to the on-resistance of the first series FET 5 can be reduced. Consequently, the degradation of the receiving sensitivity of the external terminal due to the reflected wave returning to the external terminal can be reduced.

[0112] (3) Implementation method 3

[0113] Reference Figure 4 The high-frequency switching circuit 1 according to Embodiment 3 will be described below. In the following description, the same reference numerals are sometimes used for structures that are the same as those in Embodiment 1, and the description is omitted.

[0114] (3-1) Structure

[0115] like Figure 4As shown, the high-frequency switching circuit 1 according to Embodiment 3 is configured in the same way as the high-frequency switching circuit 1 according to Embodiment 1, except that it also has a switching switch 60 to replace the first switch SW1 and the second switch SW2.

[0116] The switching switch 60 is equivalent to the switch including the first switch SW1 and the second switch SW2 configured at the connection node N1 in embodiment 1.

[0117] The switching switch 60 selectively connects one of the first path M1 and the voltage supply path 12 (in other words, one of the first output 11b of the charge pump 11 and the first output 10a of the voltage source 10) to the control electrode of FETs 5-9.

[0118] More specifically, it has a common terminal 60a, a first selection terminal 60b, and a second selection terminal 60c.

[0119] The first selection terminal 60b is connected to the first output portion 11b of the charge pump 11 via the first path M1. That is, the first selection terminal 60b is connected to one end of the first path M1. The second selection terminal 60c is connected to the first output portion 10a of the voltage source 10 via the voltage supply path 12. That is, the second selection terminal 60c is connected to one end of the voltage supply path 12. The common terminal 60a can be selectively connected to either the first selection terminal 60b or the second selection terminal 60c. The common terminal 60a is connected to the first input portions 13a-17a of the first to fifth level shifters 13-17. The first to fifth level shifters 13-17 correspond one-to-one with FETs 5-9. In addition, the first to fifth level shifters 13-17 correspond one-to-one with resistors R1-R5. The output portions 13c-17c of the first to fifth level shifters 13-17 are connected to the control electrodes of the corresponding FETs 5-9 via opposing resistors R1-R5. Therefore, the common terminal 60a is connected to the control electrodes of FETs 5-9. More specifically, the common terminal 60a is indirectly connected to the control electrodes of FETs 5-9 via the corresponding first to fifth level shifters 13-17 and the corresponding resistors R1-R5.

[0120] In transmit / receive mode, the switch 60 selectively connects the common terminal 60a to the first selection terminal 60b. That is, in transmit / receive mode, the switch 60 connects the first path M1 to the control electrode of FETs 5-9. More specifically, the switch 60 connects the first path M1 to the first input sections 13a-17a of the first to fifth level shifters 13-17. Thus, in the transmit / receive mode of Embodiment 3, similarly to the transmit / receive mode of Embodiment 1, the output voltage (positive voltage) of the first output section 11b of the charge pump 11 is applied to the first input sections 13a-17a of the first to fifth level shifters 13-17.

[0121] Furthermore, the outputs 13c to 17c of the first to fifth level shifters 13 to 17 are connected to the control electrodes of the corresponding FETs 5 to 9 via corresponding resistors R1 to R5. Therefore, the switching switch 60 connects the first path M1 to the control electrodes of FETs 5 to 9 in transmit / receive mode.

[0122] Furthermore, in low-power mode, the switch 60 selectively connects the common terminal 60a to the second selection terminal 60c. That is, in low-power mode, the switch 60 connects the voltage supply path 12 to the control electrodes of FETs 5-9. More specifically, the switch 60 connects the voltage supply path 12 to the first input sections 13a-17a of the first to fifth level shifters 13-17. Thus, in the low-power mode of Embodiment 3, similarly to the low-power mode of Embodiment 1, the output voltage (power supply voltage) of the first output section 10a of the voltage source 10 is applied to the first input sections 13a-17a of the first to fifth level shifters 13-17.

[0123] Furthermore, the outputs 13c to 17c of the first to fifth level shifters 13 to 17 are connected to the control electrodes of the corresponding FETs 5 to 9 via corresponding resistors R1 to R5. Therefore, the switching switch 60 connects the voltage supply path 12 to the control electrodes of the FETs 5 to 9 in low-power mode.

[0124] (3-2) Actions

[0125] The operation of the high-frequency switching circuit 1 in Embodiment 3 is different only in that the first switch SW1 and the second switch SW2 are changed to the switching switch 60. The rest of the operation is the same as that of the high-frequency switching circuit 1 in Embodiment 1, so its description is omitted.

[0126] (3-3) Effects

[0127] The high-frequency switching circuit 1 according to embodiment 3 includes a switching switch 60. The switching switch 60 includes a first switch SW1 and a second switch SW2. The switching switch 60 selectively connects one of the first path M1 and the voltage supply path 12 to the control electrode of the first series FET 5. According to this structure, the first switch SW1 and the second switch SW2 can be integrated by the switching switch 60. As a result, the high-frequency switching circuit 1 can be miniaturized.

[0128] The embodiments and modifications described above are only a part of the various embodiments and modifications of the present invention. Furthermore, any embodiments and modifications can be made as long as they achieve the objectives of the present invention, and various changes can be made according to design, etc.

[0129] Explanation of reference numerals in the attached figures

[0130] 1: High-frequency switching circuit; 2: Common terminal; 3: First input / output terminal; 4: Second input / output terminal; 5: First series FET; 6: First parallel FET; 7: Second series FET; 8: Second parallel FET; 9: Third parallel FET; 10: Voltage source; 10a: First output section; 10b: Second output section; 11: Charge pump; 11a: Input section; 11b: First output section (output section); 11c: Second output section; 12: Voltage supply path; 13: First level shifter; 13a: First input section; 13b: Second input section; 3c: Output section (first output section); 13d: Control signal input section; 14: Second level shifter; 14a: First input section (third input section); 14b: Second input section (fourth input section); 14c: Output section (second output section); 14d: Control signal input section; 15: Third level shifter; 15a: First input section; 15b: Second input section; 15c: Output section; 15d: Control signal input section; 16: Fourth level shifter; 16a: First input section; 16b: Second input section; 16c: Output section; 16d: Control signal input section 17: Fifth level shifter; 17a: First input section; 17b: Second input section; 17c: Output section; 17d: Control signal input section; 30: Communication device; 31: High-frequency module; 32: Signal processing circuit; 33: Antenna; 34: Baseband signal processing circuit; 35: RF signal processing circuit; 36: Receiver filter; 36a: Input section; 36b: Output section; 37: Transmitter filter; 37a: Input section; 37b: Output section; 38: Low-noise amplifier (electronic component); 38a: Input section; 38b: Output section; 39: Power amplifier 39a: Input section; 39b: Output section; 40a~10d: External terminals; 50: Receiving component (electronic component); 51: Transmitting component (electronic component); 60: Switch; 60a: Common terminal; 60b: First selection terminal; 60c: Second selection terminal; L1: First signal path; L2: Second signal path; L3, L11, L12, L21, L22: Signal paths; M1: First path; M1a: Path; N1~N6: Connection nodes; R1~R5: Resistors; SW1: First switch; SW2: Second switch.

Claims

1. A high-frequency switching circuit, comprising: Common terminal; The first input / output terminal is connected to the common terminal via a first signal path; A first series field-effect transistor is connected to the common terminal and the first input / output terminal in the first signal path; The first parallel field-effect transistor is connected between the signal path between the first input / output terminal and the first series field-effect transistor and ground. A charge pump having an output section from which a control voltage for controlling the first series field-effect transistor and a control voltage for controlling the first parallel field-effect transistor are supplied. A voltage source having a first output section and a second output section respectively supplying voltage, wherein the voltage is supplied from the second output section to the charge pump; A voltage supply path connects the first output of the voltage source to a connection node connected to the control electrode of the first series field-effect transistor. A first switch is disposed on a first path connecting the output section of the charge pump to the connection node, for turning the first path on and off; as well as The second switch is located in the voltage supply path and is used to turn the voltage supply path on and off.

2. The high-frequency switching circuit according to claim 1, wherein, The control electrode of the first parallel field-effect transistor is connected to the path that connects the connection node to the control electrode of the first series field-effect transistor.

3. The high-frequency switching circuit according to claim 1 or 2, wherein, It also has: The second input / output terminal is connected to the common terminal via a second signal path; The second series field-effect transistor is connected to the common terminal and the second input / output terminal in the second signal path; as well as The second parallel field-effect transistor is connected between the signal path between the second input / output terminal and the second series field-effect transistor and ground. The connection node is also connected to the control electrode of the second series field-effect transistor.

4. The high-frequency switching circuit according to any one of claims 1 to 3, wherein, The charge pump supplies the control voltage based on the voltage from the voltage source.

5. The high-frequency switching circuit according to any one of claims 1 to 4, wherein, It also includes a parallel field-effect transistor connected between the common terminal and the ground.

6. The high-frequency switching circuit according to any one of claims 1 to 5, wherein, It also includes a switch, which comprises a first switch and a second switch. The switching switch selectively connects one of the first path and the voltage supply path to the control electrode of the first series field-effect transistor.

7. The high-frequency switching circuit according to any one of claims 1 to 5, wherein, It also has: A first level shifter controls the first series field-effect transistor; as well as The second level shifter controls the first parallel field-effect transistor. The first level shifter has: A first input section is connected to the connection node; The second input section is connected to the negative voltage supply circuit; and A first output section, connected to the control electrode of the first series field-effect transistor, is used to selectively output the voltage input to the first input section and the voltage input to the second input section. The second level shifter has: The third input section is connected to the path between the output section of the charge pump and the first switch, or to the connection node; The fourth input section is connected to the negative voltage supply circuit; and The second output section, which is connected to the control electrode of the first parallel field-effect transistor, is used to selectively output the voltage input to the third input section and the voltage input to the fourth input section.

8. A high-frequency module, comprising: The high-frequency switching circuit according to any one of claims 1 to 7; and An electronic component connected between the first input / output terminal and an external terminal of the high-frequency switching circuit.

9. A communication device comprising: The high-frequency module according to claim 8; and A signal processing circuit, which is connected to the high-frequency module, performs signal processing on the high-frequency signal.

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