Output driving circuit
By combining the potential bootstrap circuit and the output circuit, the problem of NMOS transistors being unable to transmit high voltage without loss in FPGAs is solved, achieving full-amplitude output, simplifying system design and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GOWIN SEMICON CORP LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-21
AI Technical Summary
When using NMOS transistors in FPGAs, existing technologies cannot transmit high voltage without loss, resulting in insufficient output voltage. Furthermore, adding auxiliary power supplies or voltage doubler charge pumps increases system complexity and power consumption.
By employing a bootstrap circuit and an output circuit, the NMOS transistor is controlled to conduct under different signal levels through an energy storage element, achieving full-amplitude output and avoiding the introduction of an external power supply.
It achieves full-amplitude output of NMOS transistors without increasing system complexity and power consumption, ensuring the integrity of voltage delivery.
Smart Images
Figure CN121907231A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of FPGA high-speed interface technology, and more specifically, to an output driver circuit. Background Technology
[0002] For external communication, FPGAs and other chips typically require a configurable high-speed digital interface, GPIO, which allows the I / O to operate in different modes, such as Mobile Industry Processor Interface (MIPI), CMOS, and different power supply voltages. To avoid leakage when the I / O voltage exceeds the power supply voltage VCCX, and to improve the drive capability of LPTX, NMOS transistors are generally used instead of PMOS transistors for the output pull-up transistors. Since NMOS transistors cannot transmit high voltages without loss, a higher voltage must be applied to the NMOS control gate to ensure a full-amplitude I / O voltage (or communication voltage) output.
[0003] To address this issue, existing technologies can either add an auxiliary power supply or use a voltage doubler charge pump to generate a higher voltage internally. However, this inevitably introduces new control signals and circuits, increasing not only system complexity and cost but also system power consumption. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This disclosure provides an output driving circuit including: a potential bootstrap circuit and an output circuit; the potential bootstrap circuit includes an energy storage element; the output circuit includes an NMOS transistor; The bootstrap circuit is connected to the output circuit and is configured to control the first power supply to charge the energy storage element when the level of the input digital signal includes a first low level; when the levels of the input digital signals are all at the first high level, the level of the energy storage element is bootstrapped to a second high level, the second high level being greater than or equal to the sum of the charging level and the threshold voltage of the NMOS transistor, and the charging level being a third high level, the third high level being the level of the first power supply. The output circuit is configured to connect to a second power supply and a fourth power supply. When the level of the input digital signal includes a first low level, it outputs the level of the fourth power supply. When the levels of the input digital signals are all at the first high level, it controls the NMOS transistor to turn on through the second high level and outputs a fourth high level, which is the level of the second power supply.
[0006] In one exemplary embodiment, the bootstrap circuit further includes a first level conversion circuit, a second level conversion circuit, a power access control circuit, and a power access circuit; the energy storage element includes a first terminal and a second terminal; the first terminal is connected to the power access circuit, the power access control circuit, and the second level conversion circuit respectively, and the second terminal is configured to access the digital signal; The first level conversion circuit is configured to perform a first level conversion on the input digital signal according to the third power supply, the fourth power supply and the fifth power supply to obtain a fifth high level or a second low level, wherein the fifth high level is the level of the third power supply and the second low level is the level of the fourth power supply, and the fifth high level is greater than the second low level. The second level conversion circuit is configured to perform a second level conversion on the input digital signal based on the levels of the fourth power supply, the fifth power supply, the sixth power supply, and the energy storage element, respectively, to obtain a first output or a second output. The first output includes a sixth high level and a second low level, and the second output includes a first low level and a level determined based on the level of the energy storage element. The first output is used to control the power supply access circuit, and the second output is used to control the NMOS transistor. The sixth high level is the level of the sixth power supply. The power access control circuit is connected to the first level conversion circuit, the second level conversion circuit, and the power access circuit respectively. It is configured to control the power access circuit not to output the first power supply when the output of the first level conversion circuit is a second low level and the first output of the second level conversion circuit is a first low level; and to control the power access circuit to output the first power supply when the output of the first level conversion circuit is a fifth high level and the first output of the second level conversion circuit is a sixth high level. The power supply access circuit is configured to charge the energy storage element when a first power source is connected.
[0007] In one exemplary embodiment, the digital signal includes a first input signal; The first level conversion circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the first transistor is used to connect to the third power supply, and the second electrode of the first transistor is connected to the control electrode of the second transistor. The control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the third power supply, and the second electrode of the second transistor is connected to the control electrode of the first transistor. The control electrode of the third transistor is used to connect to the fifth power supply, the first electrode of the third transistor is used to connect to the first input signal, and the second electrode of the third transistor is connected to the second electrode of the first transistor. The control electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is used to connect to the fourth power supply, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor.
[0008] In one exemplary embodiment, the second level-shifting circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an inverter connected together. The control electrode of the fifth transistor is connected to the second electrode of the sixth transistor, the first electrode of the fifth transistor is used to connect to the sixth power supply, and the second electrode of the fifth transistor is connected to the control electrode of the sixth transistor. The control electrode of the sixth transistor is connected to the second electrode of the fifth transistor, the first electrode of the sixth transistor is used to input the voltage level of the energy storage element, and the second electrode of the sixth transistor is connected to the control electrode of the fifth transistor. The control electrode of the seventh transistor is used to connect to the fifth power supply, the first electrode of the seventh transistor is connected to the output terminal of the inverter, and the second electrode of the seventh transistor is connected to the second electrode of the fifth transistor. The control terminal of the eighth transistor is connected to the output terminal of the inverter, the first terminal of the eighth transistor is used to connect to the fourth power supply, and the second terminal of the eighth transistor is connected to the second terminal of the sixth transistor.
[0009] In one exemplary embodiment, the power access circuit includes a ninth transistor; The control electrode of the ninth transistor is connected to the output terminal of the power supply control circuit, the first electrode of the ninth transistor is used to connect to the first power supply, and the second electrode of the ninth transistor is connected to the first electrode of the sixth transistor and the first terminal of the energy storage element, respectively.
[0010] In one exemplary embodiment, the power access control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The control electrode of the tenth transistor is connected to the second electrode of the second transistor, the first electrode of the tenth transistor is connected to the first electrode of the sixth transistor, the second electrode of the ninth transistor and the first terminal of the energy storage element, and the second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor. The control terminal of the eleventh transistor is connected to the second terminal of the fifth transistor and the second terminal of the seventh transistor, the first terminal of the eleventh transistor is connected to the second terminal of the tenth transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor and the second terminal of the thirteenth transistor. The control electrode of the twelfth transistor is connected to the control electrode of the eleventh transistor and the second electrode of the fifth transistor, respectively. The first electrode of the twelfth transistor is used to connect to the fourth power supply, and the second electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor. The control electrode of the thirteenth transistor is connected to the second electrode of the second transistor, the first electrode of the thirteenth transistor is used to connect to the fourth power supply, and the second electrode of the thirteenth transistor is connected to the control electrode of the ninth transistor.
[0011] In one exemplary embodiment, the output circuit further includes a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is connected to the second electrode of the sixth transistor and the second electrode of the eighth transistor, respectively. The first electrode of the fourteenth transistor is used to connect to the second power supply, and the second electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor. The control terminal of the fifteenth transistor is connected to the output terminal of the inverter, the first terminal of the fifteenth transistor is used to connect to the fourth power supply, and the second terminal of the fifteenth transistor is connected to the second terminal of the fourteenth transistor. The common terminal of the second electrode of the fourteenth transistor and the second electrode of the fifteenth transistor is used as the output terminal of the output drive circuit.
[0012] In one exemplary embodiment, the digital signal includes a first input signal and an enable signal; The first level conversion circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the first transistor is used to connect to the third power supply, and the second electrode of the first transistor is connected to the control electrode of the second transistor. The control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the third power supply, and the second electrode of the second transistor is connected to the control electrode of the first transistor. The control electrode of the third transistor is used to connect to the fifth power supply, the first electrode of the third transistor is used to connect to the enable signal, and the second electrode of the third transistor is connected to the second electrode of the first transistor. The control electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is used to connect to the fourth power supply, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor.
[0013] In one exemplary embodiment, the bootstrap circuit further includes an AND gate; the AND gate includes two inputs and one output. The two input terminals of the AND gate are respectively used to connect the first input signal and the enable signal; The output of the AND gate is connected to the energy storage element.
[0014] In one exemplary embodiment, the energy storage element includes a capacitor.
[0015] In this embodiment, when the level of the input digital signal includes a first low level, the first power supply VCCX is controlled to charge the energy storage element, and the level of the fourth power supply is output. When the levels of the input digital signals are all first high levels, the level of the energy storage element is bootstrapped to a second high level. The second high level controls the NMOS transistor to turn on, and the level of the second power supply is output, instead of the level of the second power supply minus the threshold voltage of the NMOS transistor. Therefore, full-amplitude output is achieved.
[0016] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description
[0017] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.
[0018] Figure 1 This is one of the schematic diagrams of the output driving circuit according to an embodiment of the present disclosure; Figure 2 This is a second schematic diagram of the output driving circuit according to an embodiment of the present disclosure; Figure 3 This is a third schematic diagram of the output driving circuit according to an embodiment of the present disclosure; Figure 4 This is a fourth schematic diagram of the output driving circuit according to an embodiment of the present disclosure. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.
[0020] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.
[0021] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.
[0022] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.
[0023] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.
[0024] In this specification, the first electrode can be the drain electrode, the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. The third electrode can be the gate electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.
[0025] In this specification, "connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0026] Figure 1 This is one of the schematic diagrams of the output driving circuit of an embodiment of this disclosure, such as... Figure 1 As shown, the output drive circuit includes a potential bootstrap circuit and an output circuit; The bootstrap circuit includes an energy storage element; the output circuit includes an NMOS transistor. The bootstrap circuit is connected to the output circuit and is configured to control the first power supply VCCX1 to charge the energy storage element when the level of the input digital signal includes a first low level; when the levels of the input digital signals are all at the first high level, the level of the energy storage element is bootstrapped to a second high level, the second high level being greater than or equal to the sum of the charging level and the threshold voltage of the NMOS transistor, the charging level being a third high level, and the third high level being the level of the first power supply VCCX1. The output circuit is configured to connect to a second power supply VCC_LPTX and a fourth power supply VSS. When the level of the input digital signal includes a first low level, the circuit outputs the level of the fourth power supply VSS. When the levels of the input digital signals are all at the first high level, the circuit controls the NMOS transistor to turn on through the second high level and outputs a fourth high level, which is the level of the second power supply VCC_LPTX.
[0027] In this embodiment, when the level of the input digital signal includes a first low level, the first power supply VCCX is controlled to charge the energy storage element, and the level of the fourth power supply is output. When the levels of the input digital signals are all first high levels, the level of the energy storage element is bootstrapped to a second high level. The second high level controls the NMOS transistor to turn on, and the level of the second power supply is output, instead of the level of the second power supply minus the threshold voltage of the NMOS transistor. Therefore, full-amplitude output is achieved.
[0028] For example, the level of the first power supply VCCX1 can be 1.6V, and the level of the second power supply (VCC_LPTX) can be 1.2V. When the output drive circuit outputs a high level, due to the bias effect, the threshold of the NMOS transistor will be too high, resulting in the output level of the output drive circuit being (1.6V - the threshold of the NMOS transistor). Since (1.6V - the threshold of the NMOS transistor) is less than 1.2V, it is desirable to raise the gate level of the pull-up NMOS transistor in the output circuit to 1.6V + 0.9V to ensure an output of 1.2V, thus making it the same as the level of the second power supply. The second high level can be equal to the third high level + the first high level (the first high level can be equal to the level of the fifth power supply VCC), i.e., VCCX1 + VCC. For example, the first high level can be equal to the level of VCC, which is 0.9V, and the first low level can be lower than 0.4V, for example, 0.3V.
[0029] Figure 2 This is a second schematic diagram of the output driving circuit according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, with Figure 1 In comparison, the bootstrap circuit further includes: a first level conversion circuit, a second level conversion circuit, a power supply control circuit, and a power supply circuit; the energy storage element includes a first terminal and a second terminal; the first terminal is connected to the power supply circuit, the power supply control circuit, and the second level conversion circuit respectively, and the second terminal is configured to receive the digital signal; The first level conversion circuit is configured to perform a first level conversion on the input digital signal based on the third power supply VCCX2, the fourth power supply VSS and the fifth power supply VCC to obtain a fifth high level or a second low level. The fifth high level is the level of the third power supply VCCX2, the second low level is the level of the fourth power supply, and the fifth high level is greater than the second low level. The second level conversion circuit is configured to perform a second level conversion on the input digital signal based on the levels of the fourth power supply VSS, the fifth power supply VCC, the sixth power supply VCCX3, and the energy storage element, respectively, to obtain a first output or a second output. The first output includes a sixth high level and a second low level, and the second output includes a first low level and a level determined based on the level of the energy storage element. The first output is used to control the power supply input circuit, and the second output is used to control the NMOS transistor. The sixth high level is the level of the sixth power supply VCCX3. The power access control circuit is connected to the first level conversion circuit, the second level conversion circuit, and the power access circuit respectively. It is configured to control the power access circuit not to output the first power supply when the output of the first level conversion circuit is a second low level and the first output of the second level conversion circuit is a first low level; and to control the power access circuit to output the first power supply when the output of the first level conversion circuit is a fifth high level and the first output of the second level conversion circuit is a sixth high level. The power supply access circuit is configured to charge the energy storage element when a first power source is connected.
[0030] The embodiments disclosed herein achieve full-amplitude output through the cooperation between the various circuits included in the bootstrap circuit.
[0031] For example, the voltage level of the third power supply VCCX2 can be equal to the voltage level of the first power supply VCCX1. Alternatively, the voltage level of the third power supply VCCX2 can be different from the voltage level of the first power supply VCCX1. For instance, the voltage level of the first power supply VCCX1 is 1.6V, and the voltage level of the third power supply VCCX2 can be 1.2V.
[0032] For example, the level of the fourth power supply VSS can be below 0.4V. The level of the fifth power supply VCC can be 0.9V.
[0033] For example, the voltage level of the sixth power supply VCCX3 can be equal to that of the third power supply VCCX2. For instance, both the voltage level of the sixth power supply VCCX3 and the voltage level of the third power supply VCCX2 are 1.2V.
[0034] For example, the fifth high level can be 1.2V, the second low level can be lower than 0.4V, and the sixth high level can be 1.2V.
[0035] In one exemplary embodiment, the digital signal includes a first input signal; The first level conversion circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the first transistor is used to connect to the third power supply, and the second electrode of the first transistor is connected to the control electrode of the second transistor. The control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the third power supply, and the second electrode of the second transistor is connected to the control electrode of the first transistor. The control electrode of the third transistor is used to connect to the fifth power supply, the first electrode of the third transistor is used to connect to the first input signal, and the second electrode of the third transistor is connected to the second electrode of the first transistor. The control electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is used to connect to the fourth power supply, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor.
[0036] In one exemplary embodiment, the second level-shifting circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an inverter connected together. The control electrode of the fifth transistor is connected to the second electrode of the sixth transistor, the first electrode of the fifth transistor is used to connect to the sixth power supply, and the second electrode of the fifth transistor is connected to the control electrode of the sixth transistor. The control electrode of the sixth transistor is connected to the second electrode of the fifth transistor, the first electrode of the sixth transistor is used to input the voltage level of the energy storage element, and the second electrode of the sixth transistor is connected to the control electrode of the fifth transistor. The control electrode of the seventh transistor is used to connect to the fifth power supply, the first electrode of the seventh transistor is connected to the output terminal of the inverter, and the second electrode of the seventh transistor is connected to the second electrode of the fifth transistor. The control terminal of the eighth transistor is connected to the output terminal of the inverter, the first terminal of the eighth transistor is used to connect to the fourth power supply, and the second terminal of the eighth transistor is connected to the second terminal of the sixth transistor.
[0037] In one exemplary embodiment, the power access circuit includes a ninth transistor; The control electrode of the ninth transistor is connected to the output terminal of the power supply control circuit, the first electrode of the ninth transistor is used to connect to the first power supply, and the second electrode of the ninth transistor is connected to the first electrode of the sixth transistor and the first terminal of the energy storage element, respectively.
[0038] In one exemplary embodiment, the power access control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The control electrode of the tenth transistor is connected to the second electrode of the second transistor, the first electrode of the tenth transistor is connected to the first electrode of the sixth transistor, the second electrode of the ninth transistor and the first terminal of the energy storage element, and the second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor. The control terminal of the eleventh transistor is connected to the second terminal of the fifth transistor and the second terminal of the seventh transistor, the first terminal of the eleventh transistor is connected to the second terminal of the tenth transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor and the second terminal of the thirteenth transistor. The control electrode of the twelfth transistor is connected to the control electrode of the eleventh transistor and the second electrode of the fifth transistor, respectively. The first electrode of the twelfth transistor is used to connect to the fourth power supply, and the second electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor. The control electrode of the thirteenth transistor is connected to the second electrode of the second transistor, the first electrode of the thirteenth transistor is used to connect to the fourth power supply, and the second electrode of the thirteenth transistor is connected to the control electrode of the ninth transistor.
[0039] In one exemplary embodiment, the output circuit further includes a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is connected to the second electrode of the sixth transistor and the second electrode of the eighth transistor, respectively. The first electrode of the fourteenth transistor is used to connect to the second power supply, and the second electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor. The control terminal of the fifteenth transistor is connected to the output terminal of the inverter, the first terminal of the fifteenth transistor is used to connect to the fourth power supply, and the second terminal of the fifteenth transistor is connected to the second terminal of the fourteenth transistor. The common terminal of the second electrode of the fourteenth transistor and the second electrode of the fifteenth transistor is used as the output terminal of the output drive circuit.
[0040] In one exemplary embodiment, the digital signal includes a first input signal and an enable signal; The first level conversion circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the first transistor is used to connect to the third power supply, and the second electrode of the first transistor is connected to the control electrode of the second transistor. The control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the third power supply, and the second electrode of the second transistor is connected to the control electrode of the first transistor. The control electrode of the third transistor is used to connect to the fifth power supply, the first electrode of the third transistor is used to connect to the enable signal, and the second electrode of the third transistor is connected to the second electrode of the first transistor. The control electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is used to connect to the fourth power supply, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor.
[0041] In one exemplary embodiment, the bootstrap circuit further includes an AND gate; the AND gate includes two inputs and one output. The two input terminals of the AND gate are respectively used to connect the first input signal and the enable signal; The output of the AND gate is connected to the energy storage element.
[0042] In one exemplary embodiment, the energy storage element includes a capacitor.
[0043] For example, the output drive circuit can be enabled when the enable signal is 1.
[0044] In one exemplary embodiment, the bootstrap circuit further includes an AND gate; the AND gate includes two inputs and one output. The two input terminals of the AND gate are respectively used to connect the first input signal and the enable signal; The output of the AND gate is connected to the energy storage element.
[0045] In one exemplary embodiment, the energy storage element includes a capacitor.
[0046] For example, the capacitance value of the capacitor can be 1 pF.
[0047] The fourteenth transistor is an NMOS transistor, while the first to thirteenth transistors and the fifteenth transistor can be either NMOS transistors or PMOS transistors.
[0048] Figure 3 This is a third schematic diagram of the output drive circuit according to an embodiment of this disclosure. Figure 3 As shown, the output drive circuit includes a potential bootstrap circuit 10 and an output circuit 20. The potential bootstrap circuit 10 may include a first level conversion circuit 100, a second level conversion circuit 200, a power supply control circuit 300, a power supply input circuit 400, a circuit 500, and a circuit 600.
[0049] The first level conversion circuit 100 includes cross-coupled PMOS transistors M1 and M2, NMOS transistors M3 and M4. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M2, the source of PMOS transistor M1 is used to connect to VCCX, and the drain of PMOS transistor M1 is connected to the gate of PMOS transistor M2. The gate of PMOS transistor M2 is connected to the drain of PMOS transistor M1, the source of PMOS transistor M2 is used to connect to VCCX, and the drain of PMOS transistor M2 is connected to the gate of PMOS transistor M1. The gate of NMOS transistor M3 is used to connect to VCC, the source of NMOS transistor M3 is connected to the enable terminal, and the drain of NMOS transistor M3 is connected to the drain of PMOS transistor M1. The gate of NMOS transistor M4 is connected to the source of NMOS transistor M3, the source of NMOS transistor M4 is used to connect to VSS, and the drain of NMOS transistor M4 is connected to the drain of PMOS transistor M2. In this circuit, VCC is 0.9V, VCCX is 1.2V, and VSS is below 0.4V. The output of the first level conversion circuit 100 is the common terminal of M2 and M4. An enable signal (enable) is connected to the enable terminal. In this example, enable=1 is valid, and enable=0 is invalid. When valid, the output drive circuit operates normally; when invalid, the output drive circuit does not operate.
[0050] The second level conversion circuit 200 includes cross-coupled PMOS transistors M5 and M6, NMOS transistor M7, NMOS transistor M8, and NOT gate Q1. The gate of PMOS transistor M5 is connected to the drain of PMOS transistor M6, the source of PMOS transistor M5 is used to connect to VCCX, and the drain of PMOS transistor M5 is connected to the gate of PMOS transistor M6. The gate of PMOS transistor M6 is connected to the drain of PMOS transistor M5, the source of PMOS transistor M6 is connected to the drain of PMOS transistor M9, and the drain of PMOS transistor M6 is connected to the gate of PMOS transistor M5. The gate of NMOS transistor M7 is used to connect to VCC, the source of NMOS transistor M7 is connected to the gate of NMOS transistor M8, and the drain of NMOS transistor M7 is connected to the drain of PMOS transistor M5. The gate of NMOS transistor M8 is connected to the output of NOT gate Q1, the source of NMOS transistor M8 is used to connect to VSS, and the drain of NMOS transistor M8 is connected to the drain of PMOS transistor M6. The input terminal of NOT gate Q1 is used to receive the input digital signal Din, and the output terminal of NOT gate Q1 is connected to the source of M7, the gate of M8, and the gate of M15, respectively.
[0051] The power supply control circuit 300 includes PMOS transistors M10, M11, M12, and M13. The gate of PMOS transistor M10 is connected to the gate of NMOS transistor M13 and the drain of PMOS transistor M2. The source of PMOS transistor M10 is connected to the drain of M9, the source of M6, and capacitor C1. The drain of PMOS transistor M10 is connected to the source of PMOS transistor M11. The gate of PMOS transistor M11 is connected to the drain of NMOS transistor M7. The source of PMOS transistor M11 is connected to the drain of PMOS transistor M10. The drain of PMOS transistor M11 is connected to the drain of NMOS transistor M12. The gate of NMOS transistor M12 is connected to the gate of PMOS transistor M11. The source of NMOS transistor M12 is used to connect to VSS. The drain of NMOS transistor M12 is connected to the drain of NMOS transistor M13. The gate of NMOS transistor M13 is connected to the gate of PMOS transistor M10 and the drain of PMOS transistor M2, respectively. The source of NMOS transistor M13 is used to connect to VSS, and the drain of NMOS transistor M13 is connected to the gate of PMOS transistor M9.
[0052] The power supply circuit 400 includes a PMOS transistor M9. The gate of the PMOS transistor M9 is connected to the drain of the NMOS transistor M13, the source of the PMOS transistor M9 is used to connect to VCCX, and the drain of the PMOS transistor M9 is connected to the source of the PMOS transistors M6 and M10, as well as the capacitor C1.
[0053] Circuit 500 includes capacitor C1. The first plate of capacitor C1 is connected to the drain of PMOS transistor M9, the source of PMOS transistor M6, and the source of PMOS transistor M10, respectively. The second plate of capacitor C1 is connected to the output terminal of AND gate P1.
[0054] Circuit 600 includes an AND gate P1. The two inputs of AND gate P1 are used to connect the input signal Din and the enable signal enable, respectively. The output of AND gate P1 is connected to the second plate of capacitor C1. Din and enable are digital signals.
[0055] Output circuit 20 includes NMOS transistors M14 and M15. The gate of NMOS transistor M14 is connected to the drain of NMOS transistor M8, and the source of NMOS transistor M14 is connected to the drain of NMOS transistor M15. The drain of NMOS transistor M14 is used to connect to VCC_LPTX. The gate of NMOS transistor M15 is connected to the gate of M8, the source of M7, and the output of NOT gate Q1. The source of NMOS transistor M15 is used to connect to VSS, and the drain of NMOS transistor M15 is connected to the source of NMOS transistor M14. The source of NMOS transistor M14 and the drain of NMOS transistor M15 together serve as the output terminal, providing output to GPIO_pad.
[0056] When the enable signal is disabled (enable=0), AND gate P1 outputs 0, NMOS transistor M3 is turned on, NMOS transistor M4 is turned off, NMOS transistor M2 is turned on, and NMOS transistor M1 is turned off. The output of the first level conversion circuit 100 outputs voltage VCCX, which turns on NMOS transistor M13, making the gate voltage of PMOS transistor M9 VSS, and thus turning on NMOS transistor M9. The voltage VCCX charges capacitor C1 through the turned-on M9, making the voltage of the first plate of capacitor C1 VCCX, while the voltage of the second plate is zero.
[0057] When the enable signal `enable` is valid (i.e., `enable=1`, i.e., the first high level) and `Din=0`, the NOT gate Q1 outputs VCC, the AND gate P1 outputs 0, NMOS transistor M4 is turned on, NMOS transistor M3 is turned off, and the first level conversion circuit 100 outputs VSS. At this time, NMOS transistors M1, M2, and M13 are turned off. Since the voltage at the output of the NOT gate is 1, NMOS transistors M8 and M15 are turned on, M5 is turned on, M7 is turned off, and M6 is turned off. Since M5 is turned on, M11 is turned off, and M12 is turned on. Since M2 is turned on, the gate voltage of M9 is VSS, so M9 is turned on. Since M8 is turned on, M14 is turned off. Since M15 is turned on, the output driver circuit outputs VSS to GPIO_pad.
[0058] When the enable signal is valid (enable=1, i.e., the first high level) and Din=VCC, the NOT gate Q1 outputs 0, the AND gate P1 outputs VCC, NMOS transistor M4 is turned on, NMOS transistor M3 is turned off, the output of the first level conversion circuit 100 outputs VSS, M10 is turned on, NMOS transistor M13 is turned off, at this time NMOS transistor M1 is turned on, and NMOS transistor M2 is turned off. Since the NOT gate Q1 outputs 0, the voltage at the NOT gate output is 0, therefore, M8 and M15 are turned off. M7, M6, and M11 are turned on, and M12 is turned off. Because M10 and M11 are turned on, the gate and drain of M9 are connected, and M9 is turned off. Since the voltage level of the second plate of capacitor C1 is 0.8V to 0.9V (AND gate P1 outputs the first high level), the potential of the first plate of C1 rises from VCCX to VCCX+ (0.8V to 0.9V), and the potential of the first plate of capacitor C1 is also VCCX+ (0.8V to 0.9V). Because M6 is conducting, the voltage level of the first plate of capacitor C1, through the conducting M6, applies VCCX+ (0.8V to 0.9V) to the gate of M14, turning on M14. Since VCC is sufficient to offset the threshold voltage of the pull-up NMOS transistor M14, VCC_LPTX can be transferred to the pad without loss, thus achieving full-amplitude output.
[0059] The output drive circuit of this embodiment can charge capacitor C1 when the enable signal is invalid or when the enable signal is valid and Din=0 (i.e., the first low level). When the enable signal is valid and Din=1, the potential of the second plate of capacitor C1 is increased by 0.8V to 0.9V, thereby offsetting the threshold voltage of the pull-up NMOS transistor M14, thereby achieving full-amplitude output.
[0060] In this embodiment, VCCX can be 1.2V, and when enable is digital voltage 1, the voltage can be 0.9V. The output drive circuit can output VSS (VSS can be 0V) when Din=0, and the output voltage is 1.2V when Din=1 (i.e., the first high level).
[0061] In this embodiment, M1 to M5 correspond to the first to fifteenth transistors mentioned above, respectively. The pull-up NMOS transistor is the fourteenth transistor.
[0062] Figure 4 This is a fourth schematic diagram of the output drive circuit according to an embodiment of this disclosure. Figure 4 As shown, the output drive circuit includes a potential bootstrap circuit 10 and an output circuit 20. The potential bootstrap circuit 10 may include a first level conversion circuit 100, a second level conversion circuit 200, a power supply control circuit 300, a power supply input circuit 400, and a circuit 500.
[0063] and Figure 3 The circuit shown is different. Figure 4 The circuit does not include an enable signal, therefore circuit 600 is missing.
[0064] The resulting changes in connectivity are as follows: The source of M3 in the first level conversion circuit 100 is used to connect to Din.
[0065] The second plate of capacitor C1 is connected to Din.
[0066] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.
[0067] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
[0068] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.
[0069] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.
[0070] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
[0071] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0072] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0074] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.
Claims
1. An output driving circuit, characterized in that, include: A bootstrap circuit and an output circuit; the bootstrap circuit includes an energy storage element; the output circuit includes an NMOS transistor; The bootstrap circuit is connected to the output circuit and is configured to control the first power supply to charge the energy storage element when the level of the input digital signal includes a first low level; when the levels of the input digital signals are all at the first high level, the level of the energy storage element is bootstrapped to a second high level, the second high level being greater than or equal to the sum of the charging level and the threshold voltage of the NMOS transistor, the charging level being a third high level, and the third high level being the level of the first power supply. The output circuit is configured to connect to a second power supply and a fourth power supply. When the level of the input digital signal includes a first low level, it outputs the level of the fourth power supply. When the levels of the input digital signals are all at the first high level, it controls the NMOS transistor to turn on through the second high level and outputs a fourth high level, which is the level of the second power supply.
2. The output driving circuit as described in claim 1, characterized in that, The bootstrap circuit further includes a first level conversion circuit, a second level conversion circuit, a power access control circuit, and a power access circuit. The energy storage element includes a first terminal and a second terminal. The first terminal is connected to the power access circuit, the power access control circuit, and the second level conversion circuit, respectively. The second terminal is configured to receive the digital signal. The first level conversion circuit is configured to perform a first level conversion on the input digital signal based on the third power supply, the fourth power supply, and the fifth power supply to obtain a fifth high level or a second low level, wherein the fifth high level is the level of the third power supply; the second low level is the level of the fourth power supply, and the fifth high level is greater than the second low level. The second level conversion circuit is configured to perform a second level conversion on the input digital signal according to the levels of the fourth power supply, the fifth power supply, the sixth power supply and the energy storage element, respectively to obtain a first output or a second output. The first output includes a sixth high level and a second low level, and the second output includes a first low level and a level determined according to the level of the energy storage element. The first output is used to control the power supply access circuit, and the second output is used to control the NMOS transistor. The sixth high level is the level of the sixth power supply; The power access control circuit is connected to the first level conversion circuit, the second level conversion circuit, and the power access circuit respectively. It is configured to control the power access circuit not to output the first power supply when the output of the first level conversion circuit is a second low level and the first output of the second level conversion circuit is a first low level; and to control the power access circuit to output the first power supply when the output of the first level conversion circuit is a fifth high level and the first output of the second level conversion circuit is a sixth high level. The power supply access circuit is configured to charge the energy storage element when a first power source is connected.
3. The output driving circuit as described in claim 2, characterized in that, The digital signal includes a first input signal; The first level conversion circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the first transistor is used to connect to the third power supply, and the second electrode of the first transistor is connected to the control electrode of the second transistor. The control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the third power supply, and the second electrode of the second transistor is connected to the control electrode of the first transistor. The control electrode of the third transistor is used to connect to the fifth power supply, the first electrode of the third transistor is used to connect to the first input signal, and the second electrode of the third transistor is connected to the second electrode of the first transistor. The control electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is used to connect to the fourth power supply, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor.
4. The output drive circuit as described in claim 3, characterized in that, The second level conversion circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an inverter connected together; The control electrode of the fifth transistor is connected to the second electrode of the sixth transistor, the first electrode of the fifth transistor is used to connect to the sixth power supply, and the second electrode of the fifth transistor is connected to the control electrode of the sixth transistor. The control electrode of the sixth transistor is connected to the second electrode of the fifth transistor, the first electrode of the sixth transistor is used to input the voltage level of the energy storage element, and the second electrode of the sixth transistor is connected to the control electrode of the fifth transistor. The control electrode of the seventh transistor is used to connect to the fifth power supply, the first electrode of the seventh transistor is connected to the output terminal of the inverter, and the second electrode of the seventh transistor is connected to the second electrode of the fifth transistor. The control terminal of the eighth transistor is connected to the output terminal of the inverter, the first terminal of the eighth transistor is used to connect to the fourth power supply, and the second terminal of the eighth transistor is connected to the second terminal of the sixth transistor.
5. The output driving circuit as described in claim 4, characterized in that, The power supply circuit includes a ninth transistor; The control electrode of the ninth transistor is connected to the output terminal of the power supply control circuit, the first electrode of the ninth transistor is used to connect to the first power supply, and the second electrode of the ninth transistor is connected to the first electrode of the sixth transistor and the first terminal of the energy storage element, respectively.
6. The output driving circuit as described in claim 5, characterized in that, The power supply control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The control electrode of the tenth transistor is connected to the second electrode of the second transistor, the first electrode of the tenth transistor is connected to the first electrode of the sixth transistor, the second electrode of the ninth transistor and the first terminal of the energy storage element, and the second electrode of the tenth transistor is connected to the first electrode of the eleventh transistor. The control terminal of the eleventh transistor is connected to the second terminal of the fifth transistor and the second terminal of the seventh transistor, the first terminal of the eleventh transistor is connected to the second terminal of the tenth transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the twelfth transistor and the second terminal of the thirteenth transistor. The control electrode of the twelfth transistor is connected to the control electrode of the eleventh transistor and the second electrode of the fifth transistor, respectively. The first electrode of the twelfth transistor is used to connect to the fourth power supply, and the second electrode of the twelfth transistor is connected to the second electrode of the eleventh transistor. The control electrode of the thirteenth transistor is connected to the second electrode of the second transistor, the first electrode of the thirteenth transistor is used to connect to the fourth power supply, and the second electrode of the thirteenth transistor is connected to the control electrode of the ninth transistor.
7. The output driving circuit as described in claim 6, characterized in that, The output circuit also includes a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is connected to the second electrode of the sixth transistor and the second electrode of the eighth transistor, respectively. The first electrode of the fourteenth transistor is used to connect to the second power supply, and the second electrode of the fourteenth transistor is connected to the second electrode of the fifteenth transistor. The control terminal of the fifteenth transistor is connected to the output terminal of the inverter, the first terminal of the fifteenth transistor is used to connect to the fourth power supply, and the second terminal of the fifteenth transistor is connected to the second terminal of the fourteenth transistor. The common terminal of the second electrode of the fourteenth transistor and the second electrode of the fifteenth transistor is used as the output terminal of the output drive circuit.
8. The output driving circuit as described in claim 2, characterized in that, The digital signal includes a first input signal and an enable signal; The first level conversion circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the first transistor is used to connect to the third power supply, and the second electrode of the first transistor is connected to the control electrode of the second transistor. The control electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the third power supply, and the second electrode of the second transistor is connected to the control electrode of the first transistor. The control electrode of the third transistor is used to connect to the fifth power supply, the first electrode of the third transistor is used to connect to the enable signal, and the second electrode of the third transistor is connected to the second electrode of the first transistor. The control electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is used to connect to the fourth power supply, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor.
9. The output driving circuit as described in claim 8, characterized in that, The bootstrap circuit further includes an AND gate; the AND gate includes two input terminals and one output terminal. The two input terminals of the AND gate are respectively used to connect the first input signal and the enable signal; The output of the AND gate is connected to the energy storage element.
10. The output driving circuit as described in claim 1, characterized in that, The energy storage element includes a capacitor.