Anti-metastable SAR ADC circuit
By introducing an auxiliary unit into the SAR ADC circuit to forcibly pull up and down the input signal voltage of the comparator unit, the comparator error problem caused by metastability is solved, and the stability and accuracy of the circuit are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- IPGOAL MICROELECTRONICS (SICHUAN) CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-21
AI Technical Summary
During the high-speed conversion process of the SAR ADC circuit, when the comparator input signal changes slowly near the comparator flip threshold, it may lead to metastability, resulting in erroneous comparator results. This, in turn, affects the identification and quantization errors of subsequent digital circuits, reducing conversion accuracy.
When the circuit enters a metastable state, the auxiliary unit forcibly pulls up and down the input signal voltage of the comparator unit to complete the comparison and prevent metastability from occurring. The auxiliary unit includes components such as D flip-flops, XOR gates, AND gates, delay units, and MOSFETs to ensure that the comparator unit works normally.
This improves the stability and accuracy of the SAR ADC circuit, reduces the probability of metastability, and ensures normal output of the circuit under metastable conditions.
Smart Images
Figure CN121907244A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more specifically to a metastability-resistant SAR ADC circuit. Background Technology
[0002] During the high-speed conversion process of the SAR ADC circuit, when the input signal of the comparator changes slowly near the comparator's flip threshold (the voltage difference between the two differential input signals of the comparator is too small), the positive feedback structure inside the comparator may not be able to complete the comparison quickly, or even remain stable for a long time. At this time, the comparator's result will be wrong, that is, a metastable state will occur. The metastable state will cause the subsequent digital circuit to be unable to identify the high and low levels, resulting in logical misjudgment. In this case, the SAR ADC circuit will generate quantization error, which will lead to a significant decrease in conversion accuracy.
[0003] Therefore, it is necessary to provide a metastable SAR ADC circuit that can output comparison results normally even in metastable conditions to overcome the above-mentioned defects. Summary of the Invention
[0004] The purpose of this invention is to provide a metastability-resistant SAR ADC circuit. This SAR ADC circuit, after entering a metastable state, forcibly raises and lowers the voltages of the two input signals of the comparator unit, causing the comparator unit to complete the comparison and exit the metastable state, thus preventing metastability and improving the operational stability and accuracy of the SAR ADC circuit.
[0005] To achieve the above objectives, this invention provides a metastability-resistant SAR ADC circuit, comprising an amplification unit, a comparison unit, and a reset unit. Two external differential signals are respectively input to the amplification unit, which amplifies the input differential signals and outputs them to the comparison unit. The comparison unit compares the input signal voltages and outputs the comparison result to complete the basic function of the SAR ADC circuit. The reset unit is used to reset the comparison unit. The circuit also includes an auxiliary unit connected to the comparison unit. When the circuit enters a metastable state, the auxiliary unit pulls down one of the voltages at the two input terminals of the comparison unit and pulls up the other, so that the comparison unit can complete the comparison process and eliminate the metastability.
[0006] Preferably, the auxiliary unit includes a D flip-flop, an XOR gate, an AND gate, a delay circuit, a ninth MOSFET, a tenth MOSFET, two first switches, and two second switches. One end of each of the two first switches is grounded, and the other end of one first switch is connected to the gate of one MOSFET in the reset unit, while the other end of the other first switch is connected to the gate of the other MOSFET in the reset unit. One end of each of the two second switches is connected to the gate of one MOSFET in the reset unit. A differential signal is input to the other end of one second switch, and the other differential signal is input to the other end of the other second switch. The two outputs of the comparison unit are respectively connected to the two inputs of the XOR gate, and the output signal of the XOR gate and an external clock signal are respectively input to the AND gate. The output of the AND gate is connected to the gate of the current transistor of the amplification unit, and the AND gate outputs a second clock signal. The second clock signal is delayed by the delay unit to output a third clock signal. The third clock signal is input to the clock control terminal of the D flip-flop, the power supply voltage is connected to the data input terminal of the D flip-flop, the second clock signal is input to the reset terminal of the D flip-flop, the non-inverting output terminal of the D flip-flop is connected to the gate of the ninth MOS transistor, the inverting output terminal of the D flip-flop is connected to the gate of the tenth MOS transistor, the drain of the ninth MOS transistor is connected to one input terminal of the comparator unit, the drain of the tenth MOS transistor is connected to the other input terminal of the comparator unit, the source of the ninth MOS transistor is grounded, and the source of the tenth MOS transistor is connected to the power supply voltage.
[0007] Preferably, the auxiliary unit further includes two inverters, one output terminal of the comparator unit is connected to one inverter to output an output signal of the SAR ADC circuit, and the other output terminal of the comparator unit is connected to another inverter to output another output signal of the SAR ADC circuit.
[0008] The ninth MOS transistor is a P-type MOS transistor, and the tenth MOS transistor is an N-type MOS transistor.
[0009] Preferably, the delay time of the delay unit is greater than the comparison time of the comparison unit.
[0010] Preferably, the external clock signal controls the opening / closing of the two first switches and the two second switches. When the external clock signal is low, the two first switches are closed and the two second switches are open; when the external clock signal is high, the two first switches are open and the two second switches are closed.
[0011] Compared with existing technologies, the anti-metastable SAR ADC circuit of the present invention, by setting up the auxiliary unit, when the entire SAR ADC circuit enters a metastable state, pulls one of the voltages at the two input terminals of the comparison unit high to the power supply voltage and the other low to ground voltage, thereby enabling the comparison unit to complete the comparison process normally and obtain the comparison result. This eliminates the metastable state of the entire SAR ADC circuit and improves the working stability and accuracy of the SAR ADC circuit. In addition, in the present invention, the externally input differential signal can also be input into the circuit through the auxiliary circuit and the reset unit, so that each differential signal in the entire circuit has two inputs. When the voltage difference of the input differential signal is relatively small, the voltage difference at the input terminal of the comparison unit will increase accordingly, reducing the probability of metastability in the SAR ADC circuit.
[0012] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the anti-metastable SAR ADC circuit of the present invention. Detailed Implementation
[0014] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides a metastability-resistant SAR ADC circuit. When the circuit enters a metastable state, the SAR ADC circuit of the present invention forcibly pulls up and down the voltages of the two input signals of the comparator unit, causing the comparator unit to complete the comparison and exit the metastable state, thus preventing the occurrence of metastability and improving the operating stability and accuracy of the SAR ADC circuit.
[0015] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the anti-metastable SAR ADC circuit of the present invention. Figure 1As shown, the main structure of the SAR ADC circuit in the anti-metastable SAR ADC circuit of the present invention is the same as that of commonly used existing SAR ADC circuits, both including an amplification unit, a comparison unit, and a reset unit. Two external differential signals vip and vin are respectively input to the amplification unit. The amplification unit amplifies the input differential signals vip and vin and outputs them to the comparison unit. The comparison unit compares the input signal voltages and outputs the comparison results von and vop to complete the basic function of the SAR ADC circuit. The reset unit is used to reset the comparison unit. Specifically, the amplification unit includes a first MOS transistor M1, a second MOS transistor M2, and a current transistor M0, wherein the current transistor M0 is also a MOS transistor used to provide current to the entire SAR ADC circuit. The two external differential signals vip and vin are respectively input to the gates of the first MOS transistor M1 and the second MOS transistor M2. The first MOS transistor M1 and the second MOS transistor M2 amplify the input differential signals vip and vin and output them to the comparison unit through nodes a and b. The comparison unit includes a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6. Signals input from nodes a and b are compared in this comparison unit, and the comparison result is output through the output terminals von and vop. The reset unit includes a seventh MOSFET M7 and an eighth MOSFET M8. Its main function is to reset the input terminals (nodes a and b) of the comparison unit in the reset state, ensuring that the potentials of nodes a and b are both high. The specific working principles of the connections between the various components constituting the main structure of the SAR ADC circuit—the amplification unit, the comparison unit, and the reset unit—are based on existing conventional technology and will not be detailed here.
[0016] The anti-metastable SAR ADC circuit of the present invention further includes an auxiliary unit connected to the comparator unit. When the circuit enters a metastable state, the auxiliary unit pulls down one and up the other voltage at the two input terminals of the comparator unit to enable the comparator unit to complete the comparison process. Specifically, the auxiliary unit includes a D flip-flop U1, an XNOR gate, an AND gate ADN, a delay unit U2, a ninth MOSFET M9, and a tenth MOSFET M10. The two output terminals of the comparator unit are respectively connected to the two input terminals of the XNOR gate. In a preferred embodiment of the present invention, two inverters INV1 and INV2 are also provided. One output terminal (node a) of the comparator unit is connected to one inverter INV1 to output an output signal vop of the SAR ADC circuit, that is, the signal at node a is inverted to form the output signal vop; the other output terminal (node b) of the comparator unit is connected to another inverter INV2 to output another output signal von of the SAR ADC circuit, that is, the signal at node b is inverted to form the output signal von. The output signal of the XNOR gate and an external clock signal CLK1 are respectively input to the AND gate ADN to serve as the two input signals of the AND gate. The output terminal of the AND gate is connected to the gate of the current transistor M0 of the amplification unit to control the conduction and cutoff of the current transistor M0. The AND gate outputs a second clock signal CLK2, which is input to the reset terminal of the D flip-flop U1 to control the reset of the D flip-flop U1. The second clock signal CLK2 is delayed by the delay unit U2 and outputs a third clock signal CLK3. The third clock signal CLK3 is input to the clock control terminal of the D flip-flop U1 to control the timing of the output signal of the D flip-flop U1. The delay time of the delay unit U2 is greater than the comparison time of the comparison unit. The output of the delay unit U2 is the third clock signal CLK3, which is used to control the output of the D flip-flop U1. Setting the delay time of the delay unit U2 to be greater than the comparison time of the comparison unit ensures that the delay unit U2 cannot output the third clock CLK3 normally when the comparison unit is performing a normal comparison. However, when the SAR ADC circuit enters a metastable state, that is, when the comparison unit has not obtained a result for a long time, the delay unit U2 can output the third clock CLK3 normally, thereby eliminating the metastable state through the output of the D flip-flop U1.The power supply voltage AVD is connected to the data input terminal of the D flip-flop U1 to keep the data input terminal of the D flip-flop U1 always at a high level. The non-inverting output terminal of the D flip-flop U1 is connected to the gate of the ninth MOS transistor M9 to control the conduction and cutoff of the ninth MOS transistor M9. The drain of the ninth MOS transistor M9 is connected to one input terminal (node a) of the comparator unit, and the source of the ninth MOS transistor M9 is grounded. When the ninth MOS transistor M9 is turned on, node a is directly connected to ground, so that the voltage of one input terminal of the comparator unit is the ground voltage 0. The inverting output terminal of the D flip-flop U1 is connected to the gate of the tenth MOS transistor M10. The drain of the tenth MOS transistor M10 is connected to the other input terminal (node b) of the comparator unit. The source of the tenth MOS transistor M10 is connected to the power supply voltage AVD. When the tenth MOS transistor M10 is turned on, node b is directly connected to the power supply voltage AVD, so that the voltage of the other input terminal of the comparator unit is the power supply voltage AVD. Furthermore, in this invention, the ninth MOS transistor M9 is a P-type MOS transistor, and the tenth MOS transistor M10 is an N-type MOS transistor, allowing the two output signals of the D flip-flop U1 to simultaneously turn on both the ninth MOS transistor M9 and the tenth MOS transistor M10. Thus, the output signals from the non-inverting and inverting output terminals of the D flip-flop U1 ensure that the voltages at the two input terminals (nodes a and b) of the comparison unit are one high and one low, preventing the entire SAR ADC circuit from entering a metastable state.
[0017] In addition, as a preferred embodiment of the present invention, the auxiliary unit further includes two first switches S11 and S12 and two second switches S21 and S22; one end of each of the two first switches S11 and S12 is grounded, the other end of one first switch S11 is connected to the gate of one MOS transistor (seventh MOS transistor M7) of the reset unit, and the other end of the other first switch S12 is connected to the gate of another MOS transistor (eighth MOS transistor M7) of the reset unit; one end of each of the two second switches S21 and S22 is connected to the gate of one MOS transistor (seventh MOS transistor M7) of the reset unit, a differential signal vip is input to the other end of one second switch S21, and another differential signal vin is input to the other end of the other second switch S22. Thus, by controlling the opening and closing of the two first switches S11 and S12 and the two second switches S21 and S22, the two differential signals vip and vin can be selectively input to the gates of the seventh and eighth MOS transistors. This also allows the seventh and eighth MOS transistors to be selectively used as input amplification units in addition to resetting the comparator unit, thereby improving the overall SAR... An ADC circuit can have two input signals simultaneously. When the voltage difference between the differential signals vip and vin is relatively small, the voltage difference at nodes a and b will increase accordingly, reducing the probability of metastability in the SAR ADC circuit.Furthermore, in this invention, the external clock signal CLK1 controls the opening / closing of the two first switches S11 and S12 and the two second switches S21 and S22. Specifically, when the external clock signal CLK1 is low, the two first switches S11 and S12 are closed, and the two second switches S21 and S22 are open; when the external clock signal CLK1 is high, the two first switches S11 and S12 are open, and the two second switches S21 and S22 are closed. When the external clock signal CLK1 is high, the entire SARADC circuit is in a reset state. At this time, the two first switches S11 and S12 are closed, causing the gates of the seventh MOSFET M7 and the eighth MOSFET M8 to be grounded and turned on, thus ensuring that nodes a and b are connected to the power supply voltage AVD and pulled high. Correspondingly, when the external clock signal CLK1 is low, the entire SARADC circuit... When the ADC circuit is in the comparison state, the two second switches S21 and S22 are closed, allowing the gates of the seventh MOSFET M7 and the eighth MOSFET M8 to receive differential signals vip and vin, respectively. At this time, both the seventh MOSFET M7 and the eighth MOSFET M8 act as input amplifiers, resulting in nodes a and b each having two identical signal inputs. Specifically, node a receives two differential signals vip through the seventh MOSFET M7 and the first MOSFET M1, while node b receives two differential signals vin through the eighth MOSFET M8 and the second MOSFET M2. Therefore, when the voltage difference between the differential signals vip and vin is relatively small, the voltage difference across nodes a and b increases accordingly, reducing the probability of metastability in the SAR ADC circuit.
[0018] Please refer to the references. Figure 1 The working process of the anti-metastable SAR ADC circuit of the present invention is described as follows: When the SAR ADC circuit is in reset state: the external clock signal CLK1 is low, so the output of the AND gate ADN is low, that is, the second clock signal CLK2 and the third clock signal CLK3 are also low. The low level of the second clock signal CLK2 will reset the D flip-flop U1. At the same time, because the external clock signal CLK1 is low, the first switches S11 and S12 are closed, and the second switches S21 and S22 are open. At this time, the gates of the seventh MOSFET M7 and the eighth MOSFET M8 are connected to ground, and the two MOSFETs are turned on, so that nodes a and b are connected to the power supply voltage. That is, the voltages of nodes a and b are both high. Therefore, the voltages of the output terminals vop and von are the same, both are low, thus achieving reset. At this time, all other MOSFETs are in the off state.
[0019] In the comparison state of the SAR ADC circuit: the external clock signal CLK1 is high. Since the voltages at the output terminals vop and von are the same and both low in the reset state, the XNOR gate always outputs a high level. At this time, the external clock signal CLK1 and the output of the XNOR gate are combined with an AND gate, making the output signal of the AND gate high. This means that the second clock signal CLK2 is pulled high. This turns on the current transistor M0, thus providing current to the entire SAR ADC circuit. Furthermore, when the external clock signal CLK1 is high, the first switches S11 and S12 are open, and the second switches S21 and S22 are closed. Therefore, the four MOSFETs M1, M2, M7, and M8 simultaneously function as input transistors. This means that the external differential signals vip and vin each have two inputs to the input terminals of the comparison unit (nodes a and b), accelerating the voltage difference between nodes a and b (each node has two identical inputs, further increasing the voltage difference between the input differential signals vin and vip). This activates the positive feedback system formed by the third MOSFET M3 to the sixth MOSFET M6. Once activated, the positive feedback system can quickly perform comparisons and obtain the comparison result. After the comparison result is obtained, the output terminals vop and von will cause the output of the XNOR gate to go low. This, combined with the AND gate, pulls the second clock signal CLK2 low, turning off the current transistor M0 and terminating the comparison, thus saving power.
[0020] The above describes the normal operation and reset state of the SAR ADC circuit. If the SAR ADC circuit becomes metastable (the two output voltages, vop and von, are the same), and the voltage difference between the differential input signals vin and vip is too small, the comparison unit cannot identify the voltage difference between vin and vip, resulting in no comparison result. Nodes a and b will remain in the reset state at a high level. The same output voltages vop and von cause the XNOR gate output to be high, and the external clock signal CLK1 is also high. Therefore, the second clock signal CLK2 will always be high. After a delay by delayer U2, the third clock signal CLK3 will also be pulled high. In the D flip-flop, the second clock signal CLK2 is high when it is in the working state. Once the third clock signal CLK3 is pulled high, the non-inverting output C and the inverting output CN will output high and low levels respectively. The non-inverting output C and the inverting output CN are output to the comparator unit to control the ninth MOSFET M9 and the tenth MOSFET M10 to conduct, forcibly pulling nodes a and b low and high respectively (specifically, node a is grounded, and its voltage is pulled low; node b is directly connected to the power supply voltage AVD, and its voltage is pulled high), forcibly completing the comparison, thereby eliminating the metastable state; after eliminating the metastable state, the output terminals vop and von present different voltages, making the output of the XNOR gate low and the output of the AND gate low, that is, controlling the second clock signal CLK2 to pull low, turning off the current transistor M0, and waiting for the external clock signal CLK1 to pull low before the entire SAR ADC circuit enters the reset state.
[0021] In summary, the anti-metastable SAR ADC circuit of the present invention, by setting the auxiliary unit, when the entire SAR ADC circuit enters a metastable state, pulls one of the voltages at the two input terminals (node a and node b) of the comparison unit high to the power supply voltage AVD and the other low to ground voltage, thereby enabling the comparison unit to complete the comparison process normally and obtain the comparison result. This eliminates the metastable state of the entire SAR ADC circuit and improves the working stability and accuracy of the SAR ADC circuit. Furthermore, in this invention, the externally input differential signals vin and vip can also be input into the circuit through the auxiliary circuit and the reset unit, so that each differential signal in the entire circuit has two inputs. When the voltage difference between the differential signals vip and vin is relatively small, the voltage difference at the input terminal of the comparison unit will correspondingly increase, reducing the probability of metastability in the SAR ADC circuit.
[0022] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.
Claims
1. A metastability-resistant SAR ADC circuit, comprising an amplification unit, a comparison unit, and a reset unit, wherein two external differential signals are respectively input to the amplification unit, the amplification unit amplifies the input differential signals and outputs them to the comparison unit, the comparison unit compares the input signal voltages and outputs the comparison result to complete the basic function of the SAR ADC circuit, and the reset unit is used to reset the comparison unit; characterized in that, It also includes an auxiliary unit connected to the comparison unit. When the circuit enters a metastable state, the auxiliary unit pulls down one of the voltages at the two input terminals of the comparison unit and pulls up the other, so that the comparison unit can complete the comparison process and eliminate the metastable state.
2. The anti-metastable SAR ADC circuit as described in claim 1, characterized in that, The auxiliary unit includes a D flip-flop, an XNOR gate, an AND gate, a delay unit, a ninth MOS transistor, and a tenth MOS transistor. The two outputs of the comparator unit are connected to the two inputs of the XNOR gate. The output signal of the XNOR gate and an external clock signal are input to the AND gate. The output of the AND gate is connected to the gate of the current transistor in the amplification unit, and the AND gate outputs a second clock signal. The second clock signal is delayed by the delay unit to output a third clock signal. The third clock signal is input to the clock control terminal of the D flip-flop. The power supply voltage is connected to the data input terminal of the D flip-flop. The second clock signal is input to the reset terminal of the D flip-flop. The non-inverting output terminal of the D flip-flop is connected to the gate of the ninth MOS transistor. The inverting output terminal of the D flip-flop is connected to the gate of the tenth MOS transistor. The drain of the ninth MOS transistor is connected to one input terminal of the comparator unit. The drain of the tenth MOS transistor is connected to the other input terminal of the comparator unit. The source of the ninth MOS transistor is grounded, and the source of the tenth MOS transistor is connected to the power supply voltage.
3. The anti-metastable SAR ADC circuit as described in claim 2, characterized in that, The auxiliary unit also includes two first switches and two second switches. One end of each of the two first switches is grounded, and the other end of one first switch is connected to the gate of a MOS transistor in the reset unit. The other end of the other first switch is connected to the gate of another MOS transistor in the reset unit. One end of each of the two second switches is connected to the gate of a MOS transistor in the reset unit. A differential signal is input to the other end of one second switch, and another differential signal is input to the other end of the other second switch.
4. The anti-metastable SAR ADC circuit as described in claim 3, characterized in that, The auxiliary unit also includes two inverters. One output terminal of the comparator is connected to one inverter to output an output signal of the SAR ADC circuit, and the other output terminal of the comparator is connected to another inverter to output another output signal of the SAR ADC circuit.
5. The anti-metastable SAR ADC circuit as described in claim 3, characterized in that, The ninth MOS transistor is a P-type MOS transistor, and the tenth MOS transistor is an N-type MOS transistor.
6. The anti-metastable SAR ADC circuit as described in claim 3, characterized in that, The delay time of the delay unit is greater than the comparison time of the comparison unit.
7. The anti-metastable SAR ADC circuit as described in claim 3, characterized in that, The external clock signal controls the opening / closing of the two first switches and the two second switches. When the external clock signal is low, the two first switches are closed and the two second switches are open; when the external clock signal is high, the two first switches are open and the two second switches are closed.