Dynamic storage distribution system and method for radio frequency signal broadband stream disk

Abstract

The invention relates to the technical field of software defined storage, and discloses a dynamic storage distribution system and method of a radio frequency signal broadband stream disk, comprising: a parameter configuration module analyzes radio frequency data flow rate and storage array physical parameters, and an address mapping module, based on a data frame time index, stores the data frame time index; executing modular operation by utilizing a step length factor which is co-prime with the total storage stripe number, and generating a target logic address of discrete jump; the strip assembly module constructs a standard write-in unit according to a physical alignment size, and the direct memory access control module constructs a straight-through transmission path and dispersedly writes data into different physical channels. Through a modal co-prime mapping mechanism, full-space deterministic discrete distribution of write-in addresses is realized on a pure logic level; physical single-point congestion during multi-channel concurrent writing is eliminated, I / O long tail delay is reduced, and zero frame loss and time sequence stability of a high-bandwidth radio frequency flow disc are ensured.

Description

Technical Field

[0001] This invention relates to a dynamic storage allocation system and method for a broadband radio frequency signal disk, belonging to the field of software-defined storage technology. Background Technology

[0002] In current radar echo acquisition, spectrum monitoring, and broadband communication testing, data storage solutions are mostly based on standard file systems or linear block device drivers, utilizing on-demand allocation strategies and dynamic metadata management to balance storage space utilization and random access performance. Simply relying on high-performance hardware stacking fails to fundamentally eliminate latency uncertainty, and the bottleneck shifts to the storage allocation and control logic level. For example, Chinese invention patent CN102104438A discloses a full-spectrum time-shifting device that converts broadband radio frequency signals into digital streams and stores them in a ring buffer through analog-to-digital conversion and digital filtering demodulation to achieve time-shifted playback of broadcast programs. This type of device, based on a traditional ring buffer write strategy, essentially still uses linear sequential write logic. When faced with constant high bit rate broadband radio frequency streaming disk tasks, it ignores the non-ideal physical characteristics of the underlying storage medium, i.e., flash memory. Linear writes trigger passive garbage collection or wear leveling operations within the medium. Instantaneous blockage of a single physical channel directly leads to unpredictable long-tail latency, causing frame drops in high-speed data streams, which cannot meet the deterministic timing requirements of industrial-grade broadband streaming disks.

[0003] Faced with continuous disk operation of constant high bit rate radio frequency signals, the uncertainty of allocation at the architecture logic layer and the heterogeneity of the physical layer media create contradictions. The file system free block lookup and metadata synchronization generate non-linear latency jitter as the data volume increases. The inherent bad block distribution and passive garbage collection mechanism of the underlying flash media cause the write response time to become discrete. In real-time acquisition systems with limited buffer depth, millisecond-level input and output blocking can lead to first-in-first-out queue overflow and signal frame loss. Although expanding the volatile memory buffer or over-configuring high-performance solid-state drive arrays can smooth out the fluctuations, it does not eliminate the source of latency uncertainty from the underlying addressing logic.

[0004] Therefore, how to construct a storage allocation mechanism that is independent of file system metadata and uses arithmetic logic to achieve deterministic adaptation of non-ideal physical media, and ensure the temporal consistency and integrity of high-bandwidth data streams under limited hardware conditions, has become the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A dynamic storage allocation system for a broadband radio frequency signal disk, the system comprising: The parameter configuration module is used to parse the data rate parameters of the RF signal stream to be stored and read the total number of stripes and physical strip alignment size of the underlying storage medium array; The address mapping module is used to generate the target logical block address by performing a modulo operation based on the monotonically increasing data frame time index during the writing process of the radio frequency signal stream using a preset step factor. The step factor is set to an integer coprime to the total number of stripes, so that the target logical block address traverses the address space of the storage medium array in a non-continuous discrete sequence within one period of the time index. The strip assembly module is used to slice and fill the RF signal stream based on the physical strip alignment size, and to build a standard write unit with the same data volume as the physical strip alignment size. The direct memory access control module is used to establish a direct data transmission path without going through the operating system file system. It transmits the standard write unit to the target logical block address generated by the address mapping module and uses discrete sequences to write continuous time data frames to different physical channels of the underlying storage medium array to balance the write load.

[0006] Preferably, the address mapping module uses the following coprime step-size modulo operation logic to generate the target logical block address: ,in, For the target logical block address, The starting base address, For data frame time index, Step size factor Total number of stripes For physical strip alignment dimensions, The bad block offset is used to ensure that the write address is evenly distributed throughout the entire storage space.

[0007] Preferably, the system further includes a pre-erasure scheduling module; the pre-erasure scheduling module is used to maintain a preprocessing time index that is ahead of the data frame time index; the address mapping module is used to calculate the range of preprocessing logical addresses to be written in the future based on the preprocessing time index and the step size factor; the direct memory access control module is used to send a deallocation instruction for the preprocessing logical address range to the underlying storage medium array, so that the underlying storage medium array releases the corresponding physical storage unit before the write operation is executed.

[0008] Preferably, the system further includes a rate calibration module; the rate calibration module is used to monitor the occupancy depth of the data buffer in the strip assembly module; when the occupancy depth shows a monotonically changing trend, the rate calibration module calculates a rate correction value and sends it to the address mapping module; the address mapping module is used to compensate for the data rate parameter using the rate correction value to synchronize the frequency deviation between the RF signal source clock and the system clock.

[0009] Preferably, the address mapping module further includes a bad block mapping table; the bad block mapping table is used to store the physical bad block address information of the underlying storage medium array; when generating the target logical block address, the address mapping module retrieves the bad block mapping table and calculates the cumulative address offset, adds the cumulative address offset to the address calculation result, and generates the actual write address that avoids physical bad blocks.

[0010] Preferably, the system also includes a redirected write module; the redirected write module is used to manage the reserved spare space at the end of the underlying storage medium array; when the direct memory access control module returns an error status when writing data to the target logical block address, the redirected write module writes the corresponding data to the reserved spare space and does not perform a retry operation at the original address, so as to maintain the stability of the write timing.

[0011] Preferably, the strip assembly module is configured with a dual-buffer switching mechanism; the dual-buffer switching mechanism includes two memory buffers with a capacity equal to the physical strip alignment size; the dual-buffer switching mechanism is used to control the memory buffer to receive the radio frequency signal stream, and at the same time control the filled memory buffer to perform a write operation through the direct memory access control module, and switch the working state of the two memory buffers after the write is completed, so as to realize the pipelined processing of data.

[0012] Preferably, the direct memory access control module is configured with an asynchronous commit queue; the depth of the asynchronous commit queue is set to be greater than the product of the average write latency of the underlying storage medium array and the data rate parameter to prevent instruction blocking; the parameter configuration module is also used to read the number of parallel channels of the underlying storage medium array; the step size factor is set to a prime number greater than the number of parallel channels to increase the channel spacing between adjacent data frames in physical space.

[0013] Preferably, the underlying storage medium array is a NAND flash memory array; the physical stripe alignment size set by the parameter configuration module is equal to the product of the physical page size of the NAND flash memory array and the array parallelism, so as to ensure that each write operation covers the complete physical stripe.

[0014] A dynamic storage allocation method for a broadband radio frequency signal disk includes the following steps: The data rate parameters of the radio frequency signal stream to be stored are parsed, and the total number of stripes and physical stripe alignment size of the underlying storage medium array are read. During the writing of the radio frequency signal stream, the target logic block address is generated by performing a modulo operation using a preset step size factor based on the monotonically increasing data frame time index. The step size factor is set to an integer coprime to the total number of stripes, so that the target logical block address traverses the address space of the storage medium array in a non-continuous discrete sequence within one cycle of the time index. Based on the physical strip alignment size, the RF signal stream is segmented and filled to construct a standard write unit with the same data volume as the physical strip alignment size; A direct data transfer path is established without going through the operating system's file system. Standard write units are transferred to the target logical block address. Continuous time data frames are distributed and written to different physical channels of the underlying storage medium array using discrete sequences to balance the write load.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In the dynamic storage of broadband streaming disks, modal coprime discrete spiral mapping logic is adopted to transform the time-series continuous RF data stream into a physically spatially discrete jump write sequence. By utilizing the coprime relationship between the step factor and the total number of stripes in the storage medium, the continuously arriving data frames are evenly distributed to different physical channels and wafer cells of the underlying storage array. The spatial discretization distribution avoids the instantaneous blocking bottleneck of a single physical wafer due to programming setup time or internal management operations caused by continuous linear writing from a logical level, ensuring that the instantaneous throughput of the storage array is stable at the level of the average physical bandwidth of multi-channel concurrency. There is no need to maintain a dynamic wear leveling table or perform background data transfer. The uniform wear of the entire storage space is achieved through arithmetic traversal attributes, eliminating random I / O latency jitter caused by file system metadata operations, ensuring constant addressing operation time complexity, and meeting the requirements of broadband RF signal streaming disks for zero frame loss and temporal determinism.

[0016] 2. By co-configuring static bad block masks and overflow absorption areas, a stateless fault-tolerant write path independent of the underlying media state is constructed. During the address generation stage, the inherent defects of the physical media are internalized into arithmetic calculations of static offsets. Without performing real-time media state queries or file allocation table reads, the target physical address to avoid known bad blocks is directly generated. Combined with the overflow absorption mechanism, when occasional write errors or new bad blocks cause hardware feedback failures, the data stream is unconditionally redirected to a reserved physical contiguous area. The non-trigger time-consuming error verification and retry process, combined with this mechanism, transforms the storage system's strategy for dealing with physical media inconsistencies from traditional runtime dynamic error correction to pre-arithmetic avoidance and deterministic bypassing. This cuts off the transmission chain of system timing collapses caused by physical media errors, ensuring continuous and stable writing in a bare device environment without file system management.

[0017] 3. By coupling pre-emptive physical cleanup scheduling with adaptive rate parameter calibration, the dual challenges of physical media performance degradation and heterogeneous clock drift during long-term operation are solved. The pre-emptive cleanup mechanism utilizes the predictability of write addresses to establish a cleanup window ahead of the write action on the timeline, issuing deallocation instructions in advance. This allows the storage controller to complete physical page erasure and recycling during write intervals, ensuring that the media is in a clean state when data arrives, eliminating read / write latency caused by passive garbage collection. The rate calibration mechanism uses the direct memory access buffer fill level as a measure of clock phase difference integration, dynamically fine-tuning the address mapping algorithm rate parameters through a negative feedback loop. The combination of these two mechanisms ensures constant instantaneous response performance of the media at the physical level and locks the clock phase of the signal source and storage system at the logical level. This enables the system to achieve long-term continuous recording capabilities across cycles without relying on external hardware synchronization or expensive enterprise-grade solid-state drives. Attached Figure Description

[0018] Figure 1 This is a logical architecture diagram of the dynamic storage allocation system for the radio frequency signal broadband streaming disk of the present invention; Figure 2 This is a comparison curve of write latency performance under the pre-erase scheduling mechanism of the present invention; Figure 3 This is a sequence diagram of module interactions during the system initialization and data writing process of this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit the scope of protection of this invention.

[0020] This invention discloses a dynamic storage allocation system for a broadband radio frequency (RF) signal disk, comprising a parameter configuration module, an address mapping module, a stripe assembly module, a direct memory access control module, a pre-erase scheduling module, a rate calibration module, and a redirection write module. These modules are logically connected sequentially. The data stream enters from the RF front-end interface, undergoes striping processing, and is written to the non-volatile memory array via a direct memory access channel based on the physical address generated by the discrete spiral mapping logic. The parameter configuration module is used to normalize the physical layer parameters. During system initialization, this module establishes a communication connection with the underlying storage controller, bypassing the operating system file system, and directly sends query commands to the raw device to obtain the geometric parameters of the storage medium array. Key parameters parsed by the parameter configuration module include the total number of addressable logic blocks and the physical stripe alignment size. and the number of parallel physical channels within the storage array Based on the total number of addressable logic blocks and the physical stripe alignment size The parameter configuration module calculates the total number of stripes in the storage medium array based on the ratio. Simultaneously, this module performs a full-disk scan or reads the media's factory defect table to construct a static bad block mapping table. This table records the starting logical block address and length of all known physical bad blocks. The address mapping module executes discrete spiral mapping logic based on modal coprime to solve the load balancing problem during multi-channel concurrent writes. This logic uses arithmetic calculations to generate discrete jump target addresses. The address mapping module receives a global clock signal from the RF interface and maintains a monotonically increasing data frame time index. This module has a preset step size factor. The step size factor The value of follows a deterministic procedure, that is, it is selected to be greater than the number of parallel physical channels. The integer benchmark is determined, and the integer benchmark is verified to match the total number of stripes. Whether they are coprime, i.e., their greatest common divisor. equal If they are not coprime, then increment the integer base until the coprime condition is met.

[0021] During the data writing process, for each arriving data frame, the address mapping module calculates the target logical block address according to the following formula. : ,in, For the target logical block address, This is the preset starting base address of the storage partition. The time index of the current data frame. The step size factor is the coprime step size factor mentioned above. Total number of stripes For physical strip alignment dimensions, The address mapping module calculates the initial address and then searches the bad block mapping table to determine the bad block offset. If the initial address falls within the bad block range, the address is updated based on the bad block length. The address is shifted backward to the next valid stripe position, because and Coprime, this modulo operation guarantees that from Increase to During the complete cycle, the generated Each available stripe in the storage space is traversed without repetition, and the physical addresses corresponding to adjacent time indices span across spatial boundaries. Each stripe forces the data stream to jump significantly between different physical channels and wafer chips; the stripe assembly module is responsible for data fragmentation and regularization to ensure that the RF data matches the physical medium's write granularity. This module allocates a set of dual-switching buffers in memory, with the size of each buffer set to the physical stripe alignment size. The radio frequency signal stream is continuously filled into the currently active buffer when the data volume in the buffer reaches an integer multiple of the current active buffer. When the strip assembly module triggers a write request, it marks the buffer as ready and switches to the standby buffer to continue receiving data. This process ensures that the data payload of each write command sent to the storage controller is aligned with the physical boundary of the underlying flash page or superblock.

[0022] The Direct Memory Access Control (DMI) module establishes a pass-through data transfer path in user mode to eliminate the context overhead caused by switching between operating system kernel mode and user mode. This module uses a polling mode to take over the memory controller and manages input / output requests by constructing an asynchronous commit queue and a completion queue based on a ring buffer. The DMI module directly fills the physical memory addresses of the ready buffers in the stripe assembly module into the write instruction descriptors defined in the non-volatile memory host controller interface specification, and uses a doorbell register to notify the memory controller to initiate direct memory access transfer. The transfer process completely bypasses the operating system's page cache mechanism. To prevent instruction blocking under high concurrency, the asynchronous commit queue depth configured in this module is [not specified in the original text]. Set to meet the following conditions: ,in, To determine the depth of the submission queue, For radio frequency data stream rate, The average write response latency of the storage medium. The physical stripe alignment size is specified; the pre-erase scheduling module executes pre-processing physical cleanup logic to address the garbage collection delay issue of NAND gate flash media in overwrite scenarios. This module maintains a preprocessing time index. This index is numerically equal to the current write time index. Add the preset advance offset Lead offset The determination is based on the worst-case erase time of the storage medium. Set, satisfy The pre-erasure scheduling module utilizes the same modal coprime discrete spiral mapping formula as the address mapping module, based on... The module calculates the range of preprocessed logical addresses to be written in the future, constructs a dataset management instruction defined by the non-volatile memory host controller interface specification, sets the attribute fields to deallocation or pruning, and inserts the instruction into the asynchronous commit queue. After receiving the instruction, the underlying storage controller performs physical block erasure and reclamation operations in advance within the idle time window before the actual write data arrives, so that subsequent write operations only require the execution of programming steps.

[0023] The rate calibration module performs closed-loop adaptive adjustment to address the frequency drift issue between the RF signal source clock and the local clock of the storage system. This module monitors the occupancy depth of the direct memory access buffer in the stripe assembly module in real time. The system has a preset equilibrium water level. This value is typically set to 50% of the buffer capacity, when detected... When a continuously monotonically increasing or decreasing trend is observed, it indicates that the source clock frequency is higher or lower than the local system's nominal clock frequency. The rate calibration module calculates the rate correction factor based on the deviation. The calculation formula is: ,in, For rate correction factor, This is the proportionality coefficient. The current buffer depth. To balance the water level, This correction factor represents the total buffer capacity. Feedback is sent to the address mapping module to fine-tune the logical data rate parameter in the address calculation formula, thereby compensating for the frequency difference of the physical clock in the logical address generation speed and preventing buffer overflow or underload. The redirected write module provides a passive exception absorption mechanism to deal with occasional write errors that may occur during runtime. The system reserves a fixed proportion of physical space at the end of the storage medium array as an overflow absorption area. When the direct memory access control module detects that a write instruction returns a media error or write failure status code when processing the completion queue, it does not perform a retry operation for the original target address, but redirects the stripe data to the next available linear address in the overflow absorption area, and records the mapping relationship between the original target address and the redirected address in the memory metadata log. This mechanism ensures that the overall timing of the write process is not interrupted or delayed when a partial failure occurs in the physical medium.

[0024] Example 1: In a broadband radio frequency signal recording scenario with a non-volatile memory array, the system needs to handle a constant data flow of several gigabytes per second. The underlying storage medium consists of multiple parallel physical channels and independent wafer cells. If conventional linear sequential writing is used, the microsecond-level delay caused by internal programming or garbage collection operations on a single physical channel leads to overflow of the front-end finite-depth first-in-first-out queue and data frame loss. The parameter configuration module reads the physical parameters of the storage medium array to determine the total number of stripes. Alignment size with physical strip The address mapping module executes discrete spiral mapping logic with coprime modes based on this geometric information. As the RF data stream continues to be input, the data frame time index... It exhibits a monotonically linear increasing trend, and the address mapping module utilizes a preset step size factor. right Perform arithmetic operations, the step size factor Set to the total number of stripes Coprime integers greater than the number of parallel channels generate a sequence of logical block addresses that exhibit a discontinuous and large-jump distribution in physical space. This allows adjacent data frames arriving consecutively in time to be mapped to different physical channels and wafer cells of the underlying storage array. The instantaneous latency jitter caused by the erase and write operations of a single physical channel is absorbed and amortized by the remaining idle parallel channels in the spatial dimension, thus achieving physical load balancing.

[0025] The strip assembly module shapes the continuous RF flow into a matching module. The standard write unit, the Direct Memory Access Control (DMI) module bypasses the operating system cache through the DMI channel, directly writing data to the discretely calculated physical address. This process eliminates the metadata read / write overhead required for the file system to dynamically search for free blocks, ensuring that the instruction commit latency for each write operation depends only on the controller hardware response speed. Simultaneously, the pre-erase scheduling module utilizes the deterministic arithmetic characteristics of the address mapping module, based on an advanced preprocessing time index. The system calculates the address range to be written in the future and issues deallocation instructions in advance. This mechanism utilizes the write gap to allow the storage controller to complete the physical page reset before the data actually arrives, so that only programming operations need to be performed during the real-time write phase, avoiding the accumulation of latency caused by the read-modify-write process in a single write cycle. In addition, for clock drift during long-term disk streaming, the rate calibration module monitors the fill level of the direct memory access buffer. When the level deviates from the preset balance point, the module dynamically adjusts the rate parameters in the address mapping logic. Through a closed-loop negative feedback mechanism, it maintains the phase lock between the logical address generation rate and the physical data inflow rate, preventing buffer overflow or underload caused by the asynchronous clocks of the source and storage ends. Through deterministic mapping of arithmetic logic and active scheduling at the physical layer, the system can stabilize the instantaneous throughput of the storage array at the average physical bandwidth level of multi-channel concurrency without maintaining a dynamic file allocation table or relying on an enterprise-level controller.

[0026] Example 2: This example verifies the performance of the dynamic storage allocation system under different workloads and environmental interferences through quantitative experiments conducted on an industrial-grade server platform, and confirms the technical effectiveness in terms of synergistic efficiency and conflict resolution. The test platform is configured with a PCIe Gen4 NVMe solid-state drive array. The original input data comes from the signal generator of an analog broadband radio frequency receiver, which generates an I / Q data stream with a constant code rate and random burst noise. To evaluate the system robustness, a multi-dimensional control system is designed. The sample group of this invention fully enables discrete spiral mapping, stripe-aligned direct writing, pre-erase scheduling, and rate calibration mechanisms. The baseline control group uses the standard Linux EXT4 file system for file-level writing to simulate existing conventional technical solutions. The partially missing control group disables the pre-erase scheduling module based on the sample group of this invention to isolate and quantify the independent contribution of the pre-erasure physical cleanup mechanism to the write latency stability. The out-of-range control group uses a step size factor. The value is set to be less than the number of parallel physical channels to verify the rationality of the parameter boundary setting.

[0027] The experiment primarily focuses on the determinism of write latency. During a 72-hour full-disk cyclic write test, the completion time of each single write operation was monitored and recorded in real time. The baseline control group data showed obvious long-tail latency characteristics, with the average latency maintained at the microsecond level, but a latency spike of more than 100 milliseconds or even reaching the second level occurred every few seconds. This phenomenon is consistent with the file system performing metadata log synchronization and passively triggered garbage collection actions. The latency performance of the sample group of this invention showed extremely high convergence. See Table 1. Its maximum write latency was controlled at the sub-millisecond level, and the standard deviation of the latency distribution was lower than that of the control group.

[0028] Table 1: Comparison of Write Delay Statistics for Different Experimental Groups

[0029] The above data shows that the sample of this invention achieves dual optimization of mean and tail latency. This is attributed to the synergistic effect of discrete spiral mapping and pre-erasure scheduling. Discrete mapping evenly scatters continuous write pressure to all physical channels, avoiding single-point overheating. The pre-erasure mechanism ensures that the target physical page is always in a clear state when the write command arrives, eliminating the uncertainty caused by physical layer read / write operations. Partial missing control group data confirms that in the absence of the pre-erasure mechanism, although the average latency is lower, the P99.99 latency deteriorates, indicating that physical layer garbage collection conflicts are the main cause of long tail latency. The second key dimension of the experiment is the stability against clock drift. In the experiment, a clock frequency deviation of positive 20 / 1 million was artificially introduced at the signal generator. For the control group without the rate calibration mechanism enabled, the buffer level showed a linear upward trend over time and overflowed after about 4 hours of operation, resulting in data frame loss. The rate calibration module in the sample of this invention automatically calculates and applies a reverse rate correction factor by monitoring the rate of change of the buffer level in real time. As shown in Table 2, after calibration was enabled, the water level in the buffer zone fluctuated slightly around the preset 50% threshold without exhibiting monotonic divergence.

[0030] Table 2: Buffer Zone Water Level Changes under Clock Drift Conditions

[0031] In summary, this embodiment quantitatively verifies the effectiveness of the present invention in eliminating I / O latency jitter, balancing physical load, and adapting to hardware clock differences through multiple sets of comparative experiments.

[0032] Example 3: This example combines Figures 1 to 3 This document describes a dynamic storage allocation system and method for a broadband radio frequency signal disk, as follows: Figure 1 As shown, the dynamic storage allocation system of the RF signal broadband stream disk is composed of multiple functional modules working together. The RF signal stream to be stored serves as the system input, and after being processed by each module, it is stored into the underlying storage medium array. The parameter configuration module is responsible for parsing the data rate parameters and reading the total number of stripes and the physical stripe alignment size of the underlying storage medium array. The parsed physical parameters are passed to the stripe assembly module and the address mapping module respectively. The stripe assembly module performs fragmentation and padding operations on the input RF signal stream according to the received physical parameters to construct a standard write unit that matches the geometric characteristics of the physical medium. After receiving the parameters, the address mapping module performs modulo operation using a step size factor that is coprime to the total number of stripes to generate the target logical block address with full-space discrete jump. The direct memory access control module is located at the end of the data path. It receives the standard write unit from the stripe assembly module and the target logical block address generated by the address mapping module, establishes a direct transmission path without going through the file system, and writes the data to different physical channels of the underlying storage medium array.

[0033] like Figure 2 As shown, the horizontal axis represents the time point, i.e., the sampling point, and the vertical axis represents the write latency, in microseconds (μs). The legend distinguishes between two operating conditions: no pre-erase scheduling and pre-erase scheduling. The dashed line in the figure represents the latency variation curve without pre-erase scheduling, exhibiting periodic pulse characteristics on the time axis. Its latency peak repeatedly approaches or reaches 300 μs, indicating that the system has significant write blocking at specific time points. The solid line in the figure represents the latency variation curve with pre-erase scheduling. This curve remains stable throughout the entire sampling period, with the value consistently maintained in the low range around 50 μs, without significant fluctuations or spikes. Figure 3 As shown, the system's runtime interaction logic is divided into a system initialization phase and a data writing phase, encompassing six main components: an RF signal source, a parameter configuration module, a stripe assembly module, an address mapping module, a DMA control module, and a storage medium array. In the system initialization phase, the parameter configuration module sends a query command to the storage medium array. Upon receiving the returned total number of stripes, alignment size, and number of channels, it calculates the step size factor and verifies their coprimeity to complete the configuration of the mapping parameters. In the data writing phase, as continuous data streams are written, the RF signal source sends the input RF data frame to the stripe assembly module. After filling the buffer to the alignment size, the stripe assembly module requests the target address based on the time index T_{idx} from the address mapping module. The address mapping module performs modulo operations to generate discrete addresses and returns the target logical block address. The stripe assembly module submits a standard write unit to the DMA control module. Finally, the DMA control module performs a direct memory access write operation, storing the data in the storage medium array and receiving a write completion confirmation signal.

[0034] Example 4: This example provides an in-depth analysis of the key parameter calibration procedures and rate calibration mechanisms in dynamic memory allocation systems to eliminate potential problems regarding step size factor selection and clock drift compensation, ensuring the reproducibility of the technical solution at the engineering level. It focuses on the step size factor, a core parameter in the address mapping module. Based on the given settings, this invention constructs a deterministic computation procedure based on number theory properties, which is determined by the number of physical channels in the storage array. Determine the lower limit of the benchmark The value is equal to Initiate the coprime check loop and calculate With total number of stripes If the greatest common divisor is 1, then directly determine the value of the greatest common divisor. If it is greater than 1, then... Increment by 1 and repeat the above check until the smallest integer satisfying the coprime condition is found. This procedure ensures that the generated logical address sequence mathematically traverses the entire memory space, and that adjacent addresses are maximized discretely at the physical channel level, avoiding arbitrary settings. This applies to the rate correction factor in the rate calibration module. This embodiment discloses its closed-loop feedback control logic based on the buffer level for calculation and application. In actual operation, the system sets a high-water level threshold for the direct memory access buffer. and low water level threshold These correspond to the total capacity of the buffer, respectively. 80% and 20%, when the water level is monitored in real time continued If the sampling period is higher than 1 second. If the input rate is determined to be too fast, the rate calibration module calculates a positive correction; if it remains below a certain value... Then, the negative correction amount is calculated. The calculation of the correction amount follows the proportional-integral control algorithm, and its discretized expression is as follows: ,in, For the first Rate correction factor at each moment, The water level deviation at the current moment, i.e. , The target water level is 50% of capacity. and These are preset proportional and integral coefficients. The algorithm dynamically adjusts the logic rate of address generation based on accumulated deviation, ensuring the buffer level always converges within a safe range. This achieves adaptive phase locking between logical address generation and physical data inflow without requiring external hardware synchronization signals. The address generation unit is embedded in a five-stage FPGA hardware pipeline: the first stage performs multiplication, the second stage performs modular arithmetic using a Barrett operator instead of division, the third stage concurrently searches the on-chip SRAM bad block bitmap, the fourth stage superimposes static offsets, and the final stage outputs physical instructions; the entire path delay is locked. One clock cycle; during buffer underload, the instruction sender continuously injects no-operation instructions into the bus. Maintain the topological integrity of the control flow computation graph.

[0035] In addition, regarding the advance offset in the pre-erasure scheduling module The setting of this parameter is clearly defined in this embodiment, based on the calculation basis of the physical characteristics of the storage medium. The value of this parameter satisfies the following inequality: ,in, This is the lead offset. To obtain the worst-case block erase time from the storage medium's technical specifications, This refers to the nominal data rate of the radio frequency stream. To determine the physical strip alignment dimensions, the system reads the aforementioned physical parameters during the initialization phase and substitutes them into the formula to calculate... The theoretical minimum value is calculated, and a safety margin of 20% is added to this value as the final operating parameter. This calculation process ensures that the pre-erase command is issued sufficiently ahead of the actual data arrival time on the timeline, guaranteeing that the physical medium has been cleaned before writing, eliminating the uncertainty and delay caused by garbage collection operations. Through the above transparent description of the key parameter calibration procedure and control logic, this embodiment constructs a logical closed loop to reproduce the core functions of the system in different hardware environments. The pre-erase command is issued with forced association with NAND status register polling; the write control logic integrates hardware interlock gate circuits; and the physical page programming voltage... Before application, the comparator detects the erase voltage. Release status and Pin level; when the charge pump is reset and the status bit is toggled, the write channel instruction level block is released; the physical layer strictly controls the tunneling effect and hot electron injection timing isolation to avoid metadata corruption caused by dielectric voltage conflicts.

[0036] Example 5: This example addresses the deployment adaptability and long-term operational stability of dynamic storage allocation systems in heterogeneous hardware environments. It supplements this by constructing a standardized parameter adaptive calibration procedure and failure recovery mechanism. To address potential physical performance differences between different batches of storage media, the system has a built-in initialization calibration program that is automatically triggered upon system power-on or storage media replacement. This program writes a set of test data for specific modes to the storage array, covering sequential write, random write, and mixed read / write scenarios. By measuring the actual throughput and latency distribution under different loads, the program automatically calculates and updates the physical stripe alignment size in the parameter configuration module. Compared to average write response latency Meanwhile, the program determines the maximum number of concurrent channels on the storage medium under the current environment through traversal testing, and dynamically adjusts the step factor in the address mapping module accordingly. To ensure that it always meets the requirements of the total number of stripes They are coprime and can maximize the use of physical channel bandwidth.

[0037] To address the potential issue of uneven wear on storage units during long-term operation, the system introduces a dynamic wear leveling monitoring and remapping mechanism. This mechanism continuously monitors the write / erase counts for each physical stripe and maintains a global wear table. When the write / erase count of a stripe exceeds the overall disk average and a preset threshold, the address mapping module automatically adjusts its mapping logic, redirecting the logical address that originally pointed to the high-wear stripe to a spare stripe with lower wear. This process is performed transparently in the background without interrupting the upper-layer RF data writing process. Furthermore, to cope with abnormal operating conditions such as sudden power outages, the system establishes a breakpoint recovery procedure based on non-volatile logs. Before each write command is submitted, the direct memory access control module records the target physical address and data length in a persistent memory area with power-loss protection. After the system restarts, it scans this log area, identifies incomplete write operations, and replays or rolls them back.

[0038] Example 6: This example details a standardized pre-deployment calibration procedure for a broadband streaming disk system for radio frequency signals. It addresses engineering problems such as missing physical / geometric parameter setting criteria and unclear process control parameter calibration methods. Designed as an execution step for initial system deployment or after hardware changes, it ensures consistent system performance under non-ideal physical environments, specifically addressing the physical stripe alignment dimensions of the storage medium. To determine the block size, an automated probing process based on micro-benchmarking is executed. The system initiates a series of random write requests with different block sizes to the storage array and records the average input / output response time for each block size. The block size starts at 4KB and increases in 4KB increments up to 256KB. By analyzing the response time curve as a function of block size, the system identifies the inflection point of latency spikes or the starting point of throughput plateaus. The procedure identifies the block size corresponding to this inflection point as the optimal alignment boundary of the underlying medium's physical page or erase block and solidifies this value. The system's default parameters.

[0039] And the advance offset in the pre-erase scheduling module The settings are configured to execute an optimal operating point optimization procedure based on extreme stress testing, and the determination is made accordingly. Then, under full-load write conditions, the system increments by a preset step size. The value is recorded, and the P99.99 metric for write latency is monitored in real time. Based on the tail delay data, construct an offset delay relationship model when After increasing to a certain point, if the tail delay no longer decreases and remains at the minimum level, then this point represents the optimal lead amount to meet the media erase time requirements. This procedure eliminates dependence on manufacturer-specified parameters through measured data, ensuring that pre-erasure operations effectively cover the worst-case execution time of garbage collection on any specific batch of storage media. Finally, regarding the scaling factor in the rate calibration module... With integral coefficient The system is configured using a self-tuning method based on step response. A known clock frequency deviation step signal, such as 50 parts per million, is artificially introduced into the system, and the dynamic response curve of the buffer level is recorded. By analyzing the rise time, overshoot, and steady-state error of the response curve, the Ziegler-Nichols rule or similar engineering tuning formulas are used to calculate the optimal tuning parameters that result in the fastest and most oscillatory system response. and This calibration process combines control theory with clock synchronization in storage systems.

[0040] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A dynamic storage allocation system for a broadband radio frequency signal disk, characterized in that, The system includes: The parameter configuration module is used to parse the data rate parameters of the RF signal stream to be stored and read the total number of stripes and physical strip alignment size of the underlying storage medium array; The address mapping module is used to generate the target logic block address by performing modulo operations based on the monotonically increasing data frame time index and using a preset step size factor during the writing of the radio frequency signal stream. The step size factor is set to an integer coprime to the total number of stripes, so that the target logical block address traverses the address space of the storage medium array in a non-continuous discrete sequence within one cycle of the time index. The strip assembly module is used to slice and fill the RF signal stream based on the physical strip alignment size, and to build a standard write unit with the same data volume as the physical strip alignment size. The direct memory access control module is used to establish a direct data transmission path without going through the operating system file system. It transmits the standard write unit to the target logical block address generated by the address mapping module and uses discrete sequences to write continuous time data frames to different physical channels of the underlying storage medium array to balance the write load.

2. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The address mapping module uses the following coprime step-size modulo operation logic to generate the target logical block address: ,in, For the target logical block address, The starting base address, For data frame time index, Step size factor Total number of stripes For physical strip alignment dimensions, The bad block offset is used to ensure that the write address is evenly distributed throughout the entire storage space.

3. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The system also includes a pre-erasure scheduling module; The pre-erase scheduling module is used to maintain a preprocessing time index that is ahead of the data frame time index; the address mapping module is used to calculate the range of preprocessing logical addresses to be written in the future based on the preprocessing time index and the step size factor; the direct memory access control module is used to send a deallocation instruction for the preprocessing logical address range to the underlying storage medium array, so that the underlying storage medium array releases the corresponding physical storage unit before the write operation is executed.

4. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The system also includes a rate calibration module; the rate calibration module is used to monitor the occupancy depth of the data buffer in the strip assembly module; when the occupancy depth shows a monotonically changing trend, the rate calibration module calculates the rate correction value and sends it to the address mapping module; The address mapping module is used to compensate for the data rate parameter using the rate correction value in order to synchronize the frequency deviation between the RF signal source clock and the system clock.

5. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The address mapping module also includes a bad block mapping table; the bad block mapping table is used to store the physical bad block address information of the underlying storage medium array; when generating the target logical block address, the address mapping module retrieves the bad block mapping table and calculates the cumulative address offset, adds the cumulative address offset to the address calculation result, and generates the actual write address that avoids physical bad blocks.

6. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The system also includes a redirected write module; the redirected write module is used to manage the reserved spare space at the end of the underlying storage medium array; when the direct memory access control module returns an error status when writing data to the target logical block address, the redirected write module writes the corresponding data to the reserved spare space and does not perform a retry operation at the original address, so as to maintain the stability of the write timing.

7. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The strip assembly module is equipped with a dual-buffer switching mechanism; the dual-buffer switching mechanism includes two memory buffers with a capacity equal to the physical strip alignment size; the dual-buffer switching mechanism is used to control the memory buffer to receive the radio frequency signal stream, and at the same time control the full memory buffer to perform write operations through the direct memory access control module, and switch the working state of the two memory buffers after the write is completed, so as to realize the pipelined processing of data.

8. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The direct memory access control module is configured with an asynchronous commit queue; the depth of the asynchronous commit queue is set to be greater than the product of the average write latency and the data rate parameter of the underlying storage medium array to prevent instruction blocking. The parameter configuration module is also used to read the number of parallel channels of the underlying storage medium array; the step factor is set to a prime number greater than the number of parallel channels to increase the channel spacing between adjacent data frames in physical space.

9. The dynamic storage allocation system for a broadband radio frequency signal disk according to claim 1, characterized in that, The underlying storage medium array is a NAND flash memory array; the physical stripe alignment size set by the parameter configuration module is equal to the product of the physical page size of the NAND flash memory array and the array parallelism, so as to ensure that each write operation covers the complete physical stripe.

10. A dynamic storage allocation method for a broadband radio frequency signal disk, used to implement the system described in claim 1, characterized in that, Includes the following steps: The data rate parameters of the radio frequency signal stream to be stored are parsed, and the total number of stripes and physical stripe alignment size of the underlying storage medium array are read. During the writing of the radio frequency signal stream, the target logic block address is generated by performing a modulo operation using a preset step size factor based on the monotonically increasing data frame time index. The step size factor is set to an integer coprime to the total number of stripes, so that the target logical block address traverses the address space of the storage medium array in a non-continuous discrete sequence within one cycle of the time index. Based on the physical strip alignment size, the RF signal stream is segmented and filled to construct a standard write unit with the same data volume as the physical strip alignment size; A direct data transfer path is established without going through the operating system's file system. Standard write units are transferred to the target logical block address. Continuous time data frames are distributed and written to different physical channels of the underlying storage medium array using discrete sequences to balance the write load.

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