Enhanced diamond field effect transistor based on two silicon terminals and preparation method thereof

Abstract

The invention discloses an enhanced diamond field effect transistor based on two silicon terminals and a preparation method of the enhanced diamond field effect transistor, and relates to the technical field of semiconductors. The first silicon terminal layer is located on the upper surface of the diamond substrate and comprises two parts which are located on the two sides of the upper surface of the diamond substrate respectively; the second silicon terminal layer is located on the upper surface of the diamond substrate and located between the two parts included by the first silicon terminal layer; the first silicon terminal layer and the second silicon terminal layer have different electrical properties; the source electrode is located on the upper surface of one part of the two parts of the first silicon terminal layer; the drain electrode is positioned on the upper surface of the other part of the two parts of the first silicon terminal layer; the silicon oxide layer is located on the upper surface of the second silicon terminal layer; and the grid is located on the upper surface of the silicon oxide layer. The performance of the device can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to an enhanced diamond field-effect transistor based on two types of silicon terminals and its fabrication method. Background Technology

[0002] Diamond is a representative of ultra-wide bandgap semiconductor materials, possessing high breakdown electric field, high thermal conductivity, and excellent physicochemical stability, earning it the reputation of being the ultimate semiconductor material. Diamond material has an ideal electron mobility of 4500 cm² / Vs and an ideal hole mobility of 3800 cm² / Vs, with a saturation velocity as high as 3 × 10⁷ cm / s, indicating that diamond devices have ideal application prospects in the field of high-speed switching devices.

[0003] The excellent electrical properties of diamond materials determine the application potential of diamond devices. Currently, research on diamond devices mainly focuses on hydrogen-terminated diamond field-effect transistors (FETs). However, the inherent characteristic of hydrogen-terminated diamond is the formation of a high concentration of two-dimensional hole gas, exhibiting depletion-type characteristics. To achieve enhancement-type, i.e., a "normally closed" state, the threshold voltage of the device must be tuned to a significantly positive value, which is physically very difficult. Enhancement-type field-effect transistors (FETs) are the most fundamental and widely used switching devices in the field of power electronics. Their core characteristic is that the channel is in a closed state when the gate voltage is zero, thus ensuring the safety and controllability of the circuit. This "normally closed" characteristic makes them the default choice for power switching applications.

[0004] Currently, there are two main technical approaches for diamond enhancement-mode (DEM) field-effect transistors (FETs). One approach involves controlling the gate dielectric quality to deplete the carriers in the diamond channel, achieving a normally closed channel. The other approach involves controlling the diamond surface terminations to regulate the surface work function, also achieving a normally closed channel. Compared to mature silicon-based technologies, the fabrication of diamond FETs is still in the exploratory stage, lacking a stable, reliable, and scalable standard process for precisely manufacturing enhancement-mode devices. Each step, from substrate preparation and diamond surface termination control to gate formation, involves multiple variables that require precise control. Any minute deviation can cause the device mode to change from enhancement-mode to depletion-mode, or result in substandard performance due to limitations in overcoming hydrogen termination.

[0005] Silicon termination has emerged as a highly promising method for fabricating diamond-enhanced MOSFETs. The core idea of ​​this technology is to utilize silicon atoms to replace hydrogen atoms and bond with carbon atoms on the diamond surface, forming stable C-Si covalent bonds. The C-Si bond energy is much higher than that of the CH bond, giving the silicon termination surface greater thermal stability and chemical inertness, enabling it to withstand subsequent higher-temperature processing. The silicon termination itself does not directly induce the generation of high-concentration two-dimensional hole gas; its surface typically exhibits a high-resistivity state, providing an ideal starting point for "opening" the channel through gate voltage and achieving enhanced operating modes. Despite the enormous potential of silicon termination, this technology is still in its early research stages. Achieving high-quality, uniform, and defect-free diamond-silicon termination surfaces, and then constructing high-performance, stable enhanced field-effect transistors based on these surfaces, remains a core technical challenge for those skilled in the art. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides an enhanced diamond field-effect transistor based on two types of silicon terminals and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides an enhanced diamond field-effect transistor based on two types of silicon terminals, comprising: Diamond substrate; The first silicon termination layer is located on the upper surface of the diamond substrate and includes two parts, which are located on both sides of the upper surface of the diamond substrate, respectively. The second silicon termination layer is located on the upper surface of the diamond substrate and between the two parts of the first silicon termination layer; the electrical characteristics of the first silicon termination layer and the second silicon termination layer are different. The source electrode is located on the upper surface of one of the two parts of the first silicon termination layer; The drain is located on the upper surface of the other part of the two parts of the first silicon termination layer; A silicon oxide layer is located on the upper surface of the second silicon terminal layer; The gate is located on the upper surface of the silicon oxide layer.

[0007] Secondly, the present invention also provides a method for fabricating an enhanced diamond field-effect transistor (FET) based on two types of silicon terminals, for fabricating the aforementioned enhanced diamond field-effect transistor based on two types of silicon terminals, comprising: Provide a diamond substrate; A single-crystal silicon layer is epitaxially grown on the upper surface of a diamond substrate; The upper surface of the single-crystal silicon layer is processed using photolithography to define the active region and the channel region, and the channel region is exposed. The exposed single-crystal silicon layer in the channel region is oxidized using an oxidation process to obtain a silicon oxide layer. Hydrogen plasma is used to process the silicon oxide layer and the single-crystal silicon layers on both sides of the silicon oxide layer to form a first silicon termination layer at the interface between the single-crystal silicon layer and the diamond substrate, and a second silicon termination layer at the interface between the silicon oxide layer and the diamond substrate. An alkaline solution is used to remove the single-crystal silicon layer on the first silicon termination layer to expose the first silicon termination layer; source and drain electrodes are respectively fabricated on the upper surfaces of the two parts of the exposed first silicon termination layer. A gate is fabricated on the upper surface of a silicon oxide layer.

[0008] The beneficial effects of this invention are: This invention provides an enhancement-mode diamond field-effect transistor (EMT) based on two types of silicon terminals and its fabrication method. On the same substrate, diamond silicon terminals with different electrical properties are fabricated using different silicon dielectrics to achieve the fabrication of an EMT. Compared to traditional EMT processes, this method has fewer process steps and higher reliability. This invention utilizes two different silicon terminal dielectrics, single-crystal silicon and silicon oxide, to simultaneously define active regions and enhancement-mode channel regions with different electrical properties, and simultaneously fabricates a first silicon terminal layer and a second silicon terminal layer with different electrical properties. This avoids the complex and independent ion implantation, etching, or additional epitaxial growth steps required in traditional processes to form ohmic contacts and enhancement channels, thus significantly simplifying the device structure and process flow.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an enhanced diamond field-effect transistor based on two types of silicon terminals provided in an embodiment of the present invention; Figure 2 This is a flowchart of a method for fabricating an enhanced diamond field-effect transistor based on two types of silicon terminals provided in an embodiment of the present invention; Figures 3a-3f This is a schematic diagram of a method for fabricating an enhanced diamond field-effect transistor based on two types of silicon terminals provided in an embodiment of the present invention. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0012] Please see Figure 1 , Figure 1 This is a schematic diagram of an enhancement-mode diamond field-effect transistor (EMT) based on two types of silicon terminals provided in an embodiment of the present invention. The EMT provided by the present invention includes: Diamond substrate 1; The first silicon terminal layer 4 is located on the upper surface of the diamond substrate 1 and includes two parts, which are located on both sides of the upper surface of the diamond substrate 1 respectively. The second silicon terminal layer 5 is located on the upper surface of the diamond substrate 1 and between the two parts of the first silicon terminal layer 4; the electrical characteristics of the first silicon terminal layer 4 and the second silicon terminal layer 5 are different. Source 6-1 is located on the upper surface of one of the two parts of the first silicon termination layer 4; Drain 6-2 is located on the upper surface of the other part of the two parts of the first silicon termination layer 4; Silicon oxide layer 3 is located on the upper surface of the second silicon terminal layer 5; Gate 7 is located on the upper surface of silicon oxide layer 3.

[0013] For details, please continue to see Figure 1 The enhanced diamond field-effect transistor (EDT) based on two types of silicon terminals provided in this embodiment fabricates diamond silicon terminals with different electrical properties on the same substrate using different silicon dielectrics, thus realizing the fabrication of the EDT. Compared with the traditional EDT process, this method has fewer process steps and higher process reliability. This invention utilizes two different silicon terminal dielectrics, single-crystal silicon and silicon oxide, to simultaneously define active regions and enhancement channel regions with different electrical properties, and simultaneously fabricates a first silicon terminal layer 4 and a second silicon terminal layer 5 with different electrical properties. In this way, the complex and independent ion implantation, etching, or additional epitaxial growth steps required to form ohmic contacts and enhancement channels in the traditional process are avoided, thereby significantly simplifying the device structure and process flow.

[0014] In an optional embodiment of the present invention, the first silicon termination layer 4 includes C-Si-H bonds for inducing two-dimensional hole gas as an active region.

[0015] Specifically, in this embodiment, the first silicon terminal layer 4 includes C-Si-H bonds, which can effectively induce low-resistivity two-dimensional hole gas and ensure sufficient carrier concentration.

[0016] In an optional embodiment of the present invention, the second silicon termination layer 5 includes C-Si bonds as a channel region.

[0017] Specifically, in this embodiment, the second silicon termination layer 5 includes C-Si bonds, which enables normally-off characteristics.

[0018] In an optional embodiment of the present invention, the diamond substrate 1 is an intrinsic diamond substrate.

[0019] In an optional embodiment of the present invention, the thickness of the diamond substrate 1 is 100~1000μm.

[0020] In an optional embodiment of the present invention, the thickness of the first silicon terminal layer 4 is 2~10nm, and the thickness of the second silicon terminal layer 5 is 2~10nm.

[0021] Optionally, the thickness of the first silicon terminal layer 4 is 4nm, 6nm, or 8nm, and the thickness of the second silicon terminal layer 5 is 4nm, 6nm, or 8nm.

[0022] In an optional embodiment of the present invention, the thickness of the silicon oxide layer 3 is 10~190 nm.

[0023] Optionally, the thickness of the silicon oxide layer 3 is 20 nm, 50 nm, or 70 nm.

[0024] Based on the same inventive concept, please refer to Figure 2 and Figures 3a-3f , Figure 2 This is a flowchart of a method for fabricating an enhanced diamond field-effect transistor based on two types of silicon terminals provided in an embodiment of the present invention. Figures 3a-3f This is a schematic diagram of a method for fabricating an enhanced diamond field-effect transistor (EDT) based on two types of silicon terminals provided in an embodiment of the present invention. The present invention also provides a method for fabricating an enhanced diamond field-effect transistor based on two types of silicon terminals, used to fabricate the enhanced diamond field-effect transistor based on two types of silicon terminals provided in the above embodiments of the present invention. For embodiments of the enhanced diamond field-effect transistor, please refer to the above description, which will not be repeated here. The fabrication process includes: S101, Provide a diamond substrate 1.

[0025] Specifically, in this embodiment, intrinsic diamond epitaxially grown by chemical vapor deposition (CVD) is selected as the substrate. The diamond substrate 1 is sequentially placed in a strong acid mixture (H2SO4:HNO3), acetone, ethanol, and deionized water at 200°C for cleaning. After cleaning, it is dried with a nitrogen gun for later use.

[0026] Optionally, the thickness of the diamond substrate 1 is 100~1000μm.

[0027] S102. A single-crystal silicon layer 2 is epitaxially grown on the upper surface of the diamond substrate 1.

[0028] Specifically, in this embodiment, the thickness of the epitaxially generated single-crystal silicon layer 2 is 20~200nm.

[0029] Optionally, epitaxial growth methods include, but are not limited to, molecular beam epitaxy and vapor phase epitaxy.

[0030] S103. Using photolithography, the upper surface of the single-crystal silicon layer 2 is processed to define the active region and the channel region, and the channel region is exposed; using oxidation, the single-crystal silicon layer 2 exposed in the channel region is oxidized to obtain silicon oxide layer 3.

[0031] Specifically, in this embodiment, a photolithography process is used to define the active region and the enhancement channel region on the upper surface of the single-crystal silicon layer 2. A preset mask is placed on the upper surface of the single-crystal silicon layer 2 to expose the single-crystal silicon layer 2 corresponding to the enhancement channel region. An oxidation process is used, which may include, but is not limited to, dry oxygen oxidation, wet oxygen oxidation, and water vapor oxidation. The detailed parameters and process characteristics are as follows: Dry oxygen oxidation uses high-purity oxygen (purity ≥ 99.999%) as the oxidant at 900~1200℃. Dry oxygen oxidation is carried out under normal pressure, with a slow oxidation rate (0.1~1 nm / min), achieved by precisely controlling the oxidation time (10~120 minutes). Wet oxygen oxidation involves introducing oxygen into deionized water at 80~95℃ to create an oxidation atmosphere containing saturated water vapor (O2 to H2O volume ratio 1:1), and growth is achieved at 800~1100℃ and normal pressure. The oxidation rate (1~5 nm / min) is 3~5 times that of dry oxygen oxidation, but the film density is slightly lower (2.15~2.20 g / cm³). 3 Water vapor oxidation directly uses high-purity water vapor (purity ≥99.99%) as the oxidant and is carried out at 700~1000℃ and atmospheric pressure. The oxidation rate is the fastest (2~10nm / min), which is suitable for preparing micron-level thick oxide layers. However, the purity of water vapor must be strictly controlled to avoid impurity contamination. This part of the single crystal silicon layer 2 is oxidized to obtain silicon oxide layer 3. Optionally, the active region may include multiple active regions, with channel regions located on both sides of the active region.

[0032] In this embodiment, on the same diamond substrate 1, two different silicon terminal media, single-crystal silicon and silicon oxide, are used to define active regions and channel regions with different electrical properties. This avoids the complex and independent ion implantation, etching or additional epitaxial growth steps required in traditional processes to form ohmic contacts and enhancement channels, thereby significantly simplifying the device structure and process flow.

[0033] Furthermore, the core steps of the above process are highly compatible with mature silicon-based microelectronic processes (such as photolithography and oxidation) and diamond processing processes (such as MPCVD hydrogen plasma processing). By precisely controlling the photolithography pattern and oxidation process, the size and position of the active region and the channel region can be precisely controlled. The process has strong controllability and good repeatability, providing a practical technical path for the fabrication of high-performance, uniform enhancement-mode diamond field-effect transistors.

[0034] S104. Hydrogen plasma is used to process the silicon oxide layer 3 and the single-crystal silicon layers 2 on both sides of the silicon oxide layer 3 to form a first silicon terminal layer 4 at the contact surface between the single-crystal silicon layer 2 and the diamond substrate 1, and a second silicon terminal layer 5 at the contact surface between the silicon oxide layer 3 and the diamond substrate 1.

[0035] Specifically, in this embodiment, the device is placed in a microwave plasma chemical vapor deposition (MPCVD) apparatus, the cavity pressure is evacuated to 0.001 mbar or below, and H2 is introduced at a flow rate of 100-800 sccm. When the cavity pressure reaches 10-25 mbar, the microwave source is turned on, and the cavity pressure is maintained at 20-100 mbar. The microwave source power is 2000-3000 W, the temperature of the diamond substrate 1 is 600-1000℃, and the diamond substrate 1 is treated for 5-120 minutes. Reduce the cavity air pressure and microwave source power. Reduce the cavity air pressure to below 20 mbar and the microwave source power to below 600. Stabilize the temperature inside the cavity and turn off the microwave source. Stop the H2 supply and pump the chamber pressure to 0.001 mbar or below; turn off the pump and introduce air into the chamber to break the vacuum, then remove the heteroepitaxial diamond from the chamber to complete the heteroepitaxial diamond growth process. C-Si-H bonds will form at the contact point between the single-crystal silicon layer 2 and the diamond substrate 1, and C-Si bonds and OH- will form at the contact point between the silicon oxide layer 3 and the diamond substrate 1. The OH- will return to the hydrogen plasma, leaving behind the C-Si bonds.

[0036] Optionally, the first silicon terminal layer 4 formed at the interface between the single-crystal silicon layer 2 and the diamond substrate 1 includes C-Si-H bonds, which can induce two-dimensional holes, thus serving as an active region; the second silicon terminal layer 5 formed at the interface between the silicon oxide layer 3 and the diamond substrate 1 includes C-Si bonds and OH-. OH- will return to the hydrogen plasma, leaving C-Si bonds. It will not spontaneously induce two-dimensional holes, but the C-Si bonds will retain the conductive channel, thus serving as an enhancement channel region.

[0037] Optionally, the thickness of the first terminal silicon layer is 2-10 nm, and the thickness of the second terminal silicon layer is 2-10 nm; for example, the thickness of the first silicon terminal layer 4 is 4 nm, 6 nm, or 8 nm, and the thickness of the second silicon terminal layer 5 is 4 nm, 6 nm, or 8 nm.

[0038] Optionally, after plasma treatment, the thickness of the silicon oxide layer 3 is reduced to 10~190nm, and the thickness of the single-crystal silicon layers 2 on both sides of the silicon oxide layer 3 is reduced to 10~190nm.

[0039] In this embodiment, the C-Si-H bonds in the active region effectively induce a low-resistivity two-dimensional hole gas, ensuring sufficient carrier concentration; the C-Si bonds in the enhancement-mode channel region reliably achieve normally-off characteristics. Since the silicon terminals in the active and channel regions are formed simultaneously through a single hydrogen plasma treatment, their interface characteristics are excellent and their stability is high. Furthermore, the silicon oxide layer 3 serves as the gate insulating layer for the subsequent field-effect transistor, reducing interface defects and performance fluctuations that may be introduced by multiple processes in traditional methods, thereby improving the overall performance and reliability of the device.

[0040] S105. Use an alkaline solution to remove the single-crystal silicon layer 2 on the first silicon terminal layer 4 to expose the first silicon terminal layer 4; and prepare a source electrode 6-1 and a drain electrode 6-2 on the upper surfaces of the two parts of the exposed first silicon terminal layer 4, respectively.

[0041] Specifically, in this embodiment, the alkaline solution includes, but is not limited to, sodium hydroxide and potassium hydroxide.

[0042] Optionally, the source 6-1 and drain 6-2 are made of one or more of Ti, Au, and Pt, and the thickness of the source 6-1 and drain 6-2 is 100~200nm; for example, the source 6-1 and drain 6-2 are made of Ti / Au and the thickness is 20 / 100nm.

[0043] S106. A gate 7 is prepared on the upper surface of the silicon oxide layer 3.

[0044] Specifically, in this embodiment, the material of the gate 7 includes one or more of Al and Au, and the thickness is 100~200nm; for example, the material of the gate 7 includes Al / Au, and the thickness is 20 / 100nm.

[0045] In summary, the present invention provides a subarray-level sparsity optimization method for large-scale distributed arrays. By first filling the array area and then performing subarray-level sparsity optimization of the array surface sidelobes, it avoids the situation where the array surface does not conform to the array area constraints after conventional optimization methods. Furthermore, by transforming the subarray offset problem into subarray sparsity, although the number of subarrays may increase to some extent, the optimization space for the sparsity problem is always smaller than that for the offset problem, thus significantly reducing the optimization difficulty and improving the optimization efficiency.

[0046] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0047] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0048] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An enhanced diamond field-effect transistor based on two types of silicon terminals, characterized in that, include: Diamond substrate; The first silicon termination layer is located on the upper surface of the diamond substrate and includes two parts, which are located on both sides of the upper surface of the diamond substrate, respectively. The second silicon termination layer is located on the upper surface of the diamond substrate and between the two parts of the first silicon termination layer; the electrical characteristics of the first silicon termination layer and the second silicon termination layer are different. The source electrode is located on the upper surface of one of the two parts of the first silicon termination layer; The drain is located on the upper surface of the other part of the two parts of the first silicon termination layer; A silicon oxide layer is located on the upper surface of the second silicon terminal layer; The gate is located on the upper surface of the silicon oxide layer.

2. The enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 1, characterized in that, The first silicon termination layer includes C-Si-H bonds, which are used to induce two-dimensional hole gas as an active region.

3. The enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 1, characterized in that, The second silicon termination layer includes C-Si bonds, serving as a channel region.

4. The enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 1, characterized in that, The diamond substrate is an intrinsic diamond substrate.

5. The enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 1, characterized in that, The thickness of the diamond substrate is 100~1000μm.

6. The enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 1, characterized in that, The thickness of the first silicon terminal layer is 2~10nm, and the thickness of the second silicon terminal layer is 2~10nm.

7. The enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 1, characterized in that, The thickness of the silicon oxide layer is 10~190nm.

8. A method for fabricating an enhanced diamond field-effect transistor (FET) based on two types of silicon terminals, used to fabricate the enhanced diamond field-effect transistor based on two types of silicon terminals as described in any one of claims 1 to 7, characterized in that, include: Provide a diamond substrate; A single-crystal silicon layer is epitaxially grown on the upper surface of the diamond substrate; The upper surface of the single-crystal silicon layer is processed using photolithography to define the active region and the channel region, and the channel region is exposed. The single-crystal silicon layer exposed in the channel region is oxidized using an oxidation process to obtain a silicon oxide layer. The silicon oxide layer and the single-crystal silicon layers on both sides of the silicon oxide layer are treated with hydrogen plasma to form a first silicon termination layer at the contact surface between the single-crystal silicon layer and the diamond substrate, and a second silicon termination layer at the contact surface between the silicon oxide layer and the diamond substrate. An alkaline solution is used to remove the single-crystal silicon layer on the first silicon terminal layer to expose the first silicon terminal layer; a source and a drain are respectively fabricated on the upper surfaces of the two portions of the exposed first silicon terminal layer. A gate is fabricated on the upper surface of the silicon oxide layer.

9. The method for fabricating an enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 8, characterized in that, The silicon oxide layer and the single-crystal silicon layers on both sides of the silicon oxide layer are treated with hydrogen plasma to form a first silicon termination layer at the interface between the single-crystal silicon layer and the diamond substrate, and a second silicon termination layer at the interface between the silicon oxide layer and the diamond substrate, including: In a microwave plasma chemical vapor deposition apparatus, the cavity pressure is evacuated to 0.001 mbar or below, and H2 is introduced at a flow rate of 100-800 sccm. When the cavity pressure reaches 10-25 mbar, the microwave source is turned on, and the cavity pressure is maintained at 20-100 mbar. The microwave source power is 2000-3000 W, the diamond substrate temperature is 600-1000℃, and the diamond substrate is treated for 5-120 minutes. Reduce the cavity air pressure and microwave source power. Reduce the cavity air pressure to below 20 mbar and the microwave source power to below 600. Stabilize the temperature inside the cavity and turn off the microwave source. Stop the H2 supply and evacuate the chamber pressure to 0.001 mbar or below; C-Si-H bonds will form at the contact points between the single-crystal silicon layer and the diamond substrate, and C-Si bonds and OH- will form at the contact points between the silicon oxide layer and the diamond substrate. The OH- will return to the hydrogen plasma, leaving behind the C-Si bonds.

10. The method for fabricating an enhanced diamond field-effect transistor based on two types of silicon terminals according to claim 8, characterized in that, The oxidation process includes dry oxygen oxidation, wet oxygen oxidation, or water vapor oxidation.

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