Five-junction solar cell based on bonding of composite substrate and wafer and preparation method of five-junction solar cell

Abstract

The invention relates to the technical field of solar cells, in particular to a five-junction solar cell based on bonding of a composite substrate and a wafer and a preparation method of the five-junction solar cell, and the preparation method comprises the following steps: 1) preparing a silicon-based InP film; 2) epitaxially growing a forward two-junction solar cell on the silicon-based InP thin film through MOCVD (Metal Organic Chemical Vapor Deposition); 3) epitaxially growing a reverse triple-junction solar cell on the GaAs substrate through MOCVD (Metal Organic Chemical Vapor Deposition); 4) heterogeneously integrating two sub-cells at the bottom of the silicon-based InP thin film and three sub-cells at the top of the gallium arsenide substrate through a wafer bonding technology; the three-junction solar cell and the preparation method thereof have the advantages that the performance is excellent, the collection efficiency of photon-generated carriers is effectively improved, the photoelectric conversion efficiency of the three-junction solar cell is improved, the application prospect is wide, and the like.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically a five-junction solar cell based on composite substrate and wafer bonding and its fabrication method. Background Technology

[0002] In recent years, with the development of the global economy, the demand for energy in various countries has been increasing. Energy consumption has caused global climate change and exacerbated ecological and environmental problems in various countries. In order to solve this problem, countries are vigorously developing and utilizing sustainable energy sources, such as hydropower, solar energy, wind energy, wave energy, geothermal energy, and tidal energy, while also researching technologies to improve energy efficiency.

[0003] Solar cells absorb solar energy and convert it into electrical energy. Commonly used solar cells can be classified according to their materials: silicon solar cells, gallium arsenide (GaAs) solar cells, cadmium telluride (CdTe) solar cells, copper indium gallium selenide (CIGS) solar cells, and organic solar cells. The theoretical limit of the photoelectric conversion efficiency (PCE) of silicon solar cells is 25%. Due to its relatively low price, it is currently the most widely used photovoltaic power generation technology, used in military, aerospace, industrial, and agricultural fields. Gallium arsenide (GaAs) solar cells, as typical III-V compound solar cells, are currently the solar cell material system with the highest PCE. Triple-junction GaAs solar cells can achieve PCEs of over 33%, but due to their high price, they are generally used in space solar cells and rarely in ground-based photovoltaic power plants. Currently, the main problem with GaAs solar cells is that the lattice-matched multi-junction solar cell technology route struggles to obtain light-absorbing materials with suitable band gaps and excellent performance, while the lattice-mismatched multi-junction solar cell technology route faces difficulties in epitaxial material production, resulting in extremely low yields and hindering engineering applications. To address this issue, the US-based Spectrolab laboratory proposed a wafer bonding matching multi-junction solar cell technology route, which has advantages such as high material quality, high growth rate, and short growth time, making it the most promising technology solution for achieving mass production of high-efficiency space cells.

[0004] Wafer bonding technology refers to the process of tightly joining two smooth, clean, homogeneous or heterogeneous wafers together under high temperature and pressure through chemical and physical interactions. During bonding, atoms at the interface react under the influence of external forces to form covalent bonds, making the two wafers a single unit, and the bonding interface possesses a specific bonding strength. Because this technology can connect two lattice-mismatched materials, it can be used to fabricate multilayer tandem solar cells. Summary of the Invention

[0005] The technical problem this invention aims to solve is to provide a five-junction solar cell based on composite substrate and wafer bonding, and its fabrication method. This method utilizes substrate reuse technology to prepare silicon-based InP thin films, enabling the reusability of the InP substrate. Wafer bonding technology is used to heterogeneously integrate the bottom two-junction sub-cells of the silicon-based InP thin film with the top three-junction sub-cells of the gallium arsenide substrate. This effectively avoids the impact of defects caused by lattice mismatch (although a gradient buffer layer is grown, it is impossible to completely prevent the formation of internal defects in the sub-cells) on cell performance, shortens the high-temperature epitaxial growth time, and simplifies the epitaxial growth process. This five-junction solar cell combines the photoelectric conversion efficiency advantages of multi-junction solar cells, achieves wafer reusability, not only realizes independent control of key materials for multi-junction solar cells, but also reduces cell costs.

[0006] This invention is achieved by a method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding, comprising the following steps: (1) Prepare silicon-based InP thin film; (2) Epitaxially grow forward double-junction solar cell on silicon-based InP thin film by MOCVD; (3) Epitaxially grow reverse triple-junction solar cell on GaAs substrate by MOCVD; (4) Heterogeneously integrate bottom 2-junction cell of silicon-based InP thin film and top 3-junction cell of gallium arsenide substrate by wafer bonding technology; (5) Complete GaAs substrate stripping by etching process; (6) Prepare upper and lower electrodes of cell; (7) Prepare anti-reflection film of cell.

[0007] Furthermore, in step (1), a P-type doped Si wafer is prepared as a support substrate. The P-type doped Si wafer is polished on one side with a thickness of 150-1000 μm and a resistivity of 0.001-0.005. The InP wafer is polished on both sides with a thickness of 150-1000 μm. The surface roughness of the polished surfaces of both the P-type doped Si wafer and the InP wafer is less than 0.5 nm, ensuring that the bonding surfaces between the wafers can make full contact.

[0008] Further, in step (1), ions are implanted into the InP wafer to form a defect layer in the middle of the piezoelectric single crystal. In a vacuum environment, the surface of the InP wafer and the surface of the Si support substrate are activated by mixed plasma. Then, the two wafers, the ion-implanted InP wafer and the Si support substrate, are pre-bonded and left to stand in a low vacuum environment. After nitrogen annealing, peeling and polishing, a silicon-based InP thin film with the target thickness is prepared.

[0009] Furthermore, in step (2), an InP buffer layer with a thickness of 0.1-0.3 μm is epitaxially grown on the silicon-based InP thin film, and a fifth junction In... x Ga 1-x As battery, fourth tunnel junction, fourth junction Inx Ga 1-x As y P 1-y The battery and the InP bonding contact layer with a thickness of 100-1000nm, where 0.3≤x≤0.8 and 0.3≤y≤0.7.

[0010] Further, in step (3), a GaAs buffer layer with a thickness of 0.1-0.3 μm, a GaInP etch barrier layer with a thickness of 0.1-0.3 μm, an n-type doped GaAs cap layer with a thickness of 100-500 nm, and a first junction Al are epitaxially reverse-grown on the GaAs substrate in sequence. x Ga 1-x In 0.5 P-cell, first tunnel junction, second junction Al x Ga 1-x As cell, second tunnel junction, window layer of third junction GaAs cell with a thickness of 30-200nm, emitter layer of third junction GaAs cell with a thickness of 50-200nm, base layer of third junction GaAs cell with a thickness of 2000-4000nm, third tunnel junction, GaAs bonding contact layer with a thickness of 100-1000nm, wherein 0.2≤x≤0.5.

[0011] Further, in step (4), after the InP bonding contact layer and the GaAs bonding contact layer are bonded together, they are placed in a bonding cavity filled with nitrogen for bonding, thereby completing the bonding of the InP double-junction solar cell and the GaAs triple-junction solar cell.

[0012] Further, in step (5), after the GaAs substrate is stripped from the battery by etching with NH4OH:H2O2 = 1:4 etching solution, the GaInP etching stop layer is etched with HCl:H2O = 1:1 etching solution, and the GaInP etching stop layer is stripped from the battery, thus completing the stripping of the GaAs substrate.

[0013] Furthermore, in step (6), the upper and lower electrodes of the battery are prepared by electron beam evaporation. Furthermore, in step (7), a double-layer antireflective film of aluminum oxide and titanium oxide is deposited on the surface of the battery, wherein the thickness of aluminum oxide is in the range of 20-70 nm and the thickness of titanium oxide is in the range of 20-70 nm.

[0014] The above preparation method yields a five-junction solar cell based on a composite substrate and room-temperature bonding.

[0015] The advantages and positive effects of this invention are: 1. This invention heterogeneously integrates a bottom-two-junction solar cell on a silicon-based InP thin film with a top-three-junction solar cell on a gallium arsenide substrate. A five-junction cascaded solar cell with AlGaInP 2.2eV / AlGaAs 1.7eV / GaAs 1.4eV / InGaAsP 1.05eV / InGaAs 0.73eV is fabricated. By constructing a multi-junction cascaded solar cell using various semiconductor materials with different bandgap widths, each junction absorbs the solar spectral band that best matches its bandgap width, thereby maximizing the effective utilization of the solar spectrum and maximizing the photoelectric conversion efficiency of the solar cell.

[0016] 2. This invention provides a novel method for heterogeneous wafer bonding and peeling. A plasma activation process is used to activate the surface of a Si support substrate and an ion-implanted InP wafer. Then, the two wafers are pre-bonded in a vacuum environment. Finally, the pre-bonded wafer is annealed in nitrogen, thinned, and peeled to complete the preparation of a silicon-based InP thin film. The resulting InP thin film has uniform thickness, low defect density, and a thickness reaching the hundred-nanometer level. This silicon-based InP thin film meets the requirements for epitaxial growth, enabling the reuse of InP wafers. This not only achieves independent control of key materials for multi-junction solar cells but also significantly reduces cell costs. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the preparation process of silicon-based InP thin films involved in a specific implementation method of the present invention.

[0018] Figure 2 This is a schematic diagram of the structure of the InP double-junction solar cell and the GaAs triple-junction solar cell after bonding according to the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] The method for fabricating a five-junction solar cell based on composite substrate and wafer bonding according to the present invention includes the following steps in sequence: Step 101: Prepare silicon-based InP thin films; Step 102: Growing forward double-junction solar cells on silicon-based InP thin films via MOCVD epitaxy; Step 103: A reverse triple junction solar cell is epitaxially grown on a GaAs substrate by MOCVD. Step 104: The bottom 2-junction cell of silicon-based InP thin film and the top 3-junction cell of gallium arsenide substrate are heterogeneously integrated together using wafer bonding technology. Step 105: Complete the GaAs substrate removal through an etching process; Step 106: Prepare the upper and lower electrodes of the battery; Step 107: Prepare the antireflective coating for the battery; Further: Step 101 specifically includes: Step 1011: Prepare a P-type doped Si wafer as a support substrate. The P-type doped Si wafer is polished on one side, with a thickness of 150-1000 μm and a resistivity of 0.001-0.005. The InP wafer is polished on both sides, with a thickness of 150-1000 μm. The surface roughness and viscosity of the polished surfaces of both the P-type doped Si wafer and the InP wafer are less than 0.5 nm to ensure that the bonding surfaces between the wafers can make full contact.

[0021] Step 1012: Ions are implanted into the InP wafer to form a defect layer in the middle of the piezoelectric single crystal. In a vacuum environment, the surface of the InP wafer and the surface of the Si support substrate are activated by mixed plasma. Then, the two wafers, the ion-implanted InP wafer and the Si support substrate, are pre-bonded and left to stand in a low vacuum environment. After nitrogen annealing, peeling and polishing, a silicon-based InP thin film of good quality and reaching the target thickness is prepared.

[0022] Further, step 102 specifically involves: sequentially epitaxially growing an InP buffer layer with a thickness of 0.1-0.3 μm on a silicon-based InP thin film, and a fifth junction In... x Ga 1-x As battery, fourth tunnel junction, fourth junction In x Ga 1-x As y P 1-y The battery and the InP bonding contact layer with a thickness of 100-1000nm, where 0.3≤x≤0.8 and 0.3≤y≤0.7.

[0023] Further, step 103 specifically involves: sequentially epitaxially growing a GaAs buffer layer with a thickness of 0.1-0.3 μm, a GaInP etch barrier layer with a thickness of 0.1-0.3 μm, an n-type doped GaAs cap layer with a thickness of 100-500 nm, and a first junction Al on a GaAs substrate. x Ga 1-x In 0.5 P-cell, first tunnel junction, second junction Al x Ga 1-xAs cell, second tunnel junction, window layer of third junction GaAs cell with a thickness of 30-200nm, emitter layer of third junction GaAs cell with a thickness of 50-200nm, base layer of third junction GaAs cell with a thickness of 2000-4000nm, third tunnel junction, GaAs bonding contact layer with a thickness of 100-1000nm, wherein 0.2≤x≤0.5.

[0024] Furthermore, step 104 specifically involves: bonding the InP bonding contact layer and the GaAs bonding contact layer together and then placing them in a bonding cavity filled with nitrogen for bonding, thereby completing the bonding of the InP double-junction solar cell and the GaAs triple-junction solar cell.

[0025] Furthermore, after the GaAs substrate was peeled off from the cell by etching with an NH4OH:H2O2 = 1:4 etching solution, the GaInP etching stop layer was then peeled off by an HCl:H2O = 1:1 etching solution, thus completing the peeling off of the GaAs substrate.

[0026] Further: Step 106 specifically involves preparing the upper and lower electrodes of the battery by electron beam evaporation. Further, step 107 specifically involves: depositing a double-layer antireflective film of aluminum oxide and titanium oxide on the surface of the battery by vapor deposition, wherein the thickness of aluminum oxide ranges from 20 to 70 nm and the thickness of titanium oxide ranges from 20 to 70 nm.

[0027] To further understand the invention's content, features, and effects, the following embodiments are provided, and detailed descriptions are given below in conjunction with the accompanying drawings: A five-junction solar cell based on composite substrate and wafer bonding and its fabrication method are disclosed. First, a silicon-based InP thin film suitable for epitaxial growth is prepared, using a 4-inch single-crystal silicon substrate as the support substrate and a 4-inch InP wafer as the functional material. Figure 1 As shown; the thickness of the single-crystal silicon substrate is 625μm, and the thickness of the InP wafer is 500μm; the root mean square roughness of the polished surfaces of both the single-crystal silicon substrate and the InP wafer is less than 0.5nm, the single-crystal silicon substrate is polished on one side, and the InP wafer is polished on both sides. Two wafers to be bonded were placed in a petri dish containing acetone and ultrasonically cleaned for 30 minutes with a 30% acetone solution to remove contaminants and attached particles. Then, the two wafers were immersed in a water bath with RCA-1 standard solution for 50 minutes to dissolve organic matter and oxides on the wafer surface. Finally, the single-crystal silicon substrate and the InP wafer were placed on a cleaning stage with a speed of 3000 rpm. The surfaces were cleaned with deionized water and dried with nitrogen. The cleaning time with deionized water was 25 seconds and the drying time with nitrogen was 5 seconds.

[0028] The cleaned InP wafer was placed in an ion implanter and hydrogen ions were implanted at an energy of 50 keV and a dose of 1 × 10⁻⁶. 17 / cm², forming an InP thin film layer, an implantation layer, and a residual material layer on an InP wafer, such as Figure 1 As shown.

[0029] The wafer to be bonded is placed in the activation chamber, sealed and evacuated, and then surface activation of the single-crystal silicon substrate and InP wafer is performed using a mixed plasma of oxygen and nitrogen. The vacuum level of the plasma activation chamber is 1×10⁻⁶. -3 The oxygen gas flow rate used is 100 sccm, the nitrogen plasma gas flow rate is 100 sccm, the plasma emitter upper frequency power is 60W, the lower frequency power is 45W, and the process time is 60s.

[0030] At room temperature (23°C), the activated silicon substrate and InP wafer are aligned on the alignment stage and then sent into the bonding chamber. After vacuuming, the two wafers are bonded together and a pressure of 10kN is applied. The process time is 60s to complete the bonding.

[0031] After bonding, nitrogen flow rate is 2L / min, and the temperature is increased at a rate of 0.5℃ / min until the bonded sheet reaches 200℃ and is held at that temperature for 20h to allow the thin film layer to peel off, thus obtaining a silicon-based InP thin film. The cooling rate is 0.5℃ / min until the temperature reaches room temperature.

[0032] Schematic diagrams of the bonded InP double-junction solar cells and GaAs triple-junction solar cells are shown below. Figure 2 As shown.

[0033] A double-junction solar cell was forward grown on a silicon-based InP thin film 16 by MOCVD epitaxy. An InP buffer layer 15 with a thickness of 0.1-0.3 μm was epitaxially grown at a temperature of 500-800℃.

[0034] Epitaxial growth fifth node In x Ga 1-x As battery 15: Based on the InP buffer layer, InP back field layer and InP are sequentially epitaxially grown. x Ga 1-x As base area, In x Ga 1-x The As emitter region and InP window layer have a molecular weight of 0.3 ≤ x ≤ 0.8 and a growth temperature of 500-800℃. The InP back field layer is p-type doped with a thickness of 50-400 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The In x Ga 1- xThe As base region is p-type doped, with a thickness of 2000-5000 nm and a doping concentration of 1 × 10⁻⁶. 16 -1×10 18 cm -3 The In x Ga 1-x The As emitter region is n-type doped, with a thickness of 50-400 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The InP window layer is n-type doped with a thickness of 30-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 .

[0035] Epitaxial growth of the fourth tunnel junction 14: based on the fifth junction In x Ga 1-x As cells are epitaxially grown sequentially, consisting of an n-type InP layer and a p-type InP layer, at growth temperatures of 500-800℃, thicknesses of 10-100 nm, and doping concentrations of 1×10⁻⁶. 18 -1×10 20 cm -3 .

[0036] Epitaxial growth of the fourth node In x Ga 1-x As y P 1-y Cell 13: Based on the fourth tunnel junction, InP back field layer and InP back field layer are epitaxially grown sequentially. x Ga 1-x As y P 1-y base area, In x Ga 1-x As y P 1-y The emitter region and InP window layer have a density of 0.3 ≤ x ≤ 0.8 and 0.3 ≤ y ≤ 0.7, and the growth temperature is 500-800℃. The InP back field layer is p-type doped, with a thickness of 30-300 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The In x Ga 1-x As y P 1-y The base region is p-type doped, with a thickness of 2000-5000 nm and a doping concentration of 1 × 10⁻⁶. 16 -1×10 18 cm -3The InxGa1-xAsyP1-y emitter region is n-type doped, with a thickness of 50-400 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The InP window layer is n-type doped with a thickness of 30-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 .

[0037] Epitaxial growth of InP bonding contact layer 12: growth temperature 500-800℃, thickness 100-1000nm, doping concentration 1×10⁻⁶ 18 -1×10 20 cm -3 .

[0038] Triple-junction solar cells were reverse-grown on gallium arsenide substrate 1 by MOCVD epitaxy, and GaAs buffer layer 2 was epitaxially grown at a growth temperature of 500-800℃ and a growth thickness of 0.1-0.3μm.

[0039] GaInP corrosion stop layer 3 was epitaxially grown at a temperature of 500-800℃ and a thickness of 0.1-0.3μm.

[0040] An n-type doped GaAs cap layer 4 was epitaxially grown at a temperature of 500-800℃, with a thickness of 100-500 nm and a doping concentration of 1×10⁻⁶. 18 -1×10 19 cm -3 .

[0041] Epitaxial growth of the first Al junction x Ga 1-x In 0.5 P-cell 5: Al cells are epitaxially grown sequentially based on GaAs cap layers. x Ga 1-x In 0.5 P back field layer, Al x Ga 1-x In 0.5 P-base region, Al x Ga 1-x In 0.5 P-launch zone and Al x Ga 1-x In 0.5 The P-window layer, where 0.2 ≤ x ≤ 0.5, is grown at a temperature of 500-800℃; the Al x Ga 1-x In 0.5 The p-back field layer is p-type doped with a thickness of 30-200 nm and a doping concentration of 1 × 10⁻⁶.17 -1×10 19 cm -3 The Al x Ga 1-x In 0.5 The p-base region is p-type doped with a thickness of 500-2000 nm and a doping concentration of 1 × 10⁻⁶. 16 -1×10 18 cm -3 The Al x Ga 1-x In 0.5 The P-emitter region is n-type doped with a thickness of 50-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The Al x Ga 1-x In 0.5 The P-window layer is n-type doped with a thickness of 30-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 .

[0042] Epitaxial growth of the first tunnel junction 6: Based on the first junction Al x Ga 1-x In 0.5 P-cells are epitaxially grown with n-type Al cells. x Ga 1- x In 0.5 P-layer and p-type Al x Ga 1-x As layers, where 0.2 ≤ x ≤ 0.5, all grown at temperatures of 500-800℃, with doping concentrations of 1 × 10⁻⁶. 18 -1×10 20 cm -3 The thickness of each is 10-100nm.

[0043] Epitaxial growth of the second Al junction x Ga 1-x As battery 7: Al is epitaxially grown sequentially based on the first tunnel junction. x Ga 1-x In 0.5 P back field layer, Al x Ga 1-x As base region, Al x Ga 1-x As emitter region and AlInP window layer, wherein 0.2≤x≤0.5, growth temperature is 500-800℃; the Al x Ga 1-x In 0.5The p-type backfield layer is p-doped, with a thickness of 30-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The AlxGa1-xAs base region is p-type doped with a thickness of 1000-3000 nm and a doping concentration of 1×10⁻⁶. 16 -1×10 18 cm -3 The AlxGa1-xAs emitter region is n-type doped with a thickness of 50-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 The AlInP window layer is n-type doped, with a thickness of 30-200 nm and a doping concentration of 1 × 10⁻⁶. 17 -1×10 19 cm -3 .

[0044] Epitaxial growth of the second tunnel junction 8: Based on the second junction Al x Ga 1-x As a battery, an n-type GaInP layer and a p-type Al layer are epitaxially grown sequentially. x Ga 1-x As layer, where 0.2 ≤ x ≤ 0.5, growth temperature is 500-800℃, and doping concentration is 1×10⁻⁶. 18 -1×10 20 cm -3 The thickness is 10-100nm.

[0045] The window layer of the epitaxially grown third-junction GaAs cell is n-type doped Al. x Ga 1-x As window layer, where 0.2≤x≤0.5, growth temperature 500-800℃, thickness 30-200nm, doping concentration 1×10⁻⁶. 17 -1×10 19 cm -3 .

[0046] The emitter layer of the epitaxially grown third-junction GaAs solar cell is an n-type doped GaAs emitter region, with a growth temperature of 500-800℃, a thickness of 50-200nm, and a doping concentration of 1×10⁻⁶. 17 -1×10 19 cm -3 .

[0047] The base layer of the epitaxially grown third-junction GaAs solar cell is a p-type doped GaAs emitter region, with a growth temperature of 500-800℃, a thickness of 2000-4000 nm, and a doping concentration of 1×10¹. 6 -1×10¹8 cm -3 .

[0048] The back field layer of the epitaxially grown third-junction GaAs solar cell is p-type doped Al. x Ga 1-x As backfield region, where 0.2≤x≤0.5, growth temperature 500-800℃, thickness 30-200nm, doping concentration 1×10⁻⁶ 17 -1×10 19 cm -3 .

[0049] Epitaxial growth of the third tunnel junction 10: sequentially growing into n-type In x Ga 1-x As layer and p-type Al x Ga 1-x As layers, where 0≤x≤0.1, 0≤y≤0.5, are grown at temperatures of 500-800℃, have thicknesses of 10-100nm, and have a doping concentration of 1×10⁻⁶. 18 -1×10 20 cm -3 .

[0050] GaAs bonding contact layer 11 is epitaxially grown at a temperature of 500-800℃, with a thickness of 100-1000 nm and a doping concentration of 1×10⁻⁶. 18 -1×10 20 cm -3 .

[0051] like Figure 2 As shown, this is a solar cell structure obtained through semiconductor direct bonding. An epitaxially reverse-matched GaAs triple-junction solar cell is connected to an epitaxially forward-matched InP double-junction solar cell via semiconductor direct bonding. In this embodiment, the semiconductor direct bonding process is performed at room temperature (23°C). The activated silicon-based InP thin-film double-junction solar cell and gallium arsenide triple-junction solar cell are placed in the bonding chamber. After vacuuming, the two wafers are bonded together and a pressure of 0 kN is applied. The process time is 60 seconds, completing the pre-bonding. This is the state after the pre-bonding of the two wafers, followed by a resting period of 8 hours.

[0052] After the GaAs substrate was stripped from the cell using an NH4OH:H2O2 = 1:4 etching solution, the GaInP etching stop layer was etched using an HCl:H2O = 1:1 etching solution.

[0053] Fabrication of battery device structure: The upper and lower electrodes of the battery are prepared by electron beam evaporation. Preparation of antireflective coating for battery: A double-layer antireflective coating of aluminum oxide and titanium oxide is deposited on the surface of the battery by vapor deposition, wherein the thickness of aluminum oxide is 20-70 nm and the thickness of titanium oxide and aluminum oxide is 20-70 nm.

[0054] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding, characterized in that, Includes the following steps: (1) Prepare silicon-based InP thin film; (2) Epitaxially grow forward double-junction solar cell on silicon-based InP thin film by MOCVD; (3) Epitaxially grow reverse triple-junction solar cell on GaAs substrate by MOCVD; (4) Heterogeneously integrate bottom 2-junction cell of silicon-based InP thin film and top 3-junction cell of gallium arsenide substrate by wafer bonding technology; (5) Complete GaAs substrate stripping by etching process; (6) Prepare upper and lower electrodes of cell; (7) Prepare anti-reflection film of cell.

2. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (1), a P-type doped Si wafer is prepared as a support substrate. The P-type doped Si wafer is polished on one side with a thickness of 150-1000 μm and a resistivity of 0.001-0.

005. The InP wafer is polished on both sides with a thickness of 150-1000 μm. The surface roughness of the polished surfaces of both the P-type doped Si wafer and the InP wafer is less than 0.5 nm to ensure that the bonding surfaces between the wafers can make full contact.

3. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 2, characterized in that, In step (1), ions are implanted into the InP wafer to form a defect layer in the middle of the piezoelectric single crystal. In a vacuum environment, the surface of the InP wafer and the surface of the Si support substrate are activated by mixed plasma. Then, the two wafers, the ion-implanted InP wafer and the Si support substrate, are pre-bonded and left to stand in a low vacuum environment. After nitrogen annealing, peeling and polishing, a silicon-based InP thin film with the target thickness is prepared.

4. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (2), an InP buffer layer with a thickness of 0.1-0.3 μm is epitaxially grown on a silicon-based InP thin film, and a fifth junction In... x Ga 1-x As battery, fourth tunnel junction, fourth junction In x Ga 1-x As y P 1-y The battery and the InP bonding contact layer with a thickness of 100-1000nm, where 0.3≤x≤0.8 and 0.3≤y≤0.

7.

5. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (3), a GaAs buffer layer with a thickness of 0.1-0.3 μm, a GaInP etch barrier layer with a thickness of 0.1-0.3 μm, an n-type doped GaAs cap layer with a thickness of 100-500 nm, and a first junction Al are epitaxially reverse-grown on the GaAs substrate in sequence. x Ga 1-x In 0.5 P-cell, first tunnel junction, second junction Al x Ga 1-x As cell, second tunnel junction, window layer of third junction GaAs cell with a thickness of 30-200nm, emitter layer of third junction GaAs cell with a thickness of 50-200nm, base layer of third junction GaAs cell with a thickness of 2000-4000nm, third tunnel junction, GaAs bonding contact layer with a thickness of 100-1000nm, wherein 0.2≤x≤0.

5.

6. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (4), the InP bonding contact layer and the GaAs bonding contact layer are bonded together and placed in a bonding cavity filled with nitrogen for bonding, thereby completing the bonding of the InP double-junction solar cell and the GaAs triple-junction solar cell.

7. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (5), after the GaAs substrate is peeled off from the battery by etching with NH4OH:H2O2 = 1:4 etch solution, the GaInP etching stop layer is peeled off by HCl:H2O = 1:1 etch solution, and the GaInP etching stop layer is peeled off from the battery, thus completing the peeling off of the GaAs substrate.

8. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (6), the upper and lower electrodes of the battery are prepared by electron beam evaporation.

9. The method for fabricating a five-junction solar cell based on a composite substrate and room-temperature bonding according to claim 1, characterized in that, In step (7), a double-layer antireflective film of aluminum oxide and titanium oxide is deposited on the surface of the battery, wherein the thickness of aluminum oxide is in the range of 20-70 nm and the thickness of titanium oxide is in the range of 20-70 nm.

10. A five-junction solar cell based on a composite substrate and room-temperature bonding is prepared by the preparation method according to any one of claims 1-9.

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