SOI substrate structure and preparation method thereof

Abstract

The invention provides an SOI (Silicon On Insulator) substrate structure and a preparation method thereof, the structure comprises a bottom silicon layer, a buried oxide layer and a top silicon layer which are stacked from bottom to top, and a first concentration peak region of nitrogen ions is formed at a first depth from the upper surface of the bottom silicon layer so as to form a first O-N-O electron bound structure in the bottom silicon layer; and / or forming a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer so as to form a second O-N-O electron bound structure in the buried oxide layer. Through the binding effect of silicon nitride / silicon oxynitride in the O-N-O electron binding structure on free charges, the free charges at a buried oxide / silicon interface can be effectively bound, so that the free charges cannot oscillate back and forth under high frequency, the noise under high-frequency application is effectively reduced, and the noise suppression requirement of H3-80dBm level can be met. Meanwhile, according to the SOI substrate structure provided by the invention, the preparation can be completed without adding a photomask, the requirement on the resistance value of the bottom silicon layer is not high, and the cost of an RFSOI device is effectively reduced while the noise suppression level is improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor devices, and in particular to an SOI substrate structure and its fabrication method. Background Technology

[0002] Radio Frequency Silicon-On-Insulator (RF SOI) technology is a core technology for 6G / Sub-8G communication RF front-ends due to its isolation, low parasitics, and integrability provided by the buried oxide layer. The application of 6G / Sub-8G communication technology places core requirements on the RF front-end, such as "low noise and high linearity." In particular, it requires that RF devices (such as RFSOI-based LANs, RF switches, and phase shifters) have an equivalent noise power or spurious signal power ≤-80dBm at the output end within the target frequency band. This ensures a signal-to-noise ratio (SNR) for weak signal reception, meeting the high-speed, low-latency, and large-connectivity transmission requirements of 6G / Sub-8G, i.e., the H3-80dBm specification requirement.

[0003] Defects at the buried oxide / silicon interface in RFSOI can trap and emit electrons, generating random noise at high frequencies and becoming a major factor affecting the H3-80dBm specification. Existing technologies typically employ methods such as increasing the resistance of the underlying silicon layer or using Through Contact technology, which extracts the interface charge by passing through the buried oxide layer and stopping at the interface between the buried oxide layer and the underlying silicon layer.

[0004] Then, the existing Through Contact technology cannot adapt to the fast time domain and high density characteristics of interface state noise at high frequency because the structure and extraction mechanism of traditional through holes cannot be adapted to the interface trap electron extraction efficiency, making it difficult to suppress noise to the H3-80dBm level; and the higher the resistance of the bottom silicon layer, the more expensive it is, which greatly increases the cost of RFSOI devices.

[0005] Therefore, how to economically and effectively suppress the noise caused by free charges generated by interface defects at high frequencies has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0006] In view of the above problems, the present invention provides an SOI substrate structure and its preparation method, which can economically and effectively suppress the noise caused by free charges generated by interface defects at high frequencies.

[0007] According to a first aspect of the present invention, an SOI substrate structure is provided, characterized in that it comprises: a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked from bottom to top; A first concentration peak region of nitrogen ions is formed at a first depth from the upper surface of the bottom silicon layer to form a first ONO electron-binding structure within the bottom silicon layer; and / or A second concentration peak region of nitrogen ions is formed at a second depth from the lower surface of the buried oxide layer to form a second ONO electron-binding structure within the buried oxide layer.

[0008] Optionally, the first depth is a position 200 Å to 800 Å away from the upper surface of the top silicon layer.

[0009] Optionally, the second depth is a position 100 Å to 200 Å away from the lower surface of the buried oxide layer.

[0010] Optionally, the SOI substrate structure further includes a trap-rich layer located between the upper surface of the bottom silicon layer and the lower surface of the buried oxide layer.

[0011] According to a second aspect of the present invention, a method for fabricating the SOI substrate structure described in the first aspect is provided, comprising: A substrate is provided, wherein a bottom silicon layer, a buried oxide layer, and a top silicon layer are formed sequentially from bottom to top. The substrate is sequentially implanted with oxygen ions, nitrogen ions, and oxygen ions to form a first concentration peak region of nitrogen ions at a first depth from the upper surface of the bottom silicon layer; and / or the substrate is implanted with nitrogen ions to form a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer.

[0012] Optionally, the step of sequentially implanting oxygen ions, nitrogen ions, and oxygen ions into the substrate to form a first concentration peak region of nitrogen ions at a first depth from the upper surface of the bottom silicon layer includes: The substrate was sequentially implanted with oxygen ions, nitrogen ions, and then oxygen ions. The substrate after ion implantation is annealed to form a first concentration peak region of nitrogen ions at a first depth from the upper surface of the bottom silicon layer.

[0013] Optionally, the step of ion implanting nitrogen ions into the substrate to form a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer includes: Nitrogen ion implantation is performed on the substrate; The substrate is annealed to form a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer.

[0014] Optionally, the annealing temperature is 1000℃~1200℃.

[0015] Optionally, the sequential ion implantation of oxygen ions, nitrogen ions, and oxygen ions into the substrate includes: an incident angle of 0 degrees to 7 degrees, and an ion implantation energy of 1 MeV to 10 MeV; and / or The nitrogen ion implantation of the substrate includes: an incident angle of 0 degrees to 7 degrees and an ion implantation energy of 50 keV to 150 keV.

[0016] Optionally, after forming the bottom silicon layer and before forming the buried oxide layer, the substrate further includes: forming a trap-rich layer.

[0017] The SOI substrate structure provided by this invention includes a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked from bottom to top. A first peak concentration region of nitrogen ions is formed at a first depth from the upper surface of the bottom silicon layer to form a first ONO electron-binding structure within the bottom silicon layer; and / or a second peak concentration region of nitrogen ions is formed at a second depth from the lower surface of the buried oxide layer to form a second ONO electron-binding structure within the buried oxide layer. Through the binding effect of the silicon nitride / silicon oxynitride structure on free charges in the ONO electron-binding structure, the free charges at the buried oxide / silicon interface can be effectively bound, preventing them from oscillating back and forth under high-frequency operation, thereby effectively reducing noise in high-frequency applications and meeting the noise suppression requirements of H3-80dBm. Simultaneously, the SOI substrate structure provided by this invention can be fabricated without the need for an additional photomask and has low resistance requirements for the bottom silicon layer, thus effectively reducing the cost of RFSOI devices while improving noise suppression levels. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figures 1A to 3B This is a cross-sectional schematic diagram of the SOI substrate structure provided in an embodiment of the present invention; Figure 4 This is a schematic flowchart of the steps involved in fabricating an SOI substrate structure according to an embodiment of the present invention. Figures 5A to 7C Schematic diagrams of the various steps in the SOI substrate structure fabrication method provided in this embodiment of the invention; Explanation of reference numerals in the attached figures: 10 - Substrate; 101 - Bottom silicon layer; 102 - Buried Oxygen Layer; 103 - Top silicon layer; 104 - Rich Trap Layer; 20 - First ONO electron binding structure; 201 - First Depth; 30 - Second ONO electron binding structure; 301 - Second Depth. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] As described in the background section, existing technologies typically employ increasing the resistance of the underlying silicon layer or using Through Contact technology to extract the interface charge by passing through the buried oxide layer and stopping at the interface between the buried oxide layer and the underlying silicon layer via a via.

[0023] Furthermore, existing Through Contact technology suffers from insufficient electron extraction efficiency due to the inability of traditional via structures and extraction mechanisms to adapt to the fast time-domain and high-density characteristics of interface state noise at high frequencies, making it difficult to suppress noise to the H3-80dBm level. Additionally, higher resistance values ​​in the bottom silicon layer increase cost, significantly raising the overall cost of RFSOI devices.

[0024] In view of this, the present invention provides an SOI substrate structure and its fabrication method. The structure includes a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked from bottom to top. A first concentration peak region of nitrogen ions is formed at a first depth from the upper surface of the bottom silicon layer to form a first ONO electron-binding structure within the bottom silicon layer; and / or a second concentration peak region of nitrogen ions is formed at a second depth from the lower surface of the buried oxide layer to form a second ONO electron-binding structure within the buried oxide layer. Through the binding effect of the silicon nitride / silicon oxynitride structure on free charges in the ONO electron-binding structure, the free charges at the buried oxide / silicon interface can be effectively bound, preventing them from oscillating back and forth under high-frequency operation, thereby effectively reducing noise in high-frequency applications and meeting the noise suppression requirements of H3-80dBm. Simultaneously, the SOI substrate structure provided by the present invention can be fabricated without the need for an additional photomask and has low resistance requirements for the bottom silicon layer, thus effectively reducing the cost of RFSOI devices while improving noise suppression levels.

[0025] Please refer to Figures 1A to 3B An SOI substrate structure provided in this embodiment of the invention includes: a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked from bottom to top; A first concentration peak region of nitrogen ions is formed at a first depth 201 from the upper surface of the bottom silicon layer 101 to form a first ONO electron-binding structure 20 within the bottom silicon layer 101; and / or A second concentration peak region of nitrogen ions is formed at a second depth 301 from the lower surface of the buried oxide layer 102, so as to form a second ONO electron-binding structure 30 within the buried oxide layer 102.

[0026] As an example, the materials of the bottom silicon layer 101 and the top silicon layer 103 can be, for example, monocrystalline silicon. Of course, this invention is not limited to this; other types of bottom and top silicon layer materials, such as monocrystalline germanium and monocrystalline silicon carbide, are also within the scope of this invention. As an example, the thickness of the top silicon layer 103 can be, for example, 200 Å to 2000 Å to suit the needs of different devices.

[0027] In a preferred embodiment, the material of the bottom silicon layer 101 can be, for example, a high resistivity single-crystal silicon material (HR-Si) with a resistivity greater than 1 kΩ·cm. By using a high resistivity single-crystal silicon material, the noise current injected into the bottom silicon layer can be rapidly attenuated during propagation due to ohmic losses, thereby significantly reducing the propagation distance and coupling strength of noise in the bottom silicon layer, and further improving the noise isolation capability of the substrate.

[0028] As an example, the material of the buried oxide layer 102 is, for example, silicon dioxide. Of course, the present invention is not limited to this, and other types of silicon dioxide buried oxide layer insulating dielectric materials are also within the scope of protection of the present invention. As an example, the thickness of the buried oxide layer 102 can be, for example, 1000 Å to 3000 Å to adapt to the needs of different devices.

[0029] Example 1: As a specific implementation method, such as Figure 1A As shown, the SOI substrate structure provided by the present invention has a first concentration peak region of nitrogen ion concentration at a first depth 201 from the upper surface of the bottom silicon layer 101, so as to form a first ONO electron binding structure 20 in the bottom silicon layer 101.

[0030] As an example, the first depth 201 can be located within the bottom silicon layer 101 at a depth of 200 Å to 800 Å from the upper surface of the bottom silicon layer 101. Nitrogen ions form a first concentration peak region at the first depth 201 and form a structure similar to silicon nitride, such as a Si3N4 structure. Above and below the first depth 201, structures similar to silicon oxide are formed, such as SiO2. The silicon oxide and silicon nitride together form, for example, a sandwich structure of SiO2-Si3N4-SiO2, thereby forming a first ONO electron-binding structure 20 within the bottom silicon layer 101.

[0031] The silicon nitride (SiN) structure contains numerous deep-level traps within its bandgap. These traps can capture charges migrating from the buried oxide / bottom silicon layer interface through tunneling and hot electron injection. The deep trap levels and strong charge retention capabilities prevent loss due to thermal excitation or electric field fluctuations, thus reducing the diffusion and amplification of noise caused by free charges within the bottom silicon layer. Simultaneously, the nitrogen ion doping distribution creates a depletion region near the upper surface of the bottom silicon layer, reducing the concentration of mobile carriers and suppressing diffusion leakage. The captured charges in SiN form a local electric field, enhancing the width of the depletion region and further reducing leakage. Furthermore, the insulating properties of silicon oxide located above and below the SiN structure create a high-barrier, dense insulating layer that effectively blocks vertical leakage paths between the bottom silicon layer and the buried oxide / top silicon layer. This also passivates the interface between the bottom silicon layer and the buried oxide layer, reducing interface-state-induced tunneling leakage and significantly improving leakage stability. Therefore, the first ONO electron-binding structure 20 formed by silicon oxide-silicon nitride-silicon oxide forms a triple mechanism of "isolation + trapping + attenuation", which effectively suppresses the noise caused by free charges at the buried oxide layer / bottom silicon layer interface and significantly reduces the leakage current of the bottom silicon layer, thereby improving the reliability of the device.

[0032] As a preferred embodiment of this example, Figure 1BAs shown, the SOI substrate structure provided by this invention also includes a trap-rich layer 104 located between the upper surface of the bottom silicon layer 101 and the lower surface of the buried oxide layer 102. As an example, the material of the trap-rich layer 104 can be polycrystalline silicon, and its thickness can be, for example, 1µm to 3µm. Of course, this invention is not limited to this; other types of trap-rich layer materials, such as SiGe, are also within the scope of this invention. By utilizing the characteristics of the trap-rich layer material—dense grain boundaries and abundant defects—which enable the formation of numerous deep-level traps, free electrons and holes at the buried oxide / bottom silicon layer interface can be rapidly captured, and the Fermi level at the buried oxide / trap-rich layer interface can be pinned deep within the band gap, suppressing carrier activation and maintaining a low free carrier concentration, thereby further suppressing noise in the SOI substrate structure.

[0033] Example 2: As a specific implementation method, such as Figure 2A As shown, the SOI substrate structure provided by the present invention has a second concentration peak region of nitrogen ions at a second depth 301 from the lower surface of the buried oxide layer 102, so as to form a second ONO electron-binding structure 30 in the buried oxide layer 102.

[0034] As an example, the second depth 301 can be located within the buried oxide layer 102 at a depth of 100 Å to 200 Å from the lower surface of the buried oxide layer 102. Nitrogen ions form a second concentration peak region at the second depth 301 and form a silicon oxynitride structure similar to Si-ON bonds. Together with the silicon oxide in the buried oxide layer 102 located above and below the second depth 301, they form a sandwich structure such as SiO2-SiON-SiO2, thereby forming a second ONO electron-bound structure 30 within the buried oxide layer 102.

[0035] By utilizing the inherent negative charge of the Si-ON silicon oxynitride structure, the fixed positive charge in the silicon oxide structure (e.g., SiO2) can be neutralized, offsetting the adsorption of electrons from the buried oxide layer 102 onto the bottom silicon layer 101. This blocks the parasitic surface conduction channel (PSC channel) at the buried oxide / bottom silicon layer interface, which is one of the core causes of substrate noise. Simultaneously, the Si-ON silicon oxynitride structure has a higher potential barrier for electrons and holes than silicon oxide, preventing the injection and diffusion of charge carriers from the bottom silicon layer 101 into the buried oxide layer 102. It also suppresses charge carrier transport within the buried oxide layer 102, reducing cross-interface charge fluctuations and effectively suppressing noise in the SOI substrate structure. Furthermore, the Si-ON silicon oxynitride structure has a higher dielectric constant than silicon oxide, improving the breakdown voltage of the buried oxide layer 102. The excellent radiation resistance of the Si-ON silicon oxynitride structure also reduces the generation of radiation-induced trap charges, further suppressing noise in the SOI substrate structure.

[0036] As a preferred embodiment of this example, Figure 2B As shown, the SOI substrate structure provided by this invention also includes a trap-rich layer 104 located between the upper surface of the bottom silicon layer 101 and the lower surface of the buried oxide layer 102. As an example, the material of the trap-rich layer 104 can be polycrystalline silicon, and its thickness can be, for example, 1µm to 3µm. Of course, this invention is not limited to this; other types of trap-rich layer materials, such as SiGe, are also within the scope of this invention. By utilizing the high-density deep-level traps of the trap-rich layer material, mobile charges and trapped charges within the buried oxide layer 102 can be actively captured, and charge transport within the buried oxide layer 102 can be blocked, suppressing the modulation effect of charges on the buried oxide layer / bottom silicon layer interface, thereby further suppressing noise in the SOI substrate structure.

[0037] Example 3: As a preferred implementation method, such as Figure 3A As shown, the SOI substrate structure provided by the present invention has a first concentration peak region of nitrogen ion concentration at a first depth 201 from the upper surface of the bottom silicon layer 101 to form a first ONO electron-binding structure 20 in the bottom silicon layer 101; and a second concentration peak region of nitrogen ion concentration is also formed at a second depth 301 from the lower surface of the buried oxide layer 102 to form a second ONO electron-binding structure 30 in the buried oxide layer 102.

[0038] As an example, the first depth 201 may be located within the bottom silicon layer 101 and at a depth of 200 Å to 800 Å from the upper surface of the bottom silicon layer 101; the second depth 301 may be located within the buried oxide layer 102 and at a depth of 100 Å to 200 Å from the lower surface of the buried oxide layer 102.

[0039] In addition to the noise suppression effects of the first ONO electron-binding structure 20 and the second ONO electron-binding structure 30 mentioned in embodiments 1 and 2, respectively, within the bottom silicon layer 101 and the buried oxide layer 102, this preferred embodiment further utilizes the first ONO electron-binding structure 20 within the bottom silicon layer 101 to block the diffusion of charge carriers from the bottom silicon layer 101 to the buried oxide layer / bottom silicon layer interface, and utilizes the second ONO resistive binding structure 30 to block charge transport and cross-interface injection within the buried oxide layer 102. The combined effect of the first ONO electron-binding structure 20 and the second ONO electron-binding structure 30 cuts off... The entire charge migration chain of "bottom silicon layer 101 -> interface -> buried oxide layer 102 -> top silicon layer 103" is completed, thereby completely eliminating the transmission path of charge-coupled noise, effectively improving the noise suppression level of SOI substrate structure, reducing noise in high-frequency applications, and meeting the noise suppression requirements of H3-80dBm level; at the same time, the Fermi level pinning and charge anchoring effect of the dual electron binding structure can maintain the high resistivity characteristics of SOI substrate structure over a wide temperature (-55℃~150℃) and wide bias voltage range, solving the defect of resistivity drift with temperature / bias of traditional HR-Si substrate.

[0040] As a preferred embodiment of this example, Figure 3B As shown, the SOI substrate structure provided by this invention also includes a trap-rich layer 104 located between the upper surface of the bottom silicon layer 101 and the lower surface of the buried oxide layer 102. As an example, the material of the trap-rich layer 104 can be polycrystalline silicon, and its thickness can be, for example, 1µm to 3µm. Of course, this invention is not limited to this; other types of trap-rich layer materials, such as SiGe, are also within the scope of this invention. By utilizing the high-density deep-level traps of the trap-rich layer material, mobile charges and trapped charges within the buried oxide layer 102 can be actively captured, and charge transport within the buried oxide layer 102 can be blocked, suppressing the modulation effect of charges on the buried oxide layer / bottom silicon layer interface, thereby further improving the noise suppression level of the SOI substrate structure.

[0041] According to an embodiment of the present invention, a method for fabricating an SOI substrate structure is also provided; please refer to [reference needed]. Figure 4 and combined Figures 5A to 7C The method for preparing the SOI substrate structure provided in this embodiment of the invention may include the following steps: S1: A substrate 10 is provided, wherein a bottom silicon layer 101, a buried oxide layer 102 and a top silicon layer 103 are formed sequentially from bottom to top on the substrate 10.

[0042] As an example, the materials of the bottom silicon layer 101 and the top silicon layer 103 can be, for example, single-crystal silicon. Of course, the present invention is not limited to this; other types of bottom and top silicon layer materials, such as single-crystal germanium and single-crystal silicon carbide, are also within the scope of protection of the present invention. As an example, the thickness of the top silicon layer 103 can be, for example, 200 Å to 2000 Å to adapt to the needs of different devices. As a preferred embodiment, the material of the bottom silicon layer 101 can be, for example, high-resistivity single-crystal silicon (HR-Si), with a resistivity, for example, greater than 1 kΩ·cm. By using a high-resistivity single-crystal silicon material, the noise current injected into the bottom silicon layer can be rapidly attenuated during propagation due to ohmic losses, thereby significantly reducing the propagation distance and coupling strength of noise in the bottom silicon layer, further improving the noise isolation capability of the substrate.

[0043] As an example, the material of the buried oxide layer 102 is, for example, silicon dioxide. Of course, the present invention is not limited to this, and other types of silicon dioxide buried oxide layer insulating dielectric materials are also within the scope of protection of the present invention. As an example, the thickness of the buried oxide layer 102 can be, for example, 1000 Å to 3000 Å to adapt to the needs of different devices.

[0044] In a preferred embodiment, after forming the bottom silicon layer 101 and before forming the buried oxide layer 102, the substrate 10 further includes forming a trap-rich layer 104. A schematic diagram of the structure of the substrate 10 with the trap-rich layer 104 is shown below. Figure 1B , 2B As shown in 3B.

[0045] S2: Oxygen ions, nitrogen ions, and oxygen ions are sequentially implanted into the substrate 10 to form a first concentration peak region of nitrogen ions at a first depth 201 from the upper surface of the bottom silicon layer 101; and / or nitrogen ions are implanted into the substrate 10 to form a second concentration peak region of nitrogen ions at a second depth 301 from the lower surface of the buried oxide layer 102.

[0046] Example 1: In one specific implementation, the substrate 10 is subjected to sequential ion implantation of oxygen ions, nitrogen ions, and oxygen ions to form a first concentration peak of nitrogen ions at a first depth 201 from the upper surface of the bottom silicon layer 101. This may include, for example, the following: First, the substrate 10 is sequentially implanted with oxygen ions, nitrogen ions, and then oxygen ions, as follows: Figure 5A As shown. For example, the incident angle of ion implantation can be 0 degrees to 7 degrees, and the energy of ion implantation is determined according to the specific thickness of the top silicon layer / buried oxide layer, for example, it can be 1 MeV to 10 MeV.

[0047] As a specific implementation, ion implantation of the substrate 10 sequentially with oxygen ions, nitrogen ions, and oxygen ions may include, for example: First oxygen ion implantation: A thin oxide layer or oxygen-rich region is formed near the upper surface of the bottom silicon layer 101 to reduce the channeling effect during nitrogen ion implantation and improve the uniformity of nitrogen ion distribution; at the same time, it provides an oxygen ion source for subsequent ON bonding.

[0048] Nitrogen ion implantation: Through collisions between nitrogen ions and the silicon lattice, interstitial nitrogen ions, substitutional nitrogen ions, and lattice damage are formed, and a first concentration peak region of nitrogen ions is formed at a first depth 201 from the upper surface of the bottom silicon layer 101.

[0049] Second oxygen ion implantation: Covering both sides of the nitrogen ion peak to form an "oxygen cap", inhibiting the diffusion of nitrogen ions to the top / bottom silicon layer and fixing the nitrogen ions at the implantation depth.

[0050] The sequential implantation of oxygen ions, nitrogen ions, and oxygen ions into the substrate 10 is called blanket implantation, which means that the entire substrate 10 is implanted directly without forming any patterns. Therefore, no new photomask is needed, thereby reducing the fabrication cost of RFSOI devices.

[0051] Next, the substrate 10 is annealed to form a first concentration peak region of nitrogen ions at a first depth 201 from the upper surface of the bottom silicon layer 101. The structural schematic diagram after this step is shown below. Figure 5B As shown.

[0052] As an example, the substrate 10 may be annealed, for example, by using a isothermal holding annealing (Soak) method. As a specific implementation, Soak annealing may include, for example, the following: Low-temperature pre-soak annealing: The heating / cooling rate is, for example, 3℃ / min~5℃ / min, the temperature range is, for example, 600℃~800℃, and the holding time is, for example, 30min~40min. The entire process is carried out in an inert atmosphere (e.g., in a high-purity N2 / Ar atmosphere). Low-temperature pre-soak annealing can eliminate shallow lattice damage caused by ion implantation, promote the migration of interstitial nitrogen ions to substitutional sites, initially fix the nitrogen ion distribution, and at the same time avoid the rapid expansion and escape of nitrogen ions caused by direct high temperature.

[0053] High-temperature main Soak annealing: The heating / cooling rate is, for example, 3℃ / min~5℃ / min, the temperature range is, for example, 1000℃~1100℃, and the holding time is, for example, 1hr~1.5hr. The entire process is carried out in a dry oxygen (O2) or O2 / N2 mixed atmosphere. Through high-temperature main Soak annealing, Si and N can form stable Si-N bonds, such as the Si3N4 structure. The oxygen atoms on both sides are bonded to Si to form a dense SiO2 layer, which together with Si3N4 forms an ONO-like sandwich structure, namely the first ONO electron-bound structure 20. At the same time, the oxygen partial pressure gradient of the oxidizing atmosphere is used to confine nitrogen atoms to the first depth 201, sharpening the peak concentration of nitrogen ions. High-temperature main Soak annealing can also thoroughly repair lattice damage, passivate the dangling bonds at the Si / SiO2 interface, reduce the interface state density, and improve the stability of the ONO electron-bound structure. In addition, by using low-temperature pre-annealing + high-temperature main annealing, excessive diffusion of nitrogen ions caused by a single high temperature can be effectively avoided.

[0054] Of course, this invention is not limited to this, and other types of annealing processes are also within the scope of protection of this invention.

[0055] The first ONO electron-binding structure 20 formed by silicon oxide-silicon nitride-silicon oxide creates a triple mechanism of "isolation + trapping + attenuation", which effectively suppresses noise caused by free charges at the buried oxide layer / bottom silicon layer interface and significantly reduces leakage current of the bottom silicon layer, thereby improving the reliability of the device.

[0056] Example 2: In another specific implementation, nitrogen ion implantation is performed on the substrate 10 to form a second concentration peak region of nitrogen ion concentration at a second depth 301 from the lower surface of the buried oxide layer 102. This may include, for example,: First, nitrogen ion implantation is performed on substrate 10, such as... Figure 6A As shown. For example, the incident angle of ion implantation can be, for example, 0 degrees to 7 degrees, and the ion implantation energy is determined according to the specific thickness of the top silicon layer / buried oxide layer, for example, 50 keV to 150 keV. After nitrogen ion implantation, a Gaussian concentration distribution will be formed within the buried oxide layer 102, and a second concentration peak region of nitrogen ions will be formed at a second depth 301 from the lower surface of the buried oxide layer 102, surrounded by a SiO2 matrix.

[0057] Then, the substrate 10 is annealed to form a second nitrogen ion concentration peak region at a second depth 301 from the lower surface of the buried oxide layer 102. The structural schematic diagram after this step is shown in Figure 10. Figure 6B As shown.

[0058] As an example, the substrate 10 is annealed, for example, by using rapid thermal annealing (Spikeanneal). In a specific implementation, the heating rate of Spikeanneal can be, for example, 150°C / s to 300°C / s. By rapidly increasing the temperature to the target temperature, skipping the atomic diffusion region in the low-temperature range, it effectively freezes nitrogen ions at the second concentration peak position (second depth 301) of the buried oxide layer 102; the peak temperature is, for example, 1000°C to 1100°C, to drive oxygen and nitrogen atoms to bond and form Si-ON bonds, and together with the SiO2 matrix surrounding the second concentration peak of nitrogen ion implantation, form a second ONO electron-bound structure 30; the high-temperature holding time can be, for example, 4 seconds to 6 seconds, and the cooling rate can be, for example, 80°C / s to 100°C / s. Rapid heat preservation and cooling can effectively repair defects such as oxygen vacancies and Si-O bond breakage caused by implantation and effectively "freeze" the already formed ONO structure, preventing structural relaxation at high temperatures and ensuring that the concentration peak of nitrogen ions in the buried oxide layer 102 is accurately maintained at the second depth 301. The annealing atmosphere is mainly inert, such as in a high-purity N2+ with trace amounts of O2 (0.5%~1% by volume). The inert atmosphere can effectively suppress the oxidation of the top / bottom silicon layer at high temperatures, while the trace amounts of O2 replenish the oxygen vacancies in the buried oxide layer 102, forming a denser ONO bond with nitrogen ions and improving the stability of electron binding.

[0059] Of course, this invention is not limited to this, and other types of annealing processes are also within the scope of protection of this invention.

[0060] By utilizing the inherent negative charge of the Si-ON silicon oxynitride structure, the fixed positive charge in the silicon oxide structure (e.g., SiO2) can be neutralized, counteracting the adsorption of electrons from the buried oxide layer 102 onto the bottom silicon layer 101 and blocking the parasitic surface conductive channels at the buried oxide layer / bottom silicon layer interface. Simultaneously, the Si-ON silicon oxynitride structure has a higher potential barrier for electrons and holes than silicon oxide, preventing the injection and diffusion of charge carriers from the bottom silicon layer 101 into the buried oxide layer 102, while also suppressing carrier transport within the buried oxide layer 102, reducing cross-interface charge fluctuations, and thus effectively suppressing noise in the SOI substrate structure. Furthermore, the Si-ON silicon oxynitride structure has a higher energy-saving constant than silicon oxide, improving the withstand voltage of the buried oxide layer 102. The excellent radiation resistance of the Si-ON silicon oxynitride structure also reduces the generation of radiation-induced trap charges, further suppressing noise in the SOI substrate structure.

[0061] Example 3: In a preferred embodiment, the substrate 10 is sequentially implanted with oxygen ions, nitrogen ions, and then oxygen ions to form a first peak concentration region of nitrogen ions at a first depth 201 from the upper surface of the bottom silicon layer 101; the substrate 10 is then implanted with nitrogen ions to form a second peak concentration region of nitrogen ions at a second depth 301 from the lower surface of the buried oxide layer 102. This process may include, for example, the following: First, oxygen ions, nitrogen ions, and oxygen ions are sequentially implanted into the substrate 10 to form a first concentration peak region 201 of nitrogen ions at a first depth 201 from the upper surface of the bottom silicon layer 101, such as... Figure 7A As shown.

[0062] As an example, the incident angle for sequentially implanting oxygen ions, nitrogen ions, and oxygen ions into the substrate 10 can be, for example, 0 degrees to 7 degrees. The energy of the ion implantation is determined according to the specific thickness of the top silicon layer / buried oxide layer, for example, 1 MeV to 10 MeV.

[0063] Then, nitrogen ion implantation is performed on substrate 10, such as... Figure 7B As shown. For example, the incident angle for nitrogen ion implantation into substrate 10 can be, for example, 0 degrees to 7 degrees, and the ion implantation energy is determined based on the specific thickness of the top silicon layer / buried oxide layer, for example, 50 keV to 150 keV. After nitrogen ion implantation, a Gaussian concentration distribution is formed within the buried oxide layer 102, and a second concentration peak region of nitrogen ions is formed at a second depth 301 from the lower surface of the buried oxide layer 102, surrounded by a SiO2 matrix.

[0064] Next, the substrate 10 undergoes an annealing process to form a first peak concentration region of nitrogen ions at a first depth 201 from the upper surface of the bottom silicon layer 101, thereby forming a first ONO electron-bound structure 20 within the bottom silicon layer 101; and a second peak concentration region of nitrogen ions is formed at a second depth 301 from the lower surface of the buried oxide layer 102, thereby forming a second ONO electron-bound structure 30 within the buried oxide layer 102. A schematic diagram of the structure after this step is shown below. Figure 7C As shown.

[0065] As an example, the substrate 10 may undergo an annealing process, such as isothermal holding annealing (Soak). As a specific implementation, Soak annealing may include, for example: Low-temperature pre-soak annealing: The heating / cooling rate is, for example, 3℃ / min~5℃ / min, the temperature range is, for example, 600℃~800℃, and the holding time is, for example, 30min~40min. The entire process is carried out in an inert atmosphere (e.g., in a high-purity N2 / Ar atmosphere). Low-temperature pre-soak annealing can eliminate shallow lattice damage caused by ion implantation, promote the migration of interstitial nitrogen ions to substitutional sites, and initially fix the nitrogen ion distribution at the first depth 201 and the second depth 301, while avoiding the rapid expansion and escape of nitrogen ions caused by direct high temperature.

[0066] High-temperature main Soak annealing: heating / cooling rate is, for example, 3℃ / min~5℃ / min, temperature range is, for example, 1000℃~1100℃, holding time is, for example, 1hr~1.5hr, and the whole process is carried out in dry oxygen (O2) or O2 / N2 mixed atmosphere. High-temperature main soak annealing allows Si and N atoms in the bottom silicon layer 101 to form stable Si-N bonds, such as a Si3N4 structure. Oxygen atoms on both sides bond with Si to form a dense SiO2 layer, which, together with Si3N4, forms an ONO-like sandwich structure, i.e., the first ONO electron-bound structure 20. Simultaneously, oxygen and nitrogen atoms in the buried oxide layer 102 bond to form a Si-ON silicon oxynitride structure, which, together with the SiO2 matrix surrounding the second concentration peak of nitrogen ion implantation, forms a second ONO electron-bound structure 30. The oxygen partial pressure gradient in the oxidizing atmosphere confines nitrogen atoms to the first depth 201 and the second depth 301, sharpening the nitrogen ion concentration peak. High-temperature main soak annealing also thoroughly repairs lattice damage, passivates dangling bonds at the Si / SiO2 interface, reduces the interface state density, and improves the stability of the ONO electron-bound structure. Furthermore, by employing a low-temperature pre-annealing followed by high-temperature main annealing, excessive diffusion of nitrogen ions caused by a single high-temperature process can be effectively avoided.

[0067] Of course, this invention is not limited to this, and other types of annealing processes are also within the scope of protection of this invention.

[0068] Through a single annealing process, a first ONO electron-binding structure 20 and a second ONO electron-binding structure 30 are formed simultaneously. Through the triple mechanism of "isolation + capture + attenuation" of the ONO electron-binding structure, noise caused by free charges at the buried oxide layer / silicon layer interface is effectively suppressed, while the fabrication cost of SOI substrate structure is effectively reduced.

[0069] In addition, the SOI substrate structure 10 can be prepared by using the SOI substrate structure preparation method in Examples 1, 2 and 3 above. No additional photomask is required to complete the preparation, and the requirements for the bottom silicon layer are not high. Thus, while improving the noise suppression level, the cost of RFSOI devices is further reduced.

[0070] Those skilled in the art will understand that the embodiments provided by the present invention can be provided as methods, apparatus, or electronic devices. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An SOI substrate structure, characterized in that... It includes: a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked from bottom to top; A first concentration peak region of nitrogen ions is formed at a first depth from the upper surface of the bottom silicon layer to form a first ONO electron-binding structure within the bottom silicon layer; and / or A second concentration peak region of nitrogen ions is formed at a second depth from the lower surface of the buried oxide layer to form a second ONO electron-binding structure within the buried oxide layer.

2. The SOI substrate structure according to claim 1, characterized in that... The first depth is a position 200 Å to 800 Å away from the upper surface of the top silicon layer.

3. The SOI substrate structure according to claim 1, characterized in that... The second depth is a position 100 Å to 200 Å away from the lower surface of the buried oxide layer.

4. The SOI substrate structure according to claim 1, characterized in that... The SOI substrate structure further includes a trap-rich layer located between the upper surface of the bottom silicon layer and the lower surface of the buried oxide layer.

5. A method for preparing an SOI substrate structure, used to prepare the SOI substrate structure as described in any one of claims 1 to 4, characterized in that... ,include: A substrate is provided, wherein a bottom silicon layer, a buried oxide layer, and a top silicon layer are formed sequentially from bottom to top. The substrate is sequentially implanted with oxygen ions, nitrogen ions, and oxygen ions to form a first concentration peak region of nitrogen ions at a first depth from the upper surface of the bottom silicon layer; and / or the substrate is implanted with nitrogen ions to form a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer.

6. The method for preparing the SOI substrate structure according to claim 5, characterized in that... The step of sequentially implanting oxygen ions, nitrogen ions, and oxygen ions into the substrate to form a first concentration peak region of nitrogen ions at a first depth from the upper surface of the bottom silicon layer includes: The substrate was sequentially implanted with oxygen ions, nitrogen ions, and then oxygen ions. The substrate after ion implantation is annealed to form a first concentration peak region of nitrogen ions at a first depth from the upper surface of the bottom silicon layer.

7. The method for preparing the SOI substrate structure according to claim 5, characterized in that... The step of implanting nitrogen ions into the substrate to form a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer includes: Nitrogen ion implantation is performed on the substrate; The substrate is annealed to form a second concentration peak region of nitrogen ions at a second depth from the lower surface of the buried oxide layer.

8. The method for fabricating an SOI substrate structure according to claim 6 or 7, characterized in that... The annealing temperature is 1000℃~1200℃.

9. The method for preparing the SOI substrate structure according to claim 5, characterized in that... The sequential ion implantation of oxygen ions, nitrogen ions, and oxygen ions into the substrate includes: an incident angle of 0 degrees to 7 degrees, and an ion implantation energy of 1 MeV to 10 MeV; and / or The nitrogen ion implantation of the substrate includes: an incident angle of 0 degrees to 7 degrees and an ion implantation energy of 50 keV to 150 keV.

10. The method for preparing the SOI substrate structure according to claim 5, characterized in that... The substrate, after forming the bottom silicon layer and before forming the buried oxide layer, further includes: forming a trap-rich layer.

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