Chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging structure and electronic equipment. The chip packaging structure comprises a chip, a lead frame, a first heat conduction lead and a packaging layer, the chip is electrically connected with the lead frame; at least part of the surface of the chip is coated by the packaging layer; at least part of the first heat conduction lead is located in the packaging layer, the first end of the first heat conduction lead is connected with the lead frame, and the second end of the first heat conduction lead is flush with the first heat dissipation surface of the packaging layer or penetrates out of the first heat dissipation surface. By arranging the first heat conduction lead, the heat dissipation efficiency of the chip can be improved, and the cost of the first heat conduction lead is relatively low.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip packaging structure and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, the heat dissipation performance of chip packaging structures has become particularly important. The chip located in the middle of the packaging structure, as well as the wires between the chips, release a large amount of heat during operation. If this heat cannot be dissipated in time, it will not only cause warping and deformation of the device, but also lead to a decrease in device performance or even complete failure. It may even cause short circuits and result in serious production accidents.

[0003] Currently, the main solution to the above problem is to try to install a semiconductor heat sink inside the package.

[0004] However, the method of placing semiconductor heat sinks inside the package still has some limitations, such as high cost or complex structure. Summary of the Invention

[0005] In view of this, this application provides a chip packaging structure and an electronic device to solve the technical problem of heat dissipation in traditional chip packaging structures.

[0006] This application provides a chip packaging structure, including: a chip, a lead frame, a first thermally conductive lead, and a packaging layer; the chip is electrically connected to the lead frame; at least a portion of the surface of the chip is covered by the packaging layer; at least a portion of the first thermally conductive lead is located within the packaging layer, and a first end of the first thermally conductive lead is connected to the lead frame, and a second end of the first thermally conductive lead is flush with or extends through a first heat dissipation surface of the packaging layer.

[0007] Optionally, the chip packaging structure further includes: a second thermally conductive lead; at least a portion of the second thermally conductive lead is located within the packaging layer, and a first end of the second thermally conductive lead is connected to the chip, and a second end of the second thermally conductive lead is flush with or extends through the first heat dissipation surface.

[0008] Optionally, the first thermally conductive lead and the second thermally conductive lead are perpendicular to the first heat dissipation surface.

[0009] Optionally, the chip packaging structure further includes: a first heat dissipation layer and a second heat dissipation layer; the first heat dissipation layer and the second heat dissipation layer are attached to the first heat dissipation surface; the first heat dissipation layer is connected to the second end of the first thermally conductive lead, and the second heat dissipation layer is connected to the second end of the second thermally conductive lead.

[0010] Optionally, the lead frame includes heat dissipation pins and electrical pins, with electrical pads provided on the electrical pins; the first surface of the heat dissipation pins is attached to the back side of the chip, and the encapsulation layer covers a portion of the side and front side of the chip, with the encapsulation layer at least covering the side of the heat dissipation pins; the first surface of the electrical pads is attached to the electrical pins, and the encapsulation layer covers a portion of the side and second surface of the electrical pads, with the first and second surfaces of the electrical pads facing each other; a first pad is provided on the front side of the chip, and the first pad is electrically connected to the second surface of the electrical pad via bonding wires, with the front and back sides of the chip facing each other; the first end of the first thermally conductive lead is connected to the second surface of the electrical pad.

[0011] Optionally, a second pad is provided on the front side of the chip, and the second pad is electrically connected to the lead frame via copper pillar bumps; the encapsulation layer covers at least a portion of the side and back side of the chip, with the front and back sides of the chip facing each other.

[0012] Optionally, the lead frame includes a first packaging substrate, a third pad is provided on the front side of the chip, the portion of the front side of the chip excluding the third pad is bonded to a first dielectric layer in the first packaging substrate, and the chip is electrically connected to a fan-out pad in the first packaging substrate through the third pad; the packaging layer covers at least a portion of the side and back sides of the chip, and the front and back sides of the chip are opposite to each other.

[0013] Optionally, a third heat dissipation layer is provided on the surface of the chip away from the lead frame, and the first end of the second thermally conductive lead is connected to the chip through the third heat dissipation layer.

[0014] Optionally, the diameters of the first thermally conductive lead and the second thermally conductive lead are in the range of [15um, 1mm].

[0015] Optionally, the first thermal lead and the second thermal lead comprise at least one of gold, copper, and aluminum.

[0016] Optionally, the diameters of the first thermally conductive lead and the second thermally conductive lead are larger than the diameter of the bonding wire.

[0017] A second aspect of this application provides an electronic device, comprising: a chip package structure as described in any of the first aspects above.

[0018] The chip packaging structure provided in this application, by providing a first thermally conductive lead, can conduct heat from the lead frame to the outside of the packaging layer, thereby improving the heat dissipation efficiency of the chip. Furthermore, the first thermally conductive lead has a low cost. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0020] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application; Figure 2 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 3 This is a schematic diagram of a chip packaging structure including a first heat dissipation layer according to an embodiment of this application; Figure 4 This is a top view of a chip package structure including a first heat dissipation layer according to an embodiment of this application; Figure 5 This is a bottom view of a chip packaging structure according to an embodiment of this application; Figures 6a-6e This is a schematic diagram of the structure obtained by key manufacturing steps of a chip packaging structure according to an embodiment of this application; Figures 7-10 These are schematic diagrams of the standard chip package structure according to different embodiments of this application; Figures 11-13 These are schematic diagrams of flip-chip packaging structures according to different embodiments of this application; Figure 14 A schematic diagram of a chip packaging structure according to another embodiment of this application.

[0021] List of reference numerals in the attached diagram: Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0023] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0024] It should be understood that although this application may use the terms first, second, third, etc., to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0025] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0026] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application, as shown below. Figure 1 As shown, the chip package structure 1 includes a chip 11, a lead frame 12, a first thermally conductive lead 13, and a package layer 14. The chip 11 is electrically connected to the lead frame 12, and at least a portion of the surface of the chip 11 is covered by the package layer 14. At least a portion of the first thermally conductive lead 13 is located within the package layer 14, and a first end of the first thermally conductive lead 13 is connected to the lead frame 12, while a second end of the first thermally conductive lead 13 is flush with or extends beyond the first heat dissipation surface 141 of the package layer 14.

[0027] With the rapid development of electronic information technology and the continuous improvement of people's consumption levels, the functions of individual electronic devices are becoming increasingly diversified and their sizes are becoming increasingly smaller. This has led to a continuous increase in the density of chips and functional components in the internal structure of electronic devices, while the critical dimension (i.e., linewidth) of the devices is becoming increasingly smaller. This poses a great challenge to the semiconductor packaging industry. Although various packaging technologies are emerging, heat dissipation of packaged devices remains a difficult problem to solve. Since the main heat generation in the chip packaging structure 1 comes from the chip 11, and the chip 11 is connected to the lead frame 12, some of the heat from the chip 11 is also conducted to the lead frame 12. Therefore, a first thermally conductive lead 13 is provided in the chip packaging structure 1. The first thermally conductive lead 13 conducts the heat from the lead frame 12 to its second end. Since the second end of the first thermally conductive lead 13 is not covered by the packaging layer 14, the first thermally conductive lead 13 can dissipate the heat.

[0028] It should be noted that, Figure 1 The chip package structure 1 shown is a standard chip package structure, where the chip 11 and the lead frame 12 are electrically connected via bonding wires. However, chip package structure 1 can also be other types of package structures. Figure 1 The diagram shows that chip 11 and lead frame 12 are connected via a bonding layer 20. The bonding layer 20 may include a die-attach film (DAF), primarily composed of epoxy resin, formed into a uniform film through a coating process, or it may include a DAA fluid material. Alternatively, chip 11 and lead frame 12 can be directly soldered. Terminals 30, which may be made of tin, can also be provided on the exposed end face of lead frame 12 within the encapsulation layer 14 for connection to external devices and communication.

[0029] In this embodiment, by providing the first thermally conductive lead 13, the heat from the lead frame 12 can be conducted to the outside of the encapsulation layer 14, thereby improving the heat dissipation efficiency of the chip. Furthermore, the first thermally conductive lead 13 has a low cost.

[0030] Figure 2 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 2 As shown, the chip package structure 1 further includes a second thermally conductive lead 15. At least a portion of the second thermally conductive lead 15 is located within the package layer 14, and the first end of the second thermally conductive lead 15 is connected to the chip 11, while the second end of the second thermally conductive lead 15 is flush with or extends through the first heat dissipation surface 141.

[0031] The second thermally conductive lead 15 can be the same as or different from the first thermally conductive lead 13. The second thermally conductive lead 15 is used to conduct heat from the surface connected to the chip 11 to the outside of the encapsulation layer 14. The first thermally conductive lead 13 and the second thermally conductive lead 15 can be connected to the lead frame 12 and the chip 11 by means of thermo-ultrasonic bonding, thermo-pressure bonding, or ultrasonic bonding.

[0032] Specifically, the first thermally conductive lead 13 and the second thermally conductive lead 15 are perpendicular to the first heat dissipation surface 141. Typically, the surfaces of the chip 11 and the lead frame 12 opposite to the first heat dissipation surface 141 are parallel to it. Therefore, setting the first thermally conductive lead 13 and the second thermally conductive lead 15 perpendicular to the first heat dissipation surface 141 minimizes the material cost of the first thermally conductive lead 13 and the second thermally conductive lead 15. Furthermore, the heat dissipation path formed by the first thermally conductive lead 13 and the second thermally conductive lead 15 is the shortest at this time, improving heat dissipation efficiency.

[0033] Specifically, the diameter range of the first thermally conductive lead 13 and the second thermally conductive lead 15 is [15um, 1mm]. Since the thermal conductivity is positively correlated with the cross-sectional area of ​​the conductor (the larger the cross-sectional area, the more heat is transferred per unit time), and excessively thin leads such as <15um are prone to breakage during bonding, or localized heating due to excessive contact resistance, while leads larger than 1mm will cause excessive pressure during bonding (e.g., easily damaging the chip pads or the surface of chip 11), and it is difficult to achieve uniform coverage through epoxy resin injection molding during molding (e.g., easily generating bubbles and gaps, affecting the hermeticity of the package), by limiting the diameter range of the first thermally conductive lead 13 and the second thermally conductive lead 15, heat dissipation efficiency, process feasibility, package compatibility and electrical isolation requirements can be balanced.

[0034] Specifically, the first thermally conductive lead 13 and the second thermally conductive lead 15 include at least one of gold, copper, and aluminum. For example, the first thermally conductive lead 13 and the second thermally conductive lead 15 are made of copper, or the first thermally conductive lead 13 and the second thermally conductive lead 15 are a copper-aluminum alloy. It should be noted that the first thermally conductive lead 13 and the second thermally conductive lead 15 may include the same material or different materials. By drawing a material with high thermal conductivity and mature processing technology, such as gold, copper, and aluminum, into a thin wire or a narrow strip as the first thermally conductive lead 13 and the second thermally conductive lead 15, a trade-off can be made between heat, electricity, mechanics, and cost, maximizing the rapid conduction of heat generated by the chip 11 to the outside of the packaging layer 14 through the first thermally conductive lead 13 and the second thermally conductive lead 15.

[0035] In this embodiment of the application, by setting a second thermal conductive lead 15, together with the first thermal conductive lead 13, heat dissipation of the chip package structure 1 can be achieved, thereby improving heat dissipation efficiency.

[0036] Figure 3 This is a schematic diagram of a chip package structure including a first heat dissipation layer according to an embodiment of this application. Figure 4 This is a top view of a chip package structure including a first heat dissipation layer according to an embodiment of this application, as shown below. Figure 3-4 As shown, the chip package structure 1 further includes a first heat dissipation layer 16 and a second heat dissipation layer 17. The first heat dissipation layer 16 and the second heat dissipation layer 17 are attached to the first heat dissipation surface 141. The first heat dissipation layer 16 is connected to the second end of the first thermally conductive lead 13, and the second heat dissipation layer 17 is connected to the second end of the second thermally conductive lead 15.

[0037] To further improve heat dissipation, a first heat dissipation layer 16 and a second heat dissipation layer 17 can be provided on the first heat dissipation surface 141. The first heat dissipation layer 16 and the second heat dissipation layer 17 do not contact each other. Multiple first heat dissipation layers 16 and multiple second heat dissipation layers 17 are provided. The first heat dissipation layer 16 is connected to the first thermal conductive lead 13 one-to-one, and the second heat dissipation layer 17 is connected to the second thermal conductive lead 15 one-to-one.

[0038] In this embodiment of the application, by providing a first heat dissipation layer 16 and a second heat dissipation layer 17, the heat guided by the first heat-conducting lead 13 and the second heat-conducting lead 15 can be quickly dissipated, further improving the heat dissipation efficiency.

[0039] Figure 5 This is a bottom view of a chip package structure according to an embodiment of this application, as shown below. Figure 2 and 5 As shown, the lead frame 12 includes heat dissipation pins 121 and electrical pins 122, and electrical pads 123 are provided on the electrical pins 122.

[0040] The first surface of the heat dissipation pin 121 is attached to the back side of the chip 11. The encapsulation layer 14 covers a portion of the side and front side of the chip 11, and at least covers the side of the heat dissipation pin 121. The first surface of the electrical pad 123 is attached to the electrical pin 122. The encapsulation layer 14 covers a portion of the side and second surface of the electrical pad 123, and the first surface and second surface of the electrical pad 123 are opposite to each other. A first pad 111 is provided on the front side of the chip 11. The first pad 111 and the second surface of the electrical pad 123 are electrically connected by a bonding wire 18, and the front and back sides of the chip 11 are opposite to each other. The first end of the first thermal lead 13 is connected to the second surface of the electrical pad 123.

[0041] because Figure 2 The diagram shows a standard chip package structure, where the first pad 111 on the front side of chip 11 is electrically connected to the second surface of electrical pad 123 via bonding wire 18. The back side of chip 11 is attached to the first surface of heat dissipation pin 121 using DAF adhesive or similar materials. Figure 5 As shown, the second surface of the heat dissipation pin 121, which is opposite to the first surface of the heat dissipation pin 121, is not covered by the encapsulation layer 14, so the second surface of the heat dissipation pin 121 can also dissipate heat. The electrical pin 122 is used to enable the chip 11 to communicate with devices electrically connected to the electrical pin 122.

[0042] exist Figure 2 After a first heat dissipation layer 16 and a second heat dissipation layer 17 are disposed on the first heat dissipation surface 141 of the chip packaging structure shown, the following can be obtained: Figure 3 The chip packaging structure shown.

[0043] Specifically, the diameters of the first thermally conductive lead 13 and the second thermally conductive lead 15 are larger than the diameter of the bonding wire 18.

[0044] It should be noted that, to ensure the connection between the second thermally conductive lead 15 and the chip 11, a thermally conductive pad can be provided on the front side of the chip 11, allowing the second thermally conductive lead 15 to connect to the chip 11 via the thermally conductive pad. In this case, to save space, the thermally conductive pad can share a pad with the first pad 111. Alternatively, since the exposed second thermally conductive lead 15 may pose a risk of ESD (Electro-Static Discharge), the thermally conductive pad can also be independent and insulated from the bonding wire 18, and not share a pad.

[0045] For details, please refer to Figure 4 The second heat-conducting lead 15, which shares a first pad 111, can share the second heat dissipation layer 17. This allows for an increase in the area of ​​the second heat dissipation layer.

[0046] In this embodiment of the application, by connecting the first end of the first thermally conductive lead 13 to the second surface of the electrical pad 123, the first thermally conductive lead 13 can dissipate heat from the part of the bonding wire 18 that generates the most significant heat, thereby improving the heat dissipation efficiency.

[0047] In one possible implementation method Figure 3 The key fabrication steps of the chip package structure 1 shown are as follows: Key step S1: Fix chip 11 onto the first surface of heat dissipation pin 121, and set electrical pads 123 on electrical pin 122. For example... Figure 6a As shown.

[0048] Key step S2: The first pad 111 on the front side of the chip 11 is electrically connected to the second surface of the electrical pad 123 via bonding wire 18, and a first thermally conductive lead 13 and a second thermally conductive lead 15 are provided. For example... Figure 6b As shown.

[0049] Key step S3: Molding. (e.g., sealing.) Figure 6cAs shown.

[0050] Key step S4: Thinning the encapsulation layer 14 until the first thermal lead 13 and the second thermal lead 15 are exposed. (Example) Figure 6d As shown.

[0051] Key step S5: Metallize the first heat dissipation surface 141 and cut it to obtain the first heat dissipation layer 16 and the second heat dissipation layer 17, as shown below. Figure 6e As shown.

[0052] For a standard chip package structure, the first thermal lead 13 and the second thermal lead 15 can be adapted to various different types of packages, such as... Figure 7 The small outline package (SOP) shown has electrical pins 122 extending outwards from both sides of the package layer 14. (See diagram below.) Figure 8 The Enhanced Small Outline Package (ESOP) shown is shown. Figure 8 The heat dissipation pin 121 of the ESOP shown extends away from the first heat dissipation surface 141, and the second surface of the heat dissipation pin 121 away from the first heat dissipation surface 141 is not covered by the encapsulation layer 14. Figure 9 The heat dissipation pin 121 of the ESOP shown extends toward the first heat dissipation surface 141, and the second surface of the heat dissipation pin 121 near the first heat dissipation surface 141 is not covered by the encapsulation layer 14. Figure 10 The wire bond ball grid array (WB BGA) package shown has a lead frame 12 including a first package substrate. The chip 11 is bonded to the top layer solder mask in the first package substrate. The top layer solder mask is the heat dissipation pin 121. The electrical pin 122 is separated from the top layer solder mask and the bottom layer solder mask by a pre-preg (PPG). The electrical pin 122 also includes a metal solder ball at the bottom.

[0053] In one possible implementation, a second pad 112 is provided on the front side of the chip 11, and the second pad 112 is electrically connected to the lead frame 12 via copper pillar bumps 19. The encapsulation layer 14 covers at least a portion of the side and back sides of the chip 11, with the front and back sides of the chip 11 facing each other.

[0054] The chip package structure 1 can be a flip chip structure, in which the front side of the chip 11 faces the lead frame 12, and the chip 11 is electrically connected to the lead frame 12 through copper pillar bumps 19. At this time, the first thermally conductive lead 13 is connected to the back side of the chip 11, and the second thermally conductive lead 15 is connected to the lead frame 12.

[0055] For flip-chip package structures, the first thermal lead 13 and the second thermal lead 15 can be adapted to various different types of packages, such as... Figure 11 The flip chip quad / dual flat no-leads package (FCQFN / FCDFN) shown combines FC (flip chip) technology with QFN / DFN (leadless package), with no exposed leads and a pad array on the bottom, or, as... Figure 12 The flip-chip small outline transistor (FCSOT) shown combines FC technology with SOT (small outline transistor packaging), specifically designed for small-size transistor devices. Alternatively, as... Figure 13 The flip chip ball grid array (FC BGA) package shown is a combination of FC technology and BGA packaging, and is the mainstream packaging form for high-performance chips.

[0056] Specifically, in Figure 11 and Figure 13 As can be seen, a third heat dissipation layer 110 is disposed on the surface of chip 11 away from lead frame 12, and the first end of the second thermally conductive lead 15 is connected to chip 11 through the third heat dissipation layer 110. It should be noted that the third heat dissipation layer is not only suitable for… Figure 11 The chip packaging structure shown can also be applied to chip packaging structures provided in other embodiments of this application. By providing a third heat dissipation layer 110, the efficiency of heat conduction from the chip 11 to the second heat-conducting lead 15 can be further improved, thereby improving the overall heat dissipation efficiency.

[0057] In this embodiment, by providing a second pad 112 on the front side of the chip 11, and when the second pad 112 is electrically connected to the lead frame 12 via copper pillar bumps 19, the first thermally conductive lead 13 is connected to the back side of the chip 11, and the second thermally conductive lead 15 is connected to the lead frame 12, the heat dissipation efficiency of the flip-chip structure can be improved.

[0058] In one possible implementation, such as Figure 14 As shown, the lead frame 12 includes a first packaging substrate. A third pad 113 is provided on the front side of the chip 11. The portion of the front side of the chip 11 excluding the third pad 113 is bonded to the first dielectric layer 124 in the first packaging substrate. The chip 11 is electrically connected to the fan-out pad 125 in the first packaging substrate through the third pad 113. The packaging layer 14 covers at least a portion of the side and back sides of the chip 11, with the front and back sides of the chip 11 facing each other.

[0059] The first packaging substrate may consist of a first dielectric layer 124, fan-out pads 125, a second dielectric layer 126, and solder balls 127. The second dielectric layer 126 separates the fan-out pads 125, and the signals from the chip 11 are transmitted to the solder balls 127 through the fan-out pads 125, thereby enabling signal transmission to devices electrically connected to the solder balls 127. The packaging layer 14 may be formed using an epoxy resin injection molding process. Epoxy resin is injection molded onto the outside of the lead frame 12 and the chip 11, avoiding the bubble problem caused by the hardening of traditional potting compound at high temperatures, thus improving the hermeticity and heat dissipation performance of the package.

[0060] In this embodiment of the application, heat dissipation can be achieved through the first thermal conductive lead 13, the second thermal conductive lead 15 and the third heat dissipation layer 110.

[0061] This application provides an electronic device, which includes a chip packaging structure 1 as described in any of the foregoing embodiments. The electronic device may include one chip packaging structure 1 or multiple chip packaging structures 1.

[0062] It should be noted that the electronic device in this application embodiment is a specific application of the chip packaging structure 1 in various electronic products (such as smartphones and tablets) in the foregoing embodiments. For the specific chip packaging structure 1 in the electronic device, please refer to the description in the foregoing chip packaging structure embodiment, which will not be repeated here.

[0063] In this embodiment, by providing a first thermally conductive lead, the heat from the lead frame can be conducted to the outside of the encapsulation layer, thereby improving the heat dissipation efficiency of the chip. Furthermore, the first thermally conductive lead has a low cost.

[0064] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0065] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0067] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0068] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0069] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: Chip, lead frame, first thermal lead and packaging layer; The chip is electrically connected to the lead frame; At least a portion of the surface of the chip is covered by the encapsulation layer; At least a portion of the first thermally conductive lead is located within the encapsulation layer, and a first end of the first thermally conductive lead is connected to the lead frame, and a second end of the first thermally conductive lead is flush with or extends through the first heat dissipation surface of the encapsulation layer.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes: a second thermally conductive lead; At least a portion of the second thermal conductive lead is located within the encapsulation layer, and a first end of the second thermal conductive lead is connected to the chip, while a second end of the second thermal conductive lead is flush with or extends through the first heat dissipation surface.

3. The chip packaging structure according to claim 2, characterized in that, The first thermally conductive lead and the second thermally conductive lead are perpendicular to the first heat dissipation surface.

4. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure further includes: a first heat dissipation layer and a second heat dissipation layer; The first heat dissipation layer and the second heat dissipation layer are attached to the first heat dissipation surface; The first heat dissipation layer is connected to the second end of the first heat-conducting lead, and the second heat dissipation layer is connected to the second end of the second heat-conducting lead.

5. The chip packaging structure according to claim 2, characterized in that, The lead frame includes heat dissipation pins and electrical pins, and the electrical pins are provided with electrical pads. The first surface of the heat dissipation pin is attached to the back of the chip, the encapsulation layer covers the side of the chip and a portion of the front of the chip, and the encapsulation layer covers at least the side of the heat dissipation pin; The first surface of the electrical pad is attached to the electrical pin, and the encapsulation layer covers a portion of the side and second surface of the electrical pad, with the first surface and the second surface of the electrical pad facing each other. The chip has a first pad on its front side, and the first pad is electrically connected to the second surface of the electrical pad via a bonding wire. The front and back sides of the chip are opposite each other. The first end of the first thermally conductive lead is connected to the second surface of the electrical pad.

6. The chip packaging structure according to claim 2, characterized in that, The chip has a second pad on its front side, and the second pad is electrically connected to the lead frame via copper pillar bumps. The encapsulation layer covers at least a portion of the side and back of the chip, with the front and back sides of the chip facing each other.

7. The chip packaging structure according to claim 2, characterized in that, The lead frame includes a first packaging substrate, and a third pad is provided on the front side of the chip. The portion of the front side of the chip, excluding the third pad, is bonded to a first dielectric layer in the first packaging substrate. The chip is electrically connected to a fan-out pad in the first packaging substrate through the third pad. The encapsulation layer covers at least a portion of the side and back of the chip, with the front and back sides of the chip facing each other.

8. The chip packaging structure according to any one of claims 2-7, characterized in that, A third heat dissipation layer is provided on the surface of the chip away from the lead frame, and the first end of the second thermally conductive lead is connected to the chip through the third heat dissipation layer.

9. The chip packaging structure according to claim 8, characterized in that, The diameter range of the first thermally conductive lead and the second thermally conductive lead is [15um, 1mm].

10. The chip packaging structure according to claim 8, characterized in that, The first thermal lead and the second thermal lead comprise at least one of gold, copper and aluminum.

11. The chip packaging structure according to claim 5, characterized in that, The diameters of the first thermally conductive lead and the second thermally conductive lead are larger than the diameter of the bonding wire.

12. An electronic device, characterized in that, Includes the chip packaging structure as described in any one of claims 1-11.

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