Sensitive double-row pad metal connection layout design structure, method and chip

Abstract

The application provides a metal connection layout design structure, a method and a chip of a sensitive double-row PAD, and the structure comprises a circuit layout and a plurality of mirror image misaligned PAD units, the plurality of mirror image misaligned PAD units are arranged along the circumference of the circuit layout; the mirror image misaligned PAD unit comprises a first PAD, a second PAD, a first internal unit and a second internal unit, and the first PAD and the second PAD are arranged in a misaligned manner; the first internal unit comprises a first connection metal, a first metal connection structure and a first internal metal structure which are sequentially connected, the first metal connection structure is provided with a first metal through hole, the second internal unit comprises a second connection metal, a second metal connection structure and a second internal metal structure which are sequentially connected; the second metal connection structure is provided with a second metal through hole; the first PAD to the first internal metal structure and the second PAD to the second internal metal structure have the same metal path. The application maximally ensures the consistency of the signal PAD within an error range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout design technology, specifically to a metal interconnection layout design structure, method, and chip for sensitive dual-row PADs. Background Technology

[0002] In integrated circuit layout design, pads (PADs) serve as bridges between internal chip circuitry and external package pins, connecting power, ground, and signals. Because PADs are metallic, they inevitably exhibit parasitic effects such as resistance, capacitance, and inductance. For high-precision designs or sensitive differential signals, inconsistent parasitic capacitance caused by the metallic connection between the PAD and internal circuitry can severely impact chip performance.

[0003] When using a single-row PAD layout, the internal circuit connections in the same direction can be repeatedly replicated, allowing for better control of parasitic parameter inconsistencies within acceptable error ranges. However, when the chip size is complex and the number of signal PADs is large, the single-row PAD layout is limited by the PAD limit (the PAD limit is the chip area limited by the number of PADs), which significantly increases the chip width or height, leading to wasted area and increased cost. For example, see... Figure 1 Multiple third PADs 602 are arranged as a single row of PADs circumferentially along the chip layout 601, resulting in a significant waste of area between the single row of PADs and the chip layout 601. Furthermore, for internal analog modules with relatively small area but densely packed signal PADs, using a single-row PAD layout may force excessively long and inconsistent metal interconnects for the internal circuits connecting the PADs, thus affecting chip performance and internal layout. For example, see... Figure 2 A portion of the fourth PAD 702 extends beyond the relatively long width of the circuit layout 701, resulting in a longer metal path. Consequently, the parasitic parameters, such as parasitic capacitance and parasitic resistance, vary considerably. Therefore, the single-row PAD structure is not suitable for all scenarios.

[0004] For chips with a fixed area but a large number of signal pads, or certain internal analog modules, dual-row or multi-row pad structures are often used to solve the problem of external packaging wire bonding. However, in dual-row or multi-row structures, the pads in each row are not on the same height dimension. Conventional pad-to-internal metal connection structures often lead to inconsistent metal connection paths, resulting in significant differences in the parasitic parameters of high-precision matching signals or sensitive differential signals, ultimately adversely affecting chip performance. For example, see... Figure 3The fifth PAD 801 in the first row is connected to the fifth metal connection structure 802, and then to the fifth internal metal structure below the z-axis (i.e., the dotted line connecting the fifth PAD 801) through the fifth metal connection through hole 803 on the fifth metal connection structure 802. Similarly, the sixth PAD 901 in the second row is connected to the sixth metal connection structure 902, and then to the sixth internal metal structure below the z-axis (i.e., the dotted line connecting the sixth PAD 901) through the sixth metal connection through hole 903 on the sixth metal connection structure 902. Therefore, the fifth PAD 801 in the first row and the sixth PAD 901 in the second row are not connected by a single metal connection. Figure 3 Given that the chips are distributed vertically along the same height dimension (i.e., vertically along the y-axis), and assuming the chip layout is positioned above the fifth PAD801 in the first row (corresponding to the direction of the y-axis arrow), assuming... Figure 3 The first fifth PAD801 and the first second PAD901 along the x-axis arrow direction need to obtain signals from the same analog module in the chip layout. Due to the presence of the first PAD801 in the first row, the metal connection path of the first second PAD901 to the same analog module is farther than that of the first first PAD801. Since the metal connection path itself and the underlying silicon substrate and other adjacent metals naturally form a small capacitor, and the metal connection path itself has resistance, the change in current through the metal connection path will also generate parasitic inductance. It can be seen that there is a large difference in the parasitic parameters of the first first PAD801 and the first second PAD901. This leads to differences in the high-precision matching signal or sensitive differential signal acquired by the first PAD801 and the first second PAD901 respectively, ultimately destroying the quality of the high-precision signal and affecting the chip performance. Summary of the Invention

[0005] The primary objective of this invention is to provide a metal interconnection layout design structure for sensitive dual-row PADs, thereby resolving the problem of inconsistent parasitic parameters when connecting dual-row PADs to the internal circuitry of a chip.

[0006] A second objective of this invention is to provide a design method for implementing the aforementioned metal interconnection layout design structure for sensitive dual-row PADs.

[0007] A second objective of this invention is to provide a chip that utilizes the aforementioned metal interconnect layout design structure of sensitive dual-row PADs.

[0008] To achieve the aforementioned first objective, the present invention provides a metal interconnection layout design structure for sensitive dual-row PADs, comprising: a circuit layout and multiple mirrored misaligned pad units, the multiple mirrored misaligned pad units being arranged circumferentially along the circuit layout; each mirrored misaligned pad unit includes a first PAD, a second PAD, a first internal unit, and a second internal unit, the first PAD and the second PAD having the same width and height, the first PAD and the second PAD being vertically misaligned, the width of the first internal unit and the second internal unit being half the center-to-center distance between the two PADs in the same horizontal direction; the first internal unit includes a first connecting metal, a first metal connection structure, and a first internal metal structure; the first metal connection structure is provided with a first metal through-hole, the first metal through-hole connecting... The first internal metal structure is connected to the first PAD in the positive direction of height, and the first connecting metal is connected to the first metal connecting structure in the positive direction of height. The second internal unit includes a second connecting metal, a second metal connecting structure, and a second internal metal structure. The second metal connecting structure is provided with a second metal through hole, which connects to the second internal metal structure. The second PAD is connected to the second connecting metal in the opposite direction of height, and the second connecting metal is connected to the second metal connecting structure in the opposite direction of height. The first metal connecting structure and the second metal connecting structure are located at the center position in the height direction between the first PAD and the second PAD, and the first PAD to the first metal connecting structure and the second PAD to the second metal connecting structure have the same metal connection path.

[0009] As can be seen from the above solutions, this invention addresses the problem that signal PADs, which often require a dual-row PAD structure due to area cost constraints, typically use proximity-based metal connections, leading to inconsistencies in intrinsic parasitic capacitance and resistance between pairs of signal PADs. This inconsistency negatively impacts the performance of high-speed or sensitive differential PADs. The invention proposes a staggered mirrored metal connection layout design, ensuring that the connections between the two staggered PADs and the internal chip circuitry share the same metal layer and path, thereby guaranteeing consistent parasitic parameters. This invention can maximize the consistency of highly matched or high-precision differential data signal PADs within the acceptable error range. By employing a dual-row PAD layout, this invention optimizes the shape of internal analog modules or chip area while maintaining chip performance, and facilitates the use of controlled variable methods after chip production to reduce debugging iterations.

[0010] A further embodiment is that a first internal metal structure is used to connect a first ESD device disposed below the thickness direction of the first PAD; and a second internal metal structure is used to connect a second ESD device disposed below the thickness direction of the second PAD.

[0011] Therefore, this invention is applicable to dual-row PADs with DUP structure, where ESD devices and metal interconnects can be set in the corresponding internal units with appropriate dimensions, and have unique input and output connection points.

[0012] A further option is that the first metal connection structure and the second metal connection structure are multi-layer metal structures with the same number of layers.

[0013] This demonstrates that it can meet various design requirements.

[0014] A further approach is that the metal connection path from the first PAD to the first internal metal structure is the same as the metal connection path from the second PAD to the two internal metal structures.

[0015] Therefore, it can be seen that the accuracy of the differential signal received by the first PAD and the second PAD can be guaranteed.

[0016] To achieve the second objective mentioned above, this invention provides a design method for a metal interconnection layout structure of sensitive dual-row PADs, used to implement the aforementioned metal interconnection layout structure of sensitive dual-row PADs. The method includes the following steps: obtaining the material type and diameter of the package bonding wires, and determining the width and height of the dual-row PADs, the safety distance in height, and the center-to-center spacing in the horizontal direction based on the package bonding wire type and diameter; determining the dimensions of the first internal unit and the second internal unit based on the width and height of the dual-row PADs, the safety distance in height, and the center-to-center spacing in the horizontal direction; obtaining the metal structure of the first internal unit connected to the first PAD, and the metal structure of the second internal unit connected to the second PAD, to obtain mirrored misaligned pad units; obtaining splicing instructions, copying and splicing the mirrored misaligned pad units according to the splicing instructions, and setting them along the circumferential direction of the chip layout; obtaining connection instructions, and connecting the mirrored misaligned pad units to the chip layout according to the connection instructions.

[0017] To achieve the third objective mentioned above, the present invention provides a chip, wherein the chip is manufactured based on the aforementioned metal interconnection layout design structure of sensitive dual-row PADs. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the layout design of a single row of PADs in the existing technology.

[0019] Figure 2 This is a schematic diagram of the layout design of a single-row PAD in another application of existing technology.

[0020] Figure 3 This is a schematic diagram of a layout design in the existing technology that uses a dual-row PAD with a proximity connection method.

[0021] Figure 4This is a schematic diagram of the overall layout in the first embodiment of the metal connection layout design structure of the sensitive dual-row PAD of the present invention.

[0022] Figure 5 This is a partial schematic diagram of the layout in the first embodiment of the metal connection layout design structure of the sensitive dual-row PAD of the present invention.

[0023] Figure 6 This is a schematic diagram of the mirrored misaligned pad layout in the first embodiment of the metal connection layout design structure of the sensitive dual-row PAD of the present invention.

[0024] Figure 7 This is a schematic diagram of multiple mirrored misaligned pads spliced ​​together in the first embodiment of the metal connection layout design structure of the sensitive dual-row PAD of the present invention.

[0025] Figure 8 This is a schematic diagram of the mirrored misaligned pad layout in the second embodiment of the metal connection layout design structure of the sensitive dual-row PAD of the present invention.

[0026] Figure 9 This is a schematic diagram of multiple mirrored misaligned pads spliced ​​together in the second embodiment of the metal connection layout design structure of the sensitive dual-row PAD of the present invention.

[0027] Figure 10 This is a flowchart illustrating the design method of the metal connection layout design structure for the sensitive dual-row PAD of this invention.

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0029] The metal connection layout design structure of the sensitive dual-row PAD of the present invention, based on the dual-row PAD, adopts a unique metal input structure with mirror misalignment and symmetry, and an internal unique output structure to construct that the upper and lower dual-row PADs have consistent metal layers and paths, so as to have consistent parasitic parameters within the production error range.

[0030] The terms "first" and "second" in this invention are used to distinguish similar things and do not imply any order of precedence.

[0031] First embodiment of the metal interconnection layout design structure for sensitive dual-row PADs:

[0032] In this embodiment, see Figure 4 , Figure 5 , Figure 6 , Figure 4 , Figure 5 , Figure 6 The view is from above, with the horizontal direction as the x-axis, the height direction as the y-axis, and the thickness direction (perpendicular to the paper and inwards) as the z-axis.

[0033] See Figure 4 The metal interconnection layout design structure of the sensitive dual-row PADs in this embodiment includes a chip layout 200 and multiple mirrored misaligned pad units 100. The mirrored misaligned pad units 100 are arranged circumferentially along the chip layout 200 and connected to the chip layout 200. Each mirrored misaligned pad unit 100 includes a first PAD 11 and a second PAD 21 that are vertically misaligned. Thus, a second row of PADs and a first row of PADs are arranged sequentially outward along the chip layout 200. The second row of PADs includes multiple second PADs 21, and the first row of PADs includes multiple first PADs 11.

[0034] The first PAD11 and the second PAD21 are constructed with a top layer of metal, and both PAD11 and PAD21 have the same metal structure. Optionally, depending on the actual situation, the first PAD11 and the second PAD21 may also be constructed with two or three layers of metal as the top layer.

[0035] See Figure 5 More specifically, the chip layout 200 includes a first analog circuit layout 300, and a portion of the mirrored misaligned pad units 100 are set along and connected to the first analog circuit layout 300.

[0036] See also Figure 6 The mirrored misaligned pad unit 100 also includes a first internal unit 12 and a second internal unit 22. The width of the first internal unit 12 and the second internal unit 22 is half the center-to-center distance (pitch) between two PADs in the same horizontal direction. Specifically, for the first row of PADs composed of first PADs 11, the center-to-center distance between two adjacent first PADs 11 in the horizontal direction is a first set value; for the second row of PADs composed of second PADs 21, the center-to-center distance between two adjacent second PADs 21 in the horizontal direction is a second set value. The first set value and the second set value are equal. The width of the first internal unit 12 (i.e., the distance along the x-axis) is half of the first set value, and the width of the second internal unit 22 (i.e., the distance along the x-axis) is half of the second set value. The height of the first internal unit 12 (i.e., the distance along the y-axis) is the same as the height of the second internal unit 22 (i.e., the distance along the y-axis).

[0037] The first internal unit 12 includes a first connecting metal 121, a first metal connecting structure 122, and a first internal metal structure 123. (See attached image for details.) Figure 6 The dashed line corresponding to the first internal unit 12 is used because it is located at the bottom in terms of thickness. The first metal connection structure 122 is provided with a first metal through hole 1221, which connects to the first internal metal structure 123. The second internal metal structure 223 is shown in [reference]. Figure 6 The dashed line corresponding to the second internal unit 22 is used because it is located at the bottom in terms of thickness. The first PAD 11 is connected to the first connecting metal 121 in the positive direction of height (i.e., the direction of the arrow on the y-axis), and the first connecting metal 121 is connected to the first metal connecting structure 122 in the positive direction of height. Thus, in the first internal unit 12, the first PAD 11 can be connected to the first internal metal structure 123 in sequence through the first connecting metal 121, the first metal connecting structure 122, and the first metal through-hole 1221. The first internal metal structure 123 is connected to the chip layout 200 located above the first internal unit 12 (along the direction of the arrow on the y-axis), thereby realizing the connection between the first PAD 11 and the chip layout 200.

[0038] The second internal unit 22 includes a second connecting metal 221, a second metal connecting structure 222, and a second internal metal structure 223. The second metal connecting structure 222 has a second metal through-hole 2221, which connects to the second internal metal structure. The second PAD 21 is connected to the second connecting metal 221 in the opposite direction of its height (i.e., opposite to the y-axis arrow), and the second connecting metal 221 is connected to the second metal connecting structure 222 in the opposite direction of its height. Thus, in the second internal unit 22, the second PAD 21 can sequentially connect to the second internal metal structure via the second connecting metal 221, the second metal connecting structure 222, and the second metal through-hole 2221. The second internal metal structure connects to the chip layout 200 located above the second internal unit 22 (along the y-axis arrow direction), thereby achieving the connection between the second PAD 21 and the chip layout 200.

[0039] The first metal connection structure 122 and the second metal connection structure 222 are located at the center of the height direction between the first PAD 11 and the second PAD 21. Specifically, see Figure 6 A first straight line parallel to the y-axis is drawn through the center of the first PAD11. The center of the second PAD21 is projected onto the first point on the first straight line, and a first line segment is obtained by connecting the center of the first PAD11. A second straight line parallel to the x-axis is drawn through the midpoint of the first line segment. The centers of the first metal connection structure 122 and the second metal connection structure 222 are both on the second straight line. The aforementioned "centers" are all obtained by connecting the intersection of two diagonals. Furthermore, see [further details omitted]. Figure 6 The first metal connection structure 122 is located at the left boundary of the first internal unit 12 (see...). Figure 6 The first vertical distance from the left side of the first internal unit 12 (parallel to the y-axis) to the right boundary of the first internal unit 12 (see...) Figure 6 The second vertical distance from the right side of the first internal unit 12 (parallel to the y-axis direction) is equal to that of the second internal unit 22. Similarly, the second metal connection structure 222 is at a distance from the left boundary of the second internal unit 22 (see...). Figure 6 The third vertical distance from the left side of the second inner unit 22 (parallel to the y-axis) and the distance from the right boundary of the second inner unit 22 (see...) Figure 6 The fourth vertical distance (parallel to the y-axis direction) of the second internal unit 22 is equal to the first vertical distance, the second vertical distance, the third vertical distance, and the fourth vertical distance are equal. The fifth vertical distance from the lower edge of the first metal connection structure 122 along the y-axis arrow direction to the first PAD 11 is equal to the sixth vertical distance from the upper edge of the second metal connection mechanism 222 along the y-axis arrow direction to the second PAD 21.

[0040] The first connecting metal 121 and the second connecting metal 221 are positioned to ensure that the first metal connecting structure 122 and the second metal connecting structure 222 are centered in the height direction between the first PAD 11 and the second PAD 21. Preferably, the first connecting metal 121 and the second connecting metal 221 have the same width and height. Furthermore, the first connecting metal 121 and the second connecting metal 221 need to maintain a certain physical distance to prevent short circuits.

[0041] In terms of the metal layer arrangement in the thickness direction, the first PAD 11, the first connecting metal 121, and the first metal connecting structure 122 are disposed on the first top layer metal, and the second PAD 21, the second connecting metal 221, and the second metal connecting structure 222 are disposed on the second top layer metal. The second top layer metal is physically isolated from the first top layer metal. Optionally, the first metal connecting structure 122 and the second metal connecting structure 222 can be the same multi-layer parallel structure. While satisfying electrical rules, at least one layer of the first metal connecting structure 122 is the same as the first top layer metal, and at least one layer of the second metal connecting structure 222 is the same as the second top layer metal. The first internal metal structure 123 is disposed on the first lower metal layer of the first top layer metal and is connected to the chip layout 200. The second internal metal structure 223 is disposed on the second lower metal layer of the second top layer metal and is connected to the chip layout 200. The first lower metal layer and the second lower metal layer have the same layer structure but are physically isolated. The first metal connection structure 122 serves as the sole signal input / output point for the first PAD 11, and the second metal connection structure 222 serves as the sole signal input / output point for the second PAD 21. The first PAD 11 and the second PAD 21 have identical metal structures; the first connecting metal 121 and the second connecting metal 221 have identical metal structures; the first metal connection structure 122 and the second metal connection structure 222 have identical metal structures; and the first internal metal structure 123 and the second internal metal structure 223 have identical metal structures. Therefore, the connection path from the first PAD 11 to the first internal metal structure 123 and from the second PAD 21 to the second internal metal structure 223 are identical.

[0042] See Figure 7 Multiple identical mirror-image misaligned pad units 100 are spliced ​​together and set along the chip layout 200, finally resulting in... Figure 4 The effect.

[0043] Second embodiment of the metal interconnection layout design structure for sensitive dual-row PADs:

[0044] The difference between this embodiment and the first embodiment of the metal connection layout design structure for sensitive dual-row PADs described above is that the first embodiment is not used for DUP (Device Under Pad) structures, while this embodiment is used for DUP structures.

[0045] See Figure 8 In this embodiment, the first internal metal structure 123 is also disposed below the first PAD 11 (see Figure 8 (The dashed line in the first PAD 11) allows this portion to be used to connect the first ESD device positioned below the first PAD in the thickness direction. A second internal metal structure 223 is also positioned below the second PAD 21 (see...). Figure 8 (The dashed line of the second PAD21 in the middle), so that this part is used to connect the second ESD device located below the thickness direction of the second PAD.

[0046] See Figure 9 In this embodiment, the mirrored misaligned pad unit 100 is arranged along the circumference of the second analog circuit layout 400.

[0047] Example of a metal interconnection layout design method for sensitive dual-row PADs:

[0048] This embodiment can be implemented by executing a computer program to obtain the layout design structure of the first embodiment of the metal interconnection layout design structure of the above-mentioned sensitive dual-row PAD, specifically including the following steps:

[0049] S1: Obtain the material type and wire diameter of the packaging bonding wire, and determine the width and height of the dual-row PADs, the safety distance in height, and the center-to-center spacing in the horizontal direction based on the packaging bonding wire type and wire diameter.

[0050] Based on the type and diameter of the packaging bonding wires, as well as the setting rules given by the manufacturer, the width and height of the dual-row PADs corresponding to the chip that can be manufactured safely and reliably, the safe distance in height, and the center-to-center spacing in the horizontal direction can be determined.

[0051] S2: Determine the dimensions of the first and second internal units based on the width and height of the dual-row PADs, the safety distance in height, and the center-to-center spacing in the horizontal direction.

[0052] The widths of the first and second inner units are determined based on their horizontal center-to-center spacing. The width of the first and second inner units is the same, being half the center-to-center spacing. The heights of the first and second inner units are the same, and greater than the height occupied between the first and second pads. For example, refer to... Figure 6 The highest point of the second PAD on the y-axis (i.e., the line segment at the top of the second PAD in the figure) is projected onto a straight line passing through the center of the first PAD and parallel to the y-axis to obtain a second point. This second point is connected to the lowest point of the first PAD on the y-axis (i.e., the line segment at the bottom of the first PAD in the figure) through the center of the first PAD to obtain a second line segment. The length of the second line segment is the height occupied between the first PAD and the second PAD.

[0053] S3: Obtain the metal structure of the first internal unit connected to the first PAD and the metal structure of the second internal unit connected to the second PAD to obtain the mirrored misaligned pad unit.

[0054] Specifically, the positions of the first connecting metal, the first metal connecting structure, the first internal metal structure, the second connecting metal, the second metal connecting structure, and the second internal metal structure are determined based on the positions of the first PAD and the second PAD.

[0055] S4: Obtain the splicing instruction, copy the splicing mirror misaligned pad unit according to the splicing instruction, and set it along the circumference of the chip layout.

[0056] For non-sensitive signal PADs, the existing proximity connection structure can also be used, that is, proximity connection pad units.

[0057] S5: Obtain connection instructions and connect the mirrored misaligned pad units to the chip layout according to the connection instructions.

[0058] Chip Example:

[0059] The chip in this embodiment is manufactured based on the layout design structure of the first or second embodiment of the above-described sensitive dual-row PAD metal interconnection layout design structure.

[0060] In summary, this invention proposes a staggered mirrored metal connection layout design structure for chips using a dual-row PAD layout. Based on the dual-row PADs, it employs a unique metal input structure with mirrored staggered symmetry and a unique internal output structure to construct a consistent metal layer and path for the upper and lower dual-row PADs. This ensures consistent parasitic resistance and capacitance parameters within the production error range, thereby guaranteeing performance stability and reducing debugging and iteration after chip production.

[0061] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A metal interconnection layout design structure for sensitive dual-row PADs, characterized in that, include: A circuit layout and multiple mirrored misaligned pad units, wherein the multiple mirrored misaligned pad units are arranged circumferentially along the circuit layout; The mirrored misaligned pad unit includes a first PAD, a second PAD, a first internal unit, and a second internal unit. The first PAD and the second PAD have the same width and height, and the first PAD and the second PAD are staggered vertically. The width of the first internal unit and the second internal unit is half the center-to-center distance between the two PADs in the same horizontal direction. The first internal unit includes a first connecting metal, a first metal connecting structure, and a first internal metal structure; the first metal connecting structure is provided with a first metal through hole, and the first metal through hole is connected to the first internal metal structure; the first PAD is connected to the first connecting metal in the positive direction of height, and the first connecting metal is connected to the first metal connecting structure in the positive direction of height; The second internal unit includes a second connecting metal, a second metal connecting structure, and a second internal metal structure; the second metal connecting structure is provided with a second metal through hole, and the second metal through hole is connected to the second internal metal structure; the second PAD is connected to the second connecting metal in the opposite direction of its height, and the second connecting metal is connected to the second metal connecting structure in the opposite direction of its height; The first metal connection structure and the second metal connection structure are located at the center of the height direction between the first PAD and the second PAD, and the first PAD to the first metal connection structure and the second PAD to the second metal connection structure have the same metal connection path.

2. The metal interconnection layout design structure of the sensitive dual-row PAD as described in claim 1, characterized in that: The first internal metal structure is used to connect the first ESD device disposed below the thickness direction of the first PAD. The second internal metal structure is used to connect a second ESD device disposed below the thickness direction of the second PAD.

3. The metal interconnection layout design structure of the sensitive dual-row PAD as described in claim 1, characterized in that: It includes multiple proximity connection pad units, which are arranged circumferentially along the circuit layout along with the mirrored misaligned pad units.

4. The metal interconnection layout design structure of the sensitive dual-row PAD as described in claim 1, characterized in that: The first metal connection structure and the second metal connection structure are multi-layer metal structures with the same number of layers.

5. The metal interconnection layout design structure of the sensitive dual-row PAD as described in claim 1, characterized in that: The metal connection path from the first PAD to the first internal metal structure is the same as the metal connection path from the second PAD to the second internal metal structure.

6. A design method for a metal interconnection layout design structure of a sensitive dual-row PAD, used to implement the metal interconnection layout design structure of the sensitive dual-row PAD as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Obtain the material type and wire diameter of the packaging bonding wire, and determine the width and height of the dual-row PADs, the safety distance in height, and the center-to-center spacing in the horizontal direction based on the packaging bonding wire type and wire diameter; The dimensions of the first and second internal units are determined based on the width and height of the dual-row PADs, the safety distance in height, and the center-to-center spacing in the horizontal direction. Obtain the metal structure of the first internal unit connected to the first PAD, and the metal structure of the second internal unit connected to the second PAD, to obtain the mirrored misaligned pad unit. Obtain the splicing instructions, copy the splicing mirror misaligned pad units according to the splicing instructions, and set them along the circumference of the chip layout; Obtain connection instructions and connect the mirrored misaligned pad units to the chip layout according to the connection instructions.

7. A chip, characterized in that: The chip is manufactured based on the metal interconnection layout design structure of the sensitive dual-row PAD as described in any one of claims 1 to 5.

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