Device structure for causing layout-related threshold voltage offset

Abstract

A device layout for an integrated circuit device that includes a threshold voltage offset caused by placement of an alternative work function metal adjacent an active gate. The device layout includes a single epitaxy for active regions in the device with common source / drain regions between rows of active regions in the layout. Metal gate sections over one or more rows of active regions may be replaced with metals of different work functions in non-active regions of the layout. Different work function metals in the non-active region will cause threshold voltage offsets in adjacent (adjacent) active transistors of the device layout.

Description

Technical Field

[0001] The embodiments described herein relate to transistor structures and layouts for semiconductor devices. More specifically, the embodiments described herein relate to transistor structures and layouts including transistors that cause a threshold voltage shift in adjacent transistors. Background Technology

[0002] In advanced metal-gate CMOS technology, work function metals are commonly used as gate materials to adjust the threshold voltage of NMOS or PMOS transistors. For example, selecting a work function metal for the gate material can help set the appropriate threshold voltage for an NMOS or PMOS transistor. However, NMOS and PMOS transistors have very different work function metals. Therefore, in CMOS logic circuits or devices with physically connected NMOS and PMOS gates, the merging / bonding of the NMOS and PMOS work function gate materials can lead to an additional threshold voltage shift in one or both of the NMOS and PMOS gates. This threshold voltage shift caused by the physical connection of different work function metals is known as the metal boundary effect. Examples of devices where the metal boundary effect may occur include, but are not limited to, inverters, NAND devices, and NOR devices.

[0003] In some cases, an induced threshold voltage offset is desired due to metallic boundary effects. Current methods for adding the induced threshold voltage offset involve adding dummy NMOS / PMOS devices next to active (e.g., device under test) PMOS / NMOS devices. For example, dummy NMOS devices can be placed next to active PMOS devices to induce a threshold voltage offset in the PMOS devices. However, due to current process constraints, placing dummy devices requires a minimum number of dummy NMOS / PMOS rows of at least two. Having at least two dummy rows results in a threshold voltage offset at the expense of circuitry or device area. Therefore, there is a current need to generate the desired threshold voltage offset without sacrificing circuitry or device area growth. Attached Figure Description

[0004] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood when taken in conjunction with the accompanying drawings, by referring to the following detailed description of the currently preferred, but only exemplary, embodiments according to which the present disclosure is described: Figure 1 A top-side plan view representation of an example device layout according to some embodiments is depicted, wherein the metal for dummy NMOS transistors is adjacent to the metal for active PMOS transistors.

[0005] Figure 2A top-side plan view depicting a prospective device having a row of NMOS metal segments adjacent to an active PMOS metal segment according to some embodiments, wherein both metal segments are above the PMOS active region.

[0006] Figure 3 A top-side plan view depicting a proposed device layout according to some implementations is provided, wherein there are cutouts between NMOS metal sections and a row of active PMOS metal sections to suppress threshold voltage shift in the active transistors of that row.

[0007] Figure 4 A top-side plan view depicts a proposed device layout with two rows of NMOS metal sections having adjacent active PMOS metal sections according to some embodiments, wherein both types of metal sections are above the PMOS active region.

[0008] Figure 5 A top-side plan view depicting a proposed device layout with three rows of NMOS metal sections adjacent to the active PMOS metal sections according to some embodiments, wherein both types of metal sections are above the PMOS active region.

[0009] Figure 6 A top-side plan view depicting a proposed device layout according to some embodiments is provided, wherein NMOS metal segments alternate between rows along the x-direction, and adjacent active PMOS metal segments have two types of metal segments above the PMOS active region.

[0010] Figure 7 A top-side plan view depicting a proposed device layout according to some embodiments is shown, which has an NMOS metal segment and an adjacent active PMOS metal segment in two columns along the row in the x-direction, wherein both types of metal segments are above the PMOS active region.

[0011] Figure 8 This is a block diagram of one implementation of the example system.

[0012] While the embodiments disclosed herein are susceptible to various modifications and alternatives, specific embodiments of the invention are illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure of this application as defined by the appended claims. Detailed Implementation

[0013] This disclosure relates to specific implementations of transistor devices having active regions of a first transistor type, wherein the active transistor segments in the device have metal gates having metal having a work function corresponding to the first transistor type, and wherein the non-active (e.g., dummy) transistor segments in the device have metal gates having metal having metal having a work function corresponding to a second transistor type complementary to the first transistor type. The metal gates are implemented in various devices including CMOS (Complementary Metal-Oxide-Semiconductor) technology. The work function of the metal can be selected to set appropriate threshold voltages for NMOS (n-channel metal-oxide-semiconductor) and PMOS (p-channel metal-oxide-semiconductor) transistors in a particular CMOS device.

[0014] Typically, NMOS and PMOS transistors have very different work function metals for their gates. In some CMOS devices or logic circuits, NMOS and PMOS transistors have connected gates. For example, CMOS devices such as inverters, NAND, and NOR may have connected NMOS and PMOS metal gates. When the gates are connected, there is a merging site (e.g., a junction) between the metals of the NMOS and PMOS gates. Due to the difference in chemical composition between these metals and the exchange or movement of certain atoms or ions at the merging site, one or both of the NMOS and PMOS transistors may have an additional threshold voltage (Vt) offset. In various instances, the cause of the threshold voltage offset is referred to as the metal boundary effect.

[0015] In some implementations of circuit or device designs, it is desirable to add an additional threshold voltage offset caused by metal boundary effects to produce (e.g., induce) a desired threshold voltage characteristic in the device. The current way to induce the additional threshold voltage offset is to include metal for a dummy NMOS (or alternatively, PMOS) device next to the metal used for a complementary active PMOS (or NMOS) device (e.g., a device under test (DUT)). Figure 1 A top-side plan view representation of an example device layout according to some embodiments is depicted, wherein metal for dummy NMOS transistors is adjacent to metal for active PMOS transistors. In the illustrated embodiment, device layout 100 includes three gate structures 110A to 110C orthogonally aligned with six active regions 120A to 120F.

[0016] In various implementations, active region rows 120A to 120F include active regions (e.g., epitaxial regions including channel and source / drain regions) for a first transistor type (e.g., PMOS or p-type active region) or a second transistor type (e.g., NMOS or n-type active region). In example implementations, active region rows 120A / B / E / F are rows having first transistor type active regions 130A / B / E / F, while active region rows 120C / D are rows having second transistor type active regions 135C / D. For example, the first transistor type active regions 130A / B / E / F may be PMOS active regions, while the second transistor type active regions 135C / D may be NMOS active regions, such as... Figure 1 As indicated. Due to the different types of active regions, active region rows 120A / B / E / F have source / drain regions that are separate from active region rows 120C / D.

[0017] In the case where the active region rows 120A to 120F have different transistor types, the gate structure 110 can be a metal line having metal segments along its length corresponding to different work functions (WF) of the active regions of different transistor types. For example, in the illustrated embodiment, the metal lines 110A / B / C include a first metal segment 140A / B / C of a first WF metal type and a second metal segment 150A / B / C of a second WF metal type. The first metal segment 140A / B / C can be a metal segment having a WF corresponding to a PMOS transistor (e.g., a PMOS WF metal segment) because the first metal segment intersects with the first transistor type active region 130A / B / E / F in the active region rows 120A / B / E / F. Correspondingly, the second metal segment 150A / B / C can be a metal segment with a WF corresponding to an NMOS transistor (e.g., an NMOS WF metal segment), because the second metal segment intersects with the second transistor type active region 135C / D in the active region row 120C / D.

[0018] In the illustrated embodiment, device layout 100 is used for an active PMOS transistor device. Therefore, the first transistor type active regions 130A / B / E / F in the active region rows 120A / B / E / F form active (e.g., device under test (DUT)) transistors for device layout 100, while the second transistor type active regions 135C / D in the active region rows 120C / D are “non-active” or “dummy” transistors in the device layout. Placing a dummy NMOS transistor near an active PMOS transistor (e.g., adjacent to an active PMOS transistor) will produce a threshold voltage shift in the active PMOS transistor. The selection of the WF (weighted field) of a metal segment (e.g., a second metal segment 150) in the dummy NMOS transistor can produce a desired threshold voltage shift in the adjacent active PMOS transistor. It should be noted that alternative device layouts with active NMOS transistors and dummy PMOS transistors and corresponding WF metal segments are also conceivable.

[0019] However, placing dummy NMOS transistors with NMOS WF metal sections adjacent to (or between) active PMOS transistors with PMOS WF metal sections does indeed come at the cost of increased circuit or device area usage. For example, due to process constraints in current circuit / device designs, the minimum number of rows for dummy NMOS (or PMOS) transistors is at least two (2). Two rows may be the minimum number of rows because the epitaxial layer of the second transistor type active region 135C / D in active region row 120C / D differs from the epitaxial layer of the first transistor type active region 130A / B / E / F in active region row 120A / B / E / F, which typically requires two rows to distinguish between the different epitaxial layers. Therefore, as Figure 1 As can be seen, device layout 100 includes two rows of dummy NMOS transistors to induce a work function threshold voltage offset in the PMOS transistors above / below the two rows of dummy transistors.

[0020] In order to overcome current design (such as Figure 1 The area cost of the device layout 100 shown herein describes various contemplated device layout (e.g., circuit) designs that utilize the metal boundary effect by implementing only a single row for inserting dummy MOS “devices” into the layout. In various embodiments, single-row dummy MOS devices are formed by placing metal segments with complementary WF functional metals over the same epitaxial active regions (e.g., the same transistor-type active regions and common source / drain regions) as the active devices in the device layout. Device layouts with these single-row dummy MOS devices offer more efficient device area utilization while providing the same benefits as current designs in causing work function threshold voltage shift.

[0021] Some embodiments disclosed herein have four wide elements: 1) a plurality of active regions of a first type of transistor, the plurality of active regions of the first type of transistor being aligned in a row along a first direction in a horizontal dimension; 2) a gate structure formed above a substrate and aligned in a second direction orthogonal to the first direction in a horizontal dimension; 3) a first segment of a first metal gate material having a first work function above the first active region in the first row of the first type of transistor; and 4) a second segment of a second metal gate material having a second work function above the second active region in the second row of the first type of transistor. In various embodiments, the second metal gate material is adjacent to the first metal gate material (e.g., adjacent to the first metal gate material), such that the second metal gate material causes a threshold voltage shift in the active transistor associated with the first metal gate material based on the difference in chemical composition between these metals and the exchange or movement of certain atoms or ions at the merging sites. In some embodiments, the source / drain in the second active region is electrically floating, such that the second active region is an active transistor or a dummy transistor. In some embodiments, a third segment of a first metal gate material having a first work function is located above a third active region in a third row of a first type of transistor, wherein a second row is located between the first and third rows. In some embodiments, a cut (e.g., a metal cut or gate cut) may be made between the first metal gate material in the first segment and the second metal gate material in the third segment to suppress threshold voltage shift in the active transistor associated with the first metal gate material above the third active region.

[0022] Various illustrations of embodiments having these wide elements are now described in this disclosure. It should be noted that the exemplary embodiments of this disclosure depict design layouts of devices having PMOS active regions and corresponding PMOS active transistors, wherein the NMOS work function metal causes a threshold voltage shift in some of the PMOS active transistors. These design layouts provide basic building blocks upon which many different types of devices can be constructed. Furthermore, embodiments can be conceived based on the depicted design layouts having NMOS active regions and corresponding NMOS active transistors, wherein the PMOS work function metal causes a threshold voltage shift in some of the NMOS active transistors.

[0023] Figure 2A top-side plan view representation of a prospective device having a row of NMOS metal segments adjacent to active PMOS metal segments according to some embodiments is shown, wherein both metal segments are above the PMOS active regions. In an illustrated embodiment, device layout 200 includes three gate structures 210A to 210C oriented in a first direction in the horizontal dimension and six rows of active regions 220A to 220F oriented in a second direction in the horizontal dimension, wherein the second direction is orthogonal to the first direction. In various embodiments, the rows of active regions 220A to 220F include first transistor type active regions 230A to 230F, wherein each active region is of the same first transistor type (e.g., a PMOS transistor). For example, the first transistor type active regions 230A to 230F include a channel region and a source / drain region (e.g., an epitaxial region) for a PMOS transistor. When all rows of active regions 220A to 220F are of the same type of transistor, they may have a common type of source / drain region in rows using the same epitaxial region.

[0024] In some embodiments, gate structures 210A to 210C each have first metal segments 240A to 240C and second metal segments 250A to 250C. The first metal segments 240A to 240C may be metal segments having work functions corresponding to the transistor types of the first transistor type active regions 230A to 230F. For example, the first metal segments 240A to 240C may be metal segments having work functions corresponding to the PMOS transistors used for the first transistor type active regions 230A to 230F.

[0025] In some embodiments, a "dummy" (e.g., non-active) device is formed in device layout 200 by placing second metal segments 250A to 250C along gate structures 210A to 210C. The second metal segments 250A to 250C may be metal segments having a work function corresponding to a transistor type complementary to the transistor type of the first transistor type active regions 230A to 230F. For example, in an illustrated embodiment, when the first transistor type active regions 230A to 230F are epitaxial regions of a PMOS transistor, the second metal segments 250A to 250C may be metal segments having a work function corresponding to an NMOS transistor. A dummy device 260 is formed in device layout 200 by placing the second metal segments 250A to 250C along gate structures 210A to 210C.

[0026] like Figure 2As shown, the dummy device 260 includes a second metal segment 250A to 250C above a first transistor-type active region 230C (dashed line) in the active region row 220C. Having a second metal segment 250A to 250C above the first transistor-type active region 230C allows the dummy device 260 to be formed in the device layout 200 while maintaining the same epitaxy (e.g., having the same type of source / drain region) between the active region 230C in the device layout and other first transistor-type active regions 230A / B / D / E / F (e.g., active regions as part of an active transistor (DUT)). For example, the active region 230C may have the same type of source / drain region and share a common well with other active regions 230A / B / D / E / F. Therefore, the dummy device 260 is formed in the device layout 200 without creating any additional rows with different epitaxy (e.g., no NMOS epitaxy is required in addition to the PMOS epitaxy in the device layout).

[0027] In some implementations, second metal segments 250A through 250C are selected for the dummy device 260 such that the dummy device has a sufficiently high threshold voltage, rendering it virtually non-functional in device layout 200. With a sufficiently high threshold voltage, the source / drain regions in the first transistor type active region 230C can remain electrically floating (e.g., the source / drain regions are disconnected from any power supply or power ground associated with device layout 200). Having such electrically floating source / drain regions in device layout 200 allows a single mask process to be used for all first-type transistor (e.g., PMOS transistor) structures until processing is implemented to introduce the second metal segments 250A through 250C. This process, using the same epitaxial layer across the active region, avoids the need for additional mask processing associated with different epitaxial layers.

[0028] Several implementations are conceivable in which the source / drain regions in the first transistor type active region 230C are connected to other functional components (e.g., power / ground connections or other devices) in device layout 200. For example, in an implementation with minimal side effects or disruption to other transistors in device layout 200 (such as active transistors in active region row 220B or active region row 220D), the source / drain regions in the first transistor type active region 230C may be connected to other source / drain regions of active transistors.

[0029] In some implementations, such as Figure 2As shown, the dummy device 260 includes second metal segments 250A to 250C, which have work functions complementary (e.g., opposite) to those of the first metal segments 240A to 240C. Therefore, when the second metal segments 250A to 250C are adjacent (e.g., close to) and in contact with the first metal segments 240A to 240C, the second metal segments cause a threshold voltage shift in adjacent active transistors associated with the first metal segments (e.g., transistors associated with first transistor-type active regions 230B and 230D located above and below the dummy device 260). It should be noted that some threshold voltage shift may also be caused in active transistors at greater distances. For example, the active regions 230A, 230E, and 230F of the first transistor type may exhibit some threshold voltage shifts based on the difference in chemical composition between the first and second metals and the amount of atomic or ion exchange or movement at the merging positions between the second metal segments 250A to 250C and the first metal segments 240A to 240C.

[0030] In various implementations, the work function of the second metal segments 250A to 250C is selected to provide the desired threshold voltage offset in the active transistors of device layout 200. Therefore, device layout 200 allows a single row (e.g., a row of dummy devices 260) to provide the desired threshold voltage offset in the active portion of the device. Using only a single row of dummy / active devices to induce the threshold voltage offset saves device area usage across the entire vertical height of device layout 200 (e.g., along the direction of gate structure 210).

[0031] In some implementations, designs for device layout are conceivable where it is desirable to have some active transistors adjacent to the dummy device 260 without threshold voltage offset. In such implementations, cutouts or other gaps may be formed in the metal lines of the gate structure 210 to prevent atomic or ion exchange or movement between the second metal segment 250 in the dummy device 260 and the first metal segment associated with the active transistors for which no threshold voltage offset is desired.

[0032] Figure 3 A top-side plan view depicting a proposed device layout according to some embodiments is provided, wherein a cutout is provided between an NMOS metal segment and a row of active PMOS metal segments to suppress threshold voltage shift in the active transistors of that row. In an illustrated embodiment, by placing a cutout 310 in the gate structures 210A / B / C below the dummy device 260 and between the first metal segments 240A / B / C and the second metal segments 250A / B / C, (from...) Figure 2Device layout 200 is modified to device layout 300. For example, cutout 310 can be formed by forming a trench in gate structure 210A / B / C along a cut line below dummy device 260. Cutout 310 suppresses atomic or ion exchange or movement between first metal segment 240A / B / C and second metal segment 250A / B / C. By suppressing atomic or ion exchange or movement between these metal segments, there is no threshold voltage offset in active transistor 320 (or other active transistors along active region row 220D) caused by the presence of gate structure 210A / B / C in dummy device 260. In some embodiments, cutout 310 may be located at the boundary of a cell or a group of devices / transistors in device layout 300.

[0033] In some implementations, the second row of NMOS metal segments may be placed in a device layout with active PMOS transistors to increase the number of active transistors with threshold voltage offset in the device layout. Figure 4 A top-side plan view depicting a proposed device layout with two rows of NMOS metal segments having adjacent active PMOS metal segments according to some embodiments, wherein both types of metal segments are above the PMOS active region. In the illustrated embodiment, by placing a second set of second metal segments 250A' / B' / C' instead of PMOS metal segments (e.g., first metal segment 240) in the active region row 220F, (from...) Figure 2 The device layout 200 is modified to device layout 400. Therefore, device layout 400 includes two dummy devices - dummy device 260A in active area row 220C and dummy device 260B in active area row 220F.

[0034] The presence of a second metal segment 250 and a dummy device 260 in the two-row device layout 400 increases the number of active transistors with threshold voltage offsets in the device layout. For example, in the illustrated embodiment, dummy device 260A causes a threshold voltage offset in the active transistors of the first transistor type active regions 230B and 230D, while dummy device 260B causes a threshold voltage offset in the active transistors of the first transistor type active region 230E. It should be noted that dummy device 260B will also cause a threshold voltage offset in the active transistors of another first transistor type active region below the active region row 220F, unless the dummy device is positioned at the boundary of the device layout 400.

[0035] For the implementation scheme of device layout 400, the area cost in device layout is similar to Figure 1The area cost of device layout 100 is shown. For example, both device layouts have an area cost of two rows for the loss of active transistors in the device layout. However, device layout 400 may have other advantages over device layout 100. For example, as discussed above, device layout 400 maintains a single type of epitaxial process for implementing all active region rows across the device layout. In addition, device layout 400 can enable twice the number of active transistors with the same threshold voltage effect (e.g., threshold voltage offset) as device layout 100 and have the same area cost.

[0036] Figure 5 A top-side plan view depicting a proposed device layout with three rows of NMOS metal segments adjacent to active PMOS metal segments according to some embodiments is shown, wherein both types of metal segments are above the PMOS active region. In the illustrated embodiment, by placing the second set of second metal segments 250A' / B' / C' in the active region row 220A and placing the third set of second metal segments 250A'' / B'' / C'' in the active region row 220E instead of PMOS metal segments (e.g., the first metal segment 240), the (from) Figure 2 The device layout 200 is modified to device layout 500. Therefore, device layout 500 includes three dummy devices - dummy device 260A in active area row 220C, dummy device 260B in active area row 220A, and dummy device 260C in active area row 220E.

[0037] like Figure 5 As shown, dummy rows (e.g., active region rows 220A / 220C / 220E) alternate with active rows (e.g., active region rows 220B / D / F) such that each active row has one dummy row above and another dummy row below it in the illustration. With each active row having dummy rows directly above and below it, the threshold voltage offset in the active row is greater than in the case where the active row has only one dummy row above or below it.

[0038] Therefore, device layouts can be designed using second metal segments (e.g., metal segments with a work function corresponding to a transistor type complementary to the active transistor) based on using a single row of second metal segments to generate the desired threshold voltage offset at a smaller area cost, or using two (or more) rows of second metal segments to improve other operating characteristics of the device and the desired threshold voltage offset. Designs for large device layouts are also conceivable, where combinations of single and two (or more) rows of second metal segments are placed in different regions of the device layout to gain the advantages of both variations.

[0039] Implementations that cause different effects on the threshold voltage shift are also conceivable. For example, in some implementations, the second metal segment may include metal that increases the threshold voltage in a neighboring active transistor. In other implementations, the second metal segment may include metal that decreases the threshold voltage in a neighboring active transistor. Still other implementations may include device layout designs in which some segments increase the threshold voltage in a neighboring active transistor, and some segments decrease the threshold voltage in a neighboring active transistor.

[0040] Additional embodiments are conceivable in which the second metal segment 250 (e.g., a metal segment having a work function corresponding to a transistor type complementary to the active transistor) is horizontally constrained in the device layout (e.g., in the horizontal direction or x-direction of the device layout as depicted in the figures). The position of the second metal segment in the x-direction can also be varied between rows of active regions to provide a variation in the threshold voltage offset of the active transistor in the y-direction. Figure 6 and Figure 7 Examples of some possible variations for placing second metal segments in the x-direction (along the column associated with gate structure 210) and y-direction (along the row associated with active region row 220) to generate selective threshold voltage offsets in adjacent active transistors based on columns, rows, or combinations thereof are depicted.

[0041] Figure 6 A top-side plan view representation of a anticipated device layout according to some embodiments is depicted, wherein NMOS metal segments alternate between rows along the x-direction, and adjacent active PMOS metal segments have two types of metal segments above the PMOS active region. In the illustrated embodiment, device layout 600 includes a second metal segment 650A along gate structure 210A and in active region row 220C, a second metal segment 650B along gate structure 210B and in active region row 220B, and a second metal segment 650C along gate structure 210C and in active region row 220C. Thus, as Figure 6 As shown, the second metal segments 650A / B / C are arranged alternately in the x-direction (e.g., alternately between columns of gate structure 210 in the horizontal direction) to form three separate dummy devices—dummy device 660A, dummy device 660B, and dummy device 660C.

[0042] With these placements in the second metal sections 650A / B / C, the positions of dummy devices 660A, dummy devices 660B, and dummy devices 660C alternate between rows and columns in the device layout 600. With the alternating positions of dummy devices 660A and 660B, active transistors with sensed threshold voltage shifts also alternate between rows and columns in the device layout 600. For example, along gate structure 210A (e.g., "column A"), dummy device 660A in active region row 220C causes threshold voltage shifts in active transistors 610B to 610A in active region row 220B above the dummy device and in active transistors 610D to 610A in active region row 220D below the dummy device. Then, along gate structure 210B (e.g., "column B"), the dummy device 660B in active region row 220B causes a threshold voltage shift in the active transistors 610A to 610B in active region row 220A above the dummy device and in active transistors 610C to 610B in active region row 220C below the dummy device. Along gate structure 210C (e.g., "column C"), the dummy device 660C in active region row 220C (the same row as dummy device 660A) causes a threshold voltage shift in the active transistors 610B to 610C in active region row 220B above the dummy device and in active transistors 610D to 610C in active region row 220D below the dummy device. Therefore, active transistors with threshold voltage shifts alternate between rows in different columns of device layout 600. It should also be noted that the metal sections 650A / B / C may be made of the same metal, or it is conceivable that the metal (and the corresponding threshold voltage offset) may have different implementations for each of the metal sections and the dummy device.

[0043] It is also conceivable that the second metal segment 650 is placed horizontally across two columns rather than a third column for a single dummy device. Figure 7 A top-side plan view depicting a proposed device layout according to some embodiments is provided, the proposed device layout having NMOS metal segments and adjacent active PMOS metal segments in two columns along a row in the x-direction, wherein both types of metal segments are above the PMOS active region. In the illustrated embodiment, device layout 700 includes ( Figure 6The device layout 600 shown includes dummy devices 660A / B / C. Device layout 700 also includes a second metal segment 650D along gate structure 210A and a second metal segment 650E along gate structure 210B in the active region row 220F. The second metal segments 650D / E are in two columns (e.g., "column A" and "column B") in the same row as the first metal segment 240C in the third column (e.g., "column C"). The second metal segments 650D / E together form dummy device 760. Therefore, device layout 600 includes four separate dummy devices—dummy device 660A, dummy device 660B, dummy device 660C, and dummy device 760, wherein dummy devices 660A / B / C are single-column dummy devices, and dummy device 760 is a two-column dummy device.

[0044] When dummy device 760 is a two-column dummy device, the dummy device causes a threshold voltage offset in the active transistors along the same two columns. For example, in the illustrated embodiment, dummy device 760 causes a threshold voltage offset in active transistors 610E to 610A and active transistors 610E to 610B in active region row 220E. It should be noted that dummy device 760 will also cause a threshold voltage offset in the active transistors of another first transistor type active region below active region row 220F, unless the dummy device is positioned at the boundary of device layout 700. It should also be noted that Figure 6 and Figure 7 The device layouts provided are merely examples, and various additional device layouts are contemplated without departing from the scope of this disclosure and the appended claims. As an example, only a single active region row may include a second metal segment 650 constrained in the x-direction (e.g., the device layout may include only the second metal segments 650A, 650C in the active region row 220C).

[0045] Example computer system Next, turn to Figure 8 A block diagram of one embodiment of system 800 is shown, which may combine with and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 800 includes at least one instance of a system-on-chip (SoC) 806, which may include various types of processing units (such as a central processing unit (CPU), graphics processing unit (GPU), or others), communication architectures, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 806 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 806 is coupled to external memory 802, peripheral devices 804, and power supply 808.

[0046] A power supply 808 is also provided, which supplies power voltage to the SoC 806 and one or more power voltages to the memory 802 and / or peripheral devices 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 806 is included (and more than one external memory 802 is also included).

[0047] The memory 802 is any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), Static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, the devices may be mounted with a SoC or integrated circuit in a chip stack configuration, package stack configuration, or multi-chip module configuration.

[0048] Depending on the type of system 800, peripheral device 804 may include any desired circuitry. For example, in one embodiment, peripheral device 804 may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular phones, GPS, etc. In some embodiments, peripheral device 804 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 804 may include user interface devices such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc.

[0049] As illustrated, system 800 is shown to have applications in a wide range of fields. For example, system 800 can be used as part of a chip, circuit, component, etc., in a desktop computer 810, laptop computer 820, tablet computer 830, cellular or mobile phone 840, or television 850 (or a set-top box coupled to a television). Smartwatches and health monitoring devices 860 are also illustrated. In some embodiments, a smartwatch may include various general computing-related functions. For example, a smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0050] System 800 can be further used as part of a cloud-based service 870. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 800 can be used in one or more devices in the home 880, in addition to those previously mentioned devices. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and should provide an alert to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 8 The document also exemplifies the application of system 800 to various modes of transportation 890. For example, system 800 can be used as a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and (for rental or private use) motorcycles. In various cases, system 800 can be used to provide automated guidance (e.g., autonomous vehicles) and general system control. Many other implementations are possible and contemplated. It should be noted that... Figure 8 The devices and applications illustrated are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0051] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0052] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0053] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0054] For example, the features in the present application can be combined in any suitable manner. Thus, during the filing of the present application (or an application claiming priority therefrom), new claims can be made for any such combinations of features. Specifically, referring to the appended claims, the features of the dependent claims can, where appropriate, be combined with the features of other dependent claims, including claims that depend on other independent claims. Similarly, where appropriate, the features from the corresponding independent claims can be combined.

[0055] Thus, although the appended dependent claims can be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations can be claimed in the present application or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0056] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0057] Since the present disclosure is a legal document, various terms and phrases are subject to administrative and judicial interpretation. It is hereby announced that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how to interpret claims drafted based on the present disclosure.

[0058] Unless the context clearly dictates otherwise, a reference to an item in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "Multiple" items refers to a collection of two or more items.

[0059] The word "can" is used herein in an allowed sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0060] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0061] When the term “or” is used in this disclosure relative to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both”, and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0062] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0063] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0064] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0065] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0066] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0067] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0068] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0069] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim element. NoReferencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the structure “component for [performing function]” to describe the elements of the claims.

[0070] Different “circuits” may be described in this disclosure. These circuits, or “circuits”, constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0071] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0072] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, their relationship to each other, and the manner in which such circuits / cells / components interact form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations are derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0073] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0074] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An integrated circuit device, the integrated circuit device comprising: substrate; A plurality of active regions for a first type of transistor formed in the substrate, wherein the active regions include a channel region and a source / drain region for the first type of transistor, and wherein the active regions are aligned in a row along a first direction in the horizontal dimension relative to the substrate. A gate structure is formed above the substrate in a vertical dimension relative to the substrate, wherein the gate structure is aligned in a row along a second direction perpendicular to the first direction in the horizontal dimension, wherein the gate structure is positioned above at least two rows of active regions in the vertical dimension, and wherein the gate structure comprises: The first segment of the gate structure is positioned in the vertical dimension above a first active region in the at least two rows of active regions, the first segment comprising a first metal gate material, wherein the first metal gate material is associated with an active transistor of the first type of transistor and has a first work function; and The second segment of the gate structure is positioned in the vertical dimension above a second active region in at least two rows of active regions, wherein the second segment includes a second metal gate material adjacent to a first metal gate material in the first segment, wherein the second metal gate material has a second work function different from the first work function, and wherein the adjacency of the second gate material in the second segment with the first gate material in the first segment causes a shift in the threshold voltage of the active transistor.

2. The device of claim 1, wherein the first work function corresponds to a transistor of the first type, and wherein the second work function corresponds to a transistor of the second type, the transistor of the second type being complementary to the transistor of the first type.

3. The device of claim 1, wherein rows of active regions are separated by rows of non-active regions, wherein the non-active regions provide electrical isolation between rows of adjacent active regions.

4. The device of claim 1, wherein the gate structure is positioned above at least one additional row of the active region in the vertical dimension, and wherein the gate structure further comprises: The third segment of the gate structure, positioned in the vertical dimension above the at least one additional row of the active region, the third segment comprising the first metal gate material, wherein the third segment is adjacent to the second segment on the side of the second segment opposite to the first segment in the second direction.

5. The device of claim 4, wherein the first metal gate material in the third segment is adjacent to the second metal gate material in the second segment.

6. The device of claim 5, wherein the first metal gate material in the third segment is associated with an active transistor of the first type of transistor, and wherein the second gate material in the second segment is adjacent to the first gate material in the third segment, causing a shift in the threshold voltage of the active transistor.

7. The device of claim 6, wherein the gate structure further comprises: The fourth segment of the gate structure is positioned above the at least one additional row of the active region in the vertical dimension, the fourth segment comprising the second metal gate material, wherein the fourth segment is adjacent to the third segment on the side of the third segment opposite to the second segment in the second direction; The second gate material in the second segment and the second gate material in the fourth segment are adjacent to the first gate material in the third segment, causing a shift in the threshold voltage of the active transistor in the third segment. This shift is greater than the shift in the threshold voltage when the second gate material is present only in the second segment or the fourth segment.

8. The device according to claim 1, further comprising: A second gate structure is formed above the substrate in the vertical dimension, wherein the second gate structures are aligned in a row along the second direction in the horizontal dimension, wherein the second gate structures are separated from the gate structure in the first direction, wherein the second gate structures are positioned above the at least two rows of active regions in the vertical dimension, and wherein the second gate structure includes: A first segment of the second gate structure, positioned above a third active region in the at least two rows of active regions, the first segment comprising the first metal gate material; and The second segment of the second gate structure is positioned above the fourth active region in the at least two rows of active regions, wherein the second segment is adjacent to the first segment in the second gate structure, and wherein the second segment includes the second metal gate material.

9. The device of claim 1, wherein the source / drain region in the second active region is electrically floated.

10. An integrated circuit device, the integrated circuit device comprising: substrate; A plurality of active regions for a first type of transistor formed in the substrate, wherein the active regions include a channel region and a source / drain region for the first type of transistor, and wherein the active regions are aligned in a row along a first direction in the horizontal dimension relative to the substrate. A gate structure is formed above the substrate in a vertical dimension relative to the substrate, wherein the gate structure is aligned in a row along a second direction perpendicular to the first direction in the horizontal dimension, wherein the gate structure is positioned above at least two rows of active regions in the vertical dimension, and wherein the gate structure comprises: The first segment of the gate structure, which is associated with an active transistor of the first type of transistor, is positioned in the vertical dimension above a first active region in the at least two rows of active regions, and includes a first metal gate material having a first work function corresponding to the active transistor. and The second segment of the gate structure is positioned in the vertical dimension above a second active region in the at least two rows of active regions, wherein the second segment is adjacent to the first segment of the gate structure, wherein the second segment includes a second metal gate material having a second work function corresponding to a second type of transistor, the second type of transistor being complementary to the first type of transistor and an active transistor, and wherein the adjacency of the second gate material in the second segment with the first gate material in the first segment causes a shift in the threshold voltage of the active transistor.

11. The device of claim 10, wherein the first active region comprises a p-type channel region and a source / drain region for a transistor of the first type, and wherein the second work function is an n-type work function.

12. The device of claim 10, wherein the first active region comprises an n-type channel region and a source / drain region for a transistor of the first type, and wherein the second work function is a p-type work function.

13. The device of claim 10, wherein the gate structure is positioned above at least one additional row of the active region in the vertical dimension, and wherein the gate structure further comprises: The third segment of the gate structure, positioned in the vertical dimension above the at least one additional row of the active region, the third segment comprising the first metal gate material, wherein the third segment is adjacent to the second segment on the side of the second segment opposite to the first segment in the second direction.

14. The device of claim 10, further comprising: A second gate structure is formed above the substrate in the vertical dimension, wherein the second gate structures are aligned in a row along the second direction in the horizontal dimension, wherein the second gate structures are separated from the gate structure in the first direction, wherein the second gate structures are positioned above the at least two rows of active regions in the vertical dimension, and wherein the second gate structure includes: A first segment of the second gate structure, positioned above a third active region in the at least two rows of active regions, the first segment comprising the first metal gate material; and The second segment of the second gate structure is positioned above the fourth active region in the at least two rows of active regions, wherein the second segment is adjacent to the first segment in the second gate structure, and wherein the second segment includes the second metal gate material.

15. The device of claim 14, wherein the fourth active region is a portion of the same row of active regions that is identical to the second active region, and the fourth active region is a portion of the same row of active regions that is different from the second active region.

16. The device of claim 14, wherein the fourth active region and the second active region are located in different rows of the active regions.

17. The device of claim 14, wherein the source / drain region in the second active region is electrically floated.

18. An integrated circuit device, the integrated circuit device comprising: substrate; A plurality of active regions for a first type of transistor formed in the substrate, wherein the active regions include a channel region and a source / drain region for the first type of transistor, and wherein the active regions are aligned in a row along a first direction in the horizontal dimension relative to the substrate. A plurality of gate structures are formed above the substrate in a vertical dimension relative to the substrate, wherein the gate structures are aligned in a column along a second direction in a horizontal dimension, the second direction being perpendicular to the first direction, and wherein the gate structures are positioned above two or more rows of active regions in the vertical dimension. The first gate structure includes: A first segment of the first gate structure, positioned vertically above a first active region in one of the two or more rows of active regions, includes a first metal gate material having a first work function corresponding to a transistor of the first type; and The second segment of the first gate structure is positioned in the vertical dimension above the second active region in one of the two or more rows of active regions, wherein the second segment is adjacent to the first segment in the first gate structure, wherein the second segment includes a second metal gate material, and wherein the second metal gate material has a second work function, the second work function being the inverse work function of the transistor of the first type. The second gate structure includes: A first segment of the second gate structure, positioned vertically above a third active region in one of the two or more rows of active regions, comprises the first metal gate material; and The second segment of the second gate structure is positioned in the vertical dimension above the fourth active region in the two or more rows of active regions, wherein the second segment is adjacent to the first segment in the second gate structure, and wherein the second segment comprises the second metal gate material.

19. The device of claim 18, wherein the third active region is a portion of the same row of active regions that is identical to the first active region, and the third active region is a portion of the same row of active regions that is different from the first active region, and wherein the fourth active region is a portion of the same row of active regions that is identical to the second active region, and the fourth active region is a portion of the same row of active regions that is different from the second active region.

20. The device of claim 18, wherein the first gate structure further comprises: A third segment of the first gate structure, positioned in the vertical dimension above at least a seventh active region in one of the two or more rows of active regions, the third segment comprising the first metal gate material, wherein the third segment is adjacent to the second segment on the side of the second segment opposite to the first segment in the second direction; and The fourth segment of the first gate structure is positioned in the vertical dimension above the eighth active region in one of the two or more rows of active regions, wherein the fourth segment includes the second metal gate material, and wherein the fourth segment is adjacent to the third segment on the side of the third segment opposite to the second segment in the second direction.

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