Switching voltage controlled current source

Abstract

A switching voltage controlled current source, comprising: a current source input for receiving a first input logic signal and a current source output for outputting a current; the first logic circuit comprises a first logic input end connected to the current source input end, a first logic output end used for outputting a current control signal, a first supply end used for being connected to a power supply and a first grounding end used for being connected to the ground; a first resistor coupled between the first logic output and the current source output; a second resistor coupled between the power source and the first supply terminal and a third resistor coupled between ground and a first ground terminal; wherein the first logic circuit is operable to selectively couple the second resistor or the third resistor to the first resistor; and a first charge supply circuit and a second charge supply circuit.

Description

Technical Field

[0001] The present invention relates to a switch voltage controlled current source, a digital-to-analog converter including one or more such switch voltage controlled current sources, and a Delta-Sigma modulator including one or more such digital-to-analog converters. Background Technology

[0002] A traditional Delta-Sigma modulator (DSM) includes an integrator, a quantizer, and a digital-to-analogue converter (DAC) that can be used as analog loop filters (e.g., low-pass or band-pass filters). Figure 1 An example multi-bit DSM is schematically depicted. The DSM includes an integrator INT, which comprises an operational amplifier AMP and a capacitor C. The DSM also includes a quantizer QUT, which comprises three comparators CMP1-CMP3, each configured to output a logic signal. The DSM also includes a return DAC R-DAC, which comprises three unit current sources CS1-CS3, each controlled by one of the three logic signals output from the quantizer QUT. The input signal SIN is coupled to the integrator INT via a resistor R and outputs a modulated signal SOUT from the quantizer QUT.

[0003] One of the key performance metrics of a DSM is linearity, which represents the DSM's ability to avoid generating harmonics associated with the input signal. Returning harmonics to the DAC are often the primary cause of any unwanted harmonics. (Reference) Figure 1 Each current source CS1, CS2, and CS3 of the DACR-DAC is operable to transmit a bipolar output current, the polarity of which is determined by the logic signal output from one of the comparators CMP1, CMP2, and CMP3 of the quantizer QUT. Undesirable harmonics may arise from various factors, such as mismatches between the output current values ​​of different current sources CS1-CS3; or they may be caused by the so-called "memory effect," which is caused by the voltage of one or more nodes settling to different values ​​depending on the switching speed of the logic signal (i.e., how quickly the logic state changes).

[0004] The parasitic capacitance at the node receiving high-speed logic signals is the main cause of this "memory effect". Figure 2The diagram illustrates the input logic signal VIN used to control the unit current source returning to the DAC R-DAC, and the internal signal IS (transient voltage at a certain node) that contributes to the output current. Parasitic capacitance significantly prolongs the time required for the voltage at a certain voltage node to fully stabilize, resulting in a voltage stabilization time longer than the duration of a specific logic state (e.g., logic 0 or logic 1) (or the duration of a signal pulse). Consequently, the output current OC of the unit current source deviates from the "ideal" output current OC unaffected by memory effects, and this deviation depends on the input data (also known as input data-dependent behavior).

[0005] The purpose of this disclosure is to at least alleviate these problems of the prior art. Summary of the Invention

[0006] The aspects of this disclosure are set forth in the appended independent and dependent claims. Combinations of features of the dependent claims may be appropriately combined with features of the independent claims, and not merely as expressly set forth in the claims.

[0007] According to a first aspect of the present invention, a switch-voltage controlled current source is provided, comprising: a current source input terminal for receiving a first input logic signal and a current source output terminal for outputting current; a first logic circuit including a first logic input terminal connected to the current source input terminal, a first logic output terminal for outputting a current control signal, a first supply terminal for connecting to a power supply, and a first ground terminal for connecting to ground; a first resistor coupled between the first logic output terminal and the current source output terminal; a second resistor coupled between the power supply and the first supply terminal, and a third resistor coupled between ground and the first ground terminal; wherein the first logic circuit is operable to selectively couple either the second resistor or the third resistor to the first resistor; a first charge supply circuit configured to supply a first amount of charge to compensate for a first charge difference in a parasitic capacitance formed at an internal node of the current source connected to the first logic output terminal and one end of the first resistor in response to a switch of the first input logic signal from a first logic state to a second logic state; and a second charge supply circuit configured to supply a second amount of charge to compensate for a second charge difference in a parasitic capacitance formed at an internal node of the current source in response to a switch of the first input logic signal from a second logic state to a first logic state.

[0008] By supplying an appropriate amount of charge to compensate for the difference in charge in the parasitic capacitance formed at the internal nodes, the proposed switching voltage-controlled current source can significantly reduce or even completely eliminate the transient current caused by the change in charge in the parasitic capacitance after each logic state switch of the input logic signal. This, in turn, ensures that the final transient voltage stabilizes to its initial voltage value in a fast manner, thereby minimizing or preventing the negative impact of memory effects.

[0009] In one embodiment, the first charge supply circuit may include: a first charge supply input terminal connected to a current source input terminal; a first charge supply output terminal connected to a first supply terminal of a first logic circuit; a first internal voltage node; a second logic circuit including a second logic input terminal connected to the first charge supply input terminal and a second logic output terminal, the second logic circuit being configured to have the same functional behavior as the first logic circuit; a first capacitor coupled between the second logic output terminal and the first internal voltage node; a first switch coupled between the first charge supply output terminal and the first internal voltage node, the state of the first switch being controlled by a first input logic signal; and a second switch coupled between the first internal voltage node and a power supply, the state of the second switch being controlled by a second input logic signal having the opposite polarity to the first input logic signal.

[0010] In one embodiment, the second charge supply circuit may include: a second charge supply input terminal connected to a current source input terminal; a second charge supply output terminal connected to a first ground terminal of the first logic circuit; a second internal voltage node; a third logic circuit including a third logic input terminal connected to the second charge supply input terminal and a third logic output terminal, the third logic circuit being configured to have the same functional behavior as the first logic circuit; a second capacitor coupled between the second logic output terminal and the second internal voltage node; a third switch coupled between the second charge supply output terminal and the second internal voltage node, the state of the third switch being controlled by a first input logic signal; and a fourth switch coupled between the second internal voltage node and ground, the state of the fourth switch being controlled by a second input logic signal.

[0011] In one embodiment, the resistance of the second resistor and / or the third resistor may be adjustable. In one embodiment, the second resistor may include a first fixed resistor and one or more second fixed resistors, wherein each of the one or more second fixed resistors is connected in series with a fifth switch, and each pair of second fixed resistors and the fifth switch is connected in parallel to the first fixed resistor. In one embodiment, the third resistor may include a third fixed resistor and one or more fourth fixed resistors, wherein each of the one or more fourth fixed resistors is connected in series with a sixth switch, and each pair of fourth fixed resistors and the sixth switch is connected in parallel to the third fixed resistor.

[0012] In one embodiment, the first and second switches of the first charge supply circuit can both be P-type MOSFET transistors, and / or the third and fourth switches of the second charge supply circuit can both be N-type MOSFET transistors.

[0013] In one embodiment, when the first logic circuit decouples the first resistor from the second resistor, the first capacitor of the first charge supply circuit is coupled to the power supply and decoupled from the first charge supply output terminal. In another embodiment, when the first logic circuit decouples the first resistor from the third resistor, the second capacitor of the second charge supply circuit is coupled to ground and decoupled from the second charge supply output terminal.

[0014] In one embodiment, when the first logic circuit couples the first resistor to the second resistor, the first capacitor of the first charge supply circuit is decoupled from the power supply and coupled to the first charge supply output terminal. In another embodiment, when the first logic circuit couples the first resistor to the third resistor, the second capacitor of the second charge supply circuit is decoupled from ground and coupled to the second charge supply output terminal.

[0015] In one embodiment, the switching voltage-controlled current source is operable to output a first current when the first input logic signal is in a first state, and to output a second current when the first input logic signal is in a second state, the second current having a similar or the same absolute value as the first current, but having the opposite polarity.

[0016] In one embodiment, the second logic circuit of the first charge supply circuit and the third logic circuit of the second charge supply circuit can be the same as the first logic circuit.

[0017] In one embodiment, the second logic circuit of the first charge supply circuit and the third logic circuit of the second charge supply circuit may be different from the first logic circuit, but have the same functional behavior as the first logic circuit.

[0018] In one embodiment, the first logic circuit may be an inverter.

[0019] In one embodiment, the first logical state is logical high and the second logical state is logical low.

[0020] In a second aspect of the invention, a digital-to-analog converter is provided, including at least one current source controlled by a switching voltage according to the first aspect.

[0021] In a third aspect of the invention, a Delta-Sigma modulator is provided, comprising: at least one digital-to-analog converter of the second aspect; and at least one integrator for receiving current from at least one switching voltage-controlled current source from the at least one digital-to-analog converter of the second aspect.

[0022] In a fourth aspect of the invention, a method for compensating parasitic capacitance in a switched voltage controlled current source is provided. The switched voltage controlled current source may include: a current source input terminal for receiving a first input logic signal and a current source output terminal for outputting current; a first logic circuit including a first logic input terminal connected to the current source input terminal, a first logic output terminal for outputting a current control signal, a first supply terminal for connecting to a power supply, and a first ground terminal for connecting to ground; a first resistor coupled between the first logic output terminal and the current source output terminal; a second resistor coupled between the power supply and the first supply terminal; and a third resistor coupled between ground and the first ground terminal; wherein the first logic circuit is operable to selectively couple either the second resistor or the third resistor to the first resistor. The method may include: in response to a first input logic signal switching from a first logic state to a second logic state, generating a first amount of charge through a first charge supply circuit to compensate for a first charge difference in a parasitic capacitance formed at an internal node of a current source connected to a first logic output terminal and one end of a first resistor; and in response to a first input logic signal switching from a second logic state to a first logic state, generating a second amount of charge through a second charge supply circuit to compensate for a second charge difference in a parasitic capacitance formed at an internal node of the current source.

[0023] It should be understood that any features described herein that are suitable for inclusion in one or more aspects or embodiments of this disclosure are intended to be generalizable to any and all aspects and embodiments of this disclosure. Other aspects of this disclosure can be understood by those skilled in the art from the specification, claims, and drawings of this disclosure. The foregoing general description and the following detailed description are exemplary and explanatory only and do not limit the scope of the claims. Attached Figure Description

[0024] Embodiments of this disclosure will be described below by way of example only with reference to the accompanying drawings, wherein similar reference numerals relate to similar elements, and wherein:

[0025] Figure 1 A schematic diagram of a prior art Delta-Sigma modulator is shown;

[0026] Figure 2 The diagram schematically illustrates a method for controlling a Delta-Sigma modulator (e.g., as shown in the image). Figure 1 The input logic signal of the current source used in the diagram and the internal signal of the current source (transient voltage at a certain node) that contributes to the output current;

[0027] Figure 3 A schematic diagram of a prior art electronic circuit including a switched voltage-controlled current source connected to a single-ended integrator is shown.

[0028] Figure 4 A schematic diagram of another prior art electronic circuit is shown, including an improved switched voltage controlled current source connected to a single-ended integrator;

[0029] Figure 5 A schematic diagram of an electronic circuit including an embodiment of the proposed switch-voltage controlled current source connected to a single-ended integrator is shown.

[0030] Figure 6A and Figure 6B The diagram schematically illustrates the falling-edge operation of the proposed switching voltage-controlled current source when the input logic signal switches from logic high to logic low; and

[0031] Figure 7A and Figure 7B The diagram schematically illustrates the rising edge operation of the proposed switching voltage-controlled current source when the input logic signal switches from logic low to logic high. Detailed Implementation

[0032] When in DSM (e.g.) Figure 1 When used in a DSM (Distributed Module System), the unit current source typically comprises a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) current source followed by a pair of switching transistors configured to generate differential output currents based on the state of the input logic signal. However, due to its simpler configuration, it is advantageous to use a voltage control unit current source comprising a resistor connected at one end to the input of an integrator and at the other end to the output of a logic circuit (e.g., an inverter).

[0033] Figure 3 A switch-voltage controlled current source SCS connected to a single-ended integrator is schematically depicted. (e.g.) Figure 3 As shown, the switching voltage-controlled current source SCS includes logic circuit LGC1 and resistor R1 coupling the current source SCS to integrator INT. Logic circuit LGC1 includes a supply terminal for connection to power supply Vdd and a ground terminal for connection to ground. In this specific example, logic circuit LGC1 is an inverter, which includes a P-type MOSFET transistor MP11 and an N-type MOSFET transistor MN11, wherein the source terminal of the P-type MOSFET transistor MP11 is connected to the supply terminal (and thus to power supply Vdd), and the source terminal of the N-type MOSFET transistor MN11 is connected to the ground terminal (and thus to ground). The drain terminals of the P-type MOSFET transistor MP11 and the N-type MOSFET transistor MN11 are connected to one end of resistor R1. The configuration of integrator INT is as follows... Figure 1 The configuration shown is the same.

[0034] The input logic signal VIN controls the switching voltage, which in turn controls the output current IDAC of the current source SCS. Assuming the on-resistance of the N-type MOSFET transistor MN1 and the P-type MOSFET transistor MP1 is negligible relative to resistor R1, and the voltage VCM at the positive input of the operational amplifier AMP is half the supply voltage Vdd, then when the input signal VIN is logic low (i.e., VIN = 0V), the output current IDAC is equal to... Furthermore, when the input signal VIN is logic high (i.e., VIN = Vdd), the output current IDAC equals

[0035] Therefore, for a system comprising several identical unit current sources (e.g., Figure 3 The current source SCS shown is a multi-bit DSM (e.g., such as...). Figure 1 As shown above, it is desirable to adjust the output current defined by resistor R1 for each unit current source to compensate for any mismatch in the resistance values ​​of resistor R1 between different unit current sources. The existing method is to add two adjustable resistors R2P and R2N to each unit current source. Figure 4 As shown, a first adjustable resistor R2P is placed between the power supply Vdd and the supply terminal of the logic circuit LGC1 (which is also the source terminal of the P-type MOSFET transistor MP1), and a second adjustable resistor R2N is placed between ground and the ground terminal of the logic circuit LGC1 (which is also the source terminal of the N-type MOSFET transistor MN1). When the input signal VIN is logic low (i.e., VIN = 0V), the first adjustable resistor R2P can be used to adjust the voltage to Vdd. dd The output current IDAC is equal to / (2*(R1+R2P)). When the input signal VIN is logic high (i.e., VIN = V...), the output current IDAC is equal to / (2*(R1+R2P)). dd When the second adjustable resistor R2N is equal to -V, it can be used to adjust the value. dd The output current IDAC is / (2*(R1+R2N)).

[0036] In this example implementation, the first adjustable resistor R2P includes a first fixed resistor R2P1, which is connected in parallel to a second fixed resistor R2P2 and a third fixed resistor R2P3. The second fixed resistor R2P2 is connected in series to switch S2, and the third fixed resistor R2P3 is connected in series to switch S3. The second adjustable resistor R2N is configured in a similar manner and is therefore not shown in the figure for simplicity. The resistance value of either the first adjustable resistor R2P or the second adjustable resistor R2N can be adjusted by controlling the on / off state of the respective switches. The resistance values ​​of the first adjustable resistor R2P and the second adjustable resistor R2N can be a small fraction of the resistance value of resistor R1. In other examples, the first adjustable resistor R2P and / or the second adjustable resistor R2N can have different configurations. For example, one or both of the first adjustable resistor R2P and the second adjustable resistor R2N can include one or more variable resistors with variable resistance values.

[0037] refer to Figure 4 The switching voltage-controlled current source I-SCS exhibits a parasitic capacitance CPAR at the internal voltage node LOT1, which is a common point between the output terminal LOT1 of logic circuit LGC1 (connected to the drain terminals of P-type MOSFET transistors and N-type MOSFET transistors) and one end of resistor R1. This parasitic capacitance CPAR is the sum of the parasitic capacitance of resistor R1, the parasitic capacitance of the drain of P-type MOSFET transistor MP1, the parasitic capacitance of the drain of N-type MOSFET transistor MN1, and the parasitic capacitance of the physical interconnect at node LOT1.

[0038] When the input logic signal VIN switches from logic high to logic low, the parasitic capacitance CPAR charges from 0V to Vdd. When the input logic signal VIN switches from logic low to logic high, the parasitic capacitance CPAR discharges from Vdd to 0V. The amount of charge transferred from / to the internal voltage node (where the switching-sensing parasitic capacitance exists) causes a transient current through the first adjustable resistor R2P or the second adjustable resistor R2N, resulting in a transient voltage change at node VR2P or VR2N. The time constant determined by R2P*CPAP or R2N*CPAP can be large enough that the transient voltage at node VR2P or VR2N does not return to its initial value before the next switch of the logic state of the input logic signal VIN (e.g., in the case of a high-speed input logic signal VIN). Therefore, the transient voltage changes at nodes VR2P and VR2N may have input data-dependent behavior (similar to...). Figure 2 The behavior of the internal signal IS shown. This will produce a result similar to the input signal (e.g., Figure 1 Unwanted harmonics related to the input signal SIN can negatively impact the linearity of the DSM.

[0039] Therefore, it is necessary to modify existing switching voltage control current sources (e.g.) Figure 4 Further improvements can be made to the switch-voltage controlled current source (I-SCS) shown. These improvements can be achieved by configuring the switch-voltage controlled current source in such a way that a certain amount of charge is supplied to the internal voltage node (where a parasitic capacitance CPAR exists) during the logic state transition of the input logic signal VIN. The supplied charge effectively compensates for the difference in charge amount in the parasitic capacitance CPAR at the internal voltage node LOT1, thereby reducing or preventing transient current from flowing through the first adjustable resistor R2P or the second adjustable resistor R2N. This ensures that the transient voltages VR2P or VR2N at nodes ST1 or GT1 quickly stabilize to their initial values ​​after each logic state transition of the input logic signal VIN, thus preventing input data-dependent behavior. When this charge-compensated current source is used in the DSM, the linearity of the DSM is improved.

[0040] Accordingly, a first aspect of this disclosure provides a switching voltage controlled current source suitable for use in a DSM. Figure 5 The diagram schematically illustrates an electronic circuit including an embodiment of the proposed switch-voltage controlled current source CC-SCS, which is coupled to a single-ended integrator INT via an internal resistor R1. The single-ended integrator INT is connected to... Figure 3 or Figure 4 The electronic circuit configuration shown is the same. It should be understood that when the proposed switch-voltage controlled current source CC-SCS is used in devices other than DSMs, the integrator INT may not be required, or a different configuration may be used. Figure 4 The main difference between the I-SCS and the proposed CC-SCS is that the CC-SCS includes two additional charge supply circuits: a first charge supply circuit CSC1 and a second charge supply circuit CSC2. For the sake of brevity, the operating principle of the common parts of the electronic circuit will not be described in detail.

[0041] refer to Figure 5 The switch voltage controlled current source CC-SCS may include a current source input terminal IT for receiving the first input logic signal VIN and a current source output terminal OT for outputting the current IDAC.

[0042] The switch voltage controlled current source CC-SCS may further include a first logic circuit LGC1, which may include: a first logic input terminal (not shown) connected to the current source input terminal IT, a first logic output terminal LOT1 for outputting a current control signal, a first supply terminal ST1 for connecting to the power supply Vdd, and a first ground terminal GT1 for connecting to ground. In one embodiment, the first logic circuit LGC1 may be an inverter controlled by a single-input logic signal VIN. The first logic circuit LGC1 includes a first P-type MOSFET transistor MP11 and a first N-type MOSFET transistor MN11, wherein the source terminal of the first P-type MOSFET transistor MP11 may be connected to the first supply terminal ST1, and the source terminal of the first N-type MOSFET transistor MN11 may be connected to the first ground terminal GT1. The drain terminals of the first P-type MOSFET transistor MP11 and the first N-type MOSFET transistor MN11 may be connected to the first logic output terminal LOT1. In other embodiments, the first logic circuit LGC1 may include one or more logic circuits. For example, the first logic circuit LGC1 may include one or more AND gates, and / or one or more NAND gates, and / or one or more XOR gates, and / or one or more OR gates, and / or one or more NOR gates.

[0043] The switch voltage-controlled current source CC-SCS may further include: a first resistor R1 coupled between the first logic output terminal LOT1 and the current source output terminal OT; a second resistor R2P coupled between the power supply Vdd and the first supply terminal ST1; and a third resistor R2N coupled between ground and the first ground terminal GT1. The first logic circuit LGC1 may be operable to selectively couple either the second resistor R2P or the third resistor R2N to the first resistor R1.

[0044] The switch voltage controlled current source CC-SCS may also include a first charge supply circuit CSC1, which is configured to supply a first amount of charge to compensate for a first charge difference in the parasitic capacitance CPAR formed at the internal node CSIN of the current source connected to the first logic output LOT1 and one end of the first resistor R1 in response to the first input logic signal VIN switching from a first logic state (e.g., logic high) to a second logic state (e.g., logic low).

[0045] The switch voltage controlled current source CC-SCS may also include a second charge supply circuit CSC2, which is configured to provide a second amount of charge to compensate for a second charge difference in the parasitic capacitance CPAR formed at the internal node CSIN of the current source in response to the first input logic signal VIN switching from a second logic state (e.g., logic low) to a first logic state (e.g., logic high).

[0046] The first charge supply circuit CSC1 and the second charge supply circuit CSC2 may include the same or similar logic circuits. Importantly, the first logic circuit LGC1 of the switched voltage-controlled current source CC-SCS, the second logic circuit LGC2 of the first charge supply circuit CSC1, and the third logic circuit LGC3 of the second charge supply circuit CSC2 are driven by the same input logic signal VIN (rather than one logic circuit being driven by a single input logic signal while the others are driven by its inverted form). This allows the three logic circuits LGC1, LGC2, and LGC3 to operate in a substantially synchronous manner, thereby achieving the desired behavior at nodes ST1 and GT1.

[0047] In one embodiment, the first charge supply circuit CSC1 may include: a first charge supply input terminal CSIT1 connected to the current source input terminal IT, a first charge supply output terminal CSOT1 connected to the first supply terminal ST1 of the first logic circuit LGC1, and a first internal voltage node INV1. The first charge supply circuit CSC1 may also include a second logic circuit LGC2, which may include a second logic input terminal (not shown) connected to the first charge supply input terminal CSIT1 and a second logic output terminal LOT2. The second logic circuit LGC2 may be configured to have the same functional behavior as the first logic circuit LGC1.

[0048] In one embodiment, the second logic circuit LGC2 can be an inverter controlled by a single-input logic signal VIN. The second logic circuit LGC2 may include a second P-type MOSFET transistor MP21 and a second N-type MOSFET transistor MN21, wherein the source terminal of the second P-type MOSFET transistor MP21 can be connected to the power supply Vdd, and the source terminal of the second N-type MOSFET transistor MN21 can be connected to ground. The drain terminals of the second P-type MOSFET transistor MP21 and the second N-type MOSFET transistor MN21 can be connected to the second logic output terminal LOT2.

[0049] The first charge supply circuit CSC1 may further include: a first capacitor CP coupled between the second logic output terminal LOT2 and the first internal voltage node INV1; and a first switch MP22 coupled between the first charge supply output terminal CSOT1 and the first internal voltage node INV1, the state of which is controlled by a first input logic signal VIN. The first charge supply circuit CSC1 may also include a second switch MP23 coupled between the first internal voltage node INV1 and the power supply Vdd, the state of which is controlled by a second input logic signal having the opposite polarity to the first input logic signal VIN. Second input logic signal It can be the inverted signal of the first input logic signal VIN, for example, obtained by feeding the first input logic signal VIN to the inverter IVT. In one embodiment, the first switch MP22 and the second switch MP23 of the first charge supply circuit CSC1 can both include P-type MOSFET transistors.

[0050] In one embodiment, the second charge supply circuit CSC2 may include: a second charge supply input terminal CSIT2 connected to the current source input terminal IT, a second charge supply output terminal CSOT2 connected to the first ground terminal GT1 of the first logic circuit LGC1, and a second internal voltage node INV2. The second charge supply circuit CSC2 may also include a third logic circuit LGC3, which may include a third logic input terminal (not shown) connected to the second charge supply input terminal CSIT2 and a third logic output terminal LOT3. The third logic circuit LGC3 may be configured to have the same functional behavior as the first logic circuit LGC1.

[0051] In one embodiment, the third logic circuit LGC3 can be an inverter controlled by a single-input logic signal VIN. The third logic circuit LGC3 may include a third P-type MOSFET transistor MP31 and a third N-type MOSFET transistor MN31, wherein the source terminal of the third P-type MOSFET transistor MP31 can be connected to the power supply Vdd, and the source terminal of the third N-type MOSFET transistor MN31 can be connected to ground. The drain terminals of the third P-type MOSFET transistor MP31 and the third N-type MOSFET transistor MN31 can be connected to the third logic output terminal LOT3.

[0052] The second charge supply circuit CSC2 may further include a second capacitor CN, which may be coupled between the third logic output terminal LOT3 and the second internal voltage node INV2. The second charge supply circuit CSC2 may also include a third switch MN32 coupled between the second charge supply output terminal CSOT2 and the second internal voltage node INV2, the state of which is controlled by a first input logic signal VIN. The second charge supply circuit CSC2 may also include a fourth switch MN33 coupled between the second internal voltage node INV2 and ground, the state of which is controlled by a second input logic signal having the opposite polarity to the first input logic signal VIN. Control. In one embodiment, the third switch MN32 and the fourth switch MN33 of the second charge supply circuit CSC2 may both include N-type MOSFET transistors.

[0053] The switch-controlled voltage current source CC-SCS is operable to output a first current when the first input logic signal VIN is in a first logic state, and to output a second current when the first input logic signal VIN is in a second state. The second current has a similar or the same absolute value IDAC as the first current, but has the opposite polarity (i.e., opposite current flow direction). For example, when the first input logic signal VIN is logic low (e.g., VIN = 0V), the first current IDAC can flow to the integrator INT, while when the first input signal VIN is logic high, the second current IDAC can flow to the first logic circuit LGC1.

[0054] In one embodiment, the second logic circuit LGC2 of the first charge supply circuit CSC1 and the third logic circuit LGC3 of the second charge supply circuit CSC2 can be the same as the first logic circuit LGC1. In different embodiments, the second logic circuit LGC2 of the first charge supply circuit CSC1 and the third logic circuit LGC3 of the second charge supply circuit CSC2 can be different from the first logic circuit LGC1, but can have the same functional behavior as the first logic circuit LGC1.

[0055] Falling edge transition (i.e., switching from logic high to logic low)

[0056] Figure 6A and Figure 6B The diagram schematically illustrates the falling-edge operation of the switching voltage-controlled current source CC-SCS when the first input logic signal VIN switches from logic high (e.g., VIN = 1V) to logic low (e.g., VIN = 0V). During the falling-edge transition, the first charge supply circuit CSC1 can be activated.

[0057] refer to Figure 6A When the first input logic signal VIN is logic high (e.g., VIN = 1V), one end of the first capacitor CP is coupled to the power supply Vdd, and the other end is coupled to ground (via the second N-type MOSFET transistor MN21). The amount of charge stored in the first capacitor CP between its PLUS (+) and MINUS (-) terminals is approximately equal to Vdd * CP. The voltage across the internal node CSIN of the current source (i.e., the voltage across the parasitic capacitance CPAR) is equal to IDAC * R2N, and the amount of charge stored in the parasitic capacitance CPAR is approximately equal to (IDAC * R2N) * CPAP.

[0058] refer to Figure 6BWhen the first input logic signal VIN switches from logic high (e.g., VIN = 1V) to logic low (e.g., VIN = 0V), the first capacitor CP is coupled between the power supply Vdd (via the second P-type MOSFET transistor MP21) and the first supply terminal ST1, and the parasitic capacitance CPAR is coupled to the first supply terminal ST1 of the first logic circuit LGC1 (assuming the resistance of the first P-type MOSFET MP11 transistor is negligible). The voltage VR2P at the first supply terminal ST1 will stabilize to Vdd - IDAC*R2P. The voltage across the first capacitor CP is approximately equal to -IDAC*R2P, and the voltage across the parasitic capacitance CPAR is approximately equal to Vdd – IDAC*R2P. The new charge stored in the first capacitor CP is approximately equal to -IDAC*R2P*CP, and the new charge stored in the parasitic capacitance CPAR is approximately equal to (Vdd – IDAC*R2P)*CPAR.

[0059] As mentioned above Figure 4 The description states that, without the first charge supply circuit CSC1, the difference in charge in the parasitic capacitance CPAR before and after the falling edge transition will cause a transient current flowing through the first adjustable resistor R2P. This transient current leads to a transient voltage drop across resistor R2P, the time constant of which is determined by R2P*CPAR. In contrast, with the help of the first charge supply circuit CSC1, the first capacitor CP can operate to supply an appropriate amount of charge to compensate for the difference in charge in the parasitic capacitance CPAR before and after the falling edge transition. Thus, due to the charging of the parasitic capacitance CPAR, the current IPS flowing through the first adjustable resistor R2P is significantly reduced or essentially eliminated. When the sum of the charge difference in the first capacitor CP and the charge difference in the parasitic capacitance CPAR is equal to zero, the charge difference in the parasitic capacitance CPAR before and after the falling edge transition is perfectly compensated, which can be expressed as:

[0060] (Vdd+IDAC*R2P)*CP+((IDAC*R2N)-(Vdd–IDAC*R2P))*CPAR=0 (1)

[0061] Therefore, the capacitance of the first capacitor CP can be expressed as:

[0062]

[0063] Therefore, by using a capacitor with a capacitance determined by equation (2) as the first capacitor CP, a transient voltage VR2P can be prevented at the first supply terminal ST1, thereby preventing the input data-dependent behavior of the output current IDAC.

[0064] Rising edge transition (i.e., switching from logic low to logic high)

[0065] Figure 7A and Figure 7B The diagram schematically illustrates the rising-edge operation of the switching voltage-controlled current source when the input logic signal switches from logic low (e.g., VIN = 0V) to logic high (e.g., VIN = 1V). During the rising-edge transition, the second charge supply circuit CSC2 can be activated.

[0066] refer to Figure 7A When the first input logic signal VIN is logic low (e.g., VIN = 0V), one end of the second capacitor CN is coupled to the power supply Vdd (via the third P-type MOSFET transistor MP31), and the other end is coupled to ground. The amount of charge stored in the second capacitor CN between its PLUS (+) and MINUS (-) terminals is approximately equal to -Vdd*CN. The voltage across the internal node CSIN of the current source (i.e., the voltage across the parasitic capacitance CPAR) is equal to Vdd - IDAC*R2P, and the amount of charge stored in the parasitic capacitance CPAR is approximately equal to (Vdd - IDAC*2P)*CPAR.

[0067] refer to Figure 7B When the first input logic signal VIN switches from logic low (e.g., VIN = 0V) to logic high (e.g., VIN = 1V), the second capacitor CN is coupled between ground (via the third N-type MOSFET transistor MN31) and the first ground terminal GT1, and the parasitic capacitance CPAR is coupled to the first ground terminal GT1 of the first logic circuit LGC1 (assuming the resistance of the first N-type MOSFET transistor MN11 is negligible). The voltage VR2N at the first ground terminal GT1 will stabilize at IDAC*R2N. The voltage across the second capacitor CN is approximately equal to IDAC*R2N, and the voltage across the parasitic capacitance CPAR is approximately equal to –IDAC*R2N. The new charge stored in the second capacitor CN is approximately equal to -IDAC*R2N*CN, and the new charge stored in the parasitic capacitance CPAR is approximately equal to –IDAC*R2N*CPAR.

[0068] As mentioned above Figure 4The description states that, without the second charge supply circuit CSC2, the difference in charge in the parasitic capacitance CPAR before and after the rising edge transition will cause a transient current flowing through the second adjustable resistor R2N. This transient current leads to a transient voltage drop across resistor R2N, the time constant of which is determined by R2N*CPAR. In contrast, with the help of the second charge supply circuit CSC2, the second capacitor CN can operate to supply an appropriate amount of charge to compensate for the difference in charge in the parasitic capacitance CPAR before and after the rising edge transition. Thus, due to the charging of the parasitic capacitance CPAR, the current IPS flowing through the second adjustable resistor R2N is significantly reduced or essentially eliminated. When the sum of the charge difference in the second capacitor CN and the charge difference in the parasitic capacitance CPAR is equal to zero, the charge difference in the parasitic capacitance CPAR before and after the rising edge transition is perfectly compensated, which can be expressed as:

[0069] (-Vdd-IDAD*R2N)*CN+((Vdd–IDAC*R2P)-(IDAC*R2N))*CPAR=0 (3)

[0070] Therefore, the capacitance of the second capacitor CN can be expressed as:

[0071]

[0072] Therefore, by using a capacitor with a capacitance determined by formula (4) as the second capacitor CN, it is possible to prevent transient voltage VR2N from being generated at the first ground terminal GT1, thereby preventing the input data-dependent behavior of the output current IDAC.

[0073] A second aspect of this disclosure provides a method for compensating parasitic capacitance in a switched voltage controlled current source. The switched voltage controlled current source may include: a current source input terminal for receiving a first input logic signal and a current source output terminal for outputting current; a first logic circuit including a first logic input terminal connected to the current source input terminal, a first logic output terminal for outputting a current control signal, a first supply terminal for connecting to a power supply, and a first ground terminal for connecting to ground; a first resistor coupled between the first logic output terminal and the current source output terminal; a second resistor coupled between the power supply and the first supply terminal; and a third resistor coupled between ground and the first ground terminal; wherein the first logic circuit is operable to selectively couple either the second resistor or the third resistor to the first resistor. The method may include: in response to a first input logic signal switching from a first logic state (e.g., logic high) to a second logic state (e.g., logic low), generating a first amount of charge through a first charge supply circuit to compensate for a first charge difference in a parasitic capacitance formed at an internal node of a current source connected to a first logic output terminal and one end of a first resistor; and in response to a first input logic signal switching from a second logic state to a first logic state, generating a second amount of charge through a second charge supply circuit to compensate for a second charge difference in a parasitic capacitance formed at an internal node of the current source.

[0074] In one embodiment, the first charge supply circuit may include: a first charge supply input connected to a current source input; a first charge supply output connected to a first supply terminal of a first logic circuit; a first internal voltage node; a second logic circuit including a second logic input and a second logic output connected to the first charge supply input, the second logic circuit being configured to have the same functional behavior as the first logic circuit; a first capacitor coupled between the second logic output and the first internal voltage node; a first switch coupled between the first charge supply output and the first internal voltage node, the state of the first switch being controlled by a first input logic signal; and a second switch coupled between the first internal voltage node and a power supply, the state of the second switch being controlled by a second input logic signal having the opposite polarity to the first input logic signal.

[0075] In one embodiment, the second charge supply circuit may include: a second charge supply input connected to a current source input; a second charge supply output connected to a first ground terminal of the first logic circuit; a second internal voltage node; a third logic circuit including a third logic input and a third logic output connected to the second charge supply input, the third logic circuit being configured to have the same functional behavior as the first logic circuit; a second capacitor coupled between the second logic output and the second internal voltage node; a third switch coupled between the second charge supply output and the second internal voltage node, the state of the third switch being controlled by a first input logic signal; and a fourth switch coupled between the second internal voltage node and ground, the state of the fourth switch being controlled by a second input logic signal.

[0076] The description provided herein may be directed to specific implementations. It should be understood that the discussion provided herein is intended to enable those skilled in the art to make and use any subject matter defined herein by the claims.

[0077] It should be understood that the subject matter of the claims is not limited to the implementations and descriptions provided herein, but includes modifications of those implementations, including portions of the implementation and combinations of elements of the different implementations as defined in the claims. It should be understood that in the development of any such implementation, as in any engineering or design project, many implementation-specific decisions should be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it should be understood that such development work can be complex and time-consuming, but remains a routine task of design, manufacture, and production for those skilled in the art who benefit from this invention.

[0078] Various implementations have been referenced in detail, examples of which are illustrated in the accompanying drawings and figures. Numerous specific details are set forth in the detailed description to provide a thorough understanding of the invention presented herein. However, the invention presented herein can be practiced without these specific details. In some other instances, well-known methods, processes, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring the details of the embodiments.

[0079] It should also be understood that although the terms first, second, etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element can be called the second element, and similarly, the second element can be called the first element. The first element and the second element are both elements, but they cannot be considered the same element.

[0080] The terminology used in the description of the invention provided herein is for the purpose of describing particular implementations and is not intended to limit the invention provided herein. As used in the specification of the invention provided herein and in the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. The terms “comprising,” “including,” “comprises,” and / or “including” as used in this specification specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0081] While the foregoing addresses implementations of the various techniques described herein, other and further implementations are possible in accordance with the inventive design herein, as specified in the appended claims. Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as examples of implementing the claims.

Claims

1. A switching voltage-controlled current source, comprising: A current source input terminal for receiving the first input logic signal and a current source output terminal for outputting current; A first logic circuit, the first logic circuit including a first logic input terminal connected to the current source input terminal, a first logic output terminal for outputting a current control signal, a first supply terminal for connecting to a power supply, and a first ground terminal for connecting to ground; A first resistor coupled between the first logic output terminal and the current source output terminal; A second resistor coupled between the power source and the first supply terminal, and a third resistor coupled between the ground and the first ground terminal; The first logic circuit is operable to selectively couple the second resistor or the third resistor to the first resistor. A first charge supply circuit is configured to supply a first amount of charge in response to the first input logic signal switching from a first logic state to a second logic state to compensate for a first charge difference in the parasitic capacitance formed at an internal node of a current source connected to the first logic output terminal and one end of the first resistor; and The second charge supply circuit is configured to supply a second amount of charge in response to the first input logic signal switching from the second logic state to the first logic state to compensate for the second charge difference in the parasitic capacitance formed at the node inside the current source.

2. The switching voltage-controlled current source according to claim 1, wherein, The first charge supply circuit includes: A first charge supply input terminal is connected to the current source input terminal; The first charge supply output terminal is connected to the first supply terminal of the first logic circuit; First internal voltage node; The second logic circuit includes a second logic input terminal connected to the first charge supply input terminal and a second logic output terminal, and the second logic circuit is configured to have the same functional behavior as the first logic circuit. A first capacitor is coupled between the second logic output and the first internal voltage node; A first switch, coupled between the first charge supply output terminal and the first internal voltage node, the state of the first switch being controlled by the first input logic signal; and A second switch is coupled between the first internal voltage node and the power supply, and the state of the second switch is controlled by a second input logic signal having the opposite polarity to the first input logic signal.

3. The switching voltage-controlled current source according to claim 1 or 2, wherein, The second charge supply circuit includes: The second charge supply input terminal is connected to the current source input terminal; The second charge supply output terminal is connected to the first ground terminal of the first logic circuit. Second internal voltage node; A third logic circuit, comprising a third logic input terminal connected to the second charge supply input terminal and a third logic output terminal, the third logic circuit being configured to have the same functional behavior as the first logic circuit; The second capacitor is coupled between the second logic output and the second internal voltage node; A third switch, coupled between the second charge supply output terminal and the second internal voltage node, the state of which is controlled by the first input logic signal; and A fourth switch is coupled between the second internal voltage node and the ground, and the state of the fourth switch is controlled by the second input logic signal.

4. The switching voltage-controlled current source according to any one of the preceding claims, wherein, The resistance of the second resistor and / or the third resistor is adjustable.

5. The switching voltage-controlled current source according to claim 4, wherein, The second resistor includes a first fixed resistor and one or more second fixed resistors, wherein each of the one or more second fixed resistors is connected in series with a fifth switch, and each pair of second fixed resistors and the fifth switch is connected in parallel to the first fixed resistor; and / or, wherein the third resistor includes a third fixed resistor and one or more fourth fixed resistors, wherein each of the one or more fourth fixed resistors is connected in series with a sixth switch, and each pair of fourth fixed resistors and the sixth switch is connected in parallel to the third fixed resistor.

6. The switching voltage-controlled current source according to any one of the preceding claims, wherein, The first switch and the second switch of the first charge supply circuit are both P-type MOSFET transistors, and / or the third switch and the fourth switch of the second charge supply circuit are both N-type MOSFET transistors.

7. The switching voltage-controlled current source according to any one of the preceding claims, wherein, When the first logic circuit decouples the first resistor from the second resistor, the first capacitor of the first charge supply circuit is coupled to the power supply and decoupled from the first charge supply output terminal; and / or, when the first logic circuit couples the first resistor from the second resistor, the first capacitor of the first charge supply circuit is decoupled from the power supply and coupled to the first charge supply output terminal.

8. The switching voltage-controlled current source according to any one of the preceding claims, wherein, When the first logic circuit decouples the first resistor from the third resistor, the second capacitor of the second charge supply circuit is coupled to the ground and decoupled from the second charge supply output terminal; and / or, when the first logic circuit couples the first resistor from the third resistor, the second capacitor of the second charge supply circuit is decoupled from the ground and coupled to the second charge supply output terminal.

9. A switching voltage-controlled current source according to any one of the preceding claims, operable to output a first current when the first input logic signal is in a first state, and to output a second current when the first input logic signal is in a second state, the second current having an absolute value similar to or the same as the first current, but having the opposite polarity.

10. The switching voltage-controlled current source according to any one of the preceding claims, wherein, The second logic circuit of the first charge supply circuit and the third logic circuit of the second charge supply circuit are the same as the first logic circuit, or the second logic circuit of the first charge supply circuit and the third logic circuit of the second charge supply circuit are different from the first logic circuit, but have the same functional behavior as the first logic circuit.

11. The switching voltage-controlled current source according to any one of the preceding claims, wherein, The first logic circuit is an inverter.

12. The switching voltage-controlled current source according to any one of the preceding claims, wherein, The first logic state is logic high, and the second logic state is logic low.

13. A digital-to-analog converter, comprising at least one switching voltage-controlled current source according to any one of the preceding claims.

14. A Delta-Sigma modulator, comprising: At least one digital-to-analog converter as described in claim 13, and At least one integrator is used to receive current from at least one switched voltage controlled current source from at least one digital-to-analog converter.

15. A method for compensating for parasitic capacitance in a switching voltage-controlled current source. The switching voltage-controlled current source includes: A current source input terminal for receiving the first input logic signal and a current source output terminal for outputting current; A first logic circuit, the first logic circuit including a first logic input terminal connected to the current source input terminal, a first logic output terminal for outputting a current control signal, a first supply terminal for connecting to a power supply, and a first ground terminal for connecting to ground; A first resistor coupled between the first logic output terminal and the current source output terminal; A second resistor coupled between the power source and the first supply terminal, and a third resistor coupled between the ground and the first ground terminal; The first logic circuit is operable to selectively couple the second resistor or the third resistor to the first resistor. The method includes: In response to the first input logic signal switching from a first logic state to a second logic state, a first amount of charge is generated through the first charge supply circuit to compensate for the first charge difference in the parasitic capacitance formed at the internal node of the current source connected to the first logic output terminal and one end of the first resistor; and In response to the first input logic signal switching from the second logic state to the first logic state, a second amount of charge is generated through the second charge supply circuit to compensate for the second charge difference in the parasitic capacitance formed at the node inside the current source.

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