Engine component, chip, board card, equipment and processing method of engine component

Abstract

The invention discloses an engine component, a chip, a board card, equipment and a processing method of the engine component, and relates to the field of chips. The engine component comprises a register, a scheduler and a memory, the memory comprises K plates, and K is greater than 1; the register is used for storing N memory access instructions; all or part of the N memory access instructions are memory access instructions with plate conflicts, a plurality of sub-requests in the memory access instructions with plate conflicts comprise at least two sub-requests requesting to access the same plate, and N is greater than 1; the scheduler is used for recombining the N memory access instructions to obtain recombined memory access instructions; sending the recombination memory access instruction to a memory; the recombined memory access instruction is a memory access instruction without plate conflict, and a plurality of sub-requests in the recombined memory access instruction respectively request different plates in the K plates; the memory is used for receiving the recombination memory access instruction; and executing a read-write operation on at least two of the K plates based on the recombined memory access instruction.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an engine component, chip, board, device, and a method for processing the engine component. Background Technology

[0002] A chip consists of memory and a processor. Memory stores data and is composed of multiple banks. The processor processes the data. The addresses of multiple data items processed by the processor may not be contiguous in memory. In this case, a memory access instruction includes multiple sub-requests for non-contiguous addresses, each requesting to access data in the bank corresponding to an address. In some applications, some of these non-contiguous addresses in the memory access instruction may reside in the same bank. When multiple sub-requests in a memory access instruction need to access the same bank, a bank conflict occurs.

[0003] In related technologies, if the first memory access instruction has a block conflict, the sub-requests in the first memory access instruction need to be distributed based on the addresses of each sub-request in the first memory access instruction. In one clock cycle, each block executes one sub-request, and in the next clock cycle, each block executes the next sub-request. After multiple clock cycles, the second memory access instruction can only continue to be executed after all the sub-requests in the first memory access instruction have been executed.

[0004] However, the methods used in this technology result in low utilization of memory modules. Summary of the Invention

[0005] This application provides an engine component, a chip, a board, a device, and a method for processing the engine component. The technical solution is as follows:

[0006] On one hand, an engine component is provided, the engine component including: a register, a scheduler, and a memory, the register being connected to the scheduler, the scheduler being connected to the memory, and the memory including K blocks, where K is greater than 1;

[0007] The register is used to store N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts, and the multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, and N is greater than 1.

[0008] The scheduler is used to reassemble the N memory access instructions to obtain a reassembled memory access instruction; and send the reassembled memory access instruction to the memory; the reassembled memory access instruction is a memory access instruction without block conflicts, and the multiple sub-requests in the reassembled memory access instruction request different blocks among the K blocks respectively;

[0009] The memory is used to receive the reorganization memory access instruction and to perform read and write operations on at least two of the K blocks based on the reorganization memory access instruction.

[0010] On the other hand, a method for processing an engine component is provided, the engine component including: a register, a scheduler, and a memory, the register being connected to the scheduler, the scheduler being connected to the memory, and the memory including K blocks, where K is greater than 1;

[0011] The method includes:

[0012] The register stores N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts, and the multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, and N is greater than 1.

[0013] The scheduler reassembles the N memory access instructions to obtain a reassembled memory access instruction; the reassembled memory access instruction is sent to the memory; the reassembled memory access instruction is a memory access instruction without block conflicts, and the multiple sub-requests in the reassembled memory access instruction request different blocks among the K blocks respectively;

[0014] The memory receives the reorganization access instruction; and performs read and write operations on at least two of the K blocks based on the reorganization access instruction.

[0015] In some embodiments, the N memory access instructions are used to indicate read operations, and the engine component further includes a cache connected to the memory;

[0016] The memory performs read and write operations on at least two of the K blocks based on the reorganization memory access instruction, including:

[0017] The memory records the instruction information corresponding to each sub-request in the reorganization memory access instruction to the pending queue; returns the read data corresponding to each sub-request in the reorganization memory access instruction, and writes the read data to the buffer based on the instruction information in the pending queue; the buffer is used to return the read data to the memory access instruction terminal after all the read data corresponding to the instruction information in the pending queue is ready.

[0018] On the other hand, a chip is provided, the chip comprising: the engine component as described above.

[0019] On the other hand, a board is provided, the board including: the engine component as described above.

[0020] On the other hand, a computer device is provided, the computer device comprising: an engine component as described above, or a chip as described above, or a board as described above.

[0021] On the other hand, a computer device is provided, the computer device comprising: a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the processing method of the engine components as described above.

[0022] On the other hand, a computer-readable storage medium is provided that stores a computer program, which is loaded and executed by a processor to implement the processing method of the engine components as described above.

[0023] On the other hand, a computer program product is provided, the computer program product including computer instructions stored in a computer-readable storage medium, wherein a processor retrieves the computer instructions from the computer-readable storage medium, causing the processor to load and execute them to implement the processing method of the engine component as described above.

[0024] The beneficial effects of the technical solutions provided in this application include at least the following:

[0025] In the event of memory access instruction conflicts, this method can schedule N memory access instructions in parallel. After reassembling these N instructions, a reassembled memory access instruction without conflicts is obtained, enabling access to at least two of the K memory blocks. Compared to related technologies, which require all sub-requests of the first memory access instruction to be executed before the second instruction can proceed, resulting in excessively long waiting times for the second instruction and the idle state of unaccessed blocks during this process, this method improves the utilization rate of memory blocks, thereby enhancing overall memory access performance. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a structural block diagram of a computer system provided in an exemplary embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the related technology provided in an exemplary embodiment of this application;

[0029] Figure 3 This is a schematic diagram of the processing of an engine component provided in an exemplary embodiment of this application;

[0030] Figure 4 This is a schematic block diagram of an engine component provided in an exemplary embodiment of this application;

[0031] Figure 5 This is a schematic block diagram of an engine component provided in an exemplary embodiment of this application;

[0032] Figure 6 This is a schematic block diagram of an engine component provided in an exemplary embodiment of this application;

[0033] Figure 7 This is a schematic diagram of a memory access instruction provided in an exemplary embodiment of this application;

[0034] Figure 8 This is a schematic block diagram of an engine component provided in an exemplary embodiment of this application;

[0035] Figure 9 This is a schematic diagram of the overall architecture of an engine component provided in an exemplary embodiment of this application;

[0036] Figure 10 This is a flowchart of a processing method for an engine component provided in an exemplary embodiment of this application;

[0037] Figure 11 This is a schematic block diagram of a chip provided in an exemplary embodiment of this application;

[0038] Figure 12 This is a schematic block diagram of a board provided in an exemplary embodiment of this application;

[0039] Figure 13 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0040] Figure 14 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0041] Figure 15 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0042] Figure 16 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0043] Figure 17 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0046] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0047] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0048] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the collection of user-related data (e.g., instructions and operations related to engine components, computer devices, and chips). These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their data is being collected. This ensures that the application only begins the steps for collecting user-related data after receiving confirmation from the user regarding the prompt interface or pop-up; otherwise (i.e., without confirmation from the user), the steps for collecting user-related data end, meaning no user-related data is collected. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of related user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0049] First, let me briefly introduce the terms used in the embodiments of this application.

[0050] Chip: Also known as an artificial intelligence (AI) chip, it includes a processor and memory. The processor is used to process data.

[0051] Registers are used for temporary storage of data and / or instructions. Types of registers include: Data Register, Instruction Register, Status Register, and Program Counter.

[0052] Memory: also known as a storage system, is used to store data and / or programs, and can be a vector memory. Memory consists of multiple banks. Each bank can only perform one data access per clock cycle (T), but multiple banks can perform data access in parallel per clock cycle.

[0053] Figure 1 This is a structural block diagram of a computer system provided in an exemplary embodiment of this application. The computer system 100 can be implemented as a hardware architecture that serves as an engine component, or as a system architecture that implements a processing method that serves as an engine component. The computer system 100 includes a terminal 120 and a server 140.

[0054] In some embodiments, terminal 120 includes the engine component of this embodiment, or terminal 120 includes a chip that includes the engine component of this embodiment. Terminal 120 may be an electronic device such as a mobile phone, tablet computer, vehicle terminal (vehicle system), wearable device, PC (Personal Computer), unmanned reservation terminal, etc., and this application embodiment does not limit it to this.

[0055] In some embodiments, server 140 includes the engine component of this embodiment, or server 140 includes a board that includes the engine component of this embodiment. Server 140 may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud servers, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Server 140 may be a backend server for terminal 120, used to provide backend services for the data operation and processing of terminal 120.

[0056] Cloud technology refers to a hosting technology that unifies hardware, software, and network resources within a wide area network (WAN) or local area network (LAN) to achieve data computing, storage, processing, and sharing. Based on the cloud computing business model, cloud technology encompasses network technology, information technology, integration technology, management platform technology, and application technology. It can form resource pools, providing flexible and convenient on-demand access. Cloud computing technology will become a crucial support. Backend services of technical network systems require substantial computing and storage resources, such as video websites, image websites, and many portal websites. With the rapid development and application of the internet industry, every item may have its own identification mark in the future, requiring transmission to backend systems for logical processing. Data at different levels will be processed separately, and various industry data will require robust system support, which can only be achieved through cloud computing.

[0057] Optionally, server 140 can also be implemented as a node in a blockchain system. Blockchain is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and cryptographic algorithms. Essentially, a blockchain is a decentralized database, a chain of data blocks linked using cryptographic methods. Each data block contains information about a batch of network transactions, used to verify the validity of the information (anti-counterfeiting) and generate the next block. A blockchain can include a blockchain underlying platform, a platform product service layer, and an application service layer.

[0058] The terminal 120 and the server 140 can communicate via a network, such as a wired or wireless network. In the processing method of the engine component provided in this application embodiment, the executing entity for each step can be the engine component in a computer device, which includes the terminal 120 and / or the server 140.

[0059] A chip consists of memory and a processor. Memory stores data and is composed of multiple banks. The processor processes the data. The addresses of multiple data items processed by the processor may not be contiguous in memory. In this case, a memory access instruction includes multiple sub-requests for non-contiguous addresses, each requesting to access data in the bank corresponding to an address. In some applications, some of these non-contiguous addresses in the memory access instruction may reside in the same bank. When multiple sub-requests in a memory access instruction need to access the same bank, a bank conflict occurs.

[0060] In related technologies, if a memory access instruction encounters a block conflict, the sub-requests within the first memory access instruction need to be distributed based on their addresses. In one clock cycle, each block executes one sub-request; in the next clock cycle, each block executes the next sub-request. This process continues for multiple clock cycles until all sub-requests in the first memory access instruction have been executed before the second memory access instruction can proceed. However, this approach results in an excessively long waiting time for the second memory access instruction. During this process, unaccessed blocks remain idle, leading to low memory block utilization.

[0061] For example, refer to Figure 2 Memory access instructions include request vector instructions (req_vector). Assume the memory consists of four banks: bank 0 through bank 3. Each bank can only perform one data access per clock cycle (T), and the four banks can perform data accesses in parallel. Assume the request vector instruction includes eight sub-requests: sub-request 0, corresponding to bank 3 (req0 bank3); sub-request 1, corresponding to bank 1 (req1 bank1); sub-request 2, corresponding to bank 1 (req2 bank1); sub-request 3, corresponding to bank 2 (req3 bank2); sub-request 4, corresponding to bank 1 (req4 bank1); sub-request 5, corresponding to bank 1 (req5 bank1); sub-request 6, corresponding to bank 3 (req6 bank3); and sub-request 7, corresponding to bank 3 (req7 bank3).

[0062] The relevant technology handles this by splitting the sub-requests in a vector memory access instruction into different bank request queues based on the requested blocks. The specific access order is as follows: at time T0, block 1 / 2 / 3 accesses (req1 / 3 / 0) are executed; at time T1, block 1 / 3 accesses (req2 / 6) are executed; at time T2, block 1 / 3 accesses (req4 / 7) are executed; and at time T3, block 1 accesses (req5) are executed. Only after all sub-requests in the vector memory access instruction have been issued can subsequent vector memory access instructions begin scheduling. Since this vector memory access instruction requires four clock cycles (T) to complete the issuance of all sub-requests, subsequent vector memory access instructions cannot be scheduled until time T4. Therefore, if the current vector memory access instruction has severe block conflicts, the waiting time for subsequent vector memory access instructions is too long. During this process, unaccessed blocks remain idle, resulting in low utilization of memory blocks.

[0063] This embodiment supports parallel scheduling of multiple memory access instructions, which can improve the utilization of memory blocks and thus enhance overall memory access performance. (Reference) Figure 3 Taking two memory access instructions as an example, these include vector memory access instruction 0 (req_vector0) and vector memory access instruction 1 (req_vector1). It's understandable that in practical applications, more memory access instructions can be scheduled in parallel. Assume the memory consists of four banks: bank0-bank3. Each bank can only perform one data access per clock cycle (T), and the four banks can perform data accesses in parallel. Assume vector memory access instruction 0 includes eight sub-requests: sub-request 0, corresponding to bank3 (req0 bank3); sub-request 1, corresponding to bank1 (req1 bank1); sub-request 2, corresponding to bank1 (req2 bank1); sub-request 3, corresponding to bank2 (req3 bank2); sub-request 4, corresponding to bank1 (req4 bank1); sub-request 5, corresponding to bank1 (req5 bank1); sub-request 6, corresponding to bank3 (req6 bank3); and sub-request 7, corresponding to bank3 (req7 bank3). Suppose that the vector memory access instruction 1 includes 3 sub-requests: sub-request 0', corresponding to bank 0 (req0'bank0); sub-request 1', corresponding to bank 0 (req1'bank0); and sub-request 2', corresponding to bank 2 (req2'bank2).

[0064] The processing method in this embodiment is as follows: Based on the blocks requested by the sub-requests in Vector Memory Access Instructions 0 and 1, the sub-requests in Vector Memory Access Instructions 0 and 1 are distributed, and different sub-requests enter the corresponding block request queues. The specific access order is as follows: at time T0, block 0 / 1 / 2 / 3 access is executed for req0' / 1 / 3 / 0; at time T1, block 0 / 1 / 2 / 3 access is executed for req1' / 2 / 2' / 6; at time T2, block 1 / 3 access is executed for req4 / 7; and at time T3, block 1 access is executed for req5. Vector Memory Access Instructions 0 and 1 are scheduled in parallel, requiring only 4 clock cycles (T) to complete the issuance of all sub-requests in Vector Memory Access Instructions 0 and 1. This maximizes the access of more blocks in the memory per clock cycle, improving the utilization rate of blocks in the memory and thus enhancing the overall memory access performance.

[0065] Figure 4This is a schematic block diagram of an engine component 200 provided in an exemplary embodiment of this application. The engine component 200 includes: a register 10, a scheduler 20, and a memory 30. The register 10 is connected to the scheduler 20, and the scheduler 20 is connected to the memory 30. The memory 30 includes K banks, where K is greater than 1. Optionally, the connection can be via physical wiring or a communication connection.

[0066] Register 10 is used to store N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts. The multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, and N is greater than 1.

[0067] Memory access instructions, also known as memory access requests, are used to request access to all or part of K blocks. A single memory access instruction can include multiple sub-requests, each requesting access to one of the K blocks. Each sub-request includes an address indicating the specific block to be accessed. In some embodiments, computation of data in the chip is performed in vector form, and the memory access instruction can be a vector memory access instruction (req_vector). Vector memory access instructions are memory access instructions for processing vector data. A vector memory access instruction includes multiple sub-requests with independent addresses, which are combined in vector form.

[0068] For a memory access instruction containing multiple sub-requests, each sub-request can be used to request access to a different module out of K modules, or at least two sub-requests can be used to request access to the same module out of K modules. For example, memory access instruction 0 includes three sub-requests: sub-request 0, corresponding to module 0; sub-request 1, corresponding to module 1; and sub-request 2, corresponding to module 2. Similarly, memory access instruction 1 includes three sub-requests: sub-request 0, corresponding to module 0; sub-request 1, corresponding to module 0; and sub-request 2, corresponding to module 2.

[0069] A memory access instruction is considered to have a block conflict if it contains at least two sub-requests requesting access to the same block. A memory access instruction without block conflicts can complete the issuance of all sub-requests in a single clock cycle. However, a memory access instruction with block conflicts requires multiple clock cycles to complete the issuance of all sub-requests; the number of clock cycles required is equal to the number of sub-requests on the most conflicting block. The more sub-requests a block has, the more severe the block conflict is.

[0070] In this embodiment, N memory access instructions are allowed to be scheduled in parallel. All or some of these N memory access instructions are memory access instructions with sector conflicts. For example, each sub-request in a memory access instruction with sector conflicts requests access to the same sector, or at least two sub-requests in a memory access instruction with sector conflicts request access to the same sector, while the other sub-requests request access to other sectors respectively. For example, memory access instruction 0 includes three sub-requests: sub-request 0, corresponding to sector 0; sub-request 1, corresponding to sector 0; and sub-request 2, corresponding to sector 0. Therefore, memory access instruction 0 is a memory access instruction with sector conflicts, and each sub-request in memory access instruction 0 requests access to sector 0. Memory access instruction 1 includes three sub-requests: sub-request 0, corresponding to sector 0; sub-request 1, corresponding to sector 0; and sub-request 2, corresponding to sector 1. Therefore, memory access instruction 1 is a memory access instruction with sector conflicts, and two sub-requests in memory access instruction 1 request access to sector 0, while one sub-request requests access to sector 1.

[0071] For example, register 10 is used to store N memory access instructions as temporary storage to facilitate the subsequent scheduling of these N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts, and the multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, where N is greater than 1.

[0072] Scheduler 20 is used to reassemble N memory access instructions to obtain reassembled memory access instructions; and sends the reassembled memory access instructions to memory 30; the reassembled memory access instructions are memory access instructions without block conflicts, and the multiple sub-requests in the reassembled memory access instructions request different blocks in K blocks respectively.

[0073] Reassembly refers to the recombining of multiple sub-requests from N memory access instructions. This can involve recombining multiple sub-requests from different memory access instructions within the N instructions, or recombining multiple sub-requests from the same memory access instruction. A reassembled memory access instruction is the memory access instruction obtained after reassembling N memory access instructions; it can also be called a reassembled memory access request. Since all or some of the N memory access instructions are memory access instructions with board conflicts, refer to... Figure 2 In an example implementation, if N memory access instructions are not reorganized, subsequent memory access instructions will have long waiting times and low utilization of memory blocks. Therefore, the purpose of reorganizing N memory access instructions is to obtain reorganized memory access instructions. Reorganized memory access instructions are memory access instructions without block conflicts, that is, multiple sub-requests in the reorganized memory access instructions request different blocks in K blocks respectively.

[0074] Since some or all of the N memory access instructions are memory access instructions with block conflicts, each conflicting instruction requires multiple clock cycles to complete the issuance of all its sub-requests. The specific number of clock cycles required depends on the number of sub-requests on the most conflicting block. Each clock cycle can reassemble the N memory access instructions into a corresponding reassembled memory access instruction. Therefore, the number of reassembled memory access instructions obtained from the N instructions, and the number of clock cycles required to execute these reassembled instructions, are related to the number of sub-requests on the most conflicting block corresponding to the N instructions. When N is a fixed value, meaning the number of memory access instructions scheduled in parallel is finite, the number of clock cycles required to execute the reassembled memory access instructions is equal to the number of sub-requests on the most conflicting block corresponding to the N instructions.

[0075] Scheduler 20 can run in parallel to schedule N memory access instructions stored in scheduler register 10. For example, scheduler 20 is used to reassemble the N memory access instructions to obtain reassembled memory access instructions; and send the reassembled memory access instructions to memory 30; the reassembled memory access instructions are memory access instructions without block conflicts, and the multiple sub-requests in the reassembled memory access instructions request different blocks in K blocks respectively.

[0076] In this embodiment, to maximize the utilization of memory blocks, the multiple sub-requests in the reorganization memory access instruction can request different blocks of at least two of the K blocks, ensuring that as many memory blocks as possible are accessed each clock cycle. Ideally, the multiple sub-requests in the reorganization memory access instruction would request each of the K blocks, ensuring that all memory blocks are accessed each clock cycle, thus maximizing the utilization of memory blocks.

[0077] The memory 30 is used to receive reconfiguration memory access instructions and perform read and write operations on at least two of the K blocks based on the reconfiguration memory access instructions.

[0078] Each of the N memory access instructions requests access to all or part of the K blocks, specifically performing read or write operations on the blocks. Read and write operations include either read operations or write operations; a read operation reads specified data from a block, while a write operation writes specified data to a block.

[0079] Since the reconfiguration memory access instruction is a memory access instruction without block conflicts, the multiple sub-requests in the reconfiguration memory access instruction request different blocks among the K blocks respectively. For example, memory 30 is used to receive the reconfiguration memory access instruction and perform read / write operations on at least two blocks among the K blocks based on the reconfiguration memory access instruction. Optionally, when N memory access instructions and the reconfiguration memory access instruction are used to indicate a read operation, after performing the read operation on at least two blocks among the K blocks based on the reconfiguration memory access instruction, the read data is also returned to the memory access instruction end.

[0080] In summary, the engine component provided in this application includes: a register, a scheduler, and a memory. The register is connected to the scheduler, and the scheduler is connected to the memory. The memory includes K blocks, where K is greater than 1. The register is used to store N memory access instructions. All or part of the N memory access instructions are memory access instructions with block conflicts. The multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, where N is greater than 1. The scheduler is used to reassemble the N memory access instructions to obtain reassembled memory access instructions. The reassembled memory access instructions are memory access instructions without block conflicts. The multiple sub-requests in the reassembled memory access instructions request different blocks in the K blocks respectively. The memory is used to receive the reassembled memory access instructions and perform read and write operations on at least two blocks in the K blocks based on the reassembled memory access instructions. Therefore, in the case of block conflicts in memory access instructions, N memory access instructions can be scheduled in parallel. After reorganizing the N memory access instructions, a reorganized memory access instruction without block conflicts is obtained, realizing access to at least two of the K blocks of memory. Compared with related technologies, which require all sub-requests of the first memory access instruction to be executed before the second memory access instruction can be executed, resulting in excessively long waiting time for the second memory access instruction, and the idle state of unaccessed blocks during this process, the utilization rate of blocks in memory is improved, thereby improving the overall memory access performance.

[0081] In some embodiments, for each of the N memory access instructions, each sub-request within each memory access instruction carries an address, which may be contiguous or non-contiguous, and the address corresponds to a block. When reassembling the N memory access instructions, reassembly is performed based on these addresses, so that each sub-request in the reassembled memory access instruction requests different blocks in the K blocks respectively.

[0082] Scheduler 20 is used to reassemble the sub-requests corresponding to at least two of the K blocks based on the addresses of each sub-request in each of the N memory access instructions, to obtain reassembled memory access instructions.

[0083] For example, scheduler 20 is configured to determine the block corresponding to the address of each sub-request in each of the N memory access instructions, to obtain the sub-requests corresponding to at least two blocks out of K blocks, and to reassemble the sub-requests corresponding to at least two blocks out of K blocks to obtain a reassembled memory access instruction. Specifically, in one clock cycle, one sub-request corresponding to at least two blocks out of K blocks is reassembled to obtain the reassembled memory access instruction for that clock cycle. In the next clock cycle, the next sub-request corresponding to at least two blocks out of K blocks is reassembled to obtain the reassembled memory access instruction for that clock cycle, until all sub-requests in each of the N memory access instructions have been issued.

[0084] In this embodiment, N memory access instructions can be scheduled in parallel, and the sub-requests can be reassembled based on the addresses of each sub-request in each of the N memory access instructions to obtain reassembled memory access instructions without block conflicts, which is beneficial for subsequent access to more blocks of memory.

[0085] In some embodiments, since N memory access instructions are scheduled in parallel, N registers 10 and N schedulers 20 can be configured accordingly. There are N registers 10, each corresponding to one of the N memory access instructions. One register 10 of the N registers 10 is used to store any one of the N memory access instructions. There are N parallel schedulers 20, each corresponding one-to-one with one of the N registers 10. That is, one register 10 of the N registers 10 is used to store any one of the N memory access instructions, and one scheduler 20 of the N schedulers 20 is used to schedule the memory access instruction stored in one register 10 of the N registers 10.

[0086] For example, Figure 5 This is a schematic block diagram of an engine component 200 provided in an exemplary embodiment of this application. The N schedulers 20 include: N bank splitter modules 22 and K multiplexers (muxes) 24. Each of the K multiplexers 24 corresponds one-to-one with a bank segment, and each of the N bank splitter modules 22 is connected to one of the K multiplexers 24. That is, each of the N memory access instructions corresponds to one bank splitter module 22, each of the N bank splitter modules 22 is connected to one of the K multiplexers 24, and one of the K multiplexers 24 corresponds to one bank segment among the K bank segments. Thus, after each of the N bank splitter modules 22 splits each sub-request in each of the N memory access instructions, each sub-request can be sent to the multiplexer 24 corresponding to the bank segment it requests.

[0087] The N-block splitting module 22 is used to determine the sub-requests corresponding to the same block in the N memory access instructions based on the addresses of each sub-request in each of the N memory access instructions; and to send the sub-requests corresponding to the same block in the N memory access instructions to the same multiplexer 24 among the K multiplexers 24.

[0088] One of the N partition splitting modules 22 can split multiple sub-requests of one of the N memory access instructions. After splitting, each sub-request can be sent to the multiplexer 24 corresponding to the requested partition.

[0089] For example, the N-block splitting module 22 is used to determine the sub-requests corresponding to the same block in the N memory access instructions based on the addresses of each sub-request in each of the N memory access instructions; and to send the sub-requests corresponding to the same block in the N memory access instructions to the same multiplexer 24 among the K multiplexers 24. Specifically, the sub-requests corresponding to the same block in the N memory access instructions are sent to the same multiplexer 24 among the K multiplexers 24 in sequence according to the order of the sub-requests corresponding to the same block in the N memory access instructions. Optionally, this order can be determined based on the instruction order of the N memory access instructions and the order of each sub-request in each memory access instruction from low to high bits.

[0090] K multiplexers 24 are used to receive the sub-requests corresponding to each of the K blocks, reassemble the sub-requests corresponding to at least two of the K blocks, and obtain the reassembled memory access instruction.

[0091] One of the K multiplexers 24 corresponds to one module. A multiplexer 24 can receive multiple sub-requests from its corresponding module. These multiple sub-requests can be the same memory access instruction from N memory access instructions, or they can be different memory access instructions from N memory access instructions. For example, if multiplexer 0 corresponds to module 0, then multiplexer 0 can receive multiple sub-requests from module 0. These multiple sub-requests from module 0 can be: all from memory access instruction 0, or some from memory access instruction 0 and some from memory access instruction 1.

[0092] For example, K multiplexers 24 are used to receive sub-requests corresponding to each of the K blocks, and reassemble the sub-requests corresponding to at least two of the K blocks to obtain a reassembled memory access instruction. Specifically, each of the K multiplexers 24 can push the sub-requests it receives into the corresponding block request queue, and perform reassembly based on the sub-requests in at least two of the K block request queues to obtain a reassembled memory access instruction.

[0093] In this embodiment, it is possible to split each of the N memory access instructions, which can improve the processing efficiency of each memory access instruction. Furthermore, it is possible to reassemble the sub-requests corresponding to different blocks after splitting, so as to obtain reassembled memory access instructions without block conflicts, thereby improving the generation efficiency of reassembled memory access instructions.

[0094] In some embodiments, each of the N memory access instructions corresponds to a partitioning module 22, and the memory includes K partitions. The partitioning module 22 may include K partitioning units 220, and each of the K partitioning units 220 can perform the partitioning of a sub-request corresponding to its current partition. This improves the processing efficiency for each of the N memory access instructions.

[0095] For example, Figure 6 This is a schematic block diagram of an engine component 200 provided in an exemplary embodiment of this application. Each of the N partition splitting modules 22 includes: K partition splitting units 220, each of the K partition splitting units 220 corresponding to one of the K partitions. The j-th partition splitting unit 220 corresponding to the j-th partition is connected to the j-th multiplexer 24 corresponding to the j-th partition among the K multiplexers 24; j is less than or equal to K. That is, each partition splitting module 22 is composed of K partition splitting units 220, each of the K partition splitting units 220 corresponds to one partition, and each partition splitting unit 220 can be further connected to the multiplexer 24 corresponding to its corresponding partition. In this way, after each partition splitting unit 220 splits the sub-requests of its corresponding partition in the memory access instruction, it can directly send the split sub-requests to the corresponding multiplexer 24.

[0096] The j-th segmentation unit 220 of the i-th segmentation module 22 is used to determine the sub-request corresponding to the j-th segment in the i-th memory access instruction based on the address of each sub-request in the i-th memory access instruction of N memory access instructions; and send the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer 24 among the K multiplexers 24; i is less than or equal to N.

[0097] N memory access instructions correspond to N partitioning modules 22, and one memory access instruction corresponds to one partitioning module 22. For the i-th memory access instruction among the N memory access instructions, the i-th memory access instruction corresponds to the i-th partitioning module 22. The i-th partitioning module 22 includes K partitioning units 220.

[0098] For example, the j-th segmentation unit 220 of the K segmentation units 220 of the i-th segmentation module 22 is used to determine the sub-request corresponding to the j-th segment in the i-th memory access instruction based on the address of each sub-request in the i-th memory access instruction of N memory access instructions; and send the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer 24 among the K multiplexers 24.

[0099] In this embodiment, for each of the N memory access instructions, the sub-requests corresponding to each block in each memory access instruction can be split, which realizes targeted splitting for the current block, improves the processing efficiency of each memory access instruction, and also ensures the accuracy of the splitting.

[0100] In some embodiments, continue to refer to Figure 6 The j-th segmentation unit 220 includes a bankmask unit 221 and a leading zero detect (lzd) unit 222, with the bankmask unit 221 connected to the leading zero detect unit 222. That is, each segmentation module 22 includes K segmentation units 220, and each of the K segmentation units 220 includes a bankmask unit 221 and a leading zero detect unit 222. Specifically, the bankmask unit 221 in the j-th segmentation unit 220 is used to determine whether each sub-request corresponds to the j-th segment and generate a K-bit result vector. The leading zero detect unit 222 in the j-th segmentation unit 220 is used to detect the position of the sub-request corresponding to the j-th segment in the result vector and select these sub-requests corresponding to the j-th segment.

[0101] The module masking unit 221 is used to mask the sub-requests in the i-th memory access instruction that do not correspond to the j-th module based on the addresses of each sub-request in the i-th memory access instruction among N memory access instructions, so as to obtain the i-th masked instruction.

[0102] Specifically, the block masking unit 221 in the j-th block splitting unit 220 is used to determine the sub-requests corresponding to the j-th block and the sub-requests not corresponding to the j-th block in the i-th memory access instruction based on the addresses of each sub-request in the i-th memory access instruction from the N memory access instructions, and to mask the sub-requests not corresponding to the j-th block in the i-th memory access instruction, thus obtaining the i-th masked instruction. Optionally, the masking method includes at least one of the following: replacing the sub-requests not corresponding to the j-th block with empty, deleting the address, or setting it to invalid.

[0103] The leading zero detection unit 222 is used to detect the number of leading zeros corresponding to the i-th masked instruction, and based on the number of leading zeros, select the sub-request corresponding to the j-th block in the i-th masked instruction; and send the sub-request corresponding to the j-th block in the i-th memory access instruction to the j-th multiplexer 24 among the K multiplexers 24.

[0104] For the i-th masked instruction generated by the block masking unit 221 in the j-th block splitting unit 220, the i-th masked instruction includes masked sub-requests that do not correspond to the j-th block, as well as sub-requests that correspond to the j-th block. By detecting the number of leading zeros corresponding to the i-th masked instruction, it is possible to start the detection from the least significant bit of the i-th masked instruction until the first sub-request corresponding to the j-th block is detected, obtain the position of the sub-request, select it, and send it to the corresponding j-th multiplexer 24, continuing the above selection logic until all sub-requests corresponding to the j-th block are selected.

[0105] Specifically, the leading zero detection unit 222 in the j-th segment splitting unit 220 is used to detect the number of leading zeros corresponding to the i-th masked instruction, and based on the number of leading zeros, select the sub-request corresponding to the j-th segment in the i-th masked instruction; and send the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer 24 among the K multiplexers 24. Optionally, the sub-requests corresponding to the j-th segment in the i-th masked instruction can be selected sequentially from low bit to high bit, and the sub-requests corresponding to the j-th segment in the i-th memory access instruction can be sent to the j-th multiplexer 24 among the K multiplexers 24.

[0106] In this embodiment, for each of the N memory access instructions, for the current block splitting unit, the block masking unit in the block splitting unit can mask all the sub-requests in each memory access instruction that are not for the current block, and generate a K-bit result vector. Thus, the leading zero detection unit can detect the sub-requests corresponding to the current block and transmit them, which can improve the accuracy of splitting and the precision of transmission.

[0107] In some embodiments, to avoid repeatedly selecting and transmitting the sub-request corresponding to the j-th module in the i-th masking instruction, after each selection of a sub-request corresponding to the j-th module, the selected sub-request is invalidated to facilitate the selection and transmission of the next sub-request corresponding to the j-th module.

[0108] The leading zero detection unit 222 is used to set the sub-request corresponding to the j-th section in the i-th masking instruction to invalid after selecting the sub-request corresponding to the j-th section in the i-th masking instruction.

[0109] For example, the leading zero detection unit 222 in the j-th segment splitting unit 220 is further configured to set the sub-request corresponding to the j-th segment in the i-th masked instruction to invalid after selecting the sub-request corresponding to the j-th segment in the i-th masked instruction.

[0110] The method in this embodiment can avoid the repeated selection and issuance of the sub-request corresponding to the j-th block in each memory access instruction, thereby improving the accuracy of issuance.

[0111] As an example, Figure 7 This is a schematic diagram of a memory access instruction provided in an exemplary embodiment of this application. The memory includes four banks: bank 0 to bank 3. The memory access instruction is a vector memory access instruction (req_vector), which includes eight sub-requests: sub-request 0, corresponding to bank 3 (req0bank3); sub-request 1, corresponding to bank 1 (req1bank1); sub-request 2, corresponding to bank 1 (req2bank1); sub-request 3, corresponding to bank 2 (req3bank2); sub-request 4, corresponding to bank 1 (req4bank1); sub-request 5, corresponding to bank 1 (req5bank1); sub-request 6, corresponding to bank 3 (req6bank3); and sub-request 7, corresponding to bank 3 (req7bank3). This vector memory access instruction corresponds to a bankspliter module, which includes bankspliter units corresponding to banks 0 to 3 respectively. Each bankspliter unit includes a bank mask unit and a leading zero detection (lzd) unit. For the segmentation unit (bank1 bankspliter) corresponding to segment 1 in the segmentation module corresponding to the vector memory access instruction, after the segmentation masking unit (bank1 mask), all sub-requests not corresponding to segment 1 are masked, resulting in a masked instruction. The leading zero detection (lzd) unit starts detecting from the leftmost end of the masked instruction until the first sub-request corresponding to segment 1 is detected, i.e., the number of leading zeros is equal to 1, lzd = 1, sub-request 1 and corresponding segment 1 (req1 bank1) are detected, the position of sub-request 1 is obtained, sub-request 1 is selected and issued to the multiplexer (mux) corresponding to segment 1. After selecting sub-request 1, sub-request 1 needs to be invalidated. The above selection logic continues until all sub-requests corresponding to segment 1 are selected, then the vector memory access instruction (req_vector) is issued.

[0112] In some embodiments, each of the K blocks corresponds to a block request queue, which stores sub-requests to be issued. The block splitting module 22 of each of the N memory access instructions can push a new sub-request into the block request queue of the corresponding block of the K multiplexers 24. For a block's block request queue, the specific pushing logic is as follows: starting from the head of the N memory access instruction queue, push the first valid sub-request corresponding to that block.

[0113] For example, N memory access instructions are 3 vector memory access instructions. Assume that vector memory access instruction 0 (req_vector0) is at the head of the queue. At the current moment, vector memory access instruction 0 (req_vector0) does not have a sub-request corresponding to bank0, while vector memory access instructions 1 (req_vector1) and 2 (req_vector2) do. In this case, the sub-request corresponding to bank0 from vector memory access instruction 1 (req_vector1) is pushed into the bank0 request queue. Only after all the sub-requests corresponding to bank0 from vector memory access instruction 1 (req_vector1) are pushed into the bank0 request queue can the sub-request corresponding to bank0 from vector memory access instruction 2 (req_vector2) be pushed into the bank0 request queue.

[0114] K multiplexers 24 are used to push the sub-requests corresponding to each of the K blocks into the block request queue corresponding to each of the K blocks; and to reassemble the sub-requests at the head of the block request queues of at least two of the K blocks to obtain the reassembled memory access instruction.

[0115] The sub-requests at the head of the request queues for at least two of the K blocks can be reassembled into a single memory access instruction and sent to memory 30. For example, K multiplexers 24 are used to push the sub-requests corresponding to each of the K blocks into the respective request queues of each of the K blocks; and reassemble the sub-requests at the head of the request queues for at least two of the K blocks to obtain the memory access instruction. In a specific example, to ensure that as many blocks as possible are accessed, the sub-requests at the head of the request queues for each of the K blocks can be reassembled to obtain the memory access instruction.

[0116] In this embodiment, sub-requests corresponding to different blocks in N memory access instructions can be reorganized to obtain reorganized memory access instructions. This ensures that the reorganized memory access instructions do not have block conflicts, allowing more blocks in the memory to be accessed and improving the utilization rate of the memory blocks.

[0117] In one possible implementation, the N memory access instructions stored in register 10 are controlled and input by the memory access instruction control unit 40. Figure 8 This is a schematic block diagram of an engine component 200 provided in an exemplary embodiment of this application. Engine component 200 further includes a memory access instruction control unit 40, which is connected to register 10 and is responsible for managing N memory access instructions. In some embodiments, the N memory access instructions are maintained using a first-in-first-out queue. New memory access instructions are written to the tail of the queue. After all sub-requests in the memory access instructions at the head of the queue have been issued to subsequent pipelines, the memory access instructions at the head of the queue are popped from the queue.

[0118] The memory access instruction control unit 40 is used to write the preceding memory access instruction to the head of the queue and the following memory access instruction to the tail of the queue, and to input the N memory access instructions.

[0119] The memory access instruction control unit 40 is responsible for managing N memory access instructions. For example, the memory access instruction control unit 40 is used to write the preceding memory access instruction to the head of the queue, the following memory access instruction to the tail of the queue, and to input the N memory access instructions. When inputting the N memory access instructions, the N instructions are input one by one; new memory access instructions can be continuously input as the memory access process progresses.

[0120] In this embodiment, the management and maintenance of memory access instructions are implemented to provide support for subsequent scheduling.

[0121] Optionally, the N memory access instructions are used to indicate a write operation or a read operation. In some embodiments, the N memory access instructions are used to indicate a read operation, that is, to read specified data from the block. (Continue to refer to...) Figure 8 Engine component 200 also includes a cache 50, which is connected to memory 30. Cache 50 can be a reorder buffer. The reorder buffer can also be maintained using a first-in-first-out queue.

[0122] The memory 30 is used to record the instruction information corresponding to each sub-request in the memory reorganization instruction to the pending queue; return the read data corresponding to each sub-request in the memory reorganization instruction, and write the read data to the buffer 50 based on the instruction information in the pending queue.

[0123] If N memory access instructions are used to indicate a read operation, then a reassembly memory access instruction is used to indicate a read operation. Optionally, the instruction information of a sub-request includes: a sub-request identifier, the instruction identifier of the memory access instruction to which the sub-request belongs, the number of sub-requests included in the memory access instruction to which the sub-request belongs, the position of the sub-request in the memory access instruction, the position of the sub-request in the reassembly memory access instruction, the opcode indicating what type of read operation to perform, the source operand indicating the source of the data, the target operand indicating the storage location, and at least one of the addressing modes.

[0124] The outstanding queue (outs_queue), also known as the unfinished task queue, is a first-in, first-out (FIFO) data structure. For example, memory 30 records the instruction information corresponding to each sub-request in a memory access instruction reorganization into the outstanding queue; it returns the read data corresponding to each sub-request in the memory access instruction reorganization, and writes the read data to cache 50 based on the instruction information in the outstanding queue. Specifically, for read data corresponding to a sub-request, based on the instruction identifier of the memory access instruction to which the sub-request belongs and the position of the sub-request within the memory access instruction, the read data corresponding to the sub-request is written to the corresponding position in the memory access instruction within cache 50.

[0125] Buffer 50 is used to return read data to the memory access instruction terminal after all read data corresponding to the instruction information in the pending queue is ready.

[0126] The memory access instruction end refers to the end that requests to read data. For example, buffer 50 is used to return the read data to the memory access instruction end after all the read data corresponding to the instruction information in the pending queue is ready.

[0127] This embodiment implements the execution of read operations and the return of the corresponding read data, which can improve the overall execution efficiency of memory access instructions.

[0128] As an example, the engine components provided in the embodiments of this application are described in detail below with reference to the schematic diagrams.

[0129] 1. Product Realization

[0130] In the fields of chips, processors, high-performance processors, and high-performance AI processors, vector memory access instructions can achieve complex memory addressing and have a wide range of applications. For example, they are used in data-parallel computing and high-performance computing scenarios, such as image data processing, scientific computing, machine learning, and game data processing. The memory access engine design with parallel scheduling of multiple memory access instructions provided in this application embodiment has high performance and consumes less chip area, effectively improving product competitiveness.

[0131] 2. Technical Implementation

[0132] Figure 9 This is a schematic diagram of the overall architecture of an engine component provided in an exemplary embodiment of this application.

[0133] Taking N=3 as an example. The memory access instruction is a vector memory access instruction (req_vector). The memory 30 is implemented as a vector memory 31, which includes K banks, where K is greater than 1. The cache 50 is implemented as a reorder buffer 51. The three registers 10 store three vector memory access instructions. Each vector memory access instruction corresponds to a bank splitter module. Each bank splitter module has K bank splitter units 220. Each bank splitter unit 220 corresponds to one bank. Each bank splitter unit 220 is connected to K multiplexers 24. Each multiplexer 24 corresponds to one bank. Each bank corresponds to a bank request queue. Each bank splitter unit 220 includes a bank mask unit 221 and a leading zero detection (lzd) unit 222.

[0134] The connections are as follows: one register 10 is connected to K partitioning units 220 in a partitioning module; each of the K partitioning units 220 is connected to K multiplexers 24; the K multiplexers 24 are connected to a vector memory 31; the vector memory 31 is connected to a reordering cache 51; and the memory access instruction control (req vector control) unit 40 is also connected to each register 10. Optionally, the connections can be made via physical wiring or communication connections.

[0135] The input vector memory access instructions (req vector input) include three vector memory access instructions: vector memory access instruction 0 (req_vector0), vector memory access instruction 1 (req_vector1), and vector memory access instruction 2 (req_vector2), which are stored in three registers 10 respectively. The memory access instruction control unit 40 is responsible for managing the vector memory access instructions. The vector memory access instructions are maintained using a first-in-first-out (FIFO) queue. New vector memory access instructions are written to the rear of the queue. When all sub-requests in the vector memory access instructions at the head of the queue have been emitted to the subsequent pipeline, the vector memory access instructions at the head of the queue are popped from the queue.

[0136] Each of the three vector memory access instructions corresponds to a set of block splitting units 220. Each set of block splitting units 220 contains K block splitting units 220, and each block splitting unit 220 corresponds to a block of the vector memory 31. The K block splitting units 220 and K multiplexers 24 are connected according to the block correspondence. In the block splitting unit 220 corresponding to the current block, the block masking unit 221 determines whether the address of each sub-request in the vector memory access instruction falls on the current block, generates a K-bit result vector, and the number of leading zeros is detected by the leading zero detection unit 222 to determine which sub-request is mapped to the current block and select that sub-request. Each time a sub-request is selected, the selected sub-request is sent to the multiplexer 24 corresponding to the current block. For example, if there are no plate conflicts in all sub-requests of a vector memory access instruction, it only takes one clock cycle to complete the issuance of all sub-requests in the vector memory access instruction; otherwise, it takes multiple clock cycles to complete the issuance of all sub-requests in the vector memory access instruction. The specific number of clock cycles required is the number of sub-requests on the plate with the most severe conflict.

[0137] refer to Figure 7 For a vector memory access instruction, the bank1 banksplitter corresponding to bank1, after passing through the bank1 mask unit, masks all sub-requests not corresponding to bank1, resulting in a masked instruction. The leading zero detection (lzd) unit starts detecting from the leftmost end of the masked instruction until it detects the first sub-request corresponding to bank1, i.e., the number of leading zeros is equal to 1, lzd = 1. Sub-request 1 and its corresponding bank1 (req1 bank1) are detected, the position of sub-request 1 is determined, and sub-request 1 is selected and issued to the multiplexer 24 corresponding to bank1. After selecting sub-request 1, it needs to be invalidated. The above selection logic continues until all sub-requests corresponding to bank1 are selected, at which point the vector memory access instruction has been issued.

[0138] Each of the K blocks corresponds to a block request queue, used to store sub-requests to be issued. For example, block 0 corresponds to a block request queue (bank0 request queue), block 1 corresponds to a block request queue (bank1 request queue), and block K-1 corresponds to a block request queue (bankK-1 request queue). Each block splitting module corresponding to a vector memory access instruction may push a new sub-request into the block request queue. The specific pushing logic is as follows: starting from the head of the vector memory access instruction queue, the first valid sub-request is pushed. Assuming vector memory access instruction 0 is at the head of the queue, and at the current moment there is no sub-request corresponding to block 0 in vector memory access instruction 0, but there are sub-requests corresponding to block 0 in vector memory access instructions 1 and 2, then the sub-request corresponding to block 0 in vector memory access instruction 1 is pushed into the block request queue (bank0 request queue) of block 0. Only after all the sub-requests corresponding to block 0 in vector memory access instruction 1 are pushed into the block request queue of block 0 can the sub-request corresponding to block 0 in vector memory access instruction 2 be pushed into the block request queue of block 0.

[0139] The sub-requests at the head of the request queues of the K modules can be combined into a discrete output vector memory access instruction (req_out), also known as a reorganization memory access instruction, which is sent to the vector memory 31 through the request channel. For read requests, the instruction information corresponding to each sub-request in each reorganization memory access instruction needs to be recorded in the pending queue (outs_queue). When the vector memory 31 returns read data (mem_rdata) through the response channel, it writes the data to the corresponding position in the reordering buffer 51 according to the instruction information at the head of the pending queue and follows the write logic. The reordering buffer 51 is also maintained using a first-in-first-out queue. When all the read data of the instructions at the head of the reordering buffer 51 is ready, the entire read vector corresponding to all the read data (req vector data) is returned to the requesting end of the gather instruction.

[0140] It should be noted that all the units, devices, queues, and connections involved in this overall architecture diagram can be implemented using various hardware such as corresponding components, connecting lines or connecting circuits, and logic circuits.

[0141] In summary, the embodiments of this application maintain multiple sets of vector memory access schedulers, which can work in parallel. If a certain block is not accessed by a preceding memory access instruction, a subsequent memory access instruction can access that block. This parallel vector memory access instruction issuance structure provided by the embodiments of this application can improve the utilization rate of each block in the memory, thereby improving the overall execution efficiency of vector memory access instructions and enhancing overall memory access performance.

[0142] Figure 10 This is a flowchart illustrating a processing method of an engine component provided in an exemplary embodiment of this application. The method is executed by the engine component, which may reside in a chip, board, or computer device. The engine component includes: a register, a scheduler, and memory. The register is connected to the scheduler, and the scheduler is connected to the memory. The memory includes K blocks, where K is greater than 1. The method includes at least some of the steps 320, 340, and 360:

[0143] Step 320: The register stores N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts, and the multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, and N is greater than 1.

[0144] Step 340: The scheduler reassembles N memory access instructions to obtain reassembled memory access instructions; the reassembled memory access instructions are sent to the memory; the reassembled memory access instructions are memory access instructions without block conflicts, and the multiple sub-requests in the reassembled memory access instructions request different blocks in K blocks respectively;

[0145] Step 360: The memory receives a reorganization memory access instruction; based on the reorganization memory access instruction, read and write operations are performed on at least two of the K blocks.

[0146] In summary, the processing method of the engine component provided in this application embodiment includes: a register, a scheduler, and a memory. The register is connected to the scheduler, and the scheduler is connected to the memory. The memory includes K blocks, where K is greater than 1. The register is used to store N memory access instructions. All or part of the N memory access instructions are memory access instructions with block conflicts. The multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, where N is greater than 1. The scheduler is used to reassemble the N memory access instructions to obtain reassembled memory access instructions. The reassembled memory access instructions are memory access instructions without block conflicts. The multiple sub-requests in the reassembled memory access instructions request different blocks in the K blocks respectively. The memory is used to receive the reassembled memory access instructions and perform read and write operations on at least two blocks in the K blocks based on the reassembled memory access instructions. Therefore, in the case of block conflicts in memory access instructions, N memory access instructions can be scheduled in parallel. After reorganizing the N memory access instructions, a reorganized memory access instruction without block conflicts is obtained, realizing access to at least two of the K blocks of memory. Compared with related technologies, which require all sub-requests of the first memory access instruction to be executed before the second memory access instruction can be executed, resulting in excessively long waiting time for the second memory access instruction, and the idle state of unaccessed blocks during this process, the utilization rate of blocks in memory is improved, thereby improving the overall memory access performance.

[0147] In some embodiments, step 340 is specifically implemented as step 400:

[0148] Step 400: The scheduler reassembles the sub-requests corresponding to at least two of the K blocks based on the addresses of each sub-request in each of the N memory access instructions, thus obtaining the reassembled memory access instructions.

[0149] In this embodiment, N memory access instructions can be scheduled in parallel, and the sub-requests can be reassembled based on the addresses of each sub-request in each of the N memory access instructions to obtain reassembled memory access instructions without block conflicts, which is beneficial for subsequent access to more blocks of memory.

[0150] In some embodiments, there are N registers, each corresponding to one of the N memory access instructions. The scheduler consists of N parallel schedulers, each corresponding to one of the N registers. The N schedulers include: N partition splitting modules and K multiplexers, each corresponding to one of the K partitions. Each of the N partition splitting modules is connected to one of the K multiplexers.

[0151] In some embodiments, step 400 is specifically implemented as steps 420 and 440:

[0152] Step 420: The N-module partitioning module determines the sub-requests corresponding to the same module in the N memory access instructions based on the addresses of each sub-request in each of the N memory access instructions; and sends the sub-requests corresponding to the same module in the N memory access instructions to the same multiplexer among the K multiplexers.

[0153] Step 440: K multiplexers receive the sub-requests corresponding to each of the K blocks, reassemble the sub-requests corresponding to at least two of the K blocks, and obtain the reassembled memory access instruction.

[0154] In this embodiment, it is possible to split each of the N memory access instructions, which can improve the processing efficiency of each memory access instruction. Furthermore, it is possible to reassemble the sub-requests corresponding to different blocks after splitting, so as to obtain reassembled memory access instructions without block conflicts, thereby improving the generation efficiency of reassembled memory access instructions.

[0155] In some embodiments, each of the N segmentation modules includes: K segmentation units, each of the K segmentation units corresponding to one of the K segments; the j-th segmentation unit corresponding to the j-th segment is connected to the j-th multiplexer corresponding to the j-th segment among the K multiplexers; j is less than or equal to K; step 420 is specifically implemented as step 422:

[0156] Step 422: The j-th segmentation unit of the i-th segmentation module determines the sub-request corresponding to the j-th segment in the i-th memory access instruction based on the address of each sub-request in the i-th memory access instruction of N memory access instructions; and sends the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer among K multiplexers; i is less than or equal to N.

[0157] In this embodiment, for each of the N memory access instructions, the sub-requests corresponding to each block in each memory access instruction can be split, which realizes targeted splitting for the current block, improves the processing efficiency of each memory access instruction, and also ensures the accuracy of the splitting.

[0158] In some embodiments, the j-th segmentation unit includes: a segment shielding unit and a leading zero detection unit, wherein the segment shielding unit and the leading zero detection unit are connected; step 422 is specifically implemented as steps 4222 and 4224:

[0159] Step 4222: Based on the addresses of each sub-request in the i-th memory access instruction of N memory access instructions, the block masking unit masks the sub-requests in the i-th memory access instruction that do not correspond to the j-th block, and obtains the i-th masked instruction.

[0160] Step 4224: The leading zero detection unit detects the number of leading zeros corresponding to the i-th masked instruction, and selects the sub-request corresponding to the j-th block in the i-th masked instruction based on the number of leading zeros; and sends the sub-request corresponding to the j-th block in the i-th memory access instruction to the j-th multiplexer among the K multiplexers.

[0161] In this embodiment, for each of the N memory access instructions, for the current block splitting unit, the block masking unit in the block splitting unit can mask all the sub-requests in each memory access instruction that are not for the current block, and generate a K-bit result vector. Thus, the leading zero detection unit can detect the sub-requests corresponding to the current block and transmit them, which can improve the accuracy of splitting and the precision of transmission.

[0162] In some embodiments, step 422 further includes step 4226:

[0163] Step 4226: After selecting the sub-request corresponding to the j-th section in the i-th masked instruction, the leading zero detection unit sets the sub-request corresponding to the j-th section in the i-th masked instruction selected this time to invalid.

[0164] The method in this embodiment can avoid the repeated selection and issuance of the sub-request corresponding to the j-th block in each memory access instruction, thereby improving the accuracy of issuance.

[0165] In some embodiments, step 440 is specifically implemented as step 442:

[0166] Step 442: The K multiplexers push the sub-requests corresponding to each of the K blocks into the block request queue corresponding to each of the K blocks; and reassemble the sub-requests at the head of the block request queues of at least two of the K blocks to obtain the reassembled memory access instruction.

[0167] In this embodiment, sub-requests corresponding to different blocks in N memory access instructions can be reorganized to obtain reorganized memory access instructions. This ensures that the reorganized memory access instructions do not have block conflicts, allowing more blocks in the memory to be accessed and improving the utilization rate of the memory blocks.

[0168] In some embodiments, the engine component further includes: a memory access instruction control unit, the memory access instruction control unit being connected to a register; the method may also optionally include step 300:

[0169] Step 300: The memory access instruction control unit writes the preceding memory access instruction to the head of the queue and the following memory access instruction to the tail of the queue, and inputs N memory access instructions.

[0170] In this embodiment, the management and maintenance of memory access instructions are implemented to provide support for subsequent scheduling.

[0171] In some embodiments, N memory access instructions are used to indicate read operations, and the engine component further includes a cache connected to the memory; in some embodiments, step 360 is specifically implemented as step 362:

[0172] Step 362: The memory records the instruction information corresponding to each sub-request in the memory access instruction to the pending queue; returns the read data corresponding to each sub-request in the memory access instruction, and writes the read data to the buffer based on the instruction information in the pending queue; the buffer is used to return the read data to the memory access instruction end after all the read data corresponding to the instruction information in the pending queue is ready.

[0173] This embodiment implements the read operation and returns the corresponding read data, which improves the overall execution efficiency of memory access instructions. It should also be noted that the description of the processing method of the engine component can be found in the description of the engine component provided in the above embodiments, and will not be repeated here.

[0174] This application provides a chip. Figure 11 This is a schematic block diagram of a chip provided in an exemplary embodiment of this application. Chip 500 includes the engine component 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a chip including programmable logic circuits and / or program instructions, which, when run on a computer device, are used to implement the processing method of the engine component provided in the above method embodiment.

[0175] As an example, taking the application of chip 500 in the field of image data processing, the image data is in vector form. In some embodiments, the memory 30 of engine component 200 is specifically implemented as vector memory for storing image data. The image data to be processed by chip 500 is read from the vector memory, and the memory access instructions include vector memory access instructions (req_vector) to indicate a read operation to read the image data to be processed by chip 500. Then, engine component 200 in chip 500 schedules multiple vector memory access instructions in parallel, all or some of which are vector memory access instructions with block conflicts; and reassembles the multiple vector memory access instructions to obtain reassembled memory access instructions, which are vector memory access instructions without block conflicts; based on the reassembled memory access instructions, read operations are performed in multiple blocks of the vector memory to read the image data to be processed by chip 500.

[0176] This application provides a circuit board. Figure 12This is a schematic block diagram of a board provided in an exemplary embodiment of this application. The board 600 includes the engine component 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a board that, when running on a computer device, implements the processing method of the engine component provided in the above method embodiment.

[0177] Specifically, a board, also known as a server board, is a type of printed circuit board (PCB). During manufacturing, it includes a connector that inserts into a slot on a server's motherboard to control hardware operations, such as monitors and data acquisition cards. After installing a driver or computer program on the board, it can perform its corresponding functions. This driver or computer program can be installed on the processor, which controls its execution, working in conjunction with the engine component 200 to realize the board's functions.

[0178] This application provides a computer device. Figure 13 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 700 includes the engine component 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a computer device. Figure 14 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 800 includes the chip 500 provided in the above embodiment, and the computer device 800 may optionally be implemented as a terminal. Alternatively, an embodiment of this application provides a computer device. Figure 15 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 900 includes the board 600 provided in the above embodiment, and the computer device 900 may be implemented as a server.

[0179] Optionally, embodiments of this application also provide a computer device, which includes: a processor and a memory, wherein the memory stores a computer program; the processor is used to execute the computer program in the memory to implement the processing method of the engine component provided in the above method embodiments.

[0180] Figure 16 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device is a server 1000. Typically, the server 1000 includes a processor 1001 and a memory 1002.

[0181] Processor 1001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a central processing unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1001 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0182] The memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 are used to store at least one instruction, which is executed by the processor 1001 to implement the processing method of the engine component provided in the method embodiments of this application.

[0183] In some embodiments, the server 1000 may optionally include an input interface 1003 and an output interface 1004. The processor 1001, memory 1002, and input interfaces 1003 and 1004 can be connected via a bus or signal lines. Various peripheral devices can be connected to the input interfaces 1003 and 1004 via a bus, signal lines, or a circuit board. The input interfaces 1003 and 1004 can be used to connect at least one input / output (I / O) related peripheral device to the processor 1001 and memory 1002. In some embodiments, the processor 1001, memory 1002, and input interfaces 1003 and 1004 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1001, memory 1002, and input interfaces 1003 and 1004 can be implemented on separate chips or circuit boards, and this application does not limit this.

[0184] Figure 17 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Optionally, the computer device 2000 is a terminal.

[0185] The computer device 2000 can be a portable mobile terminal, also referred to as a mobile terminal in this embodiment. Examples include smartphones, tablets, MP3 players (Moving Picture Experts Group Audio Layer III), and MP4 players (Moving Picture Experts Group Audio Layer IV). The computer device 2000 may also be referred to as user equipment, portable terminal, or other names.

[0186] Typically, a computer device 2000 includes a processor 2001 and a memory 2002.

[0187] Processor 2001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 2001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 2001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 2001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 2001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0188] The memory 2002 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 2002 may also include high-speed random access memory devices and non-volatile storage devices, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 2002 are used to store at least one instruction, which is executed by the processor 2001 to implement the processing methods of the engine components provided in the various method embodiments of this application.

[0189] In some embodiments, the computer device 2000 may optionally include a peripheral device interface 2003 and at least one peripheral device. Specifically, the peripheral device includes at least one of a radio frequency circuit 2004, a touch display screen 2005, a camera assembly 2006, an audio circuit 2007, and a power supply 2008. The computer device 2000 also includes one or more sensors 2009. The one or more sensors 2009 include, but are not limited to, an accelerometer 2010, a gyroscope 2011, a pressure sensor 2012, an optical sensor 2013, and a proximity sensor 2014.

[0190] Those skilled in the art will understand that Figure 11 The structure shown does not constitute a limitation on the chip. Figure 12 The structure shown does not constitute a limitation on the board. Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0191] This application provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the processing method of the engine component provided in the above method embodiments.

[0192] This application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, executes the computer instructions, and causes the processor of the computer device to load and execute the processing method of the engine component provided in the above-described method embodiment.

[0193] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0194] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0195] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0196] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An engine component, characterized in that, The engine components include: a register, a scheduler, and a memory. The register is connected to the scheduler, and the scheduler is connected to the memory. The memory includes K modules, where K is greater than 1. The register is used to store N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts, and the multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, and N is greater than 1. The scheduler is used to reassemble the N memory access instructions to obtain a reassembled memory access instruction; and send the reassembled memory access instruction to the memory; the reassembled memory access instruction is a memory access instruction without block conflicts, and the multiple sub-requests in the reassembled memory access instruction request different blocks among the K blocks respectively; The memory is used to receive the reorganization memory access instruction and to perform read and write operations on at least two of the K blocks based on the reorganization memory access instruction.

2. The engine component according to claim 1, characterized in that, The scheduler is used to reassemble the sub-requests corresponding to at least two of the K blocks based on the addresses of each sub-request in each of the N memory access instructions, to obtain the reassembled memory access instructions.

3. The engine component according to claim 2, characterized in that, The registers are N registers, and the N registers correspond to the N memory access instructions. The scheduler is N parallel schedulers, and the N schedulers correspond one-to-one with the N registers. The N schedulers include: N segment splitting modules and K multiplexers. The K multiplexers correspond one-to-one with the K segments, and each segment splitting module of the N segment splitting modules is connected to the K multiplexers. The N module splitting units are used to determine the sub-requests corresponding to the same module in the N memory access instructions based on the addresses of each sub-request in each of the N memory access instructions; and send the sub-requests corresponding to the same module in the N memory access instructions to the same multiplexer among the K multiplexers. The K multiplexers are used to receive the sub-requests corresponding to each of the K blocks, reassemble the sub-requests corresponding to at least two of the K blocks, and obtain the reassembled memory access instruction.

4. The engine component according to claim 3, characterized in that, Each of the N segmentation modules includes: K segmentation units, each of the K segmentation units corresponding to one of the K segments; the j-th segmentation unit corresponding to the j-th segment is connected to the j-th multiplexer corresponding to the j-th segment; where j is less than or equal to K. The j-th segmentation unit of the i-th segmentation module is used to determine the sub-request corresponding to the j-th segment in the i-th memory access instruction based on the address of each sub-request in the i-th memory access instruction of the N memory access instructions; and send the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer among the K multiplexers; where i is less than or equal to N.

5. The engine component according to claim 4, characterized in that, The j-th segmentation unit includes: a segment shielding unit and a leading zero detection unit, wherein the segment shielding unit is connected to the leading zero detection unit; The block masking unit is used to mask the sub-requests in the i-th memory access instruction that do not correspond to the j-th block, based on the addresses of each sub-request in the i-th memory access instruction of the N memory access instructions, to obtain the i-th masked instruction; The leading zero detection unit is used to detect the number of leading zeros corresponding to the i-th masked instruction, and based on the number of leading zeros, select the sub-request corresponding to the j-th block in the i-th masked instruction; and send the sub-request corresponding to the j-th block in the i-th memory access instruction to the j-th multiplexer among the K multiplexers.

6. The engine component according to claim 5, characterized in that, The leading zero detection unit is used to set the sub-request corresponding to the j-th section in the i-th blocking instruction to invalid after selecting the sub-request corresponding to the j-th section in the i-th blocking instruction.

7. The engine component according to claim 3, characterized in that, The K multiplexers are used to push the sub-requests corresponding to each of the K blocks into the block request queue corresponding to each of the K blocks; and to reassemble the sub-requests at the head of the block request queues of at least two of the K blocks to obtain the reassembled memory access instruction.

8. The engine component according to any one of claims 1 to 7, characterized in that, The engine component further includes a memory access instruction control unit, which is connected to the register; The memory access instruction control unit is used to write the preceding memory access instruction to the head of the queue, the following memory access instruction to the tail of the queue, and input the N memory access instructions.

9. The engine component according to any one of claims 1 to 7, characterized in that, The N memory access instructions are used to indicate read operations, and the engine component also includes a cache connected to the memory; The memory is used to record the instruction information corresponding to each sub-request in the reorganization memory access instruction to the pending queue; Return the read data corresponding to each sub-request in the reorganization memory access instruction, and write the read data to the cache based on the instruction information of the pending queue; The buffer is used to return the read data to the memory access instruction terminal after all the read data corresponding to the instruction information in the pending queue is ready.

10. A chip, characterized in that, The chip includes: the engine component as described in any one of claims 1 to 9.

11. A circuit board, characterized in that, The board includes: the engine component as described in any one of claims 1 to 9.

12. A computer device, characterized in that, The computer device includes: an engine component as described in any one of claims 1 to 9, or a chip as described in claim 10, or a board as described in claim 11.

13. A method for processing an engine component, characterized in that, The engine components include: a register, a scheduler, and a memory. The register is connected to the scheduler, and the scheduler is connected to the memory. The memory includes K modules, where K is greater than 1. The method includes: The register stores N memory access instructions; all or part of the N memory access instructions are memory access instructions with block conflicts, and the multiple sub-requests in the memory access instructions with block conflicts include at least two sub-requests requesting access to the same block, and N is greater than 1. The scheduler reassembles the N memory access instructions to obtain a reassembled memory access instruction; the reassembled memory access instruction is sent to the memory; the reassembled memory access instruction is a memory access instruction without block conflicts, and the multiple sub-requests in the reassembled memory access instruction request different blocks among the K blocks respectively; The memory receives the reorganization access instruction; and performs read and write operations on at least two of the K blocks based on the reorganization access instruction.

14. The method according to claim 13, characterized in that, The scheduler reassembles the N memory access instructions to obtain reassembled memory access instructions, including: The scheduler reassembles the sub-requests corresponding to at least two of the K blocks based on the addresses of each sub-request in each of the N memory access instructions, thus obtaining the reassembled memory access instructions.

15. The method according to claim 14, characterized in that, The registers are N registers, and the N registers correspond to the N memory access instructions. The scheduler is N parallel schedulers, and the N schedulers correspond one-to-one with the N registers. The N schedulers include: N segment splitting modules and K multiplexers. The K multiplexers correspond one-to-one with the K segments, and each segment splitting module of the N segment splitting modules is connected to the K multiplexers. The scheduler, based on the addresses of each sub-request in each of the N memory access instructions, reassembles the sub-requests corresponding to at least two of the K blocks to obtain the reassembled memory access instructions, including: The N-module partitioning module determines the sub-requests corresponding to the same module in each of the N memory access instructions based on the addresses of the sub-requests in each of the N memory access instructions; and sends the sub-requests corresponding to the same module in the N memory access instructions to the same multiplexer among the K multiplexers. The K multiplexers receive the sub-requests corresponding to each of the K blocks, reassemble the sub-requests corresponding to at least two of the K blocks, and obtain the reassembled memory access instruction.

16. The method according to claim 15, characterized in that, Each of the N segmentation modules includes: K segmentation units, each of the K segmentation units corresponding to one of the K segments; the j-th segmentation unit corresponding to the j-th segment is connected to the j-th multiplexer corresponding to the j-th segment; where j is less than or equal to K. The N module partitioning units determine the sub-requests corresponding to the same module in each of the N memory access instructions based on the addresses of the sub-requests in each of the N memory access instructions; and send the sub-requests corresponding to the same module in the N memory access instructions to the same multiplexer among the K multiplexers, including: The j-th segmentation unit of the i-th segmentation module determines the sub-request corresponding to the j-th segment in the i-th memory access instruction based on the address of each sub-request in the i-th memory access instruction of the N memory access instructions; and sends the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer among the K multiplexers; where i is less than or equal to N.

17. The method according to claim 16, characterized in that, The j-th segmentation unit includes: a segment shielding unit and a leading zero detection unit, wherein the segment shielding unit is connected to the leading zero detection unit; The j-th segmentation unit of the i-th segmentation module determines the sub-request corresponding to the j-th segment in the i-th memory access instruction based on the address of each sub-request in the i-th memory access instruction from the N memory access instructions; and sends the sub-request corresponding to the j-th segment in the i-th memory access instruction to the j-th multiplexer among the K multiplexers, including: The block masking unit, based on the addresses of each sub-request in the i-th memory access instruction of the N memory access instructions, masks the sub-requests in the i-th memory access instruction that do not correspond to the j-th block, and obtains the i-th masked instruction; The leading zero detection unit detects the number of leading zeros corresponding to the i-th masked instruction, and based on the number of leading zeros, selects the sub-request corresponding to the j-th block in the i-th masked instruction; and sends the sub-request corresponding to the j-th block in the i-th memory access instruction to the j-th multiplexer among the K multiplexers.

18. The method according to claim 17, characterized in that, The method further includes: After selecting the sub-request corresponding to the j-th segment in the i-th post-blocking instruction, the leading zero detection unit sets the selected sub-request corresponding to the j-th segment in the i-th post-blocking instruction to invalid.

19. The method according to claim 15, characterized in that, The K multiplexers receive sub-requests corresponding to each of the K blocks, reassemble the sub-requests corresponding to at least two of the K blocks, and obtain the reassembled memory access instruction, including: The K multiplexers push the sub-requests corresponding to each of the K blocks into the block request queue corresponding to each of the K blocks; and reassemble the sub-requests at the head of the block request queues of at least two of the K blocks to obtain the reassembled memory access instruction.

20. The method according to any one of claims 13 to 19, characterized in that, The engine component further includes a memory access instruction control unit, which is connected to the register; The method further includes: The memory access instruction control unit writes the preceding memory access instruction to the head of the queue, the following memory access instruction to the tail of the queue, and inputs the N memory access instructions.

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