Reset function verification method and device, electronic equipment and storage medium

Abstract

The invention discloses a reset function verification method and device, electronic equipment and a storage medium, and relates to the technical field of chips, and the method comprises the steps: determining a target working scene of a function module, and obtaining a working time period of the target working scene; traversing each time point in the working time period in sequence, and executing a reset verification operation at each time point to obtain a verification result of each time point; according to the verification result of each time point, determining coverage information of a reset function of the function module in the target working scene; through the mode, the function module can be completely covered to carry out reset verification in the full working time period of the target working scene, the coverage information of the reset function can be accurately determined, and the integrity of reset function verification is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a method and apparatus for verifying a reset function, an electronic device, and a storage medium. Background Technology

[0002] With the continuous development of integrated circuit design, the general intellectual property (IP) core, as a reusable functional module in integrated circuit design, can complete operations such as chip power-on initialization and restart during operation by relying on the reset function, based on the shared chip hardware and software design resources, and ensure the stability of IP operation by detecting the chip status after reset.

[0003] In related technologies, the integrity verification of IP reset function relies on random reset testing. However, at specific times, random reset testing is difficult to meet the requirements of high-precision and reliability application scenarios of chips. Reset verification of IP throughout its entire working time window may be incomplete, resulting in insufficient verification integrity. Summary of the Invention

[0004] This disclosure provides a method, apparatus, electronic device, and storage medium for verifying reset functions, in order to address the problem of insufficient completeness in the reset verification of functional modules in related technologies.

[0005] According to a first aspect embodiment of this disclosure, a method for verifying a reset function is provided, comprising:

[0006] Determine the target working scenario for the functional module and obtain the working time period for the target working scenario; The process involves iterating through each time point within the working time period and performing a reset verification operation at each time point to obtain the verification result for each time point. Based on the verification results at each time point, the coverage information of the reset function of the functional module under the target working scenario is determined.

[0007] In some embodiments of this disclosure, performing a reset verification operation at each time point to obtain a verification result at each time point includes: The functional module is restored to its initial state in the target work scenario, and the functional module is then started to execute the target work scenario. During the execution of the target work scenario, a reset signal is applied to the functional module at each time point; wherein, the execution of the target work scenario and the application of the reset signal are concurrent operations; Check the reset status of the functional module after reset completion, and generate the verification result corresponding to each time point based on the reset status; wherein, the method of checking the reset status includes at least one of the following: using assertion to determine whether the interface timing of the functional module meets the preset timing requirements, comparing the register data of the functional module with preset benchmark data, and comparing the data of the functional module by combining front-door and back-door methods.

[0008] In some embodiments of this disclosure, the step of sequentially traversing each time point within the working time period further includes: Adjust the initial and final values ​​of the traversal time points according to the complexity of the target work scenario executed by the functional module. The time interval between adjacent time points is configured based on a preset reset clock cycle; wherein, the preset reset clock cycle is related to the total duration between the initial value and the termination value.

[0009] In some embodiments of this disclosure, determining the target working scenario of the functional module and obtaining the working time period of the target working scenario includes: Filter out the target working scenario associated with the reset function from all working scenarios of the functional module; Based on the working clock cycle of the functional module, the number of clock cycles required to execute the target work scenario is determined, and a time window is determined according to the working clock cycle and the number of clock cycles; wherein, the time window is the working time period from the start to the end of the work of the functional module.

[0010] In some embodiments of this disclosure, before determining the target working scenario of the functional module and obtaining the working time period of the target working scenario, the method further includes: Configure the target parameters required for the functional module to perform the working scenario; wherein, the target parameters include at least one of the basic configuration to be read during the power-on process of the functional module, the functional configuration and memory data loaded through the backdoor, and the register configuration written through the frontdoor.

[0011] In some embodiments of this disclosure, after performing a reset verification operation at each time point and obtaining the verification result at each time point, the method further includes: Determine whether the number of iterations of the reset verification operation has reached the preset number; If it is determined that the number of loops for the reset verification operation has not reached the preset number, the number of loops is incremented, and the functional module is executed to restore the target working scenario to its initial state. If the number of cycles of the reset verification operation reaches the preset number, the current reset function verification is terminated; wherein, the preset number is related to the working time period.

[0012] According to a second aspect embodiment of this disclosure, a verification device for a reset function is provided, comprising: The acquisition unit is used to determine the target working scenario of the functional module and acquire the working time period of the target working scenario; A traversal unit is used to sequentially traverse each point in time within the work time period; An execution unit is configured to perform a reset verification operation at each time point and obtain the verification result at each time point. The determining unit is used to determine the coverage information of the reset function of the functional module in the target working scenario based on the verification results at each time point.

[0013] In some embodiments of this disclosure, the execution unit includes: The recovery module is used to restore the functional module to the initial state of the target working scenario and start the functional module to execute the target working scenario; An application module is configured to apply a reset signal to the functional module at each time point during the execution of the target work scenario; wherein, the execution of the target work scenario and the application of the reset signal are concurrent operations; A generation module is used to check the reset status of the functional module after the reset is completed, and generate the verification result corresponding to each time point according to the reset status; wherein, the method of checking the reset status includes at least one of the following: using assertion to determine whether the interface timing of the functional module meets the preset timing requirements, comparing the register data of the functional module with preset benchmark data, and comparing the data of the functional module by combining front-door and back-door methods.

[0014] In some embodiments of this disclosure, the traversal unit further includes: The adjustment module is used to adjust the initial and final values ​​of the traversal time points according to the complexity of the target work scenario executed by the functional module. The configuration module is used to configure the time interval between adjacent time points based on a preset reset clock period; wherein the preset reset clock period is related to the total duration between the initial value and the termination value.

[0015] In some embodiments of this disclosure, the acquisition unit includes: A filtering module is used to filter out the target working scenario associated with the reset function from all working scenarios of the functional module; The determining module is used to determine the number of clock cycles for executing the target work scenario based on the working clock cycle of the functional module, and to determine a time window based on the working clock cycle and the number of clock cycles; wherein, the time window is the working time period from the start to the end of the work of the functional module.

[0016] In some embodiments of this disclosure, the apparatus further includes: A configuration unit is configured to configure target parameters required for the functional module to execute the work scenario before the acquisition unit determines the target work scenario of the functional module and acquires the work time period of the target work scenario; wherein, the target parameters include at least one of the basic configuration to be read during the power-on process of the functional module, functional configuration and memory data loaded through a backdoor, and register configuration written through a frontdoor.

[0017] In some embodiments of this disclosure, the apparatus further includes: The judgment unit is used to determine whether the number of cycles of the reset verification operation has reached a preset number after the execution unit performs the reset verification operation at each time point and obtains the verification result at each time point. An accumulation unit is used to accumulate the number of cycles when it is determined that the number of cycles of the reset verification operation has not reached the preset number, and to execute the function module to restore the target working scene to its initial state. The termination unit is used to terminate the current reset function verification when it is determined that the number of cycles of the reset verification operation has reached the preset number; wherein, the preset number is related to the working time period.

[0018] According to a third aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect embodiment.

[0019] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect of the present disclosure.

[0020] According to a fifth aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method described in the first aspect of the preceding embodiments.

[0021] In summary, the reset function verification method, apparatus, electronic device, and storage medium provided in this disclosure include: determining the target working scenario of the functional module and obtaining the working time period of the target working scenario; sequentially traversing each time point within the working time period and performing a reset verification operation at each time point to obtain the verification result at each time point; and determining the coverage information of the reset function of the functional module in the target working scenario based on the verification results at each time point. This method can completely cover the entire working time period of the functional module in the target working scenario for reset verification, accurately determine the coverage information of the reset function, and ensure the integrity of the reset function verification.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0023] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 A flowchart illustrating a method for verifying a reset function provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another method for verifying the reset function provided in this embodiment of the present disclosure; Figure 3 A flowchart illustrating another method for verifying the reset function provided in this embodiment of the present disclosure; Figure 4 A flowchart illustrating another method for verifying the reset function provided in this embodiment of the present disclosure; Figure 5 This is a schematic diagram of the working clock cycle for a target working scenario provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the reset clock cycle for a reset verification operation provided in an embodiment of the present disclosure; Figure 7 A flowchart illustrating another method for verifying the reset function provided in this embodiment of the present disclosure; Figure 8 This is a schematic diagram of the overall process of a method for verifying a reset function provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the structure of a verification device for a reset function provided in an embodiment of the present disclosure; Figure 10 A schematic diagram of the structure of another verification device for a reset function provided in an embodiment of this disclosure; Figure 11A schematic block diagram of an example electronic device provided for embodiments of this disclosure. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0025] The following description, with reference to the accompanying drawings, outlines a method and apparatus for verifying the reset function, an electronic device, and a storage medium according to embodiments of the present disclosure.

[0026] Figure 1 This is a flowchart illustrating a method for verifying a reset function provided in an embodiment of this disclosure.

[0027] like Figure 1 As shown, the method includes the following steps: Step 101: Determine the target working scenario of the functional module and obtain the working time period of the target working scenario.

[0028] In some embodiments, the functional module is a circuit or IP module with a reset function. The target working scenario is the working scenario in which the reset function verification needs to be performed on the functional module. The working scenario may include read operations, write operations, erase operations, various algorithm operations, etc. The working time period is the duration from the start of operation to the termination of operation of the functional module under the target working scenario. By determining the target working scenario and the working time period, the object and time range of the reset function verification are defined. It should be noted that the above examples are only illustrative and do not limit the specific content.

[0029] The above methods can clarify the important scope of reset function verification and provide a basis for the execution of reset verification operations.

[0030] Step 102: Iterate through each time point within the working time period and perform a reset verification operation at each time point to obtain the verification result for each time point.

[0031] In some embodiments, sequential traversal involves processing all time points within the working time period one by one in chronological order. The reset verification operation is a reset validity check operation performed on the functional module at the corresponding time point. After completing the reset verification operation for each traversed time point, a verification result corresponding to that time point is generated. The verification result is used to characterize whether the state of the functional module after performing the reset operation at that time point meets the preset requirements.

[0032] The above method can be used to complete the reset verification of all time points within the working period of the target work scenario, ensuring full coverage of the verification operation.

[0033] Step 103: Based on the verification results at each time point, determine the coverage information of the reset function of the functional module in the target working scenario.

[0034] In some embodiments, the coverage information is information that characterizes the degree of verification coverage of the reset function in the target working scenario, obtained by summarizing the verification results at all time points. The coverage information can be determined by integrating the verification results at all time points.

[0035] Using the above method, the coverage information of the reset function can be obtained based on the complete verification results, which can intuitively reflect the verification coverage of the reset function in the target working scenario.

[0036] In summary, the verification method for the reset function disclosed herein includes: determining the target working scenario of the functional module and obtaining the working time period of the target working scenario; sequentially traversing each time point within the working time period and performing a reset verification operation at each time point to obtain the verification result at each time point; and determining the coverage information of the reset function of the functional module in the target working scenario based on the verification results at each time point. This method can fully cover the entire working time period of the functional module in the target working scenario for reset verification, accurately determine the coverage information of the reset function, and ensure the integrity of the reset function verification.

[0037] Figure 2 A flowchart illustrating a method for verifying a reset function provided in an embodiment of this disclosure is further shown. Figure 2 This may include the following steps: Step 201: Restore the functional module to the initial state of the target work scenario, and start the functional module to execute the target work scenario.

[0038] In some embodiments, restoring a functional module to its initial state includes, but is not limited to, performing a power-on operation on the functional module after a power outage, enabling the functional module to complete state initialization, and then reloading the target parameters required for the functional module to execute the working scenario after initialization, ensuring that the state of the functional module before starting to execute the target working scenario remains consistent, thereby ensuring that the working time period corresponding to each reset verification is consistent. If no initialization is required, the power-on operation can be omitted.

[0039] Step 202: During the execution of the target working scenario, a reset signal is applied to the functional module at each time point; wherein, the execution of the target working scenario and the application of the reset signal are concurrent operations.

[0040] In some embodiments, the target execution scenario is a first concurrent process, and the reset signal is applied by a second concurrent process. The two processes execute synchronously. The second concurrent process must wait for a preset duration before applying the reset signal. This preset duration is an integer multiple of a preset reset clock cycle, which can be greater than, less than, or equal to the working clock cycle of the functional module. The total execution time of the second concurrent process is the same as that of the first concurrent process. The initial value of the counting parameter at each traversal point can be adjusted according to the complexity of the target execution scenario. The preset number of iterations can also be adjusted according to the complexity of the target execution scenario. For example, the initial value of the counting parameter can be 0, incremented to less than 200, 20, incremented to less than 40, 100, incremented to less than 150, or 190, incremented to less than 200. It should be noted that the configuration method is not limited.

[0041] Step 203: Check the reset status of the functional module after the reset is completed, and generate the verification result corresponding to each time point based on the reset status; wherein, the method of checking the reset status includes at least one of the following: using assertion to determine whether the interface timing of the functional module meets the preset timing requirements, comparing the register data of the functional module with preset reference data, and comparing the data of the functional module by combining the front-door method and the back-door method.

[0042] In some embodiments, assertions are used to detect whether the interface timing of the functional module meets the preset timing standard, the register data of the functional module is read and automatically compared with the preset reference register data, and the internal data of the functional module is compared by combining the front-door and back-door methods. Based on the results of at least one of the above checking methods, the verification result at the corresponding time point is generated.

[0043] The above methods can be used to accurately determine the reset status of functional modules through multiple inspection methods, ensuring the accuracy of verification results.

[0044] Figure 3 A flowchart illustrating a method for verifying a reset function provided in an embodiment of this disclosure is further shown. Figure 3 This may include the following steps: Step 301: Adjust the initial and final values ​​of the traversal time points according to the complexity of the target work scenario executed by the functional module.

[0045] In some embodiments, the starting and ending values ​​of time points within the traversal work period are adjusted according to the process complexity of the functional modules executing the target work scenario. Optionally, the time points corresponding to the periods in the target work scenario where the reset function is prone to abnormalities are selected as the adjusted initial and ending values.

[0046] Step 302: Configure the time interval between adjacent time points based on a preset reset clock cycle; wherein the preset reset clock cycle is related to the total duration between the initial value and the termination value.

[0047] In some embodiments, based on a preset reset clock cycle, the time interval between two adjacent time points during the traversal process is configured, and the total duration between the initial value and the termination value is matched to an integer multiple of the preset reset clock cycle, so that the time interval is adapted to the total duration.

[0048] The above method allows for flexible configuration of traversal parameters to adapt to target work scenarios of varying complexity, balancing the comprehensiveness and efficiency of reset verification.

[0049] Figure 4 A flowchart illustrating a method for verifying a reset function provided in an embodiment of this disclosure is further shown. Figure 4 This may include the following steps: Step 401: Select the target working scenario associated with the reset function from all working scenarios of the functional module.

[0050] In some embodiments, all working scenarios of the functional modules are traversed, and working scenarios that are prone to state abnormalities during the reset execution process and are strongly correlated with the reset function are selected as target working scenarios. The selection of target working scenarios needs to be based on the specific actual situation.

[0051] Step 402: Based on the working clock cycle of the functional module, determine the number of clock cycles for executing the target work scenario, and determine a time window according to the working clock cycle and the number of clock cycles; wherein, the time window is the working time period from the start to the end of the work of the functional module.

[0052] In some embodiments, the total number of clock cycles consumed in executing the target work scenario is counted according to the actual working clock cycle of the functional module. The working clock cycle is multiplied by the total number of clock cycles, and the resulting value is the time window corresponding to the target work scenario. The time window is the working time period during which the functional module executes the target work scenario.

[0053] The above methods can accurately quantify the working time period of the target work scenario, providing a precise basis for the time range of reset verification.

[0054] Figure 5This disclosure illustrates a schematic diagram of the working clock cycle for a target working scenario, as shown below. Figure 5 As shown, the functional module executes the target working scenario (such as the erase operation) according to the working clock cycle (CLK1). The duration of this working clock cycle is the first duration (e.g., 10ns), and the total number of clock cycles consumed in executing the target working scenario is the first quantity (e.g., 100). Based on the product of the working clock cycle and the total number of clock cycles, the working time period (time window) corresponding to the target working scenario can be determined. For example, the working time period is 100 × 10ns = 1000ns. This working time period is the simulation time from the start to the end of the functional module's erase operation.

[0055] Figure 6 This disclosure illustrates a reset clock cycle diagram for a reset verification operation, as shown below. Figure 6 As shown, the reset verification operation follows the reset clock cycle (CLK2), the duration of which is the second duration (e.g., 5ns). The total number of clock cycles consumed in executing the reset verification operation is the second quantity (e.g., 200), and the corresponding simulation time is, for example, 200 × 5ns = 1000ns. The reset clock cycle can be greater than, less than, or equal to the working clock cycle. In this example, the second duration of the reset clock cycle is less than the first duration of the working clock cycle. The total execution time of the reset verification operation is the same as the total execution time of the target working scenario to ensure that the reset verification covers the entire working time period of the target working scenario.

[0056] In some embodiments of this disclosure, the method further includes: configuring target parameters required for the functional module to perform its work scenario; wherein the target parameters include at least one of the following: basic configuration to be read during the power-on process of the functional module, functional configuration and memory data loaded through a backdoor, and register configuration written through a frontdoor.

[0057] In some embodiments, before determining the target working scenario of the functional module and obtaining the working time period, the target parameters for the functional module to execute the working scenario are configured. The target parameters include, but are not limited to, the basic configuration to be read during the power-on startup of the functional module, the functional configuration and memory data loaded through the backdoor, and the register configuration written through the frontdoor.

[0058] The above method can be used to complete the parameter configuration before reset verification, providing the basic conditions for the functional module to execute the target working scenario.

[0059] Figure 7 A flowchart illustrating a method for verifying a reset function provided in an embodiment of this disclosure is further shown. Figure 7 This may include the following steps: Step 501: Determine whether the number of cycles of the reset verification operation has reached the preset number.

[0060] In some embodiments, after each reset verification operation at a single time point is completed, the number of reset verification loops is counted, and it is determined whether the counted number of loops has reached a preset number. The preset number is related to the working time period of the target working scenario and is based on the configuration of the initial and final values ​​of the traversed time points.

[0061] Step 502: If it is determined that the number of loops of the reset verification operation has not reached the preset number, the number of loops is incremented, and the function module is executed to restore the target working scene to its initial state.

[0062] In some embodiments, if the number of loops does not reach the preset number, the number of loops is incremented, the control function module is restored to the initial state of the target working scenario, and the reset verification operation is re-executed.

[0063] Step 503: If the number of cycles of the reset verification operation reaches the preset number, terminate the current reset function verification; wherein the preset number is related to the working time period.

[0064] In some embodiments, if the number of loops reaches a preset number, the loop execution of the reset verification is stopped, and the current reset function verification process is terminated.

[0065] Using the above method, the execution flow of reset verification can be controlled by the number of loops, ensuring that reset verification is completed at all target time points within the working period.

[0066] As one way that this disclosure can be implemented Figure 8 This disclosure presents a schematic diagram illustrating the overall process of a verification method for a reset function, as shown below. Figure 8 As shown, firstly, the target parameters required for the functional module to execute the work scenario are configured, then the target work scenario of the functional module is determined and the corresponding work time period is obtained. Then, the reset verification loop process is entered, the power-down and power-on operations are performed, the functional module is restored to the initial state, the target work scenario and reset signal are applied through concurrent processes, the reset status is checked to obtain the verification result, and it is determined whether the number of loops has reached the preset number. If it has not reached the preset number, the loop continues; if it has reached the preset number, the verification is terminated. Finally, the coverage information of the reset function is determined based on all the verification results.

[0067] The embodiments disclosed herein can achieve the following beneficial effects: 1. Based on the repeatable target work scenario to be verified, quantify the working time period of the reset verification operation.

[0068] 2. Fully cover the entire reset working time period to ensure the completeness of the reset test.

[0069] 3. Independent reset clock cycle, decoupled from the working clock cycle, allows for adjustment and adaptation of cyclic test accuracy.

[0070] 4. Flexible adjustment of the initial value at the start of the loop and the termination value at the end of the loop, taking into account both testing efficiency.

[0071] Corresponding to the above-described method for verifying the reset function, this invention also proposes a device for verifying the reset function. Since the device embodiments of this invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0072] Figure 9 This is a schematic diagram of the structure of a verification device for a reset function provided in an embodiment of this disclosure, as shown below. Figure 9 As shown, it includes: acquisition unit 51, traversal unit 52, execution unit 53, and determination unit 54.

[0073] The acquisition unit 51 is used to determine the target working scenario of the functional module and acquire the working time period of the target working scenario; Traversal unit 52 is used to traverse each time point within the working time period in sequence; Execution unit 53 is used to perform a reset verification operation at each time point to obtain the verification result at each time point; The determining unit 54 is used to determine the coverage information of the reset function of the functional module in the target working scenario based on the verification results at each time point.

[0074] In summary, the reset function verification device of this disclosure includes: determining the target working scenario of the functional module and obtaining the working time period of the target working scenario; sequentially traversing each time point within the working time period and performing a reset verification operation at each time point to obtain the verification result at each time point; determining the coverage information of the reset function of the functional module in the target working scenario based on the verification results at each time point; the above method can completely cover the reset verification of the functional module in the entire working time period of the target working scenario, accurately determine the coverage information of the reset function, and ensure the integrity of the reset function verification.

[0075] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the execution unit 53 includes: The recovery module 531 is used to restore the functional module to the initial state of the target working scenario and start the functional module to execute the target working scenario; The application module 532 is used to apply a reset signal to the functional module at each time point during the execution of the target work scenario; wherein, the execution of the target work scenario and the application of the reset signal are concurrent operations; The generation module 533 is used to check the reset status of the functional module after the reset is completed, and generate the verification result corresponding to each time point according to the reset status; wherein, the method of checking the reset status includes at least one of the following: using assertion to determine whether the interface timing of the functional module meets the preset timing requirements, comparing the register data of the functional module with preset reference data, and comparing the data of the functional module by combining the front-door method and the back-door method.

[0076] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the traversal unit 52 further includes: The adjustment module 521 is used to adjust the initial and final values ​​of the traversal time points according to the complexity of the target work scenario executed by the functional module. Configuration module 522 is used to configure the time interval between adjacent time points based on a preset reset clock period; wherein, the preset reset clock period is related to the total duration between the initial value and the termination value.

[0077] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the acquisition unit 51 includes: The filtering module 511 is used to filter out the target working scenario associated with the reset function from all working scenarios of the functional module; The determining module 512 is used to determine the number of clock cycles for executing the target work scenario based on the working clock cycle of the functional module, and to determine a time window based on the working clock cycle and the number of clock cycles; wherein, the time window is the working time period from the start to the end of the work of the functional module.

[0078] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the device further includes: The configuration unit 55 is configured to configure the target parameters required for the functional module to execute the work scenario before the acquisition unit 51 determines the target work scenario of the functional module and acquires the work time period of the target work scenario; wherein, the target parameters include at least one of the basic configuration to be read during the power-on process of the functional module, the functional configuration and memory data loaded through the backdoor, and the register configuration written through the frontdoor.

[0079] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the device further includes: The judgment unit 56 is used to determine whether the number of cycles of the reset verification operation has reached the preset number after the execution unit 53 performs the reset verification operation at each time point and obtains the verification result at each time point. The accumulator unit 57 is used to accumulate the number of cycles and execute the function module to restore the target working scene to its initial state when it is determined that the number of cycles of the reset verification operation has not reached the preset number of cycles. Termination unit 58 is used to terminate the current reset function verification when it is determined that the number of cycles of the reset verification operation has reached the preset number; wherein, the preset number is related to the working time period.

[0080] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0081] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0082] Figure 11 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0083] like Figure 11 As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 602 or loaded from storage unit 608 into RAM (Random Access Memory) 603. The RAM 603 may also store various programs and data required for the operation of the electronic device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An I / O (Input / Output) interface 605 is also connected to the bus 604.

[0084] Multiple components in electronic device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of displays, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows electronic device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0085] The computing unit 601 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the method for verifying a reset function. For example, in some embodiments, the method for verifying a reset function may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured by any other suitable means (e.g., by means of firmware) to perform the verification method for the aforementioned reset function.

[0086] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0087] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0088] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0089] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0090] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0091] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0092] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0093] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0094] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for verifying the reset function, characterized in that, The method includes: Determine the target working scenario for the functional module and obtain the working time period for the target working scenario; The process involves iterating through each time point within the working time period and performing a reset verification operation at each time point to obtain the verification result for each time point. Based on the verification results at each time point, the coverage information of the reset function of the functional module under the target working scenario is determined.

2. The method according to claim 1, characterized in that, The step of performing a reset verification operation at each time point to obtain the verification result at each time point includes: The functional module is restored to its initial state in the target work scenario, and the functional module is then started to execute the target work scenario. During the execution of the target work scenario, a reset signal is applied to the functional module at each time point; wherein, the execution of the target work scenario and the application of the reset signal are concurrent operations; Check the reset status of the functional module after reset completion, and generate the verification result corresponding to each time point based on the reset status; wherein, the method of checking the reset status includes at least one of the following: using assertion to determine whether the interface timing of the functional module meets the preset timing requirements, comparing the register data of the functional module with preset benchmark data, and comparing the data of the functional module by combining front-door and back-door methods.

3. The method according to claim 1, characterized in that, The step of sequentially traversing each time point within the working time period also includes: Adjust the initial and final values ​​of the traversal time points according to the complexity of the target work scenario executed by the functional module. The time interval between adjacent time points is configured based on a preset reset clock cycle; wherein, the preset reset clock cycle is related to the total duration between the initial value and the termination value.

4. The method according to claim 1, characterized in that, The determination of the target working scenario of the functional module and the acquisition of the working time period of the target working scenario include: Filter out the target working scenario associated with the reset function from all working scenarios of the functional module; Based on the working clock cycle of the functional module, the number of clock cycles required to execute the target work scenario is determined, and a time window is determined according to the working clock cycle and the number of clock cycles; wherein, the time window is the working time period from the start to the end of the work of the functional module.

5. The method according to claim 1, characterized in that, Before determining the target working scenario of the functional module and obtaining the working time period of the target working scenario, the method further includes: Configure the target parameters required for the functional module to perform the working scenario; wherein, the target parameters include at least one of the basic configuration to be read during the power-on process of the functional module, the functional configuration and memory data loaded through the backdoor, and the register configuration written through the frontdoor.

6. The method according to claim 1, characterized in that, After performing a reset verification operation at each time point and obtaining the verification result at each time point, the method further includes: Determine whether the number of iterations of the reset verification operation has reached the preset number; If it is determined that the number of loops for the reset verification operation has not reached the preset number, the number of loops is incremented, and the functional module is executed to restore the target working scenario to its initial state. If the number of cycles of the reset verification operation reaches the preset number, the current reset function verification is terminated; wherein, the preset number is related to the working time period.

7. A verification device for a reset function, characterized in that, include: The acquisition unit is used to determine the target working scenario of the functional module and acquire the working time period of the target working scenario; A traversal unit is used to sequentially traverse each point in time within the work time period; An execution unit is configured to perform a reset verification operation at each time point and obtain the verification result at each time point. The determining unit is used to determine the coverage information of the reset function of the functional module in the target working scenario based on the verification results at each time point.

8. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-6.

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