Image sending and displaying method and electronic equipment

Abstract

The invention discloses an image transmitting and displaying method and electronic equipment, and relates to the technical field of terminals. In the image sending and displaying process, after the preset condition is met, the electronic equipment can improve the frequency of generating the TE signal so as to reduce the display lagging phenomenon of the display screen. After the frequency of generating a TE signal is improved, the arrival moment of the TE signal is within the dormancy time of a chip providing hardware computing power, and image sending and displaying fail. Before the frequency of generating the TE signal is improved, the hardware computing power of the SoC is closed, and resources required by transmitting and displaying can be calculated by using the software computing power. In this way, display lagging caused by display drive display sending failure due to dormancy of a chip providing hardware computing power can be avoided, the probability of display lagging is reduced, and the user experience is improved.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to an image display method and electronic device. Background Technology

[0002] Electronic devices can use a central processing unit (CPU) and a graphics processing unit (GPU) to complete drawing, rendering, and compositing, processing the image data of a frame of an image. Then, when a tear effect (TE) signal is detected, such as when the rising edge of the TE signal is detected, the display driver can send the image data to the display screen for display.

[0003] If the display driver fails to send the image data of the next frame to the display screen when the TE signal arrives, the same frame will be displayed continuously on the screen, resulting in display lag and affecting the user experience. Summary of the Invention

[0004] This application provides an image display method and electronic device that can reduce the probability of display lag and improve the user experience.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] Firstly, an image display method is provided, the method comprising:

[0007] With the stuttering compensation function of the first application on the electronic device already enabled, when the first application enters the foreground, the electronic device immediately disables the hardware computing power of the SoC. In this way, the SoC's display driver will not use the hardware computing power to calculate the resources required for display when sending the display, but will use the software computing power of the display driver to calculate the resources required for display.

[0008] At a second time point following the first time point, the electronic device generates a first TE signal. In response to the first TE signal, the SoC sends the first image data of the first application to the display screen. At a third time point following the second time point, the electronic device generates a next TE signal (a second TE signal). In response to the second TE signal, the SoC sends the next frame of image data (second image data) of the first application to the display screen. The time interval between the second TE signal and the first TE signal is a first time interval; correspondingly, the frequency at which the electronic device generates the TE signal is a first frequency.

[0009] At the fourth moment following the third moment, the electronic device still generates the next TE signal (the third TE signal) at the first frequency, meaning the time interval between the third TE signal and the second TE signal is the first time interval. At the fourth moment, the next frame of image data for the first application has not yet completed preparations for display. When the third TE signal arrives, the SoC does not send the next frame of image data for the first application to the display screen; that is, a processing stutter occurs.

[0010] At the fifth moment, following the fourth moment, the electronic device generates the next TE signal (the fourth TE signal). Before the fifth moment, the next frame of image data (the third image data) for the first application has completed preparations for display. When the fourth TE signal arrives, in response to the fourth TE signal, the SoC sends the third image data to the display screen. The time interval between the fourth TE signal and the third TE signal is the second time interval, which is shorter than the first time interval. In other words, after a processing lag occurs, the electronic device increases the frequency of generating TE signals. This ensures that the image data (the third image data) that experienced a processing lag can be displayed as early as possible, and that the next frame of image data can be displayed on time after completing preparations for display, reducing display lag.

[0011] In this method, with the stuttering compensation function of the first application enabled, after the first application enters the foreground, the electronic device increases the frequency of generating TE signals upon detecting a processing stutter in one frame of image data from the first application, thereby reducing display stuttering. By increasing the frequency of TE signal generation, the arrival of the TE signal occurs during the sleep period of the chip providing hardware computing capabilities. After the first application enters the foreground, the SoC's hardware computing capabilities are disabled, allowing the display driver to use software computing capabilities to calculate the resources required for display before sending the data. This avoids the chip providing hardware computing capabilities going into sleep mode upon the arrival of the TE signal, which could lead to display driver failure and resulting in stuttering. This reduces the likelihood of display stuttering and improves the user experience.

[0012] In conjunction with the first aspect, in one possible implementation, after the first application exits the foreground, at a sixth time following the fifth time, the electronic device activates the hardware computing capabilities of the SoC.

[0013] In this way, the display driver can use the hardware's computing power to calculate the resources required for display, thereby improving software performance and reducing software power consumption.

[0014] In one possible implementation, the TE signal is generated by a display screen (such as a DDIC).

[0015] In conjunction with the first aspect, in one possible implementation, if the SoC completes preparations for sending the third image data to the display screen at a seventh time (which is after the fourth time and before the fifth time), meaning the next frame of image data for the first application has not yet been prepared for display at the fourth time (i.e., a processing lag has occurred), then the SoC sends a control command to the display screen to cause the display screen to generate a TE signal at a second frequency. The second frequency is greater than the first frequency, the first frequency corresponds to a first time interval, and the second frequency corresponds to a second time interval. That is, the frequency at which the display screen generates the TE signal is increased after a processing lag occurs.

[0016] In conjunction with the first aspect, in one possible implementation, the hardware computing power of the SoC is provided by the Cesta chip. When the SoC's display driver uses the computing power provided by the Cesta chip, to reduce hardware power consumption, the display driver will wake up the Cesta chip at a specific time. After being woken up, the Cesta chip will go into sleep mode after a preset wake-up time. During the Cesta chip's sleep period, the display driver cannot perform display submission. If processing lag occurs, increasing the frequency of generating the TE signal will cause the TE signal to arrive during the Cesta chip's sleep period, leading to display driver failure to submit the display and resulting in prolonged display lag. By enabling the lag compensation function and disabling the Cesta chip's computing power, software computing power can be used to calculate the resources required for display submission, thus avoiding display driver failure to submit the display.

[0017] In conjunction with the first aspect, in one possible implementation, the electronic device disables the hardware computing capabilities of the SoC by writing to the registers of the cesta chip to disable the computing capabilities of the cesta chip.

[0018] In conjunction with the first aspect, in one possible implementation, at the eighth time after the fifth time, the electronic device generates the next TE signal (the fifth TE signal) after the fourth TE signal, and the time interval between the fifth TE signal and the fourth TE signal is the first time interval.

[0019] In this method, after the image data that caused the lag is successfully sent to the display, the high-frequency TE is turned off, that is, the TE signal is generated at the first frequency. In this way, on the one hand, the large power consumption caused by the high-frequency TE for a long time can be avoided; on the other hand, various problems caused by the hardware or software not being able to support the high-frequency TE for a long time can be avoided.

[0020] In conjunction with the first aspect, in one possible implementation, the first time interval is 8.3 milliseconds and the second time interval is 2.7 milliseconds.

[0021] In conjunction with the first aspect, in one possible implementation, the SoC includes a cesta chip, and the SoC's operating system includes a display driver, so that when a second application of the electronic device enters the foreground, the first application exits the foreground.

[0022] At the ninth moment, the display generates the sixth TE signal. After a first duration following the ninth moment (the tenth moment), the display driver sends a first instruction to the Cesta chip to wake it up. The Cesta chip then goes into sleep mode after a second duration following the tenth moment (the eleventh moment). At the twelfth moment, the display generates the next TE signal after the sixth TE signal (the seventh TE signal). In response to the seventh TE signal, the SoC sends the fourth image data for the second application to the display. The twelfth moment occurs after the tenth moment and before the eleventh moment, meaning the Cesta chip is woken up at the twelfth moment. The time interval between the seventh and sixth TE signals is the first time interval.

[0023] In this method, when the hardware computing capabilities of the SoC are enabled, the hardware computing capabilities provided by the cesta chip are used to calculate the resources required for display, thereby improving computing performance; the periodic sleep mode of the cesta chip can reduce hardware power consumption.

[0024] Secondly, an image display method is provided, the method comprising:

[0025] When the game frame tracking function of the electronic device's game application is enabled, the electronic device disables the SoC's hardware computing power immediately after the game application starts. In this way, the SoC's display driver will not use the hardware computing power to calculate the resources required for display when sending the display, but will use the display driver's software computing power to calculate the resources required for display.

[0026] At a second moment following the first moment, the electronic device generates a first TE signal. In response to the first TE signal, the SoC sends the first image data of the game application to the display screen. At a third moment following the second moment, the electronic device generates a next TE signal (second TE signal). In response to the second TE signal, the SoC sends the next frame of image data of the game application (second image data) to the display screen. The time interval between the second TE signal and the first TE signal is the first time interval; correspondingly, the frequency at which the electronic device generates the TE signal is the first frequency.

[0027] At the fourth moment following the third moment, the electronic device generates the next TE signal (the third TE signal). In response to the third TE signal, the SoC sends the next frame of image data (the third image data) of the second image data to the display screen. The time interval between the third TE signal and the second TE signal is the second time interval, which is shorter than the first time interval. In other words, the electronic device increases the frequency of generating TE signals.

[0028] By increasing the frequency of the TE signal generation, the arrival of the TE signal coincides with the sleep period of the chip providing hardware computing capabilities. After the game application enters the foreground, the SoC's hardware computing capabilities are disabled, allowing software computing capabilities to calculate the resources needed for display before the display driver sends data. This avoids the display driver failing to send data due to the chip providing hardware computing capabilities going to sleep when the TE signal arrives, thus reducing the likelihood of display stuttering and improving the user experience.

[0029] In conjunction with the second aspect, in one possible implementation, after the game application exits the foreground, at a fifth moment following the fourth moment, the electronic device activates the SoC's hardware computing capabilities. In this way, the display driver can use the hardware computing power to calculate the resources required for display, improving software performance and reducing software power consumption.

[0030] In conjunction with the second aspect, in one possible implementation, if the SoC completes preparations before sending the third image data to the display screen at the sixth moment, wherein the interval between the sixth moment and the third moment is less than a preset threshold, then the SoC sends a control command to the display screen to increase the frequency at which the display screen generates the TE signal, i.e., the display screen generates the TE signal at a second frequency. The second frequency is greater than the first frequency, the first frequency corresponds to the first time interval, the second frequency corresponds to the first period value (second period), and the second time interval is the difference between the first time interval and the first period value. Correspondingly, the time interval between the third TE signal and the second TE signal is the second time interval, which is less than the first time interval.

[0031] In other words, if the interval between the preparation time for the next frame of the second image data to be displayed and the display time of the second image data is less than a preset threshold (for example, the preset threshold is the difference between the first time interval and the first period value), then a high-frequency TE is activated to generate a TE signal at the second frequency. This allows a TE to be generated one time interval earlier than the expected arrival time of the next TE signal calculated according to the first frequency (corresponding to the first time interval) by a preset duration threshold (the first period value), enabling the frame of image data to be displayed earlier. This allows the user to perceive that the electronic device responds to user operations and updates the image more quickly, improving responsiveness.

[0032] In one possible implementation, the preset threshold is the difference between the first time interval and the second time interval.

[0033] In conjunction with the second aspect, in one possible implementation, the hardware computing power of the SoC is provided by the Cesta chip. When the SoC's display driver uses the computing power provided by the Cesta chip, to reduce hardware power consumption, the display driver will wake up the Cesta chip at a specific time. After being woken up, the Cesta chip will go into sleep mode after a preset wake-up time. During the Cesta chip's sleep period, the display driver cannot perform display delivery. Increasing the frequency of generating the TE signal means that the arrival of the TE signal will fall within the Cesta chip's sleep period, causing the display driver to fail to deliver the display, resulting in prolonged display stuttering. By enabling the game frame tracking function and disabling the Cesta chip's computing power, software computing power can be used to calculate the resources required for display delivery, avoiding display driver failure to deliver the display.

[0034] In conjunction with the second aspect, in one possible implementation, the electronic device disables the hardware computing capabilities of the SoC by writing to the registers of the cesta chip to disable the computing capabilities of the cesta chip.

[0035] In conjunction with the second aspect, in one possible implementation, after the frame image data is successfully displayed, the high-frequency TE is turned off, that is, the TE signal is generated at the first frequency. In this way, on the one hand, the large power consumption caused by the high-frequency TE for a long time can be avoided; on the other hand, various problems caused by the hardware or software not supporting the high-frequency TE for a long time can be avoided.

[0036] In conjunction with the second aspect, in one possible implementation, the first time interval is 8.3 milliseconds and the second time interval is 2.7 milliseconds.

[0037] Thirdly, this application also provides an electronic device including a display panel, a memory, and one or more processors. The display panel, memory, and processors are coupled. The memory stores computer program code, which includes computer instructions that, when executed by the processor, cause the electronic device to perform the methods described in the first aspect and any of its possible designs.

[0038] Fourthly, this application provides a chip system applied to an electronic device including a display panel and a memory; the chip system includes one or more interface circuits and one or more processors; the interface circuits and processors are interconnected via lines; the interface circuits are used to receive signals from the memory of the electronic device and send signals to the processor, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device performs a method as described in the first aspect and any of its possible design embodiments.

[0039] Fifthly, this application provides a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform a method as described in the first aspect and any of its possible design embodiments.

[0040] Sixthly, this application provides a computer program product that, when run on a computer, causes the computer to perform a method as described in the first aspect and any of its possible design methods.

[0041] Understandably, the beneficial effects achieved by the electronic device of the third aspect, the chip system of the fourth aspect, the computer-readable storage medium of the fifth aspect, and the computer program product of the sixth aspect provided above can be referred to the beneficial effects of the first aspect and any of its possible design embodiments, which will not be repeated here. Attached Figure Description

[0042] Figure 1 One of the schematic diagrams illustrating the principle of image display provided in the embodiments of this application;

[0043] Figure 2 A second schematic diagram illustrating the principle of image display provided in this application embodiment;

[0044] Figure 3 The third schematic diagram illustrating the principle of image display provided in the embodiments of this application;

[0045] Figure 4 The waveform diagrams of TE signals with frequencies of 60Hz, 90Hz, 120Hz, and 360Hz provided for embodiments of this application;

[0046] Figure 5 A schematic diagram illustrating an example of dynamically adjusting the frequency of the TE signal provided in this application embodiment;

[0047] Figure 6 A schematic diagram illustrating the process of a display lag occurrence provided in an embodiment of this application;

[0048] Figure 7 A schematic diagram illustrating the method for determining processing lag provided in an embodiment of this application;

[0049] Figure 8 This application provides an embodiment of a schematic diagram showing how an electronic device dynamically adjusts the frequency of the TE signal when a processing lag occurs after enabling the lag compensation function.

[0050] Figure 9This application provides an embodiment of a schematic diagram showing that, after enabling the game frame tracking function, in a game scene, when the preparation time for sending a certain frame image to the display is earlier, the electronic device dynamically adjusts the frequency of the TE signal.

[0051] Figure 10 A schematic diagram illustrating a scenario example of the stuttering compensation function in the image display method provided in this application embodiment;

[0052] Figure 11 A schematic diagram illustrating a scenario example of game frame tracking functionality in the image display method provided in this application embodiment;

[0053] Figure 12 A schematic diagram illustrating an example of a Cesta chip being woken up and put into sleep mode, as provided in an embodiment of this application.

[0054] Figure 13 A schematic diagram illustrating the principle of display lag that occurs for a relatively long time after enabling high-frequency TE when there is processing lag, as provided in the embodiments of this application;

[0055] Figure 14 A schematic diagram illustrating the principle of prolonged display stuttering after enabling high-frequency TE in a game frame-tracking scenario provided in this application embodiment;

[0056] Figure 15 This is a schematic diagram illustrating a scenario example of the image display method provided in the embodiments of this application.

[0057] Figure 16 A hardware structure diagram of an electronic device to which the image display method provided in the embodiments of this application is applicable;

[0058] Figure 17 A hardware and software architecture diagram of an electronic device to which the image display method provided in the embodiments of this application is applicable;

[0059] Figure 18 This is a schematic flowchart of an image display method provided in an embodiment of this application;

[0060] Figure 19 This is a schematic diagram of the chip system provided in an embodiment of this application. Detailed Implementation

[0061] In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0062] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0063] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0064] Before introducing the embodiments of this application, the following will first combine... Figures 1-3 A brief introduction to the principle of image display.

[0065] See Figure 1 Electronic devices include system-on-chips (SoCs) and displays (also known as screens).

[0066] The SoC integrates key chips such as an application processor (AP) and a baseband processor (BP, also known as a modem). Furthermore, the AP may include processing units such as a CPU and a GPU. Some SoCs may also integrate hardware chips that implement specific functions, such as hardware computing units that provide hardware computing capabilities. In one implementation, the hardware computing unit may be a CESAT chip, the specific functions of which will be described in detail later.

[0067] The display screen may include a display control module, an image storage unit, and a display panel.

[0068] For example, the display control module can be a display driver integrated circuit (DDIC). It should be noted that the display control module can also be called a controller, driver circuit, etc., and this application embodiment does not specifically limit it in this way.

[0069] For example, the image storage unit can be random access memory (RAM), such as graphics RAM (GRAM).

[0070] The following explanation will use DDIC as an example, where the display control module is a display controller and GRAM is the image storage unit.

[0071] During image processing, electronic devices can use the CPU and GPU within the SoC to execute image processing steps such as drawing, rendering, and compositing to generate image data. The display driver in the SoC's software architecture sends (writes) the processed image data to the GRAM in the display screen. Then, the DDIC refreshes the image data from the GRAM onto the display panel, thus enabling image display.

[0072] DDIC can control the writing and reading of image data in GRAM through the Tear Effect (TE) signal.

[0073] See Figure 2 The TE signal can be a periodic pulse signal, each TE signal (pulse signal) including a rising edge (TE(up)) and a falling edge (TE(down)). DDIC can generate TE signals, and the display driver in the SoC detects the arrival of the rising edge of the TE signal, such as... Figure 2 After TE (up) arrives, it can be Figure 2During the time period indicated by the "Send Image (short for sending image data from the display driver to the GRAM)" flag X, the image data of a new frame is written into the GRAM.

[0074] Subsequently, after the falling edge of the TE signal arrives, the DDIC can refresh the image data of the new frame in the GRAM onto the display panel, allowing the display panel to show the new frame of image. For example, in Figure 2 During the time period marked Y after the arrival of TE (bottom), the image data of the new frame in GRAM is refreshed to the display panel.

[0075] It is understandable that the falling edge of the TE signal arrives slightly later than the rising edge. In other words, for a new frame of image data, the display driver starts writing the data line by line into the GRAM slightly earlier than the time it starts refreshing the data line by line onto the display panel. When the speed at which the image data is written into the GRAM is greater than or equal to the speed at which it is refreshed onto the display panel, it is possible to complete the writing and reading (refreshing to the display panel) of one frame of image data within one TE cycle.

[0076] The display panel can be refreshed via a source signal. See also... Figure 2 After the falling edge of the TE signal arrives, the DDIC reads image data from the GRAM. At this time, the Source signal generated by the display panel is high. This high level illuminates the corresponding pixels on the display panel based on the image data read by the DDIC, thereby refreshing the image on the display panel. It should be noted that in actual implementation, the DDIC can also read image data from the GRAM before the falling edge of the TE signal arrives, and complete the reading of the entire image data before the falling edge of the TE signal arrives. In this way, after the falling edge of the TE signal arrives, the display panel can quickly refresh and display the new image.

[0077] After the refresh is complete, the display panel can pull the Source signal low to reduce power consumption when the image is not being refreshed. It should be noted that during the period when the Source signal is low, the image will not be refreshed; this state can be called the hold state.

[0078] As can be seen, the TE signal allows control over the process. After a frame of image data is refreshed, the display driver writes image data to the GRAM based on the rising edge of the TE signal, and the DDIC reads image data from the GRAM based on the falling edge of the TE signal. Furthermore, by controlling the rate at which the display driver writes image data to the GRAM and the rate at which the DDIC reads image data from the GRAM, the progress of the DDIC reading image data from the GRAM is always behind the progress of the display driver writing image data to the GRAM, thus preventing screen tearing. The process of the display driver writing image data to the GRAM can also be referred to as the display driver sending process.

[0079] Furthermore, electronic devices can control the image processing rhythm of the SoC (such as CPU, GPU, etc.) through the Vsync signal. It should be noted that the Vsync signal in this article refers to the software signal simulated by the SoC (such as the Surface Flinger (SF) in the SoC's software architecture) based on the rising edge of the TE signal. The SoC can simulate a software signal that coincides with the rising edge of the TE signal, causing the software signal to change with each arrival of the rising edge of the TE signal, such as a level transition (including a transition from low to high or from high to low), thereby triggering the start of processing a new frame of image when the TE signal arrives. That is, the Vsync signal can be a clock signal, such as a transition every 8.3ms.

[0080] Therefore, it should be noted that an image goes through three stages from the start of processing to its display on the screen. In the first stage, drawing and rendering begin when the Vsync signal corresponding to the rising edge of a TE signal is triggered. In the second stage, when the Vsync signal corresponding to the rising edge of the next TE signal is triggered, compositing and preparation for display begin. Then, in the third stage, when another TE signal is triggered, display is executed, and the processed image is displayed on the screen.

[0081] Furthermore, the processing and display of multiple frames can be as follows: After the rising edge of a TE signal arrives, on the one hand, the drawing and rendering of the (k+1)th frame can begin under the trigger of the corresponding Vsync signal. On the other hand, the synthesis and preparation for display of the kth frame can begin under the trigger of the corresponding Vsync signal. Finally, under the trigger of the rising edge of the TE signal, the display of the (k-1)th frame can begin, and the (k-1)th frame can be displayed on the screen.

[0082] Specifically, the DDIC can generate a TE signal. Triggered by the rising edge of this TE signal, the display driver can write the currently processed image data, such as the image data of the (k-1)th frame mentioned above, into the GRAM to achieve image display. The compositing management unit can obtain the timestamp corresponding to the rising edge of the TE signal and calculate the time of the rising edge of the next TE signal accordingly. The CPU, GPU, etc., can estimate the timing for starting a new frame image, such as the timing for drawing and rendering the (k+1)th frame mentioned above, based on the calculated time, and start drawing and rendering the new frame image after the timing arrives, so that the drawing and rendering of the new frame image can be completed before the arrival of the next TE signal. Furthermore, the CPU, GPU, etc., can also estimate the timing for starting the current frame image, such as the timing for compositing the kth frame mentioned above, based on the calculated time, and start compositing the current frame image after the timing arrives, so that the compositing of the current frame image can be completed and the image data of the current frame image can be obtained before the arrival of the next TE signal, and then given to the display driver. After the arrival of the next TE signal, the display driver can then execute the display.

[0083] The following is combined Figure 3 Taking the (k-1)th frame as the 0th frame, the kth frame as the 1st frame, and the (k+1)th frame as the 2nd frame as an example, the specific process of image processing is described below:

[0084] After TE2 arrives, the display driver can send the 0th frame image to the screen when triggered by the rising edge of TE2, so that the display screen can display the 0th frame image between TE2 and TE3.

[0085] After TE2 arrives, the compositing management unit can obtain the timestamp corresponding to the rising edge of TE2 and calculate the time of the rising edge of the next TE signal, TE3. The CPU, GPU, and other components can then estimate the timing for starting the compositing of the first frame (before the rising edge of TE3) based on this time, and begin compositing the first frame after the timing arrives. Furthermore, the compositing of the first frame is completed before TE3 arrives.

[0086] Furthermore, the CPU, GPU, and other components can estimate in advance the timing of drawing and rendering the second frame image based on the rising edge of TE3 (located before the rising edge of TE3), and start drawing and rendering the second frame image after the timing arrives, so that the drawing and rendering of the second frame image can be completed before TE3 arrives.

[0087] Next, after TE3 arrives, the display driver can execute the sending of the first frame image under the trigger of the rising edge of TE3, so that the display screen can display the first frame image between TE3 and TE4.

[0088] After TE3 arrives, the compositing management unit can obtain the timestamp corresponding to the rising edge of TE3 and calculate the time of the rising edge of the next TE signal, TE4. The CPU, GPU, etc., can estimate the timing for starting the compositing of the second frame image based on the time of the rising edge of TE4 (before the rising edge of TE4), and begin compositing the second frame image after the timing arrives. Furthermore, the compositing of the second frame image is completed before TE4 arrives. The CPU, GPU, etc., can also estimate the timing for starting the drawing and rendering of the third frame image based on the time of the rising edge of TE4 (before the rising edge of TE4), and begin drawing and rendering the third frame image after the timing arrives.

[0089] Next, after TE4 arrives, the display driver can execute the sending of the second frame image under the trigger of the rising edge of TE4, so that the display screen can display the second frame image between TE4 and the next TE.

[0090] Similarly, based on the control of the TE signal (and the Vsync signal), the refresh of each frame of the image is completed.

[0091] It should be noted that, Figure 3 Taking the display of frame 0 after TE2 as an example, in practice, when the rising edge of TE2 arrives, the display driver can first start writing the image data of frame 0 to the GRAM in the display screen. Then, after the falling edge of TE2 arrives, the DDIC in the display screen can refresh the image data of frame 0 in the GRAM to the display panel. Only then does the display of frame 0 begin. That is, the actual time when the display of frame 0 begins is slightly later than the arrival of the rising edge of TE2. The sending and display of other frames is the same, and will not be elaborated here.

[0092] As mentioned earlier, the TE signal can be a periodic pulse signal, and the DDIC can control the period (frequency) of the pulse signal generation. For example, the DDIC can generate pulse signals at frequencies such as 30Hz, 60Hz, 90Hz, 120Hz, and 360Hz, that is, generate TE signals with frequencies of 30Hz, 60Hz, 90Hz, 120Hz, and 360Hz. In this embodiment, the frequency at which the DDIC generates the TE signal (pulse signal) is called the frequency of the TE signal, and the time interval between two adjacent TE signals (rising edges) is called the period of the TE signal. When the DDIC generates a TE signal with a frequency of 60Hz, that is, the period of the TE signal is approximately 16.6ms, the refresh rate of the display panel can reach 60Hz, and the image on the display panel can be refreshed once every 16.6ms. When the DDIC generates a TE signal with a frequency of 90Hz, that is, the period of the TE signal is approximately 11.1ms, the refresh rate of the display panel can reach 90Hz, and the image on the display panel can be refreshed once every 11.1ms. When the DDIC generates a TE signal at a frequency of 120Hz, meaning the TE signal period is approximately 8.3ms, the corresponding refresh rate of the display panel can reach 120Hz, refreshing the image on the display panel approximately once every 8.3ms. When the DDIC generates a TE signal at a frequency of 360Hz, meaning the TE signal period is approximately 2.7ms, the refresh rate of the display panel can also reach 120Hz, refreshing the image on the display panel approximately once every 8.3ms. In one implementation, compared to a 360Hz TE signal: a 120Hz TE signal is equivalent to generating one TE signal every two TE signals of the 360Hz TE signal. A 60Hz TE signal is equivalent to generating one TE signal every five TE signals of the 360Hz TE signal.

[0093] For example, Figure 4 This is a waveform diagram of a TE signal with frequencies of 60Hz, 90Hz, 120Hz, and 360Hz.

[0094] like Figure 4 (a) and Figure 4 As shown in (b), for a 60Hz TE signal, the time interval between two adjacent pulse signals is approximately 16.6ms; Figure 4 As shown in (c), for a 90Hz TE signal, the time interval between two adjacent pulse signals is approximately 11.1ms; Figure 4 As shown in (d), for a 120Hz TE signal, the time interval between two adjacent pulse signals is approximately 8.3ms; Figure 4As shown in (e), the time interval between two adjacent pulses of a 360Hz TE signal is approximately 2.7ms. The high-level holding time of the pulses in the TE signal may vary depending on the specific circumstances (e.g., different hardware capabilities), for example... Figure 4 (a) and Figure 4 As shown in (b), it is also a 60Hz TE signal. Figure 4 The high-level holding time of each pulse signal in the TE signal shown in (a) is greater than Figure 4 The high-level holding time of each pulse signal in the TE signal shown in (b).

[0095] Generally, the refresh rate of a display panel is relatively stable over a period of time. For example, the refresh rate of a display panel can be fixed at 120Hz, in which case the display panel refreshes approximately every 8.3ms. This ensures that the display refreshes the image at a relatively stable frequency, and the various units in the SoC (such as the CPU and GPU) process the image data based on the Vsync signal at a fixed frequency, outputting the image to the display panel relatively stably.

[0096] In some scenarios, the frequency of the TE signal can be dynamically adjusted to optimize the image display process and improve the user experience.

[0097] refer to Figure 5 In some embodiments, the electronic device typically generates a TE signal (hardware signal) at a first frequency (e.g., 120Hz), and correspondingly, generates a Vsync signal (software signal) corresponding to the TE signal at the same first frequency (e.g., 120Hz). In one implementation, the SF manages the frequencies of the Vsync signal and the TE signal. For example, if the SF determines that the frequency of the Vsync signal is the first frequency (e.g., 120Hz), then the SF notifies the display driver that the frequency of the TE signal is the first frequency; the display driver sends a first control command to the DDIC, notifying the DDIC to generate the TE signal at the first frequency (e.g., 120Hz). The DDIC generates the TE signal at the first frequency (e.g., 120Hz), and the SF simulates a Vsync signal with the rising edge of the TE signal, so that the frequency of the Vsync signal is also the first frequency (e.g., 120Hz). Thus, the CPU, GPU, etc., perform image drawing, rendering, compositing, etc., based on the Vsync signal at the first frequency, the display driver sends images based on the Vsync signal at the first frequency (i.e., the TE signal at the first frequency), and the DDIC refreshes images based on the TE signal at the first frequency. For example, refer to... Figure 3 The process shown involves various units in the electronic device, such as the CPU, GPU, display driver, and DDIC, generating image data based on the TE signal of the first frequency, and sending the image data to the display to show frame by frame of images.

[0098] When the first condition is met, the electronic device generates a TE signal (hardware signal) at a second frequency (e.g., 360Hz). In one implementation, after the display driver determines that the first condition is met, it sends a second control command to the DDIC, instructing the DDIC to generate a TE signal at the second frequency (e.g., 360Hz), and the DDIC generates the TE signal (hardware signal) at the second frequency (e.g., 360Hz). The second frequency is greater than the first frequency, meaning the electronic device increases the frequency of the TE signal. In this embodiment, the TE signal at the second frequency is referred to as a high-frequency TE. Compared to the TE signal at the first frequency, the next one or more pulse signals of the TE signal at the second frequency arrive earlier; thus, after the image data for the next frame is ready, the display driver can display the image data of that frame in response to the rising edge of the soon-to-arrive TE signal, and the DDIC can refresh the image data to the display panel in response to the falling edge of the soon-to-arrive TE signal.

[0099] Optionally, after the second condition is met, the electronic device generates a TE signal (hardware signal) at a first frequency (e.g., 120Hz). In one implementation, after the display driver determines that the second condition is met, it sends a third control command to the DDIC, instructing the DDIC to generate a TE signal at the first frequency (e.g., 120Hz). The DDIC then generates the TE signal (hardware signal) at the first frequency (e.g., 120Hz). Various units in the electronic device, such as the CPU, GPU, display driver, and DDIC, generate image data based on the TE signal at the first frequency and send the image data to the display, showing frame-by-frame images.

[0100] During this process, the electronic device dynamically adjusts the frequency of the TE signal. Correspondingly, the timing of the display driver sending the image changes with the frequency of the TE signal, and the frequency of the display screen refreshing the image is also dynamically adjusted. In some scenarios, the image sending process can be optimized, and certain performance of the electronic device can be improved.

[0101] For example, in one scenario, the SoC takes a long time to process image data and cannot prepare a frame of image data before the TE signal arrives, causing display jerking on the screen. In this scenario, the frequency of the TE signal can be dynamically adjusted to improve the timeliness of the display driver's delivery in the SoC, thereby reducing display jerking.

[0102] The following is combined Figure 6 Describe the process that causes a display stutter.

[0103] and Figure 3 The example shown is similar, still using the case that the (k-1)th frame is the 0th frame, the kth frame is the 1st frame, and the (k+1)th frame is the 2nd frame.

[0104] like Figure 6As shown, after TE2 arrives, the display driver can execute the sending of the 0th frame image under the trigger of the rising edge of TE2, so that the display screen can display the 0th frame image between TE2 and TE3.

[0105] After TE2 arrives, the compositing management unit can obtain the timestamp corresponding to the rising edge of TE2 and calculate the time of the rising edge of the next TE signal, TE3. The CPU, GPU, and other components can then estimate the timing for starting the compositing of the first frame (before the rising edge of TE3) based on this time, and begin compositing the first frame after the timing arrives. Furthermore, the compositing of the first frame is completed before TE3 arrives.

[0106] Furthermore, the CPU and GPU can predict the timing of starting the drawing and rendering of the second frame based on the rising edge of TE3 (before the rising edge of TE3), and begin drawing and rendering the second frame after the expected timing arrives, thus completing the drawing and rendering of the second frame before TE3 arrives. In some abnormal cases, the GPU may still be rendering the second frame before TE3 arrives, failing to complete the drawing and rendering of the second frame as expected, resulting in processing stuttering.

[0107] Next, after TE3 arrives, the display driver can execute the sending of the first frame image under the trigger of the rising edge of TE3, so that the display screen can display the first frame image between TE3 and TE4.

[0108] After TE3 arrives, the compositing management unit can obtain the timestamp corresponding to the rising edge of TE3 and calculate the time of the rising edge of the next TE signal TE4. The CPU, GPU, etc. can estimate the timing of starting the drawing and rendering of the third frame image in advance based on the time of the rising edge of TE4 (located before the rising edge of TE4), and start the drawing and rendering of the third frame image after the timing arrives.

[0109] In addition, since the rendering of the second frame image has not been completed when TE3 arrives, the compositing of the second frame image will not be triggered after TE3 arrives.

[0110] Then, after TE4 arrives, because the synthesis of the second frame image has not yet been completed (in fact, it has not yet started), the display driver, triggered by the rising edge of TE4, is also unable to send the second frame image for display. Consequently, the display screen will continue to display the first frame image, meaning the first frame image will be displayed continuously for at least two frames. In other words, the processing delay of the second frame image causes the display delay of the first frame image.

[0111] The above regarding Figure 6The description mainly shows the process of processing stuttering (such as the second frame image) and display stuttering (such as the first frame image). In reality, when the CPU and GPU experience processing stuttering during the processing of multiple consecutive frames, corresponding continuous display stuttering may occur, making the stuttering problem more prominent.

[0112] This application provides an image display method that increases the frequency of the TE signal when a processing lag is detected in a frame of image. For example, under normal circumstances, the electronic device generates a TE signal (hardware signal) at a first frequency (e.g., 120Hz), and correspondingly, generates a Vsync signal (software signal) corresponding to the TE signal at the same first frequency (e.g., 120Hz). Thus, the CPU, GPU, etc., perform image drawing, rendering, and compositing based on the Vsync signal at the first frequency, the display driver sends the image to the screen based on the Vsync signal at the first frequency (i.e., the TE signal at the first frequency), and the DDIC refreshes the image based on the TE signal at the first frequency. When a processing lag is detected in a frame of image (i.e., the first condition is a frame of image processing lag), the electronic device generates a TE signal (hardware signal) at a second frequency (e.g., 360Hz). The second frequency is greater than the first frequency. In other words, the next one or more pulse signals of the second frequency TE signal will arrive earlier than the first frequency TE signal. In this way, after the frame of the image that is stuck in the processing is synthesized, the display driver can send the image data of the frame of the image to the display in response to the rising edge of the soon-to-arrive TE signal, and the DDIC can refresh the image data to the display panel in response to the falling edge of the soon-to-arrive TE signal, thereby reducing the duration of display lag.

[0113] The processing lag of a particular image frame could be due to delays in CPU or GPU processing, such as delays in SF or hardware compositor (HWcomposer, HWC) processing, delays in the drawing or rendering process, or delays in the compositing process. Any excessive time spent in any step of the process generating the image data for a particular frame will result in image data processing lag.

[0114] In one example, processing stuttering refers to a situation where the time interval between sending two adjacent frames exceeds a preset frame length, which is the frame length corresponding to the applied frame rate. When the display refresh rate matches the applied frame rate, the preset frame length is also equal to the period of the TE signal. The following explanation primarily uses the example of the preset frame length being equal to the period of the TE signal.

[0115] In one specific implementation, the image sending time interval includes the interval between the start time of the previous image sending by the display driver (short for the display driver sending image data to the GRAM) and the time when the display driver receives the image data this time.

[0116] Specifically, if the interval between the start time of the previous image transmission by the display driver and the time after the display driver receives the image data this time exceeds the preset frame length, it indicates that the interval between the two image transmissions is too long, resulting in processing lag. If the interval between the start time of the previous image transmission by the display driver and the time after the display driver receives the image data this time does not exceed the preset frame length, it indicates that the interval between the two image transmissions is appropriate, and there is no processing lag.

[0117] Furthermore, after receiving image data, the display driver can perform pre-display preparation work, such as initializing the hardware display registers and initializing the display timing. After completing the pre-display preparation work, the display driver can execute the display. This pre-display preparation work also increases the image transmission time interval. Therefore, the image transmission time interval can specifically include the interval between the start time of the previous image transmission by the display driver and the time when the display driver prepares to transmit the image this time.

[0118] See Figure 7 In (a), the display driver starts sending Figure A at time t1 and completes the preparation work before sending Figure B at time t2. If the interval between time t1 and time t2 exceeds the period of the TE signal (abbreviated as TE period in the figure, the same below), then there is a processing lag in the processing of Figure B.

[0119] See Figure 7 In (b), the display driver starts sending Figure A at time t3 and completes the preparation work before sending Figure B at time t4. The interval between time t3 and time t4 does not exceed the period of the TE signal, so there is no processing lag in the processing of Figure B.

[0120] It should be noted that the above Figure 7 (a) and Figure 7 (b) assuming the start time of the previous display (as shown in Figure A, such as time t1 or t3) coincides exactly with the rising edge of the TE signal, in practice, the start time of the previous display may not coincide with the rising edge of the TE signal, such as... Figure 7 (c) and Figure 7 As shown in (d).

[0121] The above Figure 7 (a) Figure 7 (b) Figure 7 (c) Figure 7 (d) in the examples all assume that the time when the display driver prepares to send the data (such as completing the preparation work before sending the data in Figure B) does not coincide with the rising edge of the TE signal. In reality, the time when the display driver prepares to send the data may also coincide exactly with the rising edge of the TE signal, such as... Figure 7 (e) and Figure 7As shown in (f), time t5 and time t6 coincide with the rising edge of the TE signal.

[0122] Of course, in actual implementation, the method of detecting processing lag described above is not the only option. For example, the display driver can also detect processing lag based on the interval between the time of the previous received image data and the time of the current received image data. If the interval between the time of the previous received image data and the time of the current received image data exceeds a preset frame length, it indicates that processing lag exists; if the interval between the time of the previous received image data and the time of the current received image data does not exceed the preset frame length, it indicates that processing lag does not exist.

[0123] In this embodiment of the application, the function of increasing the frequency of the TE signal to a second frequency when a processing lag occurs is called the lag compensation function. Increasing the frequency of the TE signal to the second frequency is called enabling high-frequency TE.

[0124] In one implementation, the electronic device can have a stuttering compensation function switch enabled or disabled by the user through the device's user interface (e.g., the "Settings" interface). When the stuttering compensation function is enabled, the electronic device increases the frequency of the TE signal to a second frequency when processing stutters occur. When the stuttering compensation function is disabled, the electronic device does not increase the frequency of the TE signal to the second frequency when processing stutters occur. Optionally, the electronic device may not have a stuttering compensation function switch enabled; for example, the stuttering compensation function may be enabled by default. Optionally, different stuttering compensation functions may be enabled for different applications; for example, the stuttering compensation function for application one may be enabled, while the stuttering compensation function for application two may be disabled.

[0125] Optionally, in some embodiments, after the frequency of the TE signal is increased to a second frequency, the frame of image that was processed and stuttered is synthesized and then displayed when the next TE signal arrives.

[0126] Optionally, in some embodiments, the high-frequency TE is turned off after the second condition is met. In one example, meeting the second condition includes successfully displaying the image where processing stuttering occurred; in another example, meeting the second condition includes triggering a preset number of TE signals at the second frequency; in yet another example, meeting the second condition includes the duration of triggering the TE signals at the second frequency being greater than or equal to a preset duration, etc.

[0127] In one implementation, after the second condition is met, the electronic device adjusts the frequency of the TE signal to the first frequency, i.e., turns off the high-frequency TE. This avoids the significant power consumption caused by prolonged high-frequency TE, and also prevents various problems caused by hardware or software limitations when high-frequency TE is enabled for extended periods. For example, if the SF does not support a 360Hz Vsync signal, prolonged high-frequency TE may cause the Vsync signal to become out of sync with the TE signal. Furthermore, unsuccessful SF calibration after enabling high-frequency TE may lead to application image display stuttering.

[0128] For example, Figure 8 This diagram illustrates how an electronic device dynamically adjusts the frequency of the TE signal when a processing lag occurs after the stutter compensation function is enabled.

[0129] like Figure 8 As shown, when the frequency of the TE signal is the first frequency, such as 120Hz, the period of the TE signal is approximately 8.3ms, meaning the time interval between two adjacent TE signals is approximately 8.3ms. For example, the time interval between the rising edge of TE0 and the rising edge of TE1 is approximately 8.3ms, and the time interval between the rising edge of TE1 and the rising edge of TE2 is approximately 8.3ms.

[0130] Before the rising edge of TE1 arrives, the image data of Figure A has been synthesized and prepared for display. When the rising edge of TE1 arrives, the display driver executes the display of Figure A under the trigger of the rising edge of TE1, so that the display screen displays the image of Figure A after TE1.

[0131] The next frame after Figure A is Figure B. Under normal circumstances, the image data synthesis and pre-display preparation for Figure B should be completed before TE2. Thus, when the rising edge of TE2 arrives, the display driver executes the display of Figure B on the trigger of the rising edge of TE2, causing the screen to display the image of Figure B after TE2. This allows the image displayed on the screen to be refreshed at a refresh rate of 120Hz.

[0132] If there is a processing delay in the processing of Figure B, causing the image data synthesis and pre-display preparation for Figure B to not be completed before TE2, the display driver will not execute the display of Figure B when the rising edge of TE2 arrives.

[0133] If the frequency of the TE signal remains at 120Hz, the next TE signal will arrive approximately 8.3ms after TE2. If the image data synthesis and pre-display preparation for Figure B can be completed before the arrival of the next TE signal, the display of Figure B will be executed after the rising edge of the next TE signal. Thus, Figure B will need to wait at least 8.3ms after TE2 before it can be displayed. Even if the image data synthesis and pre-display preparation for Figure B are completed very quickly after TE2, it will still require at least another 8.3ms before display. A processing delay of one frame of image data will result in a display delay of up to approximately 8.3ms; when there are processing delays across multiple frames, the display delay will be even more pronounced.

[0134] In some embodiments, when there is a processing lag in the processing of Figure B, for example, if the time interval between the start time of displaying Figure A (when the rising edge of TE1 arrives) and the time when Figure B is ready to be displayed (when the image data of Figure B is synthesized and ready for display) is greater than the first period (approximately 8.3ms) corresponding to the first frequency (120Hz), a high-frequency TE is enabled. In one implementation, after enabling the high-frequency TE, the frequency of the TE signal is the second frequency, such as 360Hz, and correspondingly, the period of the TE signal is approximately 2.7ms, that is, the time interval between two adjacent TE signals is approximately 2.7ms. For example, refer to... Figure 8 The time interval between the rising edge of TE3 and the rising edge of TE2 is approximately 2.7ms.

[0135] Before the rising edge of TE3 arrives, the image data of Figure B has already been synthesized and prepared for display. When the rising edge of TE3 arrives, the display driver executes the display of Figure B under the trigger of the rising edge of TE3, so that the display screen displays the image of Figure B after TE3. In this way, Figure B can be displayed approximately 2.7ms after TE2, that is, the image displayed on the screen is refreshed to Figure B as early as possible, reducing the duration of display stuttering caused by processing stuttering of Figure B.

[0136] Optionally, in some embodiments, after Figure B (image data with processing lag) is successfully displayed (i.e., the second condition is that an image with processing lag is displayed), the high-frequency TE is turned off. In one implementation, after turning off the high-frequency TE, the frequency of the TE signal is a first frequency, such as 120Hz. Correspondingly, the period of the TE signal is approximately 8.3ms, that is, the time interval between two adjacent TE signals is approximately 8.3ms. For example, refer to... Figure 8The time interval between the rising edge of TE4 and the rising edge of TE3 is approximately 8.3ms. Before the rising edge of TE4 arrives, the image data of Figure C has completed synthesis and preparation for display. When the rising edge of TE4 arrives, the display driver executes the display of Figure C under the trigger of the rising edge of TE4, so that the display screen displays the image of Figure C after TE4. In some implementations, after the high-frequency TE is turned off, the frequency of the TE signal can also be a third frequency, which is not equal to the first frequency, for example, the third frequency is 90Hz, 60Hz, etc.

[0137] It should be noted that DDIC can generate TE signals at different frequencies (e.g., first frequency, second frequency, third frequency, etc.). In one implementation, the periods of the various TE signals at different frequencies are synchronized. For example, refer to... Figure 7 The DDIC generates a TE signal at 360Hz, with a time interval of approximately 2.7ms between each adjacent pulse. When the DDIC generates a TE signal at 120Hz, it's equivalent to one out of every three pulses in the 360Hz TE signal being emitted. This emitted pulse is visible to the SoC, thus generating a 120Hz TE signal from the SoC's perspective. Therefore, if... Figure 8 As shown, when the high-frequency TE is turned on, the TE signal generated at the second frequency is TE3, and the time interval between TE3 and TE2 generated at the first frequency is 2.7ms.

[0138] It should be noted that, Figure 8 In the example shown, a processing stutter was detected within 2.7ms after TE2, and the image data in Figure B completed its pre-display preparation within 2.7ms after TE2. Correspondingly, a high-frequency TE signal was activated within 2.7ms after TE2, and the next TE signal emitted was TE3. In other examples, the image data in Figure B had not yet completed its pre-display preparation within 2.7ms after TE2, i.e., ... Figure 8 The image data in Figure B was not prepared for display before TE3, as shown. For example, the image data in Figure B was prepared for display within the second 2.7ms after TE2; correspondingly, the high-frequency TE was activated within the second 2.7ms after TE2, such as... Figure 8 As shown, the next TE signal to be emitted is TE3'.

[0139] For example, in another scenario, an electronic device is running a game application, and the display shows frames of the game. The frequency of the TE signal is a first frequency, such as 120Hz, which corresponds to the first cycle, approximately 8.3ms. When the image data of a frame has been synthesized and prepared for display, if the time interval between the current time and the expected arrival time of the next TE signal (calculated according to the first frequency) is greater than a preset duration threshold, that is, the interval between the time it takes for a frame to complete preparation for display and the time it takes for the previous frame to be displayed is less than the preset threshold (the preset threshold is the difference between the first cycle and the preset duration threshold), then the first condition is met, and high-frequency TE is activated. Optionally, high-frequency TE can be activated at a time earlier than the expected arrival time of the next TE signal calculated according to the first frequency by the preset duration threshold. In this way, the actual arrival time of the next TE signal is earlier than the expected arrival time of the next TE signal calculated according to the first frequency by the preset duration threshold, allowing the frame to be displayed earlier and providing users with a more responsive user experience.

[0140] In one implementation, after enabling high-frequency TE, the frequency of the TE signal is a second frequency, such as 360Hz. This second frequency corresponds to a second cycle, which is approximately 2.7ms. The preset duration threshold is the second cycle. That is, if the preparation time for a frame to be displayed is more than two cycles (e.g., 2.7ms) earlier than the expected arrival time of the next TE signal calculated according to the first frequency, then high-frequency TE is enabled at a time that is two cycles earlier than the expected arrival time of the next TE signal calculated according to the first frequency. In this way, the frame is displayed approximately two cycles (e.g., 2.7ms) earlier, reducing the display driver's waiting time for display, allowing the user to experience faster response from the electronic device to update the image, thus improving responsiveness.

[0141] In this embodiment of the application, in a game scenario, if the time for a frame to complete preparation before being displayed is more than two cycles earlier than the expected arrival time of the next TE signal, then the function of increasing the frequency of the TE signal to the second frequency is called the game frame tracking function.

[0142] In one implementation, the electronic device can have a game frame tracking function on / off switch, which the user can enable or disable via the user interface (e.g., the "Settings" interface of a game application). When the game frame tracking function is enabled, if the interval between the preparation time of a frame before display and the display time of the previous frame is less than a preset threshold, the electronic device increases the frequency of the TE signal to a second frequency. In one implementation, the preset threshold can be the difference between a first period and a preset duration threshold (e.g., a second period); that is, if the preparation time of a frame before display is more than a preset duration threshold (e.g., a second period) earlier than the expected arrival time of the next TE signal, the electronic device increases the frequency of the TE signal to the second frequency. When the game frame tracking function is disabled, if the preparation time of a frame before display is more than a second period earlier than the expected arrival time of the next TE signal, the electronic device does not increase the frequency of the TE signal to the second frequency. Optionally, the electronic device may not have a game frame tracking function on / off switch; for example, the game frame tracking function may be enabled by default.

[0143] Optionally, in some embodiments, after the frequency of the TE signal is increased to the second frequency, a frame of image is displayed when the next TE signal arrives. After the frame of image is displayed (i.e., the second condition is met), the electronic device adjusts the frequency of the TE signal back to the first frequency, i.e., turns off the high-frequency TE. In this way, on the one hand, the large power consumption caused by prolonged high-frequency TE can be avoided; on the other hand, various problems caused by insufficient hardware or software capabilities after prolonged high-frequency TE can be avoided. For example, the frames of images in a game application may not be able to continuously complete the preparation for display within the second cycle. When the high-frequency TE signal arrives, the image data is not ready and cannot be displayed, resulting in display stuttering.

[0144] For example, Figure 9 This diagram illustrates how, when the game frame tracking function is enabled, the electronic device dynamically adjusts the frequency of the TE signal in a game scene when a frame completes its preparation time for display earlier than expected.

[0145] like Figure 9 As shown, when the frequency of the TE signal is the first frequency, such as 120Hz, the period of the TE signal is the first period, such as 8.3ms, meaning the time interval between two adjacent TE signals is approximately 8.3ms. For example, the time interval between the rising edge of TE3 and the rising edge of TE4 is approximately 8.3ms.

[0146] Before the rising edge of TE4 arrives, the image data of Figure C has been synthesized and prepared for display. When the rising edge of TE4 arrives, the display driver executes the display of Figure C under the trigger of the rising edge of TE4, so that the display screen displays the image of Figure C after TE4.

[0147] Since the frequency of the TE signal is the first frequency, the next TE signal after TE4 is TE5', and the time interval between the rising edge of TE4 and the rising edge of TE5' is approximately 8.3ms.

[0148] In some examples, when the image data of Figure D is synthesized and preparations for display are completed, the time elapsed before the expected arrival of TE5' is greater than a preset duration threshold. If Figure D is only displayed when TE5' arrives, the display driver will need to wait for a period of time (greater than or equal to the preset duration threshold) before executing the display, wasting time.

[0149] In some embodiments, when the time between the completion of the preparation for display of Figure D and the expected arrival time of TE5' is greater than a preset duration threshold, a high-frequency TE is activated at a time that is a preset duration threshold earlier than the arrival time of TE5'. In one implementation, after activating the high-frequency TE, the frequency of the TE signal is a second frequency, such as 360Hz, and correspondingly, the period of the TE signal is approximately 2.7ms, that is, the time interval between two adjacent TE signals is approximately 2.7ms.

[0150] In one implementation, a preset duration threshold is defined as the second cycle corresponding to the second frequency. The second frequency is greater than the first frequency, and correspondingly, the second cycle is less than the first cycle. For example, when the second frequency is 360Hz, the second cycle is approximately 2.7ms. The high-frequency TE is activated at a time earlier than the preset duration threshold before the arrival time of TE5', that is, at a time two cycles earlier than the arrival time of TE5'. (Reference) Figure 9 The second cycle is approximately 2.7ms, meaning that the TE signal is generated about 2.7ms earlier than the expected arrival time of TE5'. This TE signal is TE5, and the arrival time of TE5 is about 2.7ms earlier than the expected arrival time of TE5'.

[0151] In another implementation, the preset duration threshold can also be a value greater than the second cycle. This is because adjusting the TE signal frequency also takes time, and a preset duration threshold greater than the second cycle allows the TE signal frequency adjustment to be completed at a time two cycles earlier than the arrival time of TE5'.

[0152] When the rising edge of TE5 arrives, the display driver executes the sending of image D under the trigger of the rising edge of TE5, so that the display screen displays the image of image D after TE5. Compared with the implementation without game frame tracking, the time for image D to be sent for display is advanced by about a preset duration threshold (e.g., 2.7ms) after enabling high-frequency TE, which shortens the time for electronic devices to respond to user operations and update images, and brings users a more responsive user experience.

[0153] Optionally, in some embodiments, the high-frequency TE is turned off after the second condition is met. In one example, meeting the second condition includes successfully displaying Figure D; in another example, meeting the second condition includes triggering a preset number of TE signals at the second frequency; in yet another example, meeting the second condition includes the duration of triggering the TE signals at the second frequency being greater than or equal to a preset duration, etc.

[0154] In one implementation, after disabling the high-frequency TE signal, the frequency of the TE signal is a first frequency, such as 120Hz. Correspondingly, the period of the TE signal is approximately 8.3ms, meaning the time interval between two adjacent TE signals is approximately 8.3ms. For example, refer to... Figure 9 The time interval between the rising edges of TE5 and TE6 is approximately 8.3ms. Before the rising edge of TE6 arrives, the image data of Figure E has completed synthesis and pre-display preparation. The time between the completion of pre-display preparation of Figure E and the expected arrival time of TE6 is equal to or less than a preset duration threshold. When the rising edge of TE6 arrives, the display driver executes the display of Figure E under the trigger of the rising edge of TE6, so that the display screen displays the image of Figure E after TE6. In some implementations, after the high-frequency TE is turned off, the frequency of the TE signal can also be a third frequency, which is not equal to the first frequency. For example, the third frequency is 90Hz, 60Hz, etc.

[0155] This concludes the examples of handling stuttering and frame-tracking scenarios in games, illustrating the scenarios, timing, and specific implementations for enabling high-frequency TE (Time-of-Flight) responses. Of course, high-frequency TE can also be enabled in other scenarios. For example, enabling high-frequency TE when displaying the first frame of a game application advances the display of the first frame, providing users with a faster response time on their electronic devices. Other scenarios for enabling high-frequency TE will not be detailed in this embodiment.

[0156] In some scenarios, abnormal display stuttering may occur when high-frequency TE is enabled.

[0157] In one example, such as Figure 10 As shown, when the frequency of the TE signal is the first frequency, such as 120Hz, the period of the TE signal is approximately 8.3ms. For example, the time interval between the rising edge of TE0 and the rising edge of TE1 is approximately 8.3ms, and the time interval between the rising edge of TE1 and the rising edge of TE2 is approximately 8.3ms.

[0158] Before the rising edge of TE1 arrives, the image data of Figure A has been synthesized and prepared for display. When the rising edge of TE1 arrives, the display driver executes the display of Figure A under the trigger of the rising edge of TE1, so that the display screen displays the image of Figure A after TE1.

[0159] The next frame after Figure A is Figure B. There is a processing lag in the processing of Figure B, preventing the image data synthesis and pre-display preparation for Figure B from being completed before TE2. The electronic device detects this processing lag and activates a high-frequency TE. After activating the high-frequency TE, the TE signal frequency is a second frequency, such as 360Hz, and the TE signal period is approximately 2.7ms. For example, refer to... Figure 10 The time interval between the rising edge of TE3 and the rising edge of TE2 is approximately 2.7ms.

[0160] In some cases, Figure B is not displayed for an extended period of time, the screen does not refresh the image and continues to display Figure A, resulting in prolonged display lag.

[0161] In another example, such as Figure 11 As shown, when the frequency of the TE signal is the first frequency, such as 120Hz, the period of the TE signal is the first period, such as 8.3ms. For example, the time interval between the rising edge of TE3 and the rising edge of TE4 is approximately 8.3ms.

[0162] Before the rising edge of TE4 arrives, the image data of Figure C has been synthesized and prepared for display. When the rising edge of TE4 arrives, the display driver executes the display of Figure C under the trigger of the rising edge of TE4, so that the display screen displays the image of Figure C after TE4.

[0163] The next frame after Figure C is Figure D. In Figure D, the time between the completion of pre-display preparation and the arrival time of the next TE signal (predicted based on the first frequency) is greater than a preset duration threshold, causing the electronic device to activate high-frequency TE. After activating high-frequency TE, the TE signal frequency is the second frequency, such as 360Hz, and the TE signal period is approximately 2.7ms. For example, refer to... Figure 11 The time interval between the rising edge of TE5 and the rising edge of the next TE signal is approximately 2.7ms.

[0164] In some cases, image D is not sent to the display for an extended period of time, the image on the screen is not refreshed, and image C is displayed continuously, resulting in prolonged display lag.

[0165] In the above scenario, after enabling high-frequency TE, the image is not displayed when the next TE signal arrives, and may not be displayed for a long period of time, resulting in display stuttering for a long time, such as more than 300ms.

[0166] In some scenarios, when the display driver uses the cesta function, there may be prolonged display stuttering after enabling high-frequency TE.

[0167] Cesta functionality is a solution that uses hardware chips (such as the Cesta chip) to vote on and calculate the clock and bandwidth resources required by the display driver for display output. By using hardware chips to provide computing power instead of the display driver in the SoC software architecture, software performance can be improved and power consumption reduced.

[0168] In some embodiments, if the computing power is provided by the display driver (software), the display driver can perform calculations at any time before the arrival of the next TE signal. When the next TE signal arrives, the necessary calculation process has been completed, and the display can be completed in response to the arrival of the rising edge of the next TE signal.

[0169] In other embodiments, the display driver employs the CESTA function, utilizing the computing power provided by the CESTA chip. This necessitates strict timing coordination between the display driver (software) and the CESTA chip (hardware). Generally, the display driver sends a frame of image resources for display, and this sending action does not need to continue throughout one cycle of the TE signal. To reduce hardware power consumption, the CESTA chip can be woken up at a specific time. After being woken up, the display driver can use the capabilities provided by the CESTA chip to calculate the clock and bandwidth resources required for sending the image, and then execute the sending. After a preset wake-up time, the CESTA chip goes into sleep mode. During the CESTA chip's sleep period, the display driver cannot perform image sending. In one implementation, the wake-up time of the CESTA chip is strongly correlated with the TE signal; for example, the display driver can determine the wake-up time of the CESTA chip based on the arrival time of the TE signal.

[0170] For example, Figure 12 This diagram illustrates an example of a Cesta chip being woken up and put into sleep mode.

[0171] like Figure 12 As shown, the frequency of the TE signal is the first frequency, for example, 120Hz, and the period of the TE signal is approximately 8.3ms. For example, TEa, TEb, and TEc are three adjacent TE signals.

[0172] In one example, the display driver anchors to TEa, determining that the cesta chip will be woken up after a duration T1 following the arrival of TEa (the rising edge of TEa). The cesta chip is in sleep mode before being woken up; while the cesta chip is in sleep mode, the display driver cannot perform display sending. After the cesta chip is woken up, it calculates the clock and bandwidth resources required for displaying the current image frame, and after a wake-up duration T... a Afterwards, the Cesta chip enters sleep mode. In other words, the duration for which the display driver is allowed to send data to the display is T. aGenerally, the allowed display period includes a period before and after the arrival of the TE signal. (Reference) Figure 12 Anchoring TEa, the calculated allowed display time period includes a period before and after the arrival time of TEb, and the duration of this allowed display time period is T. a During the permitted display period, when the rising edge of TEb arrives, the display driver can execute the display request triggered by the rising edge of TEb.

[0173] The display driver anchors to TEb, determining that the cesta chip will be woken up after a duration T2 following the arrival of TEb (its rising edge). Once woken up, the cesta chip calculates the clock and bandwidth resources required for displaying the current image frame, and after a wake-up duration T... b Afterwards, the Cesta chip enters sleep mode. In other words, the duration for which the display driver is allowed to send data to the display is T. b . refer to Figure 12 Anchoring TEb, the calculated allowed display time period includes a period before and after the arrival time of TEc, and the duration of this allowed display time period is T. b During the permitted display sending period, when the rising edge of TEc arrives, the display driver can execute display sending triggered by the rising edge of TEc. Wherein, T... a With T b The values ​​can be the same or different; correspondingly, the values ​​of T1 and T2 can be the same or different.

[0174] In other words, the display driver can only send the display signal when the rising edge of the TE signal arrives within the allowed display sending period. When high-frequency TE is enabled, the timing of the rising edge of the TE signal may miss the time period allowed by the hardware chip, causing the display driver to fail to send the display signal, resulting in a longer period of display stuttering.

[0175] For example, Figure 13 This diagram illustrates the principle behind the prolonged display lag that occurs after enabling high-frequency TE when processing lag exists.

[0176] like Figure 13 As shown, when the frequency of the TE signal is the first frequency, such as 120Hz, the period of the TE signal is approximately 8.3ms. For example, the time interval between the rising edge of TE0 and the rising edge of TE1 is approximately 8.3ms, and the time interval between the rising edge of TE1 and the rising edge of TE2 is approximately 8.3ms.

[0177] The allowed display period determined by anchoring TE0 includes a period before and after the arrival of TE1. Before the rising edge of TE1 arrives, the image data of Figure A has been synthesized and prepared for display. When the rising edge of TE1 arrives, the display driver executes the display of Figure A under the trigger of the rising edge of TE1, so that the display screen displays the image of Figure A after TE1.

[0178] The allowed display time period determined by anchoring TE1 includes a period before and after the arrival of TE2. The next frame image after Figure A is Figure B. There is a processing lag in the processing of Figure B, preventing the image data synthesis and pre-display preparation for Figure B from being completed before TE2. The electronic device detects this processing lag and activates a high-frequency TE. After activating the high-frequency TE, the TE signal frequency is the second frequency, for example, 360Hz, and the TE signal period is approximately 2.7ms. Figure 13 As shown, the next TE signal after TE2 is TE3, and the time interval between TE2 and TE3 is approximately 2.7ms. When the rising edge of TE3 arrives, the time period for display transmission determined by anchoring TE1 has ended. The Cesta chip is in sleep mode, and the display driver cannot use the Cesta chip's computing power, thus failing to successfully transmit the display and causing display stuttering.

[0179] For example, Figure 14 This diagram illustrates the principle behind the prolonged display stuttering that occurs when high-frequency TE is enabled in a game frame-tracking scene.

[0180] like Figure 14 As shown, when the frequency of the TE signal is the first frequency, such as 120Hz, the period of the TE signal is the first period, such as 8.3ms. For example, the time interval between the rising edge of TE3 and the rising edge of TE4 is approximately 8.3ms.

[0181] The allowed display period determined by anchor TE3 includes a period before and after the arrival of TE4. Before the rising edge of TE4 arrives, the image data of Figure C has been synthesized and prepared for display. When the rising edge of TE4 arrives, the display driver executes the display of Figure C under the trigger of the rising edge of TE4, so that the display screen displays the image of Figure C after TE4.

[0182] The next frame after Figure C is Figure D. In Figure D, the time between the completion of pre-display preparation and the arrival time of the next TE signal (predicted based on the first frequency) is greater than a preset duration threshold, causing the electronic device to activate high-frequency TE. After activating high-frequency TE, the TE signal frequency is the second frequency, such as 360Hz, and the TE signal period is approximately 2.7ms. For example, refer to... Figure 14The time interval between the rising edge of TE5 and the rising edge of the next TE signal is approximately 2.7ms. However, the display driver anchors to TE4 and determines the next allowed display time period based on the frequency of the TE signal, which does not include TE5. When the rising edge of TE5 arrives, the allowed display time period determined by anchoring to TE4 has not yet started. The Cesta chip is in sleep mode, and the display driver cannot use the Cesta chip's computing power, failing to successfully send a display signal, resulting in display stuttering.

[0183] As shown in the aforementioned embodiments, functions such as stuttering compensation and game frame tracking can trigger high-frequency TE when preset conditions are met. The timing of the display driver sending data after high-frequency TE is enabled is incompatible with the timing of the hardware chip being woken up after CES is enabled. This can lead to display stuttering issues in some scenarios (such as platforms supporting CES).

[0184] In some embodiments of this application, when functions that can trigger high-frequency TE (Transmission Timeout) are enabled, such as stuttering compensation and game frame tracking, the corresponding CESA (Continuous Settlement) function is disabled. Thus, when high-frequency TE is enabled due to stuttering compensation or game frame tracking, the display driver can perform calculations using its software computing power to complete the display signal delivery upon arrival of the TE signal. Conversely, when functions that can trigger high-frequency TE are disabled, such as stuttering compensation and game frame tracking, the corresponding CESA function is enabled. This allows the display driver to perform calculations using the hardware chip's computing power, improving computational performance and reducing software power consumption.

[0185] Let's continue with the stuttering compensation function and the game frame tracking function as examples.

[0186] In one example, the electronic device can respond to user input by turning the lag compensation function on or off. For instance, a user can turn the lag compensation function on or off in the device's settings. When the lag compensation function is on, the lag compensation function is enabled; when it is off, the lag compensation function is disabled. As another example, the electronic device may have an application whitelist containing predefined application identifiers. The user can turn the lag compensation function on or off in the settings. When the lag compensation function is on, the lag compensation function for applications in the whitelist is enabled; when it is off, the lag compensation function for those applications is disabled. Yet another example, a user can turn the lag compensation function on or off for an application in its settings. When the application's lag compensation function is on, the application's lag compensation function is enabled; when it is off, the application's lag compensation function is disabled. In another example, the electronic device may not have a dedicated lag compensation function switch. For example, you can set up an application whitelist on your electronic device, and enable the lag compensation function for the applications included in the whitelist.

[0187] In one example, the electronic device can also respond to user input by turning the switch corresponding to the game frame tracking function on or off. For example, the game application's settings interface includes a game frame tracking switch, which the user can turn on or off in the game application's settings. When the game frame tracking switch is on, the game application enables the game frame tracking function. In one implementation, the electronic device can save the on / off state of the game frame tracking switch for each game application, thus eliminating the need to turn the game frame tracking switch on every time the game application is launched. In another example, the electronic device may not include a switch corresponding to the game frame tracking function. That is, the game frame tracking function is enabled for each game application.

[0188] like Figure 15 As shown in (a), with the corresponding stuttering compensation function enabled, the CESTA function is disabled at time T1 after the application starts. The frequency of the TE signal is the first frequency, for example, 120Hz. At time T2, a processing stutter is detected, and a high-frequency TE is enabled. After enabling the high-frequency TE, the frequency of the TE signal is the second frequency. According to the second frequency, at time T3, the next TE signal arrives, and the frame of the image where the processing stutter occurred is successfully displayed. Optionally, after the frame of the image where the processing stutter occurred is successfully displayed, the high-frequency TE is disabled. After disabling the high-frequency TE, the frequency of the TE signal is the first frequency. Then, when the application is exited, the CESTA function is enabled at time T4.

[0189] like Figure 15As shown in (b), with the game application's frame tracking function enabled, when the game application starts, at time T... a The CESTA function is disabled. The frequency of the TE signal is the first frequency, for example, 120Hz. At time T... b Once it is determined that an image frame has completed preparations for display and the time (T0) between the arrival of the next TE signal calculated based on the first frequency and the actual arrival time is greater than a preset duration threshold, a high-frequency TE is activated. After activating the high-frequency TE, the frequency of the TE signal is the second frequency. According to the second frequency, at time T... c Upon the arrival of the next TE signal, the frame image is successfully displayed. Optionally, after the frame image is successfully displayed, the high-frequency TE is turned off. After turning off the high-frequency TE, the frequency of the TE signal is the first frequency. Then, when exiting the game application, at time T... d Enable Cesta features.

[0190] In one implementation, with the cesta function disabled, the display driver calculates the required clock and bandwidth resources for each display request before it is sent to the screen, using the software's (display driver's) computing power. (See reference) Figure 15 Even with high-frequency TE enabled, the display can still be successfully sent to the screen without causing display stuttering. After the Cesta function is enabled, the display driver uses the computing power of the hardware (Cesta chip) to calculate the clock and bandwidth resources required for each display transmission before sending the display.

[0191] In some embodiments, stuttering compensation and game frame tracking can be turned on or off after the application starts. Therefore, when stuttering compensation or game frame tracking is turned on, the CESTA function can be turned off; conversely, when stuttering compensation or game frame tracking is turned off, the CESTA function can be turned on.

[0192] It should be noted that for a game application, both the stuttering compensation function and the game frame tracking function can be enabled.

[0193] If you want to enable or disable the stuttering compensation and frame tracking features after launching the game application, please refer to [the relevant documentation / reference]. Figure 15 If you enable the stuttering compensation function first, and then enable the game frame tracking function, that is, time T1 is earlier than time T... a Since the CESTA function was already disabled at time T1, it does not need to be disabled again after enabling the game frame tracking function. If the game frame tracking function is enabled first, followed by the stuttering compensation function (i.e., time T1 is later than time T), then... a Because the cesta function at time T a It is already turned off. Once the lag compensation function is enabled, there is no need to turn off the Cesta function again.

[0194] If you disable the stuttering compensation function first, and then disable the game frame tracking function, that is, time T4 is earlier than time T... d When the stuttering compensation function is turned off, the game frame tracking function is not yet turned off, and the CES function is temporarily not enabled; after turning off the game frame tracking function, at time T d Enable CESTA. If you disable game frame tracking first, and then disable stutter compensation, meaning time T4 is later than time T... d When the game frame tracking function is disabled, the stuttering compensation function is not yet disabled, and the CESTA function is temporarily not enabled. After the stuttering compensation function is disabled, the CESTA function is enabled at time T4. In some embodiments, if multiple functions (such as stuttering compensation function, game frame tracking function, etc.) can trigger the activation of high-frequency TE, when the first function is enabled, the CESTA function is disabled. When the last function is disabled, the CESTA function is enabled. This ensures that when high-frequency TE is enabled, the CESTA function is disabled, and the display driver calculates the required clock and bandwidth resources for display before sending data, thus preventing display stuttering.

[0195] The image display method provided in this application can be applied to electronic devices with image processing and display requirements. These electronic devices may include mobile phones, tablets, laptops, personal computers (PCs), ultra-mobile personal computers (UMPCs), handheld computers, netbooks, smart home devices, personal digital assistants (PDAs), wearable devices (e.g., smartwatches, smart bracelets), in-vehicle devices, virtual reality devices, smart city devices, etc., and this application does not impose any limitations on these.

[0196] Figure 16 This is a hardware structure diagram of an electronic device to which the image display method provided in the embodiments of this application is applicable. For example... Figure 16 As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 130, a display screen 140, a communication module 150, a power supply module 160, a sensor module 170, etc. The sensor module 170 may include a pressure sensor, a touch sensor, etc.

[0197] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0198] Processor 110 may include one or more processing units. For example, processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), and / or a neural network processing unit (NPU). Different processing units may be independent components or integrated into one or more processors. In some embodiments, electronic device 100 may also include one or more processors 110.

[0199] The controller is the nerve center and command center of the electronic device 100. It can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0200] An operating system for the electronic device 100 can run on the application processor to manage the hardware and software resources of the electronic device 100. This includes managing and configuring memory, determining the priority of system resource allocation, controlling input and output devices, operating the network, managing the file system, and managing drivers. The operating system can also provide a user interface for interacting with the system. Various types of software can be installed within the operating system, such as drivers and applications (Apps).

[0201] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0202] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM card interface, and / or a USB interface, etc.

[0203] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0204] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0205] Internal memory 130 can be used to store one or more computer programs, which include instructions. Processor 110 can execute the instructions stored in internal memory 130, thereby causing electronic device 100 to perform the methods provided in some embodiments of this application, as well as various applications and data management. Internal memory 130 may include a code storage area and a data storage area. The data storage area may store data created during the use of electronic device 100. In addition, internal memory 130 may include high-speed random access memory, and may also include non-volatile memory, such as one or more disk storage components, flash memory components, universal flash storage (UFS), etc. In some embodiments, processor 110 can execute instructions stored in internal memory 130 and / or instructions stored in memory disposed in processor 110 to cause electronic device 100 to perform the methods provided in embodiments of this application, as well as other applications and data management.

[0206] Electronic device 100 implements display functions through a GPU, display screen 140, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 140 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0207] The communication module 150 can provide solutions for wireless communication applications on the electronic device 100, including cellular, Wi-Fi, Bluetooth, and wireless data transmission modules (e.g., 433MHz, 868MHz, 915MHz). The communication module 150 can be one or more devices integrating at least one communication processing module.

[0208] The power module 160 can be used to supply power to the various components included in the electronic device 100. In some embodiments, the power module 160 can be a battery, such as a rechargeable battery.

[0209] Display screen 140 is used to display images, videos, etc. Display screen 140 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 140, where N is a positive integer greater than 1.

[0210] In some embodiments, the display screen 140 is provided with a pressure sensor, a touch sensor, etc. The pressure sensor senses pressure signals and converts them into electrical signals. When a touch operation is applied to the display screen 140, the electronic device 100 detects the intensity of the touch operation based on the pressure sensor. The electronic device 100 can also calculate the touch location based on the detection signal from the pressure sensor. The touch sensor, also called a "touch panel," can form a touchscreen with the display screen 140, also called a "touch screen." The touch sensor detects touch operations applied to or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can also be provided through the display screen 140.

[0211] In some embodiments, the display screen 140 further includes a driving circuit and a storage unit (such as GRAM, which will be described below as an example). The GRAM can be used to store image data of the image to be displayed.

[0212] For details on the functions and working principles of the display panel, DDIC, and GRAM, please refer to the previous text. Figure 1 and Figure 2 The details and related information will not be elaborated here.

[0213] The display panel can be a low-temperature polycrystalline oxide (LTPO) display panel, a low-temperature polycrystalline silicon (LTPS) display panel, etc. Furthermore, based on the number of transistors in the pixel circuit of the LTPO display panel, the display screen 140 can be classified as a 7T-LTPO screen, an 8T-LTPO screen, etc. Here, 7T refers to a pixel circuit containing 7 transistors, and 8T refers to a pixel circuit containing 8 transistors.

[0214] In this embodiment, the electronic device described above is an electronic device capable of running an operating system and installing applications. Optionally, the operating system running on the electronic device may be Android. system, system, Systems, etc.

[0215] The operating system of the aforementioned electronic device (such as the software system on the AP side) can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses a layered architecture of Android. Taking a system as an example, this section illustrates the software structure of an electronic device. A layered architecture divides the software system of an electronic device into several layers, each with a clear role and function, and the layers communicate with each other through software interfaces.

[0216] See Figure 17 The hardware and software architecture of an electronic device can include an application layer, an application framework layer, a native layer, a hardware abstraction layer (HAL), a kernel layer, and a hardware layer. Specifically, the software architecture of an electronic device includes the application layer, application framework layer, native framework layer, hardware abstraction layer, and kernel layer.

[0217] The application layer can include a series of application packages. For example, game manager applications, desktop applications, game applications, settings applications, system UI applications, etc.

[0218] The application framework layer provides application programming interfaces (APIs) and programming frameworks for applications in the application layer. The application framework layer includes predefined functions. For example, it includes modules such as a game assistant and system services. The game assistant manages the game application, and system services may include Window Manager Service (WMS), Activity Manager Service (AMS), Display Manager Service (DMS), and Package Manager Service (PMS). Specifically, WMS manages the window view and controls the correct display and input of the application's interface; AMS manages and tracks all application activities and lifecycles; DMS manages display-related processes, including screen brightness adjustment; and PMS is used to install, manage, and uninstall applications in the operating system.

[0219] The local framework layer includes various system components, such as touch services and the compositing management unit (SurfaceFlinger, SF). Touch services manage touch-related processes. The compositing management unit, also known as an image compositor, surface drawing module, or image compositing processing service, can be used for refresh rate control and image compositing control. In one specific implementation, as explained above, the compositing management unit can simulate a corresponding Vsync signal based on the TE signal. This Vsync signal can trigger the CPU, GPU, etc., to perform image processing, thereby controlling the frequency of the obtained image data and achieving refresh rate control. In another specific implementation, the compositing management unit can include layer compositing. After receiving multiple layers with drawn content, it allocates compositing tasks to the Hardware Composer (HWC) in the Hardware Abstraction Layer or the GPU. For example, if the compositing task includes tasks such as rounded corner clipping, it can be allocated to the GPU for image compositing; if the compositing task only includes simple layer overlay tasks, it can be allocated to the HWC for image compositing, thus enabling control of image compositing. The compositing management unit may also include an AIDL (Android Interface Definition Language) interface, which can be used for data transmission between the compositing management unit and HWC. The compositing management unit may also include a whitelist for storing application whitelists. The application whitelist includes identifiers for some preset applications, which are those that support enabling stuttering compensation or game frame tracking.

[0220] The hardware abstraction layer and kernel layer include some chip components.

[0221] The Hardware Abstraction Layer (HWC) runs in user space, encapsulates kernel-level drivers, and provides calling interfaces to higher layers. The HWC can include HWC. HWC can be used for image compositing and for providing the composited image data to the display driver. It should be noted that image data obtained from GPU-composited images can also be provided to the display driver via HWC.

[0222] The kernel layer runs in kernel mode and includes drivers that control hardware operations, such as the display driver. The display driver can send the composited image data to the display screen, such as writing image data to RAM and then refreshing it to the display screen in response to the arrival of a TE signal. The driver can also include display control functions, such as controlling display timing, resolution, refresh rate, etc., as well as sending and updating the framebuffer.

[0223] The hardware layer may include hardware such as CPU, GPU, and display screen (further including display panel, DDIC, GRAM, etc.).

[0224] Furthermore, image data can be transmitted between the kernel layer and the hardware layer through the Mobile Industry Processor Interface (MIPI).

[0225] It should be noted that the above Figure 16 and Figure 17 In the descriptions of electronic devices, the division of hardware and software modules is exemplary and not limited to this in practice. For example, the display driver function described in this article may also be implemented by other modules or merged into other modules.

[0226] The image display method provided in this application can be executed in an electronic device having the above-described hardware structure and software architecture. This electronic device supports the CESTA function and supports enabling high-frequency TE signals; for example, the display screen of this electronic device is an 8T-LTPO screen, capable of generating high-frequency (e.g., 360Hz) TE signals. The image display method of this application embodiment will be further described in detail below in conjunction with the above-described hardware structure and software architecture.

[0227] like Figure 18 As shown, the image display method provided in this application includes:

[0228] S1801. The electronic device receives the user's operation to enable the first function of the first application and enables the first function corresponding to the first application.

[0229] Optionally, when the electronic device has a first switch for the first function, the user can activate the first function by turning on the corresponding first switch. The first function is a function that can trigger the activation of high-frequency TE (Time Transmission), such as stuttering compensation or game frame tracking.

[0230] In one implementation, when the first switch is turned on, the first function corresponding to the first application is activated. For example, when the first switch is a global switch, the first application can be any application; another example is when an application whitelist is set on the electronic device, the first application is any application in the application whitelist; yet another example is that the first application is a game application. In another implementation, when the first switch is turned on, the first function is activated for applications that meet the activation conditions; that is, the first function is activated for the image display process of applications that meet the activation conditions. Specifically, when the first switch is turned on, if the current foreground application meets the activation conditions, that is, the image displayed on the screen is an image of the foreground application, then the first function is activated. For example, an application that meets the activation conditions can be an application included in the application whitelist; for example, an application that meets the activation conditions can be a specific type of application (such as a game); yet another example is that an application that meets the activation conditions can be a specific application, such as a game application, etc.

[0231] Optionally, the first switch for the first function may not be set on the electronic device, that is, the first function of the first application on the electronic device is already turned on.

[0232] Combination Figure 17 In one example, the Game Manager app's settings interface includes a first switch, which the user can turn on within the app's settings. Once the first switch is turned on, the Game Manager notifies the Game Assistant, which in turn notifies the Touch Service. The Touch Service's Game Touch Enhancement notification then reaches the Synthesis Management Unit. The Synthesis Management Unit calls the AIDL interface to write the on / off state of the first switch into the HWC's Display Panel Dynamic Management Node. The Display Panel Dynamic Management Node then notifies the Display Driver to enable the first function.

[0233] In another example, the settings interface of the electronic device's settings application includes a first switch, which the user can turn on. Once the first switch is turned on, the settings application notifies the system service to activate the first switch, and the system service then notifies the synthesis management unit to activate the first switch. The synthesis management unit determines that the whitelist includes the currently foreground application; for example, if the currently foreground application is a game, it calls the AIDL interface to write the on / off state of the first switch to the HWC's display panel dynamic management node. The display panel dynamic management node then notifies the display driver to enable the first function.

[0234] The display driver enables a first function, such as enabling stuttering compensation or game frame tracking. In one implementation, the display driver can save the state of the first function, which includes being enabled or disabled. After the display driver enables the first function, its state is set to enabled. After enabling the first function, the electronic device enables a high-frequency TE signal when a preset first condition is met. For example, before enabling the high-frequency TE, a TE signal is generated at a first frequency (e.g., 120Hz); after enabling the high-frequency TE, a TE signal is generated at a second frequency (e.g., 360Hz). For example, as shown... Figure 8 or Figure 9 Example of a scenario shown.

[0235] S1802. After the first application enters the foreground, disable the cesta function.

[0236] In some embodiments, when the first function corresponding to the first application is enabled, the display driver disables the Cesta function after the first application enters the foreground (the first application switches from background to foreground, or enters the foreground after startup). In one implementation, the display driver writes a message to the Cesta chip's register disabling the Cesta function.

[0237] In one implementation, the display driver can disable the cesta function during the display of the next frame image after the first application starts. For example, see [reference]. Figure 17 When the current foreground application, such as a game application, needs to refresh the image, it calls a system service to update the Activity. The game application writes the updated Activity data to the framebuffer. SF (Surface View) reads the Activity data from the framebuffer when triggered by the Vsync signal. SF's layer compositing calls HWC (Hardware Controller) or GPU to draw and render the various layers of the image based on the Activity data. SF's layer compositing further performs compositing and rendering to generate image data. The display control sends the image data to the display driver. After completing pre-display preparation based on the image data, the display driver determines whether to enable or disable the Cesta function. In one example, if the display driver determines that the first function corresponding to the first application is enabled and the Cesta function is enabled (e.g., the Cesta chip's register indicates the Cesta function is enabled), the display driver writes "disable Cesta function" to the Cesta chip's register.

[0238] S1803. After the cesta function is turned off, the display driver of the electronic device uses software computing power.

[0239] In some embodiments, after the cesta function is disabled, the display driver uses its software computing power to calculate the clock, bandwidth, and other resources required for display transmission. After enabling the first function, a high-frequency TE can be enabled during the display driver's transmission process. Because the display driver uses software computing power, enabling a high-frequency TE will not cause display stuttering.

[0240] In one example, the first function is a stuttering compensation function, such as... Figure 15 As shown in (a), after the cesta function is turned off at time T1, the frequency of the TE signal is the first frequency, and at time T... b If a frame of image completes preparations for display and the time (T0) between the arrival of the next TE signal (calculated based on the first frequency) and the arrival time is greater than a preset duration threshold, then high-frequency TE is enabled. After enabling high-frequency TE, the frequency of the TE signal is the second frequency. The display driver can complete image preparations before the arrival of the TE signal, using the software's computing power to calculate the clock, bandwidth, and other resources required for display, and then execute display in response to the arrival of the TE signal.

[0241] In yet another example, the first function is game frame tracking, such as... Figure 15 As shown in (b), at time T a After disabling the CESTA function, the TE signal frequency is the first frequency. At time T2, a processing lag is detected, and a high-frequency TE is activated. After activating the high-frequency TE, the TE signal frequency becomes the second frequency. The display driver can complete the pre-display preparation before the TE signal arrives, using the software's computing power to calculate the clock, bandwidth, and other resources required for display, and then execute the display in response to the arrival of the TE signal.

[0242] In some embodiments, the electronic device can also enable the cesta function.

[0243] S1804. After exiting the first application, enable the cesta function.

[0244] In one implementation, after exiting the first application (either the first application runs in the background or its process is closed), the second application is entered (either the second application runs in the foreground or it is launched). If the first function corresponding to the second application is not enabled, the display driver can enable the CESTA function during the next frame image display process after the second application starts. For example, after completing pre-display preparation based on image data, the display driver determines whether to enable or disable the CESTA function. In one example, the display driver determines that the first function corresponding to the second application is disabled and the CESTA function is disabled; for example, if the CESTA function is disabled in the CESTA chip's register, the display driver writes "Enable CESTA" to the CESTA chip's register.

[0245] After disabling the first function, the electronic device will not activate the high-frequency TE signal even if the preset first condition is met. For example, the electronic device generates a TE signal at a first frequency (e.g., 120Hz); even after the preset first condition is met, the electronic device will still generate a TE signal at the first frequency (e.g., 120Hz). In this scenario, display stuttering may occur. For example, ... Figure 6 The scene shown.

[0246] S1805. After enabling the cesta function, the display driver of the electronic device uses hardware computing power.

[0247] In some embodiments, after the cesta function is enabled, the display driver uses the hardware's computing power to calculate the clock, bandwidth, and other resources required for display.

[0248] This application also provides an electronic device, which may include a memory and one or more processors (such as a CPU, GPU, NPU, etc.). The memory and processor are coupled. The memory is used to store computer program code, which includes computer instructions. When the processor executes the computer instructions, the electronic device can perform various functions or steps performed by the device in the above method embodiments.

[0249] This application also provides a chip system, such as... Figure 19 As shown, the chip system 1900 includes at least one processor 1901 and at least one interface circuit 1902. The processor 1901 and the interface circuit 1902 are interconnected via lines. For example, the interface circuit 1902 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 1902 can be used to send signals to other devices (e.g., the processor 1901). Exemplarily, the interface circuit 1902 can read instructions stored in memory and send those instructions to the processor 1901. When the instructions are executed by the processor 1901, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, and this application embodiment does not specifically limit this.

[0250] This embodiment also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the image display method described above.

[0251] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the image display method described above.

[0252] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the image display method in the above method embodiments.

[0253] In this embodiment, the electronic device, computer-readable storage medium, computer program product, or chip system are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0254] Through the above description of the implementation methods, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0255] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0256] The unit described as a separate component may or may not be physically separate. The component shown as a unit can be one physical unit or multiple physical units, that is, it can be located in one place or distributed in multiple different places. Some or all of the units can be selected to achieve the purpose of the solution in this embodiment according to actual needs.

[0257] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0258] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0259] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. An image display method, characterized in that, Applied to an electronic device, the electronic device including a system-on-a-chip (SoC) and a display screen, the method includes: After the first application of the electronic device enters the foreground, the electronic device immediately shuts down the hardware computing capabilities of the SoC. At a second moment, the electronic device generates a first TE signal, and in response to the first TE signal, the SoC sends the first image data of the first application to the display screen, wherein the second moment is after the first moment; At the third moment, the electronic device generates a second TE signal. In response to the second TE signal, the SoC sends the second image data of the first application to the display screen. The third moment is after the second moment, the second TE signal is the next TE signal of the first TE signal, the second image data is the next frame image data of the first image data, and the time interval between the second TE signal and the first TE signal is the first time interval. At the fourth moment, the electronic device generates a third TE signal, wherein the fourth moment is after the third moment, the third TE signal is the next TE signal after the second TE signal, and the time interval between the third TE signal and the second TE signal is a first time interval; At the fifth moment, the electronic device generates a fourth TE signal. In response to the fourth TE signal, the SoC sends the third image data of the first application to the display screen. The fifth moment is after the fourth moment, the fourth TE signal is the next TE signal after the third TE signal, the third image data is the next frame image data of the second image data, and the time interval between the fourth TE signal and the third TE signal is a second time interval, which is less than the first time interval.

2. The method according to claim 1, characterized in that, The method further includes: After the first application exits the foreground, at the sixth moment, the electronic device activates the hardware computing capabilities of the SoC, wherein the sixth moment is after the fifth moment.

3. The method according to claim 1 or 2, characterized in that, The method further includes: If the SoC completes preparations before sending the third image data to the display screen at the seventh time, the SoC sends a control command to the display screen to cause the display screen to generate a TE signal at a second frequency, wherein the seventh time is after the fourth time and before the fifth time, the second frequency is greater than the first frequency, the first frequency corresponds to the first time interval, and the second frequency corresponds to the second time interval.

4. The method according to any one of claims 1-3, characterized in that, The hardware computing power of the SoC is provided by the cesta chip.

5. The method according to claim 4, characterized in that, The electronic device disables the hardware computing capabilities of the SoC, including: The electronic device writes a message to the registers of the cesta chip to disable the cesta chip's computing capabilities.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: At the eighth moment, the electronic device generates a fifth TE signal, wherein the eighth moment is after the fifth moment, the fifth TE signal is the next TE signal after the fourth TE signal, and the time interval between the fifth TE signal and the fourth TE signal is a first time interval.

7. The method according to any one of claims 1-6, characterized in that, The first time interval is 8.3 milliseconds, and the second time interval is 2.7 milliseconds.

8. The method according to claim 2, characterized in that, The SoC includes a cesta chip, and the operating system of the SoC includes a display driver. When the second application of the electronic device enters the foreground, the first application exits the foreground. The method further includes: At the ninth moment, the display screen generates the sixth TE signal; At the tenth moment, the display driver sends a first instruction to the cesta chip to wake up the cesta chip, wherein the tenth moment is the moment after the ninth moment for a first duration, the cesta chip goes into sleep at the eleventh moment, and the eleventh moment is the moment after the tenth moment for a second duration; At the twelfth moment, the display generates a seventh TE signal. In response to the seventh TE signal, the SoC sends the fourth image data of the second application to the display. The twelfth moment is after the tenth moment and before the eleventh moment. The seventh TE signal is the next TE signal after the sixth TE signal. The time interval between the seventh TE signal and the sixth TE signal is a first time interval.

9. An image display method, characterized in that, Applied to an electronic device, the electronic device including a system-on-a-chip (SoC) and a display screen, the method includes: Upon startup of the game application, the electronic device immediately shuts down the hardware computing capabilities of the SoC. At a second moment, the electronic device generates a first TE signal, and in response to the first TE signal, the SoC sends the first image data of the game application to the display screen, wherein the second moment is after the first moment; At the third moment, the electronic device generates a second TE signal. In response to the second TE signal, the SoC sends the second image data of the game application to the display screen. The third moment is after the second moment, the second TE signal is the next TE signal after the first TE signal, the second image data is the next frame image data of the first image data, and the time interval between the second TE signal and the first TE signal is the first time interval. At the fourth moment, the electronic device generates a third TE signal. In response to the third TE signal, the SoC sends the third image data of the game application to the display screen. The fourth moment is after the third moment, the third TE signal is the next TE signal of the second TE signal, the third image data is the next frame image data of the second image data, and the time interval between the third TE signal and the second TE signal is a second time interval, which is less than the first time interval.

10. The method according to claim 9, characterized in that, The method further includes: After the game application exits the foreground, at the fifth moment, the electronic device activates the hardware computing capabilities of the SoC, wherein the fifth moment is after the fourth moment.

11. The method according to claim 9 or 10, characterized in that, The method further includes: If the SoC completes preparations before sending the third image data to the display screen at the sixth moment, the SoC sends a control command to the display screen to cause the display screen to generate a TE signal at a second frequency, wherein the interval between the sixth moment and the third moment is less than a preset threshold, the second frequency is greater than the first frequency, the first frequency corresponds to the first time interval, the second frequency corresponds to the first period value, and the second time interval is the difference between the first time interval and the first period value.

12. The method according to claim 11, characterized in that, The preset threshold is the difference between the first time interval and the first period value.

13. The method according to any one of claims 9-12, characterized in that, The hardware computing power of the SoC is provided by the cesta chip.

14. The method according to any one of claims 9-13, characterized in that, The first time interval is 8.3 milliseconds, and the second time interval is 2.7 milliseconds.

15. An electronic device, characterized in that, include: A display panel, one or more processors, and one or more memories; the one or more processors are coupled to the display panel and the one or more memories; the one or more memories are used to store computer program code, the computer program code including computer instructions, which, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of claims 1-14.

16. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the processors being configured to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1-14.

17. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed on the electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-14.

18. A computer program product comprising computer instructions, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method as described in any one of claims 1-14.

Images