Display device and electronic apparatus

Abstract

The invention provides a display device and electronic equipment, the display device comprises a plurality of pixel columns and a plurality of data lines, the plurality of data lines comprise a first data line and a second data line, and the first data line and the second data line are respectively used for inputting data voltage to a first pixel and a second pixel in the same pixel column; the first pixel comprises a first transistor and a first interconnection line, the first transistor is coupled with the first data line through the first via hole, the first interconnection line and the second via hole in sequence, the projection of the first interconnection line in the first direction is not overlapped with the second data line, and the first direction is perpendicular to the display device; the second pixel comprises a second transistor and a second interconnection line, the second transistor is coupled with the second data line through the third via hole, the second interconnection line and the fourth via hole in sequence, and the projection of the second interconnection line in the first direction is not overlapped with the first data line. According to the display device and the electronic equipment provided by the invention, the problem of coupling crosstalk under a double-data-line architecture can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display device and an electronic device. Background Technology

[0002] For display screens with high resolution and a large number of pixel columns and rows, a double dataline (DDL) pixel circuit connection design is usually adopted to ensure that the display panel has sufficient charging time during the refresh cycle, thereby improving the display effect of the display panel.

[0003] In display panels using this dual data line design, improper wiring design can lead to a large parasitic capacitance between the two data lines connecting pixels in the same column. When one data line switches voltage, the pixels controlled by the other data line will be coupled and crosstalked, resulting in deviations in color points and brightness, and producing crosstalk images.

[0004] Therefore, the coupling crosstalk problem in dual data line scenarios urgently needs to be solved. Summary of the Invention

[0005] This application provides a display device and electronic device that can reduce coupling crosstalk problems in display panels with dual data lines.

[0006] In a first aspect, a display device is provided, comprising a plurality of pixel columns and a plurality of data lines. Each of the plurality of pixel columns consists of a plurality of pixels. The plurality of pixel columns includes a first pixel column. The plurality of data lines include a first data line and a second data line. The first data line is used to input a data voltage to a first pixel in the first pixel column, and the second data line is used to input a data voltage to a second pixel in the first pixel column. The first pixel includes a first transistor and a first interconnect. A first end of the first transistor is coupled to the first interconnect through a first via, and the first interconnect is coupled to the first data line through a second via. The projection of the first interconnect along a first direction does not overlap with the second data line. The first direction is perpendicular to the light-emitting surface of the display device. The second pixel includes a second transistor and a second interconnect. A first end of the second transistor is coupled to the second interconnect through a third via, and the second interconnect is coupled to the second data line through a fourth via. The projection of the second interconnect along the first direction does not overlap with the first data line.

[0007] In the embodiments provided in this application, for a first pixel, a first transistor is coupled to a first data line through a first via, a first interconnect, and a second via. The projection of the first interconnect in a first direction does not overlap with the second data line, which can reduce the parasitic capacitance between the second data line and the first interconnect, thereby reducing the coupling crosstalk problem between the first data line and the second data line at the first pixel position. For a second pixel, a second transistor is coupled to a second data line through a third via, a second interconnect, and a fourth via. The projection of the second interconnect in a first direction does not overlap with the first data line, which can reduce the parasitic capacitance between the first data line and the second interconnect, thereby reducing the coupling crosstalk problem between the first data line and the second data line at the second pixel position.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the first data line and the second data line are located in different regions of the first metal layer, the first end of the first transistor and the first end of the second transistor are located in different regions of the first conductive layer, the first interconnect and the second interconnect are located in different regions of the second metal layer, and the second metal layer is located between the first conductive layer and the first metal layer along the first direction.

[0009] In the embodiments provided in this application, the second metal layer is located between the first conductive layer and the first metal layer along the first direction, which makes it easy for the first transistor to be connected to the first data line and for the second transistor to be connected to the second data line.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the first conductive layer includes a first lead and a second lead, the first lead forming a first end of the first transistor and the second lead forming a first end of the second transistor; in a projection along the first direction, the end of the first lead near the second data line is located between the first data line and the second data line, and the end of the second lead near the first data line is located between the first data line and the second data line.

[0011] In the embodiments provided in this application, the projection of the end of the first lead closest to the second data line in the first direction is located between the first data line and the second data line. This further ensures that the projection of the end of the first interconnect near the second data line in the first direction is located between the first data line and the second data line, thereby preventing the projection of the first interconnect in the first direction from overlapping with the second data line and reducing the coupling crosstalk problem between the first data line and the second data line. Similarly, the projection of the end of the second lead closest to the first data line in the first direction is located between the first data line and the second data line, ensuring that the projection of the second interconnect in the first direction does not overlap with the first data line and reducing the coupling crosstalk problem between the first data line and the second data line.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the linewidth of the first lead is the same as the linewidth of the second lead.

[0013] In the embodiments provided in this application, the line width of the first lead and the line width of the second lead are the same, which makes the parasitic capacitance in the first pixel and the parasitic capacitance in the second pixel closer, so that there is no need to configure different crosstalk compensation codes for the first pixel and the second pixel, which is beneficial for display effect compensation.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the first lead has a first area, which is the overlapping area of ​​the projection of the first lead along the first direction and the first data line, and the second lead has a second area, which is the overlapping area of ​​the projection of the second lead along the first direction and the first data line, and the first area and the second area are the same size.

[0015] In the embodiments provided in this application, the first area of ​​the first lead is the same as the second area of ​​the second lead, which makes the structure of the first transistor and the structure of the second transistor more similar, thereby making the parasitic capacitances of the first data line and the second data line at different positions more similar, which is beneficial for display effect compensation.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the distance between the end of the first interconnect closest to the second data line and the second data line is less than or equal to the distance between the end of the second interconnect closest to the first data line and the first data line.

[0017] In the embodiments provided in this application, the distance between the end of the first interconnect line closest to the second data line and the second data line is less than or equal to the distance between the end of the second interconnect line closest to the first data line and the first data line, which can further improve the balance of parasitic capacitance in the first pixel and the second pixel, and is beneficial for display effect compensation.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the first interconnect line extends in the opposite direction to the second interconnect line.

[0019] In the embodiments provided in this application, the first interconnect line and the second interconnect line extend in opposite directions, which can further ensure that the first interconnect line and the second data line do not overlap in the first direction, and the second interconnect line and the first data line do not overlap in the first direction, and facilitate the connection of the first interconnect line and the first data line, as well as the connection of the second interconnect line and the second data line.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the projection of the first via along the first direction is located between the first data line and the second data line, and the projection of the second via along the first direction is located between the first data line and the second data line.

[0021] In the embodiments provided in this application, the projections of the first via and the third via along the first direction are located between the first data line and the second data line, which can further ensure that the first interconnect line and the second data line do not overlap in the first direction, and the second interconnect line and the first data line do not overlap in the first direction, thereby reducing the coupling crosstalk problem between the first data line and the second data line.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the first data line and the second data line extend along the pixel column direction, and the first data line winds away from the second data line at the via location, and / or the second data line winds away from the first data line at the via location; the via location includes the location corresponding to at least one of the following vias: the first via, the second via, the third via, and the fourth via.

[0023] In the embodiments provided in this application, the first data line is wound away from the second data line at the via location, and the second data line is wound away from the first data line at the via location. This increases the line spacing between the first and second data lines, and also increases the line spacing between the second data line and the first interconnect in the first pixel, as well as the line spacing between the first data line and the second interconnect in the second pixel. This reduces the parasitic capacitance between the first and second data lines in the first and second pixels, thereby reducing the coupling crosstalk problem between the first and second data lines.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the first data line includes a first main body portion and a first extension portion, the first extension portion being disposed on the side of the first main body portion near the second data line, and the first interconnect line being coupled to the first extension portion through the second via; the second data line includes a second main body portion and a second extension portion, the second extension portion being disposed on the side of the second main body portion near the first data line, and the second interconnect line being coupled to the second extension portion through the fourth via; the distance between the first main body portion and the second main body portion at a first position is d1, the first position corresponding to the via position, and the distance between the first main body portion and the second main body portion at a second position is d2, the second position being any position other than the first position, where d2≤d1≤2d2.

[0025] In the embodiments provided in this application, the spacing between the first main body portion and the second main body portion at the via position and the non-via position satisfies d2≤d1≤2d2, which can further reduce the parasitic capacitance between the first data line and the second data line, reduce the coupling crosstalk problem between the first data line and the second data line, and prevent the winding portion of the data line from overlapping with the adjacent metal portion.

[0026] In conjunction with the first aspect, in some implementations of the first aspect, the plurality of pixels includes a first driving transistor for controlling the driving current of the light-emitting element in the pixel. The display device further includes a first metal region disposed above the first driving transistor and insulated from it. The projection of the first metal region along the first direction covers at least a portion of a first region of the first driving transistor. The first region is one of the source and drain regions of the first driving transistor that is closer to the first data line and the second data line.

[0027] In the embodiments provided in this application, the first metal region covers at least a portion of the first region of the first driving transistor, which can reduce the coupling crosstalk of the data line to the first driving transistor and improve display artifacts and color shift problems.

[0028] In conjunction with the first aspect, in some implementations of the first aspect, the display device further includes a first gate metal line, which is the gate region of a transistor connected to the first driving transistor, and the minimum spacing d between the first metal region and the first gate metal line in a second direction satisfies: 1μm≤d≤5μm, and the second direction is parallel to the display device.

[0029] In the embodiments provided in this application, the spacing between the first metal region and the first gate metal line in the second direction satisfies 1μm≤d≤5μm, which can improve the shielding effect of the first metal region on the signal and reduce the coupling crosstalk problem between adjacent metal layers.

[0030] In conjunction with the first aspect, in some implementations of the first aspect, the voltage of the first metal region is configured as the power supply voltage of the display device.

[0031] In the embodiments provided in this application, the voltage of the first metal region is configured to be the power supply voltage of the display device, which enables the voltage of the first metal region to be constant and improves the shielding effect of the first metal region.

[0032] In conjunction with the first aspect, in some implementations of the first aspect, at least one of the plurality of pixels includes a first sub-pixel and a second sub-pixel, the first sub-pixel being used to control a blue light-emitting element, and the second sub-pixel being used to control a red light-emitting element or a green light-emitting element; the first sub-pixel includes a second driving transistor, the second driving transistor being used to control the driving current of the light-emitting element in the first sub-pixel, the source region and drain region of the second driving transistor being connected through a first silicon line; the second sub-pixel includes a third driving transistor, the third driving transistor being used to control the driving current of the light-emitting element in the second sub-pixel, the source region and drain region of the third driving transistor being connected through a second silicon line, the linewidth of the first silicon line being greater than the linewidth of the second silicon line.

[0033] In the embodiments provided in this application, the linewidth of the first silicon line in the first sub-pixel is greater than the linewidth of the second silicon line in the second sub-pixel, which can improve the signal conduction capability in the blue sub-pixel, making the data writing in the blue sub-pixel more complete, thereby improving the charging speed and charging rate of the blue sub-pixel.

[0034] In conjunction with the first aspect, in some implementations of the first aspect, the linewidth W1 of the first silicon line satisfies: 3μm≤W1≤5μm.

[0035] In the embodiments provided in this application, the linewidth W1 of the first silicon line satisfies 3μm≤W1≤5μm, which can further improve the data writing effect of the blue sub-pixel.

[0036] In conjunction with the first aspect, in some implementations of the first aspect, the linewidth difference ΔW between the first silicon line and the second silicon line satisfies: 0.3μm≤ΔW≤3μm.

[0037] In the embodiments provided in this application, the linewidth difference ΔW between the first silicon line and the second silicon line satisfies 0.3μm≤ΔW≤3μm, which can improve the data writing effect of the blue sub-pixel, save wiring space, and improve the resolution of the pixel.

[0038] In a second aspect, a display device is provided, comprising a plurality of pixels, at least one of the plurality of pixels including a first sub-pixel and a second sub-pixel, the first sub-pixel being used to control a blue light-emitting element, and the second sub-pixel being used to control a red light-emitting element or a green light-emitting element; the first sub-pixel including a second driving transistor being used to control the driving current of the light-emitting element in the first sub-pixel, the source region and drain region of the second driving transistor being connected by a first silicon line; the second sub-pixel including a third driving transistor being used to control the driving current of the light-emitting element in the second sub-pixel, the source region and drain region of the third driving transistor being connected by a second silicon line, the linewidth of the first silicon line being greater than the linewidth of the second silicon line.

[0039] In the embodiments provided in this application, the linewidth of the first silicon line in the first sub-pixel is greater than the linewidth of the second silicon line in the second sub-pixel, which can improve the signal conduction capability in the blue sub-pixel, making the data writing in the blue sub-pixel more complete, thereby improving the charging efficiency of the blue sub-pixel.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the linewidth W1 of the first silicon line satisfies: 3μm≤W1≤5μm.

[0041] In the embodiments provided in this application, the linewidth W1 of the first silicon line satisfies 3μm≤W1≤5μm, which can further improve the data writing effect of the blue sub-pixel.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, the linewidth difference ΔW between the first silicon line and the second silicon line satisfies: 0.3μm≤ΔW≤3μm.

[0043] In the embodiments provided in this application, the linewidth difference ΔW between the first silicon line and the second silicon line satisfies 0.3μm≤ΔW≤3μm, which can improve the data writing effect of the blue sub-pixel, save wiring space, and improve the resolution of the pixel.

[0044] Thirdly, an electronic device is provided, including the display device described in the first aspect or any possible implementation thereof.

[0045] In conjunction with the third aspect, in some implementations of the third aspect, the electronic device is a foldable electronic device, the electronic device includes a hinge mechanism; the display device includes a first chip disposed on a first side of the electronic device, the first side being parallel to the hinge mechanism.

[0046] In the embodiments provided in this application, the first chip is disposed on one side of the electronic device parallel to the rotating shaft mechanism, which can save the device space occupied by the first chip and simplify the processing steps of the electronic device. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the dual data cable connection architecture in the display panel;

[0048] Figure 2 This is a schematic diagram of the overall structure of the display device;

[0049] Figures 3 to 6 This is a cross-sectional structural schematic diagram of the display device provided in the embodiments of this application;

[0050] Figure 7 This is a schematic diagram of the connection structure of a pixel circuit provided in an embodiment of this application;

[0051] Figure 8 This is a schematic diagram of the connection structure between a pixel circuit and a data line provided in an embodiment of this application;

[0052] Figures 9 to 11 This is a partial top view of the display device provided in the embodiments of this application;

[0053] Figure 12 This is a cross-sectional structural schematic diagram of a display device provided in an embodiment of this application;

[0054] Figures 13 to 16 This is a partial top view of the display device provided in the embodiments of this application;

[0055] Figure 17 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0056] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0057] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0058] In the various embodiments of this application, the terms "first," "second," etc., are merely to indicate that multiple objects are different. For example, "first transistor" and "second transistor" are only to indicate different transistors. They should not have any effect on the transistors themselves or their number, and the aforementioned "first," "second," etc., should not impose any limitations on the embodiments of this application.

[0059] The terms “including,” “comprising,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

[0060] As mentioned above, for pixel circuits with dual data lines, there is parasitic capacitance between the two data lines connected to adjacent rows, which makes the display panel prone to crosstalk. Figure 1 The left image is a schematic diagram of the connection structure of a pixel circuit with two data lines, as shown below. Figure 1As shown, each pixel column has two data lines, which are alternately connected to pixels in odd-numbered and even-numbered rows, respectively. For example, the pixels in the first column are connected to two data lines D1a and D1b, where D1a is connected to pixels in odd-numbered rows of the first column, and D1b is connected to pixels in even-numbered rows of the same first column. The pixels in the second column are connected to two data lines D2a and D2b, where D2a is connected to pixels in odd-numbered rows of the second column, and D2b is connected to pixels in even-numbered rows of the same second column. The connection method between pixels in other columns and the data lines is similar.

[0061] In display panels employing this dual-data-line design, parasitic capacitance exists between the two data lines connected to pixels in the same column. When one data line switches voltage, the pixels controlled by the other data line experience crosstalk and voltage fluctuations as well. Figure 1 As shown in the right figure, this leads to deviations in color points and brightness, resulting in crosstalk. Therefore, this application provides a display device to reduce coupling crosstalk problems in dual-data-line scenarios.

[0062] Figure 2 This is a schematic diagram of the overall structure of a display device provided in an embodiment of this application. The device may include a display panel 110, a data control circuit 120, and a peripheral control circuit 130. The display panel 110 includes an active display area (AA) 112 and a non-active display area (NA) 111. The data control circuit 120 can provide data signals (DS) to the display panel 110 after receiving external image information and signals. The peripheral control circuit 130 can provide multiple sets of control signals (CS) and multiple pixel operating voltages (PV) required by the display panel 110. The following is a description of the various sub-parts of the organic light-emitting diode (OLED) display device:

[0063] Area AA 112: Contains multiple periodically arranged pixels, multiple data lines, and multiple gate scan lines. A single data line is connected to multiple pixels along the Y direction, and a single gate scan line is connected to multiple pixels along the X direction. Each pixel in the panel is connected to the data lines, gate scan lines, power supply voltages ELVDD and ELVSS, and initialization voltage VINI. A pixel can be represented as a pixel circuit. Area AA can be composed of an m-row n-column pixel circuit array, with the smallest repeating unit being a pixel circuit. In the diagram, P11 represents the pixel in the 1st row and 1st column, and Pmn represents the pixel in the m-row and n-column. The pixel circuit includes the OLED and the circuit units used to control the OLED. The circuit units execute specific pixel circuit timing sequences, controlling the current from the positive power supply voltage VDD through the OLED to the negative power supply voltage VSS. The OLED emits light of a specific brightness at a specific current value.

[0064] NA region 111: Located on both sides of AA region, it contains multiple scan line drive circuits 1111. Because it employs gate driver on array (GOA) technology, it can also be called a GOA circuit. NA region can include multiple GOA modules. Each GOA module has a shift register function. After receiving the control signal CS, the GOA circuit can generate shift pulse signals output line by line, providing multiple gate signals to multiple gate lines (GL). Each GL is connected to one or more rows of pixels. The GOA signals are output line by line through GL, controlling the thin-film transistors (TFTs) in the pixel circuit to turn on or off line by line. Different GOA circuits can use the same or different potential frequencies of the control signal CS, depending on the signal conditions.

[0065] Data control circuit 120: Provides a data signal DS, which is input to the display panel via multiple data lines and connected to the pixel circuit elements to enable the pixels to function properly. For display devices with a dual data line architecture, as described above, a column of pixels can be connected to two data lines, and the two data lines can be connected to the odd-numbered rows and even-numbered rows of pixels in the same column, respectively. This DS signal contains pixel data voltage information, used to control the brightness of the light-emitting elements.

[0066] The peripheral driving circuit 130 provides multiple sets of control signals CS, including a start voltage signal (STV), clock signals (CLK1, CLK2), gate high voltage VGH (Vgate high), and gate low voltage VGL (Vgate low). The GOA receives the CS signals and generates corresponding high and low voltage gate signals. Additionally, the peripheral driving circuit can provide multiple sets of pixel operating voltages PV, including power supply voltages VDD and VSS, and initialization voltage VINI. The PV voltages are input to the display panel via multiple signal lines and connected to the pixel circuit elements, enabling the pixels to function normally.

[0067] Figure 3 and Figure 4 yes Figure 2 The schematic diagrams shown are cross-sectional views of the display device at different locations, intended to illustrate the design features of this application. Figure 3 and Figure 4 Only the transistor structure connected to the data line in the pixel circuit is shown, and the others are not shown. Figure 2 Signal lines such as gate lines in the circuit. Among them, Figure 3 This is the cross-sectional structure corresponding to the first pixel in the display device. Figure 4 The cross-sectional structure corresponding to the second pixel in the display device is shown below. The first pixel and the second pixel can be located in the same pixel column, and the first pixel and the second pixel can be two pixels in adjacent rows. For example, multiple pixels of the display device are arranged in an array to form multiple pixel columns and multiple pixel rows. Along a certain direction, the first pixel and the second pixel are arranged alternately to form a pixel column. For example, the first pixel can be a pixel in an odd-numbered row and the second pixel can be a pixel in an even-numbered row, or the first pixel can be a pixel in an even-numbered row and the second pixel can be a pixel in an odd-numbered row.

[0068] It should be noted that the distinction between the first pixel and the second pixel here is for the purpose of easily distinguishing electrical connections. In practical applications, the first pixel and the second pixel can be pixels of the same light emission type or the same shape, or they can be pixels of different light emission types or different shapes. This application does not impose specific limitations on this.

[0069] The display device may include a first data line 209 and a second data line 210. The first data line 209 may be connected to a first pixel for inputting data voltage to the first pixel, such as... Figure 3 As shown. The second data line 210 can be connected to the second pixel and used to input data voltage to the second pixel, such as... Figure 4 As shown.

[0070] Continue to refer to Figure 3 The first pixel may include a first transistor 220 and a first interconnect 224. The first end of the first transistor 220 can be coupled to the first interconnect 224 through a first via 223, and the first interconnect 224 can be coupled to the first data line 209 through a second via 225. The projection of the first interconnect 224 along a first direction may not overlap with the second data line 210. The first direction is perpendicular to the light-emitting surface of the display device. The light-emitting surface of the display device can be the surface on which the display emits light, that is, the plane where the display screen of the display device is located. The first direction is the z-axis direction shown in the figure.

[0071] Similarly, continue to refer to Figure 4 The second pixel may include a second transistor 230 and a second interconnect 234. The first end of the second transistor 230 may be coupled to the second interconnect 234 through a third via 233, and the second interconnect 234 may be coupled to the second data line 210 through a fourth via 235. The projection of the second interconnect 234 along the first direction may not overlap with the first data line 209.

[0072] In the embodiments provided in this application, for the first pixel, the first data line 209 is coupled to the first transistor 220 through the second via 225, the first interconnect line 224, and the first via 223. The projection of the first interconnect line 224 along the first direction does not overlap with the second data line 210, which enables the first interconnect line 224 and the second data line 210 to have a small parasitic capacitance. Since the first interconnect line 224 is connected to the first data line 209, the potential on the first interconnect line 224 and the first data line 209 is the same, which can reduce the parasitic capacitance between the first data line 209 and the second data line 210, thereby reducing the coupling crosstalk problem between the first data line 209 and the second data line 210 at the location of the first pixel. Similarly, for the second pixel, the second data line 210 is coupled to the second transistor 230 through the fourth via 235, the second interconnect line 234, and the third via 233. The projection of the second interconnect line 234 along the first direction does not overlap with the first data line 209, which enables the second interconnect line 234 and the first data line 209 to have a small parasitic capacitance, that is, the second data line 210 and the first data line 209 to have a small parasitic capacitance. This reduces the coupling crosstalk problem between the first data line 209 and the second data line 210 at the location of the first pixel, thereby reducing the screen color point and brightness deviation problems caused by the coupling crosstalk between data lines and improving the display effect of the entire display device.

[0073] Continue to refer to Figure 3 and Figure 4The first terminal of the first transistor 220 and the first terminal of the second transistor 230 can be located in the same structural layer, but at different locations within that layer. For example, the first terminal of the first transistor 220 and the first terminal of the second transistor 230 can be located in different regions of the first conductive layer. When the first transistor 220 and the second transistor 230 are silicon transistors, the material of the first conductive layer can be polycrystalline silicon or low-temperature polysilicon (LTPS), and the first conductive layer can also be referred to as a P-Si layer. The P-Si layer can be formed into silicon traces with a specific linewidth through exposure and patterning processes. The portion of the P-Si layer corresponding to the first transistor 220 can be referred to as the first portion 221 of the P-Si layer, and the portion corresponding to the second transistor 230 can be referred to as the second portion 231 of the P-Si layer.

[0074] Several regions of the P-Si layer can be doped (e.g., p-type doping or n-type doping) to form the source and drain regions in a silicon transistor. The first end of the first transistor 220 can be the source region 2211 of the first transistor 220, and the first end of the second transistor 230 can be the source region 2311 of the second transistor 230. Alternatively, the first end of the first transistor 220 can also be the drain region 2212 of the first transistor 220, and the first end of the second transistor 230 can be the drain region 2312 of the second transistor 230. The positions of the source and drain regions can be interchanged.

[0075] The display device may further include a first gate metal layer (hereinafter referred to as the GM1 layer), which can be formed into the gate region of the first transistor 220 and the gate region of the second transistor 230 through exposure and patterning processes. For example, the GM1 layer can be formed into a first portion 222 and a second portion 232 through exposure and patterning processes. The first portion 222 of the GM1 layer can serve as the gate region of the first transistor 220, and the second portion 232 of the GM1 layer can serve as the gate region of the second transistor 230. The GM1 layer may be one or more layers, and the material of the GM1 layer may be a metal or alloy material such as titanium, aluminum, nickel, copper, silver, or gold.

[0076] The portion of the first part 221 of the P-Si layer not covered by the GM1 layer can form the source region 2211 and drain region 2212 of the first transistor 220. For Figure 3The first transistor 220 shown has a first via 223 connected to the source region 2211, which can be referred to as the first terminal of the first transistor 220. The first via 223 can also be connected to the drain region 2212 of the first transistor 220. The area of ​​the first portion 221 of the P-Si layer covered by the GM1 layer can be the channel region 2213 of the first transistor. Under the control of the gate voltage, the channel region 2213 can form a conductive path, making the source region 2211 and the drain region 2212 conductive.

[0077] Similarly, for Figure 4 The portion of the second P-Si layer 231 not covered by the GM1 layer in the second transistor 230 shown can form the source region 2311 and the drain region 2312 of the second transistor 230, respectively. The source region 2311 and the drain region 2312 of the second transistor 230 can also be interchanged. The third via 233 can be connected to the source region 2311 of the second transistor 230 or to the drain region 2312 of the second transistor 230.

[0078] In some embodiments, the first conductive layer includes a first lead and a second lead. The first lead forms a first end of a first transistor 220, and the second lead forms a first end of a second transistor 230. The projection of the end of the first lead near the second data line 210 along a first direction is located between the first data line 209 and the second data line 210, and the projection of the end of the second lead near the first data line 209 along a first direction is located between the first data line 209 and the second data line 210.

[0079] In other words, the first lead can be located in the first part 221 mentioned above, for Figure 3 The first transistor 220 shown can have its first lead as the source region 2211 of the first transistor 220. Similarly, the second lead can be located in the second portion 231 described above. Figure 4 The second transistor 230 shown can have its second lead as the source region 2311 of the second transistor 230.

[0080] As mentioned above, the source and drain regions of a transistor can be interchanged. The first lead can also be the drain region 2212 of the first transistor 220, and the second lead can also be the drain region 2312 of the second transistor 230.

[0081] The projection of the end of the first lead near the second data line 210 along the first direction is located between the two data lines, which can further ensure that the first interconnect line 224 connected to the first lead and the second data line 210 have no overlapping area in the first direction, thereby reducing the coupling crosstalk problem between the two data lines; similarly, the projection of the end of the second lead near the first data line 209 along the first direction is located between the two data lines, which can reduce the coupling crosstalk problem between the two data lines.

[0082] See also Figure 3 and Figure 4 In some embodiments of the structure shown, the projection of the first via 223 along the first direction may be located between the first data line 209 and the second data line 210, and the projection of the third via 233 along the first direction may be located between the first data line 209 and the second data line 210.

[0083] The first via 223 and the third via 233 can be interconnect vias. For example, the metal material in the first via 223 can be the same as the material of the first interconnect 224. The metal layer containing the first interconnect 224 can be formed by a metal deposition process, during which the first via 223 can be filled, allowing the first interconnect 224 and the first lead to be connected through the first via 223. Similarly, the metal material in the third via 233 can be the same as the material of the second interconnect 234, and the third via 233 can be filled during the deposition process of the metal layer containing the second interconnect 234, allowing the second interconnect 234 to be connected to the second lead. The formation process of other vias involved in this application is similar, and they are filled during the deposition of the connected upper metal layer.

[0084] In some embodiments, the first via 223, the second via 225, the third via 233, and the fourth via 235 may extend along a first direction. The vias extending along the first direction facilitates their machining.

[0085] See also Figure 3 and Figure 4 In some embodiments of the structure shown, the first interconnect 224 and the second interconnect 234 may extend in opposite directions.

[0086] For example, the first end of the first transistor 220 is coupled to the first interconnect 224 through the first via 223, and can be coupled to the first end of the first interconnect 224, which can be the end of the first interconnect 224 closer to the second data line 210. The first interconnect 224 can extend along the positive x-axis direction shown in the figure, toward the direction where the first data line 209 is located, and the second end of the first interconnect 224 is connected to the first data line 209 through the second via 225, which can be the end of the first interconnect 224 closer to the first data line 209. The first end of the second transistor 230 is coupled to the second interconnect 234 through the third via 233. The first end of the second interconnect 234 is the end of the second interconnect 234 that is close to the first data line 209. The second interconnect 234 can extend in the negative x-axis direction shown in the figure, towards the direction where the second data line 210 is located. The second end of the second interconnect 234 is connected to the second data line 210 through the fourth via 235. The second end of the second interconnect 234 can be the end of the second interconnect 234 that is close to the second data line 210.

[0087] The first interconnect 224 and the second interconnect 234 extend in opposite directions, which can further ensure that the first interconnect 224 and the second data line 210 do not overlap in the first direction, and the second interconnect 234 and the first data line 209 do not overlap in the first direction. It also facilitates the connection between the first interconnect 224 and the first data line 209 and the second interconnect 234 and the second data line 210.

[0088] In some embodiments, the distance between the end of the first interconnect 224 near the second data line 210 and the second data line 210 is less than or equal to the distance between the end of the second interconnect 234 near the first data line 209 and the first data line 209.

[0089] For example, Figure 5 This is a schematic diagram of a partial cross-sectional structure of another first pixel provided in an embodiment of this application, such as... Figure 5 As shown, in the first pixel, the first end of the first interconnect 224 can further extend towards the second data line 210, and the coupling position between the first via 223 and the first interconnect 224 can be located between the first end and the second end of the first interconnect 224. In this example, the structure of the second pixel can be similar to... Figure 4The structure of the second pixel shown is similar, so that the distance between the end of the first interconnect 224 near the second data line 210 and the second data line 210 in the x-axis direction is less than the distance between the end of the second interconnect 224 near the first data line 209 and the first data line 209 in the x-axis direction. In other words, the distance between the end of the first interconnect 224 near the second data line 210 and the second data line 210 is less than the distance between the end of the second interconnect 224 near the first data line 209 and the first data line 209.

[0090] Figure 4 In the second pixel shown, the second transistor 230 is coupled to the second data line 210 through the third via 233, the second interconnect 234 and the fourth via 235. The source region 2311 and the drain region 2312 of the second transistor 230 are located in the second part 231 of the P-Si layer. The second part 231 of the P-Si layer overlaps with the first data line 209 in the first direction, which can easily cause the first data line 209 and the second part 231 to have a large parasitic capacitance.

[0091] And in Figure 3 or Figure 5 In the first pixel shown, the source region 2311 and drain region 2312 of the second transistor 230 are located in the second portion 231 of the P-Si layer. The second portion 231 of the P-Si layer is coupled to the first data line 209 through a first via 223, a first interconnect 224, and a second via 225. The second data line 210 has no overlapping area with the first portion 221 of the P-Si layer in a first direction, such that the parasitic capacitance present in the first pixel is smaller than the parasitic capacitance present in the second pixel.

[0092] Therefore, the distance between the end of the first interconnect 224 closest to the second data line 210 and the second data line 210 is less than or equal to the distance between the end of the second interconnect 234 closest to the first data line 209 and the first data line 209. This can increase the parasitic capacitance in the first pixel, making the parasitic capacitance in the first pixel and the second pixel closer. As a result, it is not necessary to configure different crosstalk compensation codes for the first pixel and the second pixel, which is beneficial for achieving crosstalk compensation.

[0093] See also Figures 3 to 5 In some embodiments of the structure shown, the first data line 209 and the second data line 210 may be located in different regions of the first metal layer, the first interconnect 224 and the second interconnect 234 may be located in different regions of the second metal layer, and the second metal layer is located between the first conductive layer and the first metal layer along the first direction.

[0094] The first metal layer can also be called the second source / drain metal layer (hereinafter referred to as SD2 layer). The material of the SD2 layer can be metal or alloy materials such as titanium, aluminum, nickel, copper, silver, and gold. The SD2 layer can be exposed and patterned to form a wiring layer for one or more signals such as positive power supply voltage VDD signal, negative power supply voltage VSS signal, and data signal, for example, to form the first data line 209 and the second data line 210.

[0095] The second metal layer can also be called the first source / drain metal layer (hereinafter referred to as the SD1 layer). The material of the SD1 layer can be a metal or alloy such as titanium, aluminum, nickel, copper, silver, or gold. The material of the SD1 layer can be the same as or different from that of the SD2 layer. The thickness of the SD2 layer can be the same as or different from that of the SD1 layer. The SD1 layer can be exposed and patterned to form several metal wirings, such as the first interconnect 224 and the second interconnect 234. The SD1 layer can be connected to the SD2 layer through the aforementioned vias so that data signals can be transmitted to the transistors of the pixel circuit.

[0096] The second metal layer is located between the first conductive layer and the first metal layer along the first direction, which facilitates the connection between the first conductive layer and the first metal layer. This makes the connection structure between the first end of the first transistor and the first data line, as well as the connection structure between the first end of the second transistor and the second data line, simpler and easier to manufacture.

[0097] The above text combines Figures 3 to 5 The structure of the first transistor 220, the second transistor 230, the first data line 209, the second data line 210, the first interconnect 224, and the second interconnect 234 in the display device is described. The display device may also include other structural layers to support the formation of the above-mentioned structures such as the first transistor 220 and the second transistor 230.

[0098] See also Figures 3 to 5 The cross-sectional structural diagram shown indicates that the display device may include a substrate (SUB) 201, on which other structural layers of the display device may be supported. The substrate 201 may be made of polyimide (PI) or glass.

[0099] A buffer layer (BUF) 202 may be disposed on the substrate 201. The buffer layer 202 may be one or more layers. The material of the buffer layer 202 may be one or more dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0100] The display device may further include a first interlayer dielectric layer (hereinafter referred to as ILD1 layer) 203, which is formed above the buffer layer 202. The ILD1 layer 203 may be formed of a suitable dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. A P-Si layer for forming the first terminal of the first transistor 220 and the first terminal of the second transistor 230 is formed on the ILD1 layer 203.

[0101] The display device may also include a first gate insulating layer (hereinafter referred to as GI1 layer) 204, which may be formed above the ILD1 layer 203 and the P-Si layer. The GI1 layer 204 may be formed of a suitable dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0102] The aforementioned GM1 layer is formed on the GI1 layer 204. In addition to forming the gate region of the first transistor 220 and the gate region of the second transistor, the GM1 layer can also be formed into the terminals of a capacitor, such as the lower terminal of a storage capacitor Cst, through exposure and patterning processes.

[0103] The display device may also include a second interlayer dielectric layer (hereinafter referred to as ILD2 layer) 205, which may be formed above the GI1 layer 204 and the GM1 layer. The ILD2 layer 205 may be one or more buffer layers, and may be formed of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0104] The display device may also include an insulating layer 206 (hereinafter referred to as the INS layer), which may be formed on top of the ILD2 layer 205. The INS layer 206 may be a single layer or a multilayer structure, and may be formed of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0105] The aforementioned SD1 layer can be formed above the INS layer 206. This SD1 layer can serve not only as an interconnect layer between silicon transistors and signal lines, but also as an interconnect layer for oxide transistors, connecting to the source or drain of the oxide transistors via vias. Alternatively, the SD1 layer can also be connected to capacitor terminals via vias. The aforementioned first via 223 can sequentially pass through the INS layer 206, ILD2 layer 205, and GI1 layer 204, connecting one end of the first via 223 to the SD1 layer and the other end to the P-Si layer, thereby connecting the first interconnect 224 to the first end of the first transistor 220. Similarly, the third via 233 can also sequentially pass through the INS layer 206, ILD2 layer 205, and GI1 layer 204, connecting the second interconnect 234 to the first end of the second transistor 230.

[0106] The display device may further include a first planarization layer (hereinafter referred to as PLN1 layer) 207, which is formed above the SD1 layer. The material of the PLN1 layer 207 may be a dielectric material of an organic polymer. The arrangement of the PLN1 layer 207 facilitates the formation of other structural layers located above the PLN1 layer 207.

[0107] The aforementioned SD2 layer can be formed on the PLN1 layer 207, and the SD2 layer can be a single layer or multiple layers. The aforementioned second via 225 can penetrate the PLN1 layer 207, such that one end of the second via 225 is connected to the SD1 layer and the other end is connected to the SD2 layer, thereby connecting the first interconnect 224 to the first data line 209. Similarly, the fourth via 235 can penetrate the PLN1 layer 207, thereby connecting the second interconnect 234 to the second data line 210.

[0108] The display device may also include a second planarization layer (hereinafter referred to as PLN2 layer) 208, which may be formed on top of the SD2 layer and the PLN1 layer 207. The material of the PLN2 layer 208 may be an organic polymer dielectric material. The material of the PLN2 layer 208 may be the same as or different from the material of the PLN1 layer 207.

[0109] It should be understood that Figure 3 and Figure 4 The cross-sectional structure shown is only schematically illustrated at the corresponding positions of the first transistor 220 in the first pixel and the second transistor 230 in the second pixel. For the first pixel, the first transistor 220 is a silicon transistor. The first pixel may also include oxide transistors, capacitors, and other components. The oxide transistors and capacitors can be deployed together with the silicon transistors in the structural layer of the display device. The second pixel is similar. Other structures in the first and second pixels can be found in the description below.

[0110] Figure 6 This is another cross-sectional structure of the first pixel provided in the embodiments of this application, wherein the structure located to the left of the dashed line can be the same as described above. Figure 3The described structure is similar. This part can be the first transistor 220 in the first pixel and the connection structure between the first transistor 220 and the first data line 209. The structure to the right of the dashed line can be the structure of other components in the first pixel. The structure located to the right of the dashed line is described below. It should be understood that the dashed line is only used as a region marker. The cross-sectional structures on both sides of the dashed line can be cross-sectional structures at different locations in the first pixel. In order to display different components in the first pixel in the same cross-sectional view, the cross-sectional structures at different locations are combined and the dashed line is used as a region division marker. It should not limit the structure of the display device itself.

[0111] like Figure 6 As shown, the first pixel may further include a driving transistor 310, which is used to control the current of the light-emitting element. The driving transistor 310 can be a silicon transistor, and similar to the structure of the first transistor 220 and the second transistor 230 described above, the source and drain regions of the driving transistor 310 can be located in a P-Si layer, and the third portion 312 of the P-Si layer can be used to form the source and drain regions of the driving transistor 310. The gate region of the driving transistor 310 can be located in a GM1 layer, and the third portion 313 of the GM1 layer can form the gate region of the driving transistor 310.

[0112] The third part 313 of the GM1 layer can be connected to the interconnect 315 through the via 314. The interconnect 315 can be located in the SD1 layer and formed in the same structural layer as the first interconnect 224 and the second interconnect 234 through exposure and patterning.

[0113] The display device may further include a bottom shield metal (BSM) layer 311, which may be located at the bottom of the driving transistor 310, for example, below the P-Si layer, and below the third portion 312 of the P-Si layer. The BSM layer 311 may be formed on the buffer layer 202, and the ILD1 layer 203 may be formed on the BSM layer 311 and the buffer layer 202. The BSM layer 311 may be formed as the bottom gate of the driving transistor 310 through exposure and patterning processes. This bottom gate can serve as the bottom structure of the driving transistor 310, used to adjust the threshold voltage of the driving transistor 310. The bottom gate can also be used to control and change the operating characteristics of the driving transistor 310 in the channel region.

[0114] In some embodiments, the GM1 layer can serve not only as the gate terminal of a transistor but also as a terminal of a capacitor, such as the lower terminal of a capacitor. Accordingly, the display device may further include a second gate metal layer (hereinafter referred to as the GM2 layer), and the first portion 411 of the GM2 layer may form the upper terminal of the capacitor. At least a portion of the projection of the first portion 411 of the GM2 layer along a first direction may overlap with the third portion 313 of the GM1 layer, and the first portion 411 of the GM2 layer and the third portion 313 of the GM1 layer together constitute the capacitor. The GM2 layer may be a single layer or multiple layers, and the material of the GM2 layer may be a metal or alloy material such as titanium, aluminum, nickel, copper, silver, or gold.

[0115] It should be understood that the lower terminal of the capacitor and the gate terminal of the driving transistor may not share a metal layer; they can each be independent metal parts. For example, the lower terminal of the capacitor and the gate terminal of the driving transistor can be staggered.

[0116] The upper and lower terminals of the capacitor can be isolated from each other. The ILD2 layer 205 can be disposed on the GM1 layer, and the GM2 layer can be formed on the ILD2 layer 205.

[0117] When the first pixel includes an oxide transistor 510, the display device may further include an oxide layer 512 and a third gate metal layer (hereinafter referred to as the GM3 layer) 513. The oxide layer 512 can be exposed and patterned to form oxide traces with a specific linewidth. Several regions of the oxide layer 512 (e.g., regions not covered by the GM3 layer 513) can be doped (e.g., p-type doping and n-type doping) to form the source and drain regions of the oxide transistor 510. The GM3 layer 513 can be disposed above the oxide layer 512 to form the drain region of the oxide transistor 510.

[0118] When the oxide transistor 510 is connected to a silicon transistor, it can be connected to the interconnect 515 via via 514, and then connected to the corresponding silicon transistor via the interconnect 515. When the interconnect 515 is connected to the corresponding silicon transistor, it can also be connected to the source or gate region of the silicon transistor via via. The interconnect 515 can be located in the SD1 layer.

[0119] Similarly, the GM3 layer can be connected to the interconnect 517 via via 516, and to the gate signal line (the gate signal line of the oxide transistor 510 is not shown in the figure) via the interconnect 517. The interconnect 517 can also be located in the SD1 layer.

[0120] The oxide transistor 510 may also have a bottom gate, which may be located at the bottom of the oxide layer 512. The bottom gate may be located in the aforementioned GM2 layer and may be formed by the second portion 511 of the GM2 layer.

[0121] The GM3 layer 513, oxide layer 512, and GM2 layer are mutually insulated. Exemplarily, the INS layer 206 may include a first insulating layer 206-1, a second insulating layer 206-2, and a third insulating layer 206-3. The first insulating layer 206-1 may be formed on the GM2 layer, and the oxide layer 512 may be formed on the first insulating layer 206-1. The second insulating layer 206-2 may be formed on the oxide layer 512, and the GM3 layer 513 may be formed on the second insulating layer 206-2. Further, the third insulating layer 206-3 may be formed on the GM3 layer 513.

[0122] The first insulating layer 206-1 can also be referred to as the third interlayer dielectric layer (hereinafter referred to as ILD3), the second insulating layer 206-2 can also be referred to as the second gate insulating layer (hereinafter referred to as GI2), and the third insulating layer 206-3 can also be referred to as the oxide interlayer dielectric layer (hereinafter referred to as OILD).

[0123] The first pixel may further include a light-emitting element, such as an organic light-emitting diode (OLED). Correspondingly, the display device may also include an anode layer 612, which may be formed on the PLN2 layer and constitute the anode terminal of the light-emitting element. The anode layer 612 can be coupled to an interconnect line 611 through a via 613, allowing the TFT circuit signals within the pixel to be coupled to the light-emitting element. The interconnect line 611 may be located in the SD2 layer, and it can be coupled to the SD1 layer through a via 518, allowing the light-emitting element to be coupled to a transistor.

[0124] It should be understood that the anode conductor layer 612 may also include optical structure layers, such as pixel defining layers, organic light-emitting diode light-emitting materials, cathode layers, polarizers, glass cover plates, etc., which will not be listed here. The anode conductor layer 612 may also be formed on the third planarization layer (hereinafter referred to as the PLN3 layer). The PLN3 layer may be formed on the PLN2 layer and the third source / drain metal layer (SD3 layer) (not shown in the figure). The SD3 layer may serve as an interconnect layer for coupling between the transistor and the light-emitting element, or it may serve as an interconnect layer for the transistor and other signal lines. This application does not limit this.

[0125] It should be understood that the first pixel may include multiple transistors. For example, the pixel circuit included in the first pixel may be of type 6T1C, 7T1C, 8T1C, 8T2C, 9T1C, 9T2C, etc. For a 7T1C circuit, each pixel circuit may include 7 transistors and 1 capacitor. The 7 transistors may include one or more silicon transistors or one or more oxide transistors. This application does not limit the structure of the pixel circuit. Figure 6 The image only schematically illustrates one example of a silicon transistor, oxide transistor, or capacitor that may be present in a pixel circuit; the same type of transistor structure can be used with... Figure 6 The corresponding structures are similar, and will not be shown one by one here. Figure 6 The structure of the display device is described using the first pixel as an example. The transistor and capacitor structures involved in the second pixel can be compared with... Figure 6 Similar examples are found elsewhere, and will not be listed here.

[0126] Figure 7 and Figure 8 This is an example of a pixel circuit provided in an embodiment of this application, wherein, Figure 7 This is a schematic diagram of the complete connection structure of the pixel circuit. Figure 8 This is a schematic diagram of a partial connection structure of the pixel circuit. This pixel circuit can constitute a sub-pixel in a display device. A group of red, green, and blue sub-pixels can constitute a pixel, for example, a first pixel or a second pixel. The connection relationship between transistors in the pixel circuit of the first pixel can be the same as the connection relationship between transistors in the pixel circuit of the second pixel. The first transistor 220 in the first pixel can be a transistor in the red sub-pixel, a transistor in the green sub-pixel, or a transistor in the blue sub-pixel. Similarly, the second transistor 230 in the second pixel can be a transistor in the red sub-pixel, a transistor in the green sub-pixel, or a transistor in the blue sub-pixel.

[0127] like Figure 7 As shown, the pixel circuit may include a driving transistor Td, which can be connected in series with the light-emitting element D to control the driving current of the light-emitting element D. The cross-sectional structure of the driving transistor Td can be... Figure 6The structure is similar to that of the driving transistor 310 described herein. The light-emitting element D can be a light-emitting diode (LED) or an organic light-emitting diode (OLED), etc., and the light-emitting element D1 can emit light under current drive. When the light-emitting element D1 is a red light-emitting element, the corresponding pixel circuit can form a red sub-pixel; when the light-emitting element is a green light-emitting element, the corresponding pixel circuit can form a green sub-pixel; and when the light-emitting element is a blue light-emitting element, the corresponding pixel circuit can form a blue sub-pixel.

[0128] The pixel circuit may further include a transistor T1, the first terminal of which can be connected to a data line (DL) for inputting a data voltage (DATA) to the transistor T1, and the second terminal of which can be connected to the first terminal of a driving transistor Td. When this pixel circuit is the pixel circuit in the first pixel, the transistor T1 is as described above. Figure 3 or Figure 5 The first transistor 220 described herein, the data line connected to which transistor T1 is connected can be referred to as the first data line 209. When the pixel circuit is the pixel circuit in the second pixel, transistor T1 is the one described above. Figure 4 The second transistor 230 described herein, the data line to which the transistor T1 is connected may be referred to as the second data line 210.

[0129] The connection between transistor T1 in the first pixel and transistor T1 in the second pixel and the data line can be as follows: Figure 8 As shown, DL1 can be the first data line 209, DL2 can be the second data line 210, and the first pixel can be located at... Figure 8 The pixels in the upper middle half, the second pixel can be located in Figure 8 In the lower half of the pixel, the first terminal of the first transistor is connected to DL1, and the first terminal of the second transistor can be connected to DL2. DL1 and DL2 can be located on the same side of the first and second pixels.

[0130] See also Figure 7 In the pixel circuit shown, the third terminal of transistor T1 can be connected to a gate signal S1, which can be used to control the on / off state of transistor T1. The gate signal S1 can be... Figure 2 The GOA circuit in the middle is generated according to the control signal CS transmitted by the peripheral driving circuit, and output to the pixel line by line through the gate line GL. The S2 signal, S3 signal and EM signal mentioned later are similar.

[0131] The pixel circuit may further include transistors T3 and T4. The first terminal of transistor T3 can be connected to the positive power supply voltage ELVDD, and the second terminal of transistor T3 can be connected to the first terminal of the driving transistor. The first terminal of transistor T4 can be connected to the second terminal of the driving transistor Td, and the second terminal of transistor T4 can be connected to the light-emitting element D. The third terminal of transistors T3 and T4 can be connected to a light-emitting signal (EM), which can be used to simultaneously control the on / off state of transistors T3 and T4.

[0132] The pixel circuit may further include a transistor T7, the first terminal of which may be connected to an initialization voltage VINI3, which can be used to initialize the source and drain of the driving transistor. The second terminal of the transistor T7 may be connected to the first terminal of the driving transistor Td.

[0133] The pixel circuit may further include a transistor T5, the first terminal of which can be connected to an initialization voltage VINI2, which can be used to initialize the gate of the driving transistor Td. The second terminal of the transistor T5 can be connected to the second terminal of the driving transistor Td, and the third terminal of the transistor T5 can be connected to a gate signal S4, which can be used to control the on / off state of the transistor T5.

[0134] Transistors T1, T3, T4, T5, T6, and T7 can be silicon transistors, and can be P-type transistors. The structures of transistors T3, T4, T5, T6, and T7 can be similar to... Figure 5 The first transistor 220 described herein can have a structure similar to that of transistor T1.

[0135] The pixel circuit may also include a transistor T2, the first end of which may be connected to the second end of the driving transistor Td, and the second end of the transistor T2 may be connected to the third end of the driving transistor Td.

[0136] The transistor T2 can be an oxide transistor, that is, an N-type transistor, and its structure can be similar to... Figure 5 The structure is similar to that of the oxide transistor 510 described in the text.

[0137] The first terminal of a transistor can be the source, the second terminal can be the drain, and the third terminal can be the gate. As mentioned above, the source and drain of a transistor can also be interchanged, where the first terminal can be the drain and the second terminal can be the source.

[0138] The pixel circuit may also include a capacitor C, whose first terminal is connected to the positive power supply voltage ELVDD, and whose second terminal is connected to the third terminal of the driving transistor Td. The cross-sectional structure of the capacitor C can be as follows: Figure 5 Similar to the capacitor structure described in the text, the first end of the capacitor C can be the upper plate and the second end can be the lower plate, or the first end can be the lower plate and the second end can be the upper plate.

[0139] It should be understood that Figure 7 and Figure 8 This application is merely an example of a pixel circuit that can be applied to the embodiments of this application. As mentioned above, the pixel circuit can also be of the 6T1C or 8T1C type, etc. This application does not limit the type of pixel circuit or the connection relationship between the transistors.

[0140] Figure 9 for Figures 3 to 6 A partial top view of the described display device is shown, in which... Figure 9 The image above is a partial top view of the structure of the first pixel in this display device. Figure 9 The image below is a partial top-down view of the second pixel's structure. Figure 9 The connection relationship between transistors can be related to Figure 7 and Figure 8 The corresponding transistors in the first and second pixels have the same connection relationship, and the connection relationship between the transistors can be the same, only the connection structure between the transistors connected to the data line and the data line is different.

[0141] Figure 9 The diagram shows a top view of driving transistors Td, T1, T3, and T4. These transistors can be silicon transistors, and silicon traces are used to connect them, meaning the silicon transistors can be interconnected on a P-Si layer. For transistor T1, the portion not covered by the GM1 layer forms its source (S) and drain (D), and the source (S) of T1 can be connected to the source (S) of driving transistor Td.

[0142] For the first pixel, the drain D of the transistor T1 can be connected to the SD1 layer through the first via 223 and to the SD2 layer through the second via 225, so that the transistor T1 is connected to the first data line 209.

[0143] Specifically, the first data line 209 may include a first main body portion 2091 and a first extension portion 2092. The first extension portion 2092 may be disposed on the side of the first main body portion 2091 near the second data line 210. The first main body portion 2091 may extend along the pixel column direction, that is, along the y-axis direction shown in the figure. The first extension portion 2092 may be disposed at an angle to the first main body portion 2091, for example, it may be perpendicular to the first main body portion 2091. The second via 225 may be connected to the first extension portion 2092.

[0144] It should be understood that the projection of the first via 223 along the first direction is located between the first data line 209 and the second data line 210, which means that the projection of the first via 223 along the first direction is located between the second data line 210 and the first main body portion 2091. Figure 9 In the above figure, the linewidth of the first extension portion 2092 is greater than the linewidth of the first interconnect 224, and also greater than the linewidth of the first terminal of transistor T1, i.e., the first lead. The linewidth of the first extension portion 2092 can also be less than the linewidth of the first interconnect 224, or vice versa; this application does not impose any limitations on this. The features of the corresponding structure in the second pixel are similar and will not be repeated below.

[0145] Similarly, for the second pixel, the drain D of the transistor T1 can be connected to the SD1 layer through the third via 233 and to the SD2 layer through the fourth via 235, so that the transistor T1 is connected to the second data line 210.

[0146] The second data line 210 may include a second main body portion 211 and a second extension portion 212. The second extension portion 212 may be disposed on the side of the second main body portion 211 near the first data line 209. The second main body portion 211 may extend along the pixel column direction, and the second extension portion 212 may be disposed at an angle to the second main body portion 211, for example, the second extension portion 212 may be perpendicular to the second main body portion 211. The fourth via 225 may be connected to the second extension portion 212.

[0147] For transistor T3, the portion not covered by the GM1 layer can form the source S and drain D of transistor T3. The source S of transistor T3 can be connected to the source S of the driving transistor Td, and the drain D of transistor T3 can be connected to the positive power supply voltage ELVDD. Figure 8The connection relationship of the drain D of transistor T3 is not shown in the diagram. For transistor T4, the portion not covered by the GM1 layer can form the source S and drain D of transistor T4. The drain D of transistor T4 can be connected to the source D of the driving transistor Td, and the source S of transistor T4 can be connected to the light-emitting element D. Figure 9 The connection relationship of the source S of transistor T4 is not shown in the figure.

[0148] In some embodiments, the linewidth of the first lead can be the same as the linewidth of the second lead. As described above, the first lead can be the first end of transistor T1 in the first pixel, such as the drain of transistor T1, or it can be the source of transistor T1. The linewidth of the first lead can refer to the dimension L1 of the first lead perpendicular to its extension direction, and the linewidth of the second lead can refer to the dimension L2 of the second lead perpendicular to its extension direction, where L1 = L2.

[0149] The line width of the first lead is the same as that of the second lead, which makes the structure of the first transistor 220 and the structure of the second transistor 230 more similar. This makes the parasitic capacitance between the two data lines in the first pixel and the second pixel more similar, and the same crosstalk compensation code can be configured for the first pixel and the second pixel, which is beneficial for display effect compensation.

[0150] In some embodiments, the first lead has a first area, which can be the overlapping area of ​​the projection of the first lead along a first direction and the first data line, and the second lead has a second area, which can be the overlapping area of ​​the projection of the second lead along the first direction and the first data line, and the size of the first area is the same as the size of the second area.

[0151] When the linewidths of the first and second leads are the same, the lengths of the overlapping areas of the first and second leads and the first data line in the first direction can also be the same, and the shapes of the overlapping areas can also be the same, so that the first area and the second area are the same size. Having the first and second areas of the same size allows the structures of the first and second transistors to be more similar, thereby making the parasitic capacitances in the first and second pixels more similar.

[0152] It should be understood that, apart from the linewidth and area described above, other structural features of the first transistor 220 and the second transistor 230 may also be the same. For example, the dimensions of the first lead and the second lead in the x-axis direction may be the same, and the dimensions in the y-axis direction may also be the same; the linewidths of the entire first portion 221 and the entire second portion 231 may also be the same; the distance in the x-axis direction between the end of the first lead near the second data line 210 and the first data line 209 may also be the same as the distance in the x-axis direction between the end of the second lead near the second data line 210 and the first data line 209; the distance in the x-axis direction between the end of the first lead near the second data line 210 and the gate of the first transistor 220 may also be the same as the distance in the x-axis direction between the end of the second lead near the second data line 210 and the gate of the second transistor 230.

[0153] Figure 10 and Figure 11 This is another top view of the display device. The first data line 209 and / or the second data line 210 can be wound around the via to increase the line spacing between the first data line 209 and the second data line 210.

[0154] As an example, Figure 10 The image above can be seen as a partial top-down view of the structure of the first pixel. Figure 10 The image below can be seen as a partial top-down view of the second pixel's structure. For example... Figure 10 As shown in the upper figure, the first data line 209 and the second data line 210 can extend along the y-axis direction. When passing through the locations of the first via 223 and / or the second via 225, the second data line 210 can wrap around away from the first data line 209. This makes the distance between the first data line 209 and the second data line 210 at the first position greater than the distance at the second position. The first position is the via position, and the second position is any position other than the via position. The via position of the first data line 209 can be defined as the projection of the first data line 209 along the x-axis direction overlapping with the via. Similarly, the via position of the second data line 210 can be defined as the projection of the first data line 209 along the x-axis direction overlapping with the via.

[0155] Specifically, the second data line 210 may include a winding portion 211B and a straight portion 211A, or in other words, the second main body portion 211 of the second data line 210 may include the winding portion 211B and the straight portion 211A. The winding portion 211B is the portion of the second data line 210 that passes through the via. The distance d1 between the winding portion 211B and the first data line 209 may be greater than the distance d2 between the straight portion 211A and the first data line 209. The distance between the winding portion 211B and the first data line 209 may refer to the vertical distance between the winding portion 211B and the first data line 209, and may also refer to the vertical distance between the winding portion 211B and the first main body portion 2091 of the first data line 209. The distance between the straight section 211A and the first data line 209 can also refer to the vertical distance between the straight section 211A and the first data line 209, and can also refer to the vertical distance between the straight section 211A and the first main body section 2091.

[0156] In some embodiments, the distance d1 between the first main body portion 2091 and the second main body portion 211 at the first position and the distance d2 at the second position satisfy: d2≤d1≤2d2.

[0157] For example, the value of d1 can be 1.1d2, 1.2d2, 1.3d2, 1.4d2, 1.5d2, 1.6d2, 1.7d2, 1.8d2, 1.9d2, etc.

[0158] Similarly, such as Figure 10 As shown in the figure below, when the second data line 210 extends along the y-axis to the location of the second pixel, it can also wind away from the first data line 209 when passing through the locations of the third via 233 and / or the fourth via 235. That is, the second data line 210 can include multiple winding portions 211B and multiple straight portions 211A. When the second data line 210 includes a second extension portion 212 and is connected to the via through this second extension portion 212, the second extension portion 212 can be connected to the side of the winding portion 211B closest to the first data line 209 to facilitate the connection between the second data line 210 and the via. The locations of the third via 233 and the fourth via 235 can also be referred to as the first location.

[0159] It should be understood that the shape of the winding portion 211B of the second data line 210 shown in the figure is only an example to illustrate the winding method of the data line. The shape of the winding portion 211B can also be other shapes. For example, the angle between the winding portion 211B and the straight portion 211A can be a right angle, or the entire winding portion 211B can be an arc shape. The second data line 210 can be wound when it extends above the via, or it can be wound when it extends to be aligned with the upper edge of the via in the x-axis direction. Similarly, the second data line 210 can continue to be routed in a straight line when it is wound to the bottom of the via, or it can continue to be routed in a straight line when it is wound to be aligned with the lower edge of the via in the x-axis direction. The shape of the winding portion of the first data line 209 in the following text is similar, and this application does not limit it.

[0160] As another example, such as Figure 11 As shown, both the first data line 209 and the second data line 210 can be wound around the via when they extend to the position, and... Figure 10 Similarly, Figure 11 The image above can be seen as a partial top-down view of the structure of the first pixel. Figure 11 The image below is a partial top-view structural diagram of the second pixel. The first data line 209 can be wound away from the second data line 210 at the via location, and the second data line 210 can be wound away from the first data line 209 at the via location.

[0161] Specifically, the structure of the second data line 210 can be related to... Figure 10 The structure of the second data line 210 is similar. The first data line 209 may include a straight portion 2091A and a wound portion 2091B, the position of which can correspond to the position of the wound portion 211B. The correspondence between the positions of the wound portion 2091B and the wound portion 211B can mean that the projection of the wound portion 2091B along the x-axis direction overlaps with that of the wound portion 211B. The aforementioned first position can be the position corresponding to the wound portion 2091B and the wound portion 211B, and the distance d1 between the wound portion 2091B and the wound portion 211B is greater than the distance d2 between the straight portion 2091A and the straight portion 211A. The distance between the wound portion 2091B and the wound portion 211B can refer to the vertical distance between them.

[0162] Similarly, the distance d1 between the winding portion 2091B and the winding portion 211B and the distance d1 between the straight portion 2091A and the straight portion 211A satisfy: d2≤d1≤2d2.

[0163] It should be noted that, in the embodiments provided in this application, the structure of the display device can also be such that the first data line 209 is wound away from the second data line 210, while the second data line 210 is not wound away from the first data line 209. In this example, the structure of the first data line 209 can be the same as... Figure 11 The structure of the first data line 209 described herein is similar and will not be repeated here. When the first data line 209 and the second data line 210 are wound, the winding portion 211B and the winding portion 2091B do not overlap with the projection of the gate metal layer of the transistor in the pixel in the z-axis direction. For example, for... Figure 11 The structure shown has a projection of the winding portion 2091B along the z-axis direction that does not overlap with the GM1 layer corresponding to transistor T1, thus preventing the winding portion 2091B from affecting the performance of transistor T1.

[0164] When both the first data line 209 and the second data line 210 are wound, the shape of the winding portion 2091B of the first data line 209 can be the same as the shape of the winding portion 211B of the second data line 210, and the size of the winding portion 2091B can also be the same as the size of the winding portion 211B, so that the structure of the first data line 209 and the second data line 210 is more symmetrical, thereby making the parasitic capacitance between the first data line 209 and the second data line 210 more balanced.

[0165] When the first data line 209 and / or the second data line 210 are wound around the via location, the line spacing between the first data line 209 and the second data line 210 can be increased, as can the distance between the first data line 209 and the second interconnect 234, and the distance between the second data line 210 and the first interconnect 224. This can reduce the parasitic capacitance in the first pixel and the second pixel and reduce crosstalk coupling problems.

[0166] In some embodiments, the display device may include a first driving transistor and a first metal region. The first metal region may be located above the first driving transistor and is insulated from it. The projection of the first metal region along a first direction overlaps with at least a portion of a first region of the first driving transistor. The first region may be the source region or the drain region of the first driving transistor, and the first region may be closer to one of the source region and the drain region of the first driving transistor than the first data line 209 and the second data line 210.

[0167] Figure 12This is a cross-sectional structural diagram of the display device provided in this application embodiment at the position corresponding to the driving transistor. The driving transistor is transistor 310 shown in the diagram. This driving transistor 310 can be referred to as the first driving transistor. The structure of the driving transistor 310 can be similar to... Figure 6 The structure of the driving transistor 310 described is similar, and will not be repeated here to avoid repetition. The first metal region is the metal region 414 shown in the figure, and this first metal region can be located in the GM2 layer. This first metal region is located above the first driving transistor, that is, above the gate region of the driving transistor 310. As mentioned above, the ILD2 layer can be deposited on the GM1 layer, and the GM2 layer can be disposed on the ILD2 layer, thereby insulating the first metal region from the first driving transistor. Figure 12 The driving transistor 310 shown is a silicon transistor, that is, a P-type transistor. The source region and drain region of the driving transistor 310 are both located in the P-Si layer. The source region of the driving transistor 310 is closer to the first data line 209 and the second data line 210 than the drain region. Therefore, the first region can be the source region of the driving transistor 310. The first metal region can cover at least a part of the source region of the driving transistor 310.

[0168] The first metal region covers at least a portion of the first region of the first driving transistor, which can reduce the coupling crosstalk of the data line to the source of the first driving transistor and improve display artifacts and color shift problems.

[0169] It should be understood that the first driving transistor can be a driving transistor in a first pixel, a driving transistor in a second pixel, or a driving transistor in any of the pixels other than the first and second pixels. The first regions of all driving transistors in the display device can also be covered by the first metal region. In the above example, the first metal region can cover the drain region of the driving transistor 310, or it can not. When the driving transistor 310 is an N-type transistor, the drain region of the driving transistor 310 can be the region of the driving transistor 310 near the first data line 209 and the second data line 210, and the first metal region can cover at least a portion of the drain region of the driving transistor 310. In this example, the first metal region can cover the source region of the driving transistor 310, or it can not. Furthermore, when the driving transistor 310 is a P-type transistor, the first region is located in the aforementioned P-Si layer; when the driving transistor 310 is an N-type transistor, the first region can be located in the aforementioned... Figure 6 In the oxide layer described, the source and drain regions of other oxide transistors in the pixel are formed in the same structural layer.

[0170] In some embodiments, the voltage of the first metal region can be configured as the power supply voltage of the display device. This power supply voltage can be a positive power supply voltage, ELVDD.

[0171] The voltage of the first metal region is configured as the power supply voltage of the display device, which enables the voltage of the first metal region to be a constant voltage value so as to shield the source of the driving transistor Td.

[0172] It should be understood that a constant voltage value for the first metal region can mean that the voltage value of the first metal region remains unchanged or changes by less than a preset range during the working time. During pixel operation, the voltage value may decay due to power consumption and other reasons; however, this decay issue is not considered in this application. Furthermore, the voltage of the first metal region can also be configured to other constant voltage values, such as the negative power supply voltage ELVSS, the first initialization voltage VINI1, or the second initialization voltage VINI2, etc.

[0173] Figure 13 yes Figure 12 The top view of the described display device shows that the GM2 layer may be located in the area indicated by the thick line box in the figure. There may be a gap in the planar direction between the gate region of the transistor connected to the driving transistor Td and the GM2 layer; in other words, the projection of the gate region of the transistor connected to the driving transistor Td and the GM2 layer in the first direction does not overlap. The gate region of the transistor connected to the driving transistor Td may be located in the GM1 layer shown in the figure. There may be a gap in the planar direction between the GM1 layer and the GM2 layer corresponding to the transistor connected to the driving transistor Td.

[0174] For example, the source of the driving transistor Td is connected to transistors T3 and T1, respectively, and there may be a gap between the gate regions of transistors T3 and T1 and the GM2 layer on the plane. The gate regions of transistors T3 and T1 may also be referred to as the first gate metal line.

[0175] In some embodiments, the spacing d between the first metal region and the first gate metal line in the second direction satisfies: 1μm ≤ d ≤ 5μm. This second direction can be parallel to the light-emitting surface of the display device. The spacing between the first metal region and the first gate metal line in the second direction can refer to the shortest distance between them. Figure 13 The display device shown can be defined as the distance between the boundary of the first metal region and the boundary of the first gate metal line in the y-axis direction shown in the figure. That is, the spacing between the GM2 layer and the GM1 layer corresponding to the transistor T3 can be in the range of 1 to 5 μm, and the spacing between the GM2 layer and the GM1 layer corresponding to the transistor T1 can also be in the range of 1 to 5 μm.

[0176] The spacing d between the first metal region and the first gate metal line in the second direction satisfies 1μm≤d≤5μm, which can further reduce the coupling crosstalk between the data line and the source of the driving transistor.

[0177] For example, the spacing between the first metal region and the first gate metal line in the second direction can be 1.3μm, 1.5μm, 1.8μm, 2μm, 2.1μm, 2.4μm, 2.5μm, 2.7μm, 3μm, 3.4μm, 3.5μm, 3.7μm, 4μm, 4.4μm, 4.5μm, 4.9μm, etc.

[0178] It should be understood that the shortest distance between the first metal region and the gate regions of different transistors may be the same or different, and this application does not limit this. For example, the shortest distance between the first metal region and the gate region of transistor T1 and the shortest distance between the first metal region and transistor T3 may be the same or different.

[0179] In some embodiments, among the plurality of pixels of the display device, at least one pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel is used to control a blue light-emitting element, and the second sub-pixel is used to control a red light-emitting element or a green light-emitting element. The first sub-pixel includes a second driving transistor, the source region and the drain region of the second driving transistor being connected through a first silicon line. The second sub-pixel includes a third driving transistor, the source region and the drain region of the third driving transistor being connected through a second silicon line, the linewidth of the second silicon line being smaller than the linewidth of the first silicon line.

[0180] Figure 14 This is a partial top view schematic diagram of another display device provided in an embodiment of this application, wherein, Figure 14 (a) in the diagram can be a partial top-view structural diagram of the area corresponding to the blue sub-pixel in the display device. Figure 14 (b) in the diagram can be a partial top-view structural diagram of the area corresponding to the red sub-pixel in the display device, or it can be a partial top-view structural diagram of the area corresponding to the green sub-pixel. The connection relationship of the transistors in the red sub-pixel, green sub-pixel, and blue sub-pixel can be the same, that is, it can be the above. Figure 6 The pixel structure described.

[0181] Figure 14 The driving transistor Td shown in (a) can be called the second driving transistor. The portion of the first silicon line, which is the part of the P-Si layer corresponding to the second driving transistor, covers the portion below the gate metal of the second driving transistor, such as... Figure 14The structure shown in the circle (a) is the first silicon line. This first silicon line can also be referred to as the channel region of the second driving transistor, which connects the source region and the drain region. The linewidth of the first silicon line is W1 as shown in the figure.

[0182] Figure 14 The driving transistor Td shown in (b) can be called the third driving transistor. The portion of the first silicon line, which is the part of the P-Si layer corresponding to the third driving transistor, covers the portion below the gate metal of the third driving transistor, such as... Figure 14 The structure shown in circle (b) is the second silicon line. This second silicon line can also be referred to as the channel region of the third driving transistor. The linewidth of this second silicon line is W2 as shown in the diagram. Figure 14 As shown, W2 < W1.

[0183] It should be understood that the aforementioned second sub-pixel can be either a red sub-pixel or a green sub-pixel. The linewidth of the first silicon line connecting the driving transistor in the blue sub-pixel can be greater than the linewidth of the silicon line connecting the source and drain regions of the driving transistor in the red sub-pixel, or it can be greater than the linewidth of the silicon line connecting the source and drain regions of the driving transistor in the green sub-pixel. The linewidth of the silicon line connecting the source and drain regions of the driving transistor in the red sub-pixel can be the same as or different from the linewidth of the silicon line connecting the source and drain regions of the driving transistor in the green sub-pixel. The blue, red, and green sub-pixels can be sub-pixels of the first pixel, sub-pixels of the second pixel, or sub-pixels of other pixels besides the first and second pixels.

[0184] In a pixel, the material of the blue light-emitting element is usually a fluorescent light-emitting material, while the materials of the red and green light-emitting elements are usually phosphorescent light-emitting materials. When displaying a white screen, the blue light-emitting element requires a larger driving current. The charging efficiency of the blue light-emitting element is usually lower than that of the red and green light-emitting elements. The data voltage range of the blue sub-pixel is larger. The linewidth of the first silicon line corresponding to the driving transistor controlling the blue light-emitting element is larger than the linewidth of the second silicon line corresponding to the driving transistor controlling the red and green light-emitting elements. This can improve the signal conduction capability in the blue sub-pixel, making the data writing in the blue sub-pixel more complete and improving the charging efficiency of the blue light-emitting element.

[0185] In some embodiments, the linewidth W1 of the first silicon line can satisfy: 3μm≤W1≤5μm.

[0186] For example, the linewidth W1 of the first silicon line can be 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, 4μm, 4.1μm, 4.2μm, 4.3μm, 4.4μm, 4.5μm, 4.6μm, 4.7μm, 4.8μm, 4.9μm, etc.

[0187] The linewidth of the first silicon line satisfies 3μm≤W1≤5μm, which can further improve the charging efficiency of the blue light-emitting element.

[0188] In some embodiments, the linewidth difference ΔW between the first silicon line and the second silicon line satisfies: 0.3μm≤ΔW≤3μm.

[0189] For example, the linewidth difference ΔW between the first silicon line and the second silicon line can be 0.5μm, 0.7μm, 1μm, 1.2μm, 1.5μm, 1.7μm, 2μm, 2.3μm, 2.5μm, 2.8μm, 2.9μm, etc.

[0190] The linewidth difference ΔW between the first silicon line and the second silicon line satisfies: 0.3μm≤ΔW≤3μm, which can further improve the charging efficiency of the blue light-emitting element.

[0191] It should be understood that in the display device with the dual data line architecture, the linewidth of the first silicon line is greater than the linewidth of the second silicon line. In the display device with the single data line architecture, the linewidth of the first silicon line can also be greater than the linewidth of the second silicon line. The single data line architecture means that pixels located in the same column of the display device are all connected to the same data line.

[0192] In some embodiments, the second driving transistor includes a third silicon line, which can be the source region of the second driving transistor, and the linewidth of the third silicon line can be smaller than the linewidth of the first silicon line. The linewidth of the third silicon line is W3 as shown in the figure.

[0193] In some embodiments, the third driving transistor includes a fourth silicon line, which can be the source region of the third driving transistor, and the linewidth of the fourth silicon line can be smaller than the linewidth of the second silicon line. The linewidth of the third silicon line is W4 as shown in the figure.

[0194] The linewidth of the source region of the driving transistor is smaller than that of the channel region, which increases the electric field strength between the gate and the channel of the driving transistor, and helps to reduce the coupling effect of data voltage changes on the gate.

[0195] It should be understood that in the red, green, and blue sub-pixels, the linewidth of the source region of the driving transistor can be greater than the linewidth of the channel region. Alternatively, only in the blue sub-pixel can the linewidth of the source region of the driving transistor be greater than the linewidth of the channel region to save wiring space. The source linewidths of the driving transistors in the red, green, and blue sub-pixels can be the same or different, and the linewidths of the channel regions of the driving transistors can also be the same or different.

[0196] Figure 9 , Figure 10 , Figure 11 , Figure 13 as well as Figure 14 In the display device shown, the silicon line connecting the source and drain regions of the driving transistor Td is U-shaped, but the shape of this region can also be other shapes. For example, as Figure 15 As shown, the shape of this section of the silicon wire can also be Z-shaped. For example, as... Figure 16 As shown, the shape of this silicon line can also be a straight line. This application does not limit the shape of the silicon line for the driving transistor Td; the structure of the silicon line can be set according to other structures in the pixel, for example, the silicon line portions corresponding to adjacent transistors can be avoided. In multiple pixels of this display device, the connection relationship between transistors can be the same, while the specific structural shape and size can be the same or different.

[0197] It should be understood that Figures 9-11 as well as Figures 13-16 The top view shown is a partial top view of the display device. The P-Si layer, GM1 layer and GM2 layer shown are partial structures in the corresponding structural layers. They can form a continuous structure with other parts in the same structural layer. For example, interconnected transistors can be continuous in the P-Si layer. Only a part of the structure is shown in the figure.

[0198] This application also provides an electronic device 700, the structural schematic diagram of which is shown below. Figure 17 As shown, the electronic device 700 may include a display device as described above.

[0199] In some embodiments, the electronic device 700 may be a foldable electronic device 700, which may include a hinge mechanism 710. Exemplarily, the foldable electronic device 700 may be a foldable mobile phone, a foldable personal computer, or other similar devices. The foldable electronic device 700 may fold vertically or horizontally; this application does not limit the type of foldable electronic device 700. The display device may further include a first chip 720, which can be used to convert input digital signals into analog voltage signals suitable for use by the display device and output different grayscale voltages to multiple columns of pixels. The first chip 720 may be a data driver chip, a source driver chip, or a display driver chip.

[0200] The first chip 720 can be disposed on a first side of the display device, and the first side can be parallel to the pivot mechanism 710. There can be one or more first chips 720, and multiple first chips 720 can be arranged sequentially along the first side. Multiple data lines 730 can be fanned out by the first chip and connected to the pixel array; the aforementioned first data line 209 and second data line 210 can be included within the multiple data lines 730.

[0201] The first chip 720 is positioned parallel to the first side of the hinge mechanism 710, allowing it to avoid the folding area and reducing the structural space it occupies. When the first chip 720 is positioned perpendicular to the hinge mechanism 710, its position needs to avoid the hinge area, and the data line 730 fanned out by the first chip 720 needs to connect to pixels located in the folding area. Therefore, the data line 730 needs to be extended to connect with pixels in the hinge area, resulting in the extended portion of the data line 730 occupying a larger structural space and increasing the black border of the screen.

[0202] Furthermore, if the first chip 720 is disposed on the first side parallel to the hinge mechanism 710, only one flexible printed circuit (FPC) is needed to connect multiple first chips 720, which simplifies the manufacturing process of the display device. When the first chip 720 is disposed on the side perpendicular to the hinge mechanism 710, multiple first chips 720 are distributed on both sides of the hinge mechanism 710. Each first chip 720 located on both sides of the hinge mechanism 710 needs to be connected to an FPC, meaning two FPCs are required, making the manufacturing process of the display device more complex.

[0203] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display device, characterized in that, It includes multiple pixel columns and multiple data lines. Each pixel column consists of multiple pixels. The multiple pixel columns include a first pixel column. The multiple data lines include a first data line and a second data line. The first data line is used to input data voltage to the first pixel in the first pixel column, and the second data line is used to input data voltage to the second pixel in the first pixel column. The first pixel includes a first transistor and a first interconnect line. The first end of the first transistor is coupled to the first interconnect line through a first via, and the first interconnect line is coupled to the first data line through a second via. The projection of the first interconnect line along a first direction does not overlap with the second data line. The first direction is perpendicular to the light-emitting surface of the display device. The second pixel includes a second transistor and a second interconnect. The first end of the second transistor is coupled to the second interconnect through a third via, and the second interconnect is coupled to the second data line through a fourth via. The projection of the second interconnect along the first direction does not overlap with the first data line.

2. The display device according to claim 1, characterized in that, The first data line and the second data line are located in different regions of the first metal layer, the first end of the first transistor and the first end of the second transistor are located in different regions of the first conductive layer, the first interconnect line and the second interconnect line are located in different regions of the second metal layer, and the second metal layer is located between the first conductive layer and the first metal layer along the first direction.

3. The display device according to claim 2, characterized in that, The first conductive layer includes a first lead and a second lead, wherein the first lead forms a first terminal of the first transistor and the second lead forms a first terminal of the second transistor; In the projection along the first direction, the end of the first lead near the second data line is located between the first data line and the second data line, and the end of the second lead near the first data line is located between the first data line and the second data line.

4. The display device according to claim 3, characterized in that, The line width of the first lead is the same as that of the second lead.

5. The display device according to claim 3 or 4, characterized in that, The first lead has a first area, which is the overlapping area of ​​the projection of the first lead along the first direction and the first data line. The second lead has a second area, which is the overlapping area of ​​the projection of the second lead along the first direction and the first data line. The first area and the second area are the same size.

6. The display device according to any one of claims 3 to 5, characterized in that, The distance between the end of the first interconnect closest to the second data line and the second data line is less than or equal to the distance between the end of the second interconnect closest to the first data line and the first data line.

7. The display device according to any one of claims 2 to 6, characterized in that, The plurality of pixels includes a first driving transistor, which is used to control the driving current of the light-emitting element in the pixel. The display device further includes a first metal region disposed above the first driving transistor and insulated from the first driving transistor. The projection of the first metal region along the first direction covers at least a portion of a first region of the first driving transistor. The first region is one of the source and drain regions of the first driving transistor that is closer to the first data line and the second data line.

8. The display device according to claim 7, characterized in that, The display device further includes a first gate metal line, which is the gate region of a transistor connected to the first driving transistor. The projection of the first gate metal line along the first direction does not overlap with the first metal region, and the minimum distance d between the first metal region and the first gate metal line in the second direction satisfies: 1μm≤d≤5μm. The second direction is parallel to the light-emitting surface of the display device.

9. The display device according to claim 7 or 8, characterized in that, The voltage of the first metal region is configured as the power supply voltage of the display device.

10. The display device according to any one of claims 1 to 9, characterized in that, The first data line and the second data line extend along the pixel column direction, and the first data line wraps around the second data line away from the via location, and / or, The second data line, at the location where it passes through the via, winds away from the first data line. The via location includes the location corresponding to at least one of the following vias: the first via, the second via, the third via, and the fourth via.

11. The display device according to claim 10, characterized in that, The first data line includes a first main body portion and a first extension portion. The first extension portion is disposed on the side of the first main body portion near the second data line. The first interconnect line is coupled to the first extension portion through the second via. The second data line includes a second main body portion and a second extension portion. The second extension portion is disposed on the side of the second main body portion near the first data line. The second interconnect line is coupled to the second extension portion through the fourth via. The distance between the first main body portion and the second main body portion at a first position is d1, the first position corresponding to the via position, and the distance between the first main body portion and the second main body portion at a second position is d2, the second position being any other position besides the first position, where d2≤d1≤2d2.

12. The display device according to any one of claims 1 to 11, characterized in that, At least one of the plurality of pixels includes a first sub-pixel and a second sub-pixel, wherein the first sub-pixel is used to control a blue light-emitting element, and the second sub-pixel is used to control a red light-emitting element or a green light-emitting element; The first sub-pixel includes a second driving transistor, which is used to control the driving current of the light-emitting element in the first sub-pixel. The source region and drain region of the second driving transistor are connected by a first silicon line. The second sub-pixel includes a third driving transistor, which is used to control the driving current of the light-emitting element in the second sub-pixel. The source region and drain region of the third driving transistor are connected by a second silicon line. The linewidth of the first silicon line is greater than the linewidth of the second silicon line.

13. The display device according to claim 12, characterized in that, The linewidth W1 of the first silicon line satisfies: 3μm≤W1≤5μm.

14. The display device according to claim 12 or 13, characterized in that, The linewidth difference ΔW between the first silicon line and the second silicon line satisfies: 0.3μm≤ΔW≤3μm.

15. The display device according to any one of claims 1 to 14, characterized in that, The first interconnect line extends in the opposite direction to the second interconnect line.

16. The display device according to any one of claims 1 to 15, characterized in that, The projection of the first via along the first direction is located between the first data line and the second data line; The projection of the third via along the first direction is located between the first data line and the second data line.

17. An electronic device, characterized in that, The display device includes any one of claims 1 to 16.

18. The electronic device according to claim 17, characterized in that, The electronic device is a foldable electronic device, and the electronic device includes a pivot mechanism; The display device includes a first chip, which is disposed on a first side of the electronic device, and the first side is parallel to the rotating shaft mechanism.

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