Display device

Abstract

A display device according to an embodiment of the present application includes: a substrate including a display area, a camera hole, and a non-display area; a light emitting element disposed in the display area; a gate driver disposed in the non-display area; and an initialization signal line disposed in the display area, in which the display area includes a left display area, a right display area, and an array pixel area with respect to the camera hole, and the initialization signal line is disposed in each of the left display area and the right display area.

Description

[0001] This application is a divisional application. The original application was filed with the China Patent Office on December 23, 2022, with application number 202211665101.1 and the invention title "Display Device". Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0192141, filed on December 30, 2021, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device, and more particularly, to a display device in which a camera hole is provided. Background Technology

[0004] Recently, with the advent of the information age, displays that visually express electrical information signals have developed rapidly. In response to this trend, various display devices with excellent performance characteristics, such as thin profiles, light weight, and low power consumption, have been developed.

[0005] Specific examples of such display devices include liquid crystal display (LCD) devices, organic light-emitting diode (OLED) display devices, and quantum dot display devices.

[0006] Display devices may include a display panel and multiple components for providing various functions. For example, in existing display devices, cameras and various optical sensors are positioned on the periphery of the display panel to perform various functions such as photography, facial recognition, and infrared distance measurement. However, through successive generations, so-called bezel-less or borderless designs (where the screen is completely filled with the display area when a user views the display device) have become more common, making it difficult to arrange such cameras and optical sensors. To achieve such bezel-less or borderless designs, methods for moving cameras and optical sensors within the display area of ​​the display panel have been investigated. As a result of this research, a technique called hole-in display (HID) has been developed, in which holes can be formed in the display panel to house cameras and optical sensors within these holes.

[0007] Although HID has been described above to indicate that the hole exists in the display area, hole-in active area (HiAA) can also be used to indicate that the hole exists inside the active area.

[0008] When developing HID or HiAA and moving all cameras and sensors that were previously placed in the bezel area to the interior of the active area of ​​the display panel, extreme bezel-less or borderless designs can be applied.

[0009] The display area and the active area can be used synonymously to describe the area that drives the pixels to emit light. Summary of the Invention

[0010] This specification aims to address the aforementioned problems that may arise when designing Hidden-In Display (HID) or Hi-Aperture-On Display (HiAA) structures. Holes housing cameras or optical sensors can be formed in the display area or active area. In this case, components required for the display, such as light-emitting elements or driving transistors, can be omitted from the hole area, and even the substrate of the display panel can be removed. Therefore, since wiring and the like cannot be placed in the hole area, the gate signal lines between the display areas on the left and right sides of the hole area can be designed to bypass the hole area. Due to this design, a difference in RC load exists between the left and right display areas relative to the hole area, and consequently, a degradation in the quality of the display device has been recognized.

[0011] In particular, a slight reddish brightness phenomenon exists in the right display area of ​​the hole area on a black screen. Therefore, the inventors of this disclosure have developed a display device with a novel structure to solve the problem caused by the RC load difference that may occur in display devices with hole areas.

[0012] Specifically, one aspect of this disclosure is to provide a display device that can compensate for the RC load difference in the display area caused by the formation of the HiAA structure by arranging a line structure for compensating for the RC load around the hole area formed by the formation of the HiAA structure.

[0013] Another aspect of this disclosure is to provide a display device that can compensate for the RC load difference between the left and right display areas of the hole region and between the upper and lower display areas of the hole region based on the formation of the HiAA structure.

[0014] The key point of this disclosure is that, in order to design borderless or bezel-less display panels, which represent a trend in the development of display devices, holes are formed for arranging cameras and sensors in the display area, and products that also prevent defects caused by the holes are produced.

[0015] In one aspect, embodiments of the present disclosure may provide a display device including a substrate, a light-emitting element disposed in a display area, a gate driver disposed in a non-display area, and an initialization signal line disposed in the display area, the substrate including a display area, a camera hole, and a non-display area.

[0016] The display area may include a left display area, a right display area, and an array pixel area relative to the camera aperture, and an initialization signal line may be set in each of the left and right display areas.

[0017] In another aspect, embodiments of the present disclosure may provide a display device including a substrate, a light-emitting element disposed in a display area, a gate driver disposed in a non-display area, and an initialization signal line disposed in the display area, wherein the substrate includes a display area, a camera hole, and a non-display area.

[0018] The display area may include a left display area, a right display area, and an array pixel area relative to the camera aperture, and the initialization signal lines may include low-resistance initialization signal lines and high-resistance initialization signal lines.

[0019] Further details of the embodiments are included in the detailed description and the accompanying drawings.

[0020] In the display device according to the embodiments of this specification, a line structure for compensating for RC load is provided in each of the left and right display areas of the hole area according to the HiAA structure, so as to reduce the RC load difference between the left and right display areas and thus prevent quality degradation.

[0021] According to this disclosure, a line structure based on the HiAA structure is provided to compensate for the RC load difference between the left and right display areas of the hole area and between the upper and lower display areas of the hole area, thereby reducing the RC load difference between the surrounding display areas caused by the hole area and preventing a decline in the overall quality of the display device.

[0022] Therefore, users of the display device can aesthetically enjoy a device in which the front surface of the display device is completely filled with a light-emitting screen, and by using a compact module that is functionally applied to a narrow bezel, it can provide users with a better grip and a lighter feel.

[0023] The effects of this specification are not limited to those described above, and other effects not described above will be apparent to those skilled in the art from the following description.

[0024] The objectives to be achieved by the present invention, the modules for achieving those objectives, and the effects of the present invention described above do not specify the essential features of the claims, and therefore the scope of the claims is not limited to the disclosure of the present invention. Attached Figure Description

[0025] The above and other aspects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein: Figure 1This is a plan view showing the front surface of a display panel according to an embodiment of this specification; Figure 2 yes Figure 1 An enlarged plan view of region A, which shows the display area; Figure 3 It is along Figure 2 A cross-sectional view of line I-I', which shows the sub-pixels; Figure 4 yes Figure 1 An enlarged plan view of region B, which shows the wiring around the hole region according to an embodiment of this specification; Figure 5 This is a plan view showing the brightness anomaly that may occur in a comparative example of the present disclosure due to resistor-capacitor (RC) load deviation; Figure 6 This is a circuit diagram illustrating pixels of an organic light-emitting display device according to an embodiment of the present disclosure; Figure 7 It is used to identify in Figure 6 The timing diagram of the cause of the increased brightness due to the third scan signal line (182) and the initialization voltage line (181) in the circuit diagram; Figure 8A and Figure 8B This is a plan view illustrating a planar line structure according to an embodiment of the present disclosure; Figure 9 This is a cross-sectional view showing a contact hole (CNT) according to an embodiment of the present disclosure; and Figure 10A and Figure 10B It is a graph showing the numerical values ​​related to the RC load deviation for each region. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as methods for implementing it, will become clearer from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various different forms. These embodiments are provided merely to complete this disclosure and to fully provide the scope of this disclosure to those skilled in the art to which this disclosure pertains, and this disclosure is defined by the appended claims.

[0027] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. The same reference numerals always denote the same elements. In describing this disclosure, detailed descriptions of related known functions or configurations will be omitted where it would unnecessarily obscure the focus of this disclosure. Where the terms "comprising," "having," and "including" are used in this specification, an additional part may be added unless "only" is used. Any reference to the singular may include the plural unless explicitly stated otherwise.

[0028] When interpreting a component, even if it is not explicitly described, the component is interpreted as including a tolerance range.

[0029] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", or "adjacent", one or more other parts can be described as "immediately" or "directly".

[0030] When describing temporal relationships, such as when describing chronological order as “after,” “following,” “next,” or “before,” discontinuous cases may be included unless “immediately” or “right away” is used.

[0031] It should be understood that although terms such as "first" and "second" may be used herein to describe various components, these components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, without departing from the scope and spirit of this disclosure, the first component described below may be referred to as the second component.

[0032] In describing the components of this specification, terms such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used. These terms are used only for the purpose of distinguishing one component from another, and the nature, sequence, order, or number of the corresponding elements shall not be limited by these terms. When a component is described as “connected,” “coupled,” or “linked” to another component, it may mean not only that the components are directly “connected,” “coupled,” or “linked,” but also that they are indirectly “connected,” “coupled,” or “linked” through yet another component.

[0033] In this specification, "display device" can include display devices in the narrow sense (such as liquid crystal module (LCM), organic light-emitting diode (OLED) module, or quantum dot (QD) module), which includes a display panel and a driver for driving the display panel. Display devices can include assemblies of electronic equipment or assemblies (or assemblies of devices), such as laptop computers, televisions, computer monitors, equipment including automotive devices or other types of devices for vehicles, or mobile electronic devices such as smartphones or electronic boards, which are complete products (or final products) including LCMs, OLED modules, QD modules, etc.

[0034] Therefore, in this specification, a display device may include the display device itself in the narrow sense (such as an LCM, OLED module, or QD module), as well as a complete set of equipment as an application product or end consumer device including an LCM, OLED module, QD module, etc.

[0035] In some cases, an LCM, OLED, or QD module, including a display panel, driver, etc., can be referred to as a "narrowly defined display device," and an electronic device that is a final product including an LCM, OLED, or QD module can be referred to as an "equipment assembly." For example, a narrowly defined display device may include a display panel (such as a liquid crystal display (LCD), OLED, or QD display panel) and a source printed circuit board (PCB) that serves as a controller for driving the display panel. An equipment assembly may also include an assembly PCB, which is an assembly controller electrically connected to the source PCB to control the entire equipment assembly.

[0036] As the display panel used in this embodiment, any type of display panel can be used, such as an LCD panel, an OLED display panel, or a QD display panel. However, this disclosure is not limited to a specific display panel that is flexible by including a flexible substrate for an OLED display panel and a back support structure underneath it. The shape or size of the display panel used in the display device according to the embodiments of this specification is not limited.

[0037] More specifically, when the display panel is an OLED display panel, the display panel may include multiple gate lines, multiple data lines, and pixels formed in the intersection areas of the gate lines and data lines. The display panel may include an array, an OLED layer on the array, and an encapsulation substrate or encapsulation layer disposed on the array to cover the OLED layer. The array includes thin-film transistors (TFTs), which are elements for selectively applying voltage to each pixel. The encapsulation layer can protect the TFTs and OLED layer from external impacts and can prevent moisture or oxygen from penetrating into the OLED layer. The layers formed on the array may include inorganic light-emitting layers, such as nanoscale material layers, QD (Quick Difference) layers, etc.

[0038] In this instruction manual, Figure 1 An exemplary OLED display panel 100 is shown that can be integrated with components inside a display device.

[0039] Figure 1 This is a plan view showing a display panel 100 according to an embodiment of this specification. In this specification, Figure 1 An exemplary OLED display panel 100 is shown that can be integrated with components inside a display device. (Reference) Figure 1 In the OLED display panel 100, multiple camera holes HA1 and HA2 are formed within the display area, thereby reducing the bezel area that is a non-display area and maximizing the display area. A product designed to maximize the display area may be aesthetically preferred because it maximizes the user's level of immersion.

[0040] In multiple camera holes HA1 and HA2, such as Figure 1 As shown, the first camera hole HA1 and the second camera hole HA2 can be located in the upper center of the display area, but this disclosure is not limited thereto. The first camera hole HA1 and the second camera hole HA2 can be located in various positions.

[0041] Figure 2 Is as Figure 1 An enlarged view of region A, a portion of the display area of ​​the display panel 100, is shown, and the planar shape of the sub-pixels disposed in the display area is also shown.

[0042] exist Figure 2 In the display panel 100, multiple anodes 151 can be disposed in the display area, and a dam 154 can fill the area between the anodes 151. The dam 154 can be configured to cover the edges of the anodes 151 and can be used to define the emission area of ​​a sub-pixel by allowing only the central area of ​​the anodes 151 to contact the organic light-emitting stack. Spacers 155 can be disposed in a portion of the area in which the dams 154 are disposed. The spacers 155 can be configured to have a constant density throughout the display panel 100. The spacers 155 can be used to support a mask such that when a deposition process is performed to form the organic light-emitting stack, the mask used for deposition, which covers or opens the organic layer of each sub-pixel, does not directly contact the display panel 100. Although Figure 2 An example of a planar structure of type PenTile in which subpixels are arranged in a point shape is shown, but this disclosure is not limited thereto, and a real type planar structure may also be used.

[0043] Figure 3 It shows along Figure 2 The cross-sectional structure of line I-I' shows the sub-pixels.

[0044] refer to Figure 3A substrate 101, multiple buffer layers 102, and a lower buffer layer 103 may be provided, and a first transistor 120 may be disposed on the lower buffer layer 103. A lower gate insulating film 104 may be disposed on the first semiconductor layer 123 constituting the first transistor 120, so that the first semiconductor layer 123 is insulated from the first gate electrode 122. A first lower interlayer insulating film 105 and a second lower interlayer insulating film 106 may be sequentially disposed on the first gate electrode 122, and an upper buffer layer 107 may be disposed thereon.

[0045] The multiple buffer layers 102 can delay the diffusion of moisture or oxygen that has penetrated into the substrate 101, and can be achieved by at least one alternating stacking of silicon nitride (SiN). x ) and silicon dioxide (SiO) x It is formed by )

[0046] The lower buffer layer 103 protects the first semiconductor layer 123 and functions to block various types of defects introduced from the substrate. The lower buffer layer 103 can be made of a-Si, silicon nitride (SiN), etc. x ), silicon dioxide (SiO) x Made from (etc.)

[0047] The first semiconductor layer 123 of the first transistor 120 can be formed as a polycrystalline semiconductor layer and can include a channel region, a source region and a drain region.

[0048] Polycrystalline semiconductor layers can exhibit higher mobility than amorphous and oxide semiconductor layers, thus enabling lower power consumption and superior reliability. Due to these advantages, polycrystalline semiconductor layers can be used to drive transistors.

[0049] The first gate electrode 122 can be disposed on the lower gate insulating film 104 and can be configured to overlap with the first semiconductor layer 123.

[0050] The second transistor 130 can be disposed on the upper buffer layer 107, and the light-blocking layer 136 can be disposed below the region corresponding to the second transistor 130. (See reference) Figure 3The light-blocking layer 136 can be disposed on the first lower interlayer insulating film 105 in the region corresponding to the second transistor 130, and the second semiconductor layer 133 of the second transistor 130 can be disposed on the second lower interlayer insulating film 106 and the upper buffer layer 107 to overlap with the light-blocking layer 136. The upper gate insulating film 137 can be disposed on the second semiconductor layer 133 to insulate the second gate electrode 132 from the second semiconductor layer 133, and then the upper interlayer insulating film 108 can be disposed on the second gate electrode 132. The first gate electrode 122 and the second gate electrode 132 can be formed as a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but the present disclosure is not limited thereto.

[0051] The first lower interlayer insulating film 105 and the second lower interlayer insulating film 106 can be formed as inorganic films with a higher hydrogen particle content compared to the upper interlayer insulating film 108. For example, the first lower interlayer insulating film 105 and the second lower interlayer insulating film 106 are made of silicon nitride (SiN) formed by a deposition process using NH3 gas. x The upper interlayer insulating film 108 can be made of silicon oxide (SiO2). x The first transistor 120 is made of an oxide semiconductor. Hydrogen particles contained in the first lower interlayer insulating film 105 and the second lower interlayer insulating film 106 can diffuse into the polycrystalline semiconductor layer during the hydrogenation process to fill the pores in the polycrystalline semiconductor layer with hydrogen. Therefore, the polycrystalline semiconductor layer can be stabilized, thereby preventing degradation of the characteristics of the first transistor 120. After the activation and hydrogenation process of the first semiconductor layer 123 of the first transistor 120, the second semiconductor layer 133 of the second transistor 130 can be formed, and in this case, the second semiconductor layer 133 can be made of an oxide semiconductor. Since the second semiconductor layer 133 is not exposed to the high-temperature atmosphere of the activation and hydrogenation process of the first semiconductor layer 123, damage to the second semiconductor layer 133 can be prevented, thereby improving reliability. After the upper interlayer insulating film 108 is formed, a first source contact hole 125S and a first drain contact hole 125D can be formed to correspond to the source region and drain region of the first transistor, and a second source contact hole 135S and a second drain contact hole 135D can be formed to correspond to the source region and drain region of the second transistor 130, respectively. (Reference) Figure 3The first source contact 125S and the first drain contact 125D can be continuously formed from the upper interlayer insulating film 108 to the lower gate insulating film 104, and the second source contact 135S and the second drain contact 135D can also be formed in the second transistor 130. The first source electrode 121 and the first drain electrode 124 corresponding to the first transistor 120 and the second source electrode 131 and the second drain electrode 134 corresponding to the second transistor 130 can be formed simultaneously, thereby reducing the number of processes required to form the source and drain electrodes of each of the first transistor 120 and the second transistor 130.

[0052] The first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134, can be formed as a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but this disclosure is not limited thereto. The first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134, can have a three-layer structure. For example, the first source electrode 121 may include a first layer 121a, a second layer 121b, and a third layer 121c, and the other source electrodes and drain electrodes may have the same structure as the first source electrode 121.

[0053] The storage capacitor 140 can be disposed between the first transistor 120 and the second transistor 130. For example... Figure 3 As shown, the storage capacitor 140 can be formed by overlapping the storage lower electrode 141 and the storage upper electrode 142 with the first lower interlayer insulating film 105 inserted therebetween.

[0054] The storage lower electrode 141 can be located on the lower gate insulating film 104, formed coplanar with the first gate electrode 122, and made of the same material as the first gate electrode 122. The storage upper electrode 142 can be electrically connected to the pixel circuit via the storage supply line 143. The storage upper electrode 142 can be formed coplanar with the light blocking layer 136 and made of the same material as the light blocking layer 136. The storage upper electrode 142 is exposed through a storage contact hole 144 passing through the second lower interlayer insulating film 106, the upper buffer layer 107, the upper gate insulating film 137, and the upper interlayer insulating film 108, and is connected to the storage supply line 143. Meanwhile, although... Figure 3As shown, the storage upper electrode 142 is spaced apart from the photoblocking layer 136, but the storage upper electrode 142 can be connected to the photoblocking layer 136 to be integrally formed with it. The storage supply line 143 can be formed to be coplanar with the first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134, and is made of the same material as the first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134. Therefore, the storage supply line 143 can be formed simultaneously with the first source electrode 121 and the first drain electrode 124, as well as the second source electrode 131 and the second drain electrode 134, using the same masking process.

[0055] This can be achieved by depositing materials such as SiN on the entire surface of the substrate 101. x or SiO x An inorganic insulating material is used to form a protective film 109, and a first source electrode 121 and a first drain electrode 124, a second source electrode 131 and a second drain electrode 134, and a storage supply line 143 are formed on the entire surface of the substrate 101. A first planarization layer 110 can be formed on the substrate 101 on which the protective film 109 is formed. Specifically, the first planarization layer 110 can be formed by applying an organic insulating material, such as acrylic resin, to the entire surface of the substrate 101 on which the protective film 109 is formed.

[0056] After the protective film 109 and the first planarization layer 110 are formed, a contact hole exposing the first source electrode 121 or the first drain electrode 124 of the first transistor 120 can be formed by photolithography. A connection electrode 145 made of a material including Mo, Ti, Cu, AlNd, Al, Cr, or alloys thereof can be disposed in the area of ​​the contact hole exposing the first drain electrode 124.

[0057] The second planarization layer 111 can be disposed on the connection electrode 145, and contact holes exposing the connection electrode 145 can be formed in the planarization layer 111 to arrange the light-emitting element 150 connected to the first transistor 120.

[0058] The light-emitting element 150 may include an anode 151 connected to a first drain electrode 124 of a first transistor 120, at least one organic light-emitting stack 152 formed on the anode 151, and a cathode 153 formed on the organic light-emitting stack 152.

[0059] The organic light-emitting stack 152 may include a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer, and in a series structure where multiple emission layers overlap each other, a charge generation layer may be additionally disposed between the emission layers. In some cases, the emission layer may emit light of a different color for each sub-pixel. For example, a red emission layer, a green emission layer, and a blue emission layer may be formed separately for each sub-pixel. However, a common emission layer may be formed to emit white light without color differentiation for each pixel, and color filters for color differentiation may be provided separately. Differentiation may be categorized as red-green-blue (RGB) type (true RGB type) and white OLED (WOLED). Each emission layer may be formed separately, but the injection layer or transport layer may be provided as a common layer and may be equally disposed for each sub-pixel.

[0060] The anode 151 can be connected to a connection electrode 145 exposed through a contact hole passing through the second planarization layer 111. The anode 151 can be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film is made of a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), while the opaque conductive film has a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof. For example, the anode 151 can be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are stacked sequentially, or as a structure in which a transparent conductive film and an opaque conductive film are stacked sequentially. The anode 151 can be disposed in the emission region provided by the embankment 154 and on the second planarization layer 111 to overlap with the pixel circuit region in which the first transistor 120 and the second transistor 130 and the storage capacitor 140 are disposed, thereby increasing the area for emitting light.

[0061] The organic light-emitting stack 152 can be formed by stacking a hole transport layer, an organic emission layer, and an electron transport layer on the anode 151 in this order or the reverse order. In addition, the organic light-emitting stack 152 may also include a charge generation layer, and may include a first light-emitting stack and a second light-emitting stack facing each other with the charge generation layer inserted therebetween.

[0062] The dam 154 may be formed to expose the anode 151. The dam 154 may be made of an organic material such as photoacrylic acid and may include a translucent material, but this disclosure is not limited thereto. The dam 154 may be made of an opaque material to prevent light interference between subpixels.

[0063] The cathode 153 can be formed on the upper surface of the organic light-emitting stack 152, facing the anode 151, wherein the organic light-emitting stack 152 is inserted between the cathode 153 and the anode 151. When the cathode 153 is applied to a top-emitting organic light-emitting display device, the cathode 153 can be formed by using ITO, IZO or magnesium-silver (Mg-Ag) to form a thin transparent conductive film.

[0064] An encapsulation layer 170 for protecting the light-emitting element 150 can be formed on the cathode 153. Because of the properties of the organic material in the organic light-emitting stack 152, the light-emitting element 150 may react with external moisture or oxygen, potentially causing dark spots or pixel shrinkage. To prevent dark spots or pixel shrinkage, the encapsulation layer 170 can be disposed on the cathode 153. The encapsulation layer 170 may include a first inorganic insulating film 171, a foreign matter compensation layer 172, and a second inorganic insulating film 173.

[0065] Figure 4 yes Figure 1 An enlarged plan view of region B, showing the wiring around the hole region according to an embodiment of this specification. (See reference...) Figure 4 A gate controller 180 (gate in panel (GIP)) for controlling the light-emitting element 150 can be disposed on the left and right sides of the display area. An initialization voltage line 181 (Vini) and a third scan signal line 182 (SC3(n)) can extend from the gate controller 180 to be disposed in the left and right display areas of the first camera hole HA1 and the second camera hole HA2, and can pass through the first camera hole HA1 and the second camera hole HA2. Specifically, in the example describing the initialization voltage line 181, the initialization voltage line 181, starting from the gate controller 180 disposed in the left non-display area, can pass through the left display area HL, and through the first camera hole HA1 and the second camera hole HA2 to pass through the right display area HR. In this case, a line made of a material different from existing metals can be bridged near the first camera hole HA1 and the second camera hole HA2. In the first camera aperture HA1 and the second camera aperture HA2, the data lines and high-potential power lines required to drive the light-emitting element 150 should also avoid passing through the camera aperture area from top to bottom. Typically, the data lines and high-potential power lines are set as low-resistance lines and overlap with the lines used as the initialization voltage line 181. Therefore, a bridging structure is necessary for this.

[0066] Figure 5 This is a plan view illustrating the brightness anomalies that may occur in a comparative example of this disclosure due to resistor-capacitor (RC) load deviation. Reference Figure 5 The display area can be divided into a left display area HL, a right display area HR, and an array pixel area AP relative to the first camera hole HA1 and the second camera hole HA2.

[0067] For example, the left display area HL can be the display area located to the left of the first camera hole HA1 and the second camera hole HA2, the right display area HR can be the display area located to the right of the first camera hole HA1 and the second camera hole HA2, and the array pixel area AP can be the display area excluding the left display area HL and the right display area HR.

[0068] First, for the initialization voltage line 181, in order to compare the brightness of the left display area HL with the brightness of the right display area HR, the RC load of the right display area HR can be greater than the RC load of the left display area HL. Therefore, ripple can occur in the initialization voltage line 181 of the right display area HR, thereby increasing the brightness of the right display area HR.

[0069] Furthermore, for the initialization voltage line 181, in order to compare the brightness of the right display area HR with the brightness of the array pixel area AP, the RC load of the right display area HR can be greater than the RC load of the array pixel area AP. Therefore, ripple can occur in the initialization voltage line 181 of the right display area HR, so that the brightness of the right display area HR can be increased compared with that of the array pixel area AP.

[0070] The following will refer to Figure 6 and Figure 7 To provide a more detailed description.

[0071] Figure 6 This is a circuit diagram illustrating pixels of an organic light-emitting display device according to an embodiment of the present disclosure. Each pixel P includes an OLED, a driving transistor T1, second to seventh transistors T2 to T7, and a storage capacitor Cstg.

[0072] The OLED emits light using a drive current supplied from the driving transistor T1. Multiple organic compound layers are formed between the anode and cathode of the OLED. These organic compound layers may include at least one hole transfer layer and at least one electron transfer layer, as well as an emitter layer EML. Here, the hole transfer layer can be a layer that injects or transfers holes into the emitter layer. For example, the hole transfer layer may include a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, etc. The electron transfer layer can be a layer that injects or transfers electrons into the emitter layer. For example, the electron transfer layer may include an electron transport layer ETL, an electron injection layer EIL, a hole blocking layer HBL, etc. The anode of the OLED is connected to a fourth node N4, and the cathode of the OLED is connected to the input terminal of a low-potential drive voltage source VSSEL.

[0073] The driving transistor T1 controls the driving current applied to the OLED based on the source-gate voltage Vsg. The driving transistor T1 can be a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) (p-channel metal-oxide-semiconductor (PMOS) transistor) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The source electrode of the driving transistor T1 is connected to the first node N1, its gate electrode is connected to the second node N2, and its drain electrode is connected to the third node N3. The driving transistor T1 can be referred to as the first transistor.

[0074] The second transistor T2 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor T1. The second transistor T2 can be a p-type MOSFET (PMOS transistor) or an LTPS thin-film transistor. The second transistor T2 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to the second scan signal line used to transmit the second scan signal SC2(n).

[0075] Therefore, in response to the second scan signal SC2(n) which is at a low level as the on level, the second transistor T2 applies the data voltage Vdata provided from the data line to the first node N1, which is the source electrode of the driving transistor T1.

[0076] The third transistor T3 is connected to the gate and drain electrodes of the driving transistor T1 via a diode. The third transistor T3 can be an n-type MOSFET (n-channel metal-oxide-semiconductor (NMOS) transistor) or an oxide thin-film transistor to minimize leakage current. The third transistor T3 includes a drain electrode connected to the third node N3, a source electrode connected to the second node N2, and a gate electrode connected to the first scan signal line for transmitting the first scan signal SC1(n). Therefore, in response to the first scan signal SC1(n) being at a high level (on-state), the third transistor T3 is connected to the gate and drain electrodes of the driving transistor T1 via a diode.

[0077] The fourth transistor T4 connects the initialization voltage line 181 to the third node N3, which serves as the drain electrode of the driving transistor T1. The fourth transistor T4 can be a p-type MOSFET (PMOS transistor) or an LTPS thin-film transistor. The fourth transistor T4 includes a source electrode connected to the initialization voltage line 181 for transmitting the initialization voltage, a drain electrode connected to the third node N3, and a gate electrode connected to the third scan signal line for transmitting the third scan signal SC3(n). Therefore, in response to the third scan signal SC3(n) being at a low level (on-state), the fourth transistor T4 connects the initialization voltage line 181 to the third node N3, which serves as the drain electrode of the driving transistor T1.

[0078] The fifth transistor T5 applies a high-potential drive voltage VDDEL to the first node N1, which serves as the source electrode of the driving transistor T1. The fifth transistor T5 can be a p-type MOSFET (PMOS transistor) or an LTPS thin-film transistor. The fifth transistor T5 includes a source electrode connected to a high-potential drive voltage line for transmitting the high-potential drive voltage VDDEL, a drain electrode connected to the first node N1, and a gate electrode connected to a transmit signal line for transmitting the transmit signal EM(n). Therefore, in response to the transmit signal EM(n) being at a low level (on-state), the fifth transistor T5 applies the high-potential drive voltage VDDEL to the first node N1, which serves as the source electrode of the driving transistor T1.

[0079] A sixth transistor T6 forms a current path between the driving transistor T1 and the OLED. The sixth transistor T6 can be a p-type MOSFET (PMOS transistor) or an LTPS thin-film transistor. The sixth transistor T6 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to the emitter signal line for transmitting the emitter signal EM(n). In response to the emitter signal EM(n), the sixth transistor T6 forms a current path between the third node N3 (which is the source electrode of the sixth transistor T6) and the fourth node N4 (which is the drain electrode of the sixth transistor T6). Therefore, in response to the emitter signal EM(n) being at a low level (on-state), the sixth transistor T6 forms a current path between the driving transistor T1 and the OLED.

[0080] The seventh transistor T7 applies the reset voltage VAR to the fourth node N4, which serves as the anode of the OLED. The seventh transistor T7 can be a p-type MOSFET (PMOS transistor) or an LTPS thin-film transistor. The seventh transistor T7 includes a source electrode connected to a reset voltage line for transmitting the reset voltage VAR, a drain electrode connected to the fourth node N4, and a gate electrode connected to a second scan signal line for transmitting the second scan signal SC2(n). Therefore, in response to the second scan signal SC2(n) being at a low level (on-state), the seventh transistor T7 applies the reset voltage VAR to the fourth node N4, which serves as the anode of the OLED.

[0081] The storage capacitor Cstg holds the data voltage Vdata stored in each pixel during one frame. The storage capacitor Cstg includes a first electrode connected to the second node N2 and a second electrode connected to the high-potential drive voltage line used to transmit the high-potential drive voltage VDDEL. That is, one electrode of the storage capacitor Cstg is connected to the gate electrode of the driving transistor T1, and the other electrode of the storage capacitor Cstg is connected to the high-potential drive voltage line used to transmit the high-potential drive voltage VDDEL.

[0082] Figure 7 It is used to identify in Figure 6 The timing diagram in the circuit diagram shows the reason for the increase in brightness caused by the third scan signal line 182 and the initialization voltage line 181. (Reference) Figure 7 When the third scan signal line 182 is turned on, the RC load of the initialization voltage line 181 increases due to coupling, and ripple occurs accordingly. Ripple can occur when a particular line is affected by coupling with an adjacent line, and in particular, the output voltage of the particular line fluctuates like a wave depending on whether the adjacent line is turned on or off.

[0083] Due to the ripple phenomenon of the initialization voltage line 181, applied to Figure 6 The voltages at the first node N1 and the third node N3 in the circuit diagram increase. This causes an increase in the source-gate voltage Vsg of the first transistor T1, which is used as the driving transistor, resulting in an increase in emission brightness.

[0084] refer to Figure 5 and Figure 7 The RC load of the initial voltage line 181 of the right display area HR can be greater than the RC load of the initial voltage line 181 of the left display area HL. Therefore, ripple occurs in the right display area HR, and ultimately, the emission brightness of the right display area HR increases due to the increase in the voltage of the first node N1 and the third node N3 in the circuit applied to the right display area HR and the increase in the source-gate voltage Vsg of the first transistor T1, which is the driving transistor.

[0085] Furthermore, even when comparing the right display area HR with the array pixel area AP, the RC load of the initialization voltage line 181 may be larger in the right display area HR, thus causing ripple in the right display area HR. Similarly, due to the increase in the voltages of the first node N1 and the third node N3 in the circuit applied to the right display area HR, and the increase in the source-gate voltage Vsg of the first transistor T1, which serves as the driving transistor, the emission brightness of the right display area HR is ultimately higher than that of the array pixel area AP.

[0086] Figure 8A and Figure 8B This is a plan view illustrating a planar line structure according to an embodiment of the present disclosure. Figure 8A and Figure 8B In this context, the second camera hole HA2 will be described as representative of multiple camera holes. (Reference) Figure 8AThe diagram illustrates the wiring arrangement at the periphery of the second camera aperture HA2. High-resistance lines 183 and low-resistance lines 184 are mixed to form an initialization voltage line 181 near the second camera aperture HA2, thereby increasing the overall line resistance. This reduces the RC load deviation between the right display area HR and the left display area HL of the second camera aperture HA2. Additionally, the RC load deviation between the right display area HR and the array pixel area AP can be reduced relative to the second camera aperture HA2.

[0087] In this specification, the high-resistance wire 183 may have a first resistance value, and the low-resistance wire 184 may have a second resistance value lower than the first resistance value. The first and second resistance values ​​do not represent absolute resistance values. The first resistance value only needs to be higher than the second resistance value. This can also be applied to other types of circuits.

[0088] The initialization voltage line 181 set in the display area can be arranged as a high resistance line 183 and a low resistance line 184, and can form a contact hole CNT for bridging.

[0089] The portion of the high-resistance line 183 located in the display area may be limited to the portion overlapping with the data line 200. Since the low-resistance line, having low resistance, is primarily used for the data line 200, the data line 200 cannot overlap with the low-resistance line 184, which constitutes the initialization voltage line 181. Therefore, near the data line 200, the low-resistance line 184 can be electrically connected to the high-resistance line 183 via the contact hole CNT and extend therefrom.

[0090] refer to Figure 8A The high-resistance line 183 and low-resistance line 184 of the initialization voltage line 181 can be set to have a constant length each throughout the display area.

[0091] refer to Figure 8A The data line 200 may include a first data line 210 and a second data line 220 near the second camera hole HA2. The data line 200 is typically connected to pixels in the display area via the first data line 210; however, since the data line 200 cannot overlap with the low-resistance line 184 of the initialization voltage line 181 near the second camera hole HA2, other lines can be used, for example, those referenced above. Figure 3 The described connection electrode 145. Near the second camera aperture HA2, a low-resistance line 184 of the initialization voltage line 181 can be provided, and a high-resistance line 183 may not be provided. Since the initialization voltage line 181 bypasses the second camera aperture HA2 and has a curved planar shape, its length may increase and potential resistance damage may occur. Therefore, to minimize the increase in resistance, it is preferable to provide only the low-resistance line 184.

[0092] refer to Figure 8B Similar to Figure 8A As shown, the initialization voltage line 181 may include a high-resistance line 183 and a low-resistance line 184 electrically connected through a contact hole CNT. For example... Figure 8A As shown, the RC load deviation between the left and right sides or between the upper and lower sides of the second camera hole HA2 can be reduced by increasing the total resistance of the initialization voltage line 181. Figure 8A The difference shown is that, in Figure 8B In this process, the lengths of the high-resistance line 183 and the low-resistance line 184 that constitute the initialization voltage line 181 are different for each part.

[0093] For example, the low-resistance line 184 and the high-resistance line 183 are configured such that their lengths in the left display area HL of the second camera hole HA2 are similar to their lengths in the right display area HR of the second camera hole HA2, thereby reducing the RC load deviation in each area.

[0094] However, the low-resistance line 184 and the high-resistance line 183 are configured such that their lengths in the left display area HL and right display area HR of the second camera aperture HA2 differ from their lengths in the array pixel area AP. In the array pixel area AP, the length of the high-resistance line 183 is minimized to minimize the increase in resistance. Since the area of ​​the second camera aperture HA2 is relatively small in the display area, but the remaining array pixel area AP occupies a relatively wide space, the length of the high-resistance line 183 in the array pixel area AP is minimized, thereby preventing overall performance degradation.

[0095] Figure 9 This is a cross-sectional view showing a contact hole CNT according to an embodiment of the present disclosure.

[0096] refer to Figure 9 It can be seen how the high-resistance line 183 and the low-resistance line 184 of the initialization voltage line 181 are electrically connected in the contact hole CNT. The high-resistance line 183 may be made of metal and used for the first gate electrode 122 in the pixel region. The low-resistance line may be made of metal and used for the first source electrode 121 and the first drain electrode 124 in the pixel region. A second lower interlayer insulating film 106, an upper buffer layer 107, an upper gate insulating film 137, etc., may be disposed between the high-resistance line 183 and the low-resistance line 184, thereby insulating the high-resistance line 183 from the low-resistance line 184 in the region other than the contact hole CNT.

[0097] Figure 10A and Figure 10B This is a graph showing the numerical values ​​related to the RC load deviation for each region. Figure 10AIn this example, when the entire initialization voltage line 181 according to the comparative example of this disclosure is set to a low resistance line, the RC load deviation is measured. The x-axis of the graph represents the left display area HL, the right display area HR, and the array pixel area AP from left to right, and the y-axis of the graph represents the measured value of the RC load for the corresponding area. It can be seen that each of the measured resistance R, capacitance C, and RC delay τ is a percentage relative to a reference value. Figure 10A In the comparative example, it can be seen that the RC load value is lowest in the left display area HL, highest in the right display area HR, and decreases in the array pixel area AP. Specifically, the percentage of RC load deviation can exceed approximately 900% in the right display area HR. This level is very high compared to the levels of other third scan signal lines such as 182. The brightness of the right display area HR increases due to the RC load deviation.

[0098] refer to Figure 10B , should be with Figure 10A When measurements are performed on the structure of an embodiment to which this disclosure is applied in the same manner as shown, it can be seen that the RC load deviation of the initialization voltage line 181 is significantly reduced, and therefore the deviation is lower than that of the first scan signal line.

[0099] Although the display device according to an embodiment of this specification has been described based on the fact that the substrate corresponding to the camera hole CH is removed by laser, the disclosure is not limited thereto, and parts of the substrate or only a portion of the substrate may be removed.

[0100] The display device according to the embodiments of this specification may include LCD, field emission display (FED), OLED display device and QD display device.

[0101] The display device according to the embodiments of this specification may include a set of electronic devices / apparatus or a set of equipment (or a set of apparatus), such as a laptop computer, a television, a computer monitor, an equipment display device including an automotive display device or another type of device for a vehicle, or a mobile electronic device / apparatus such as a smartphone or an electronic board, which is a complete product (or final product) including an LCM, an OLED module, etc.

[0102] The display device according to the embodiments of this specification described above can be briefly described again as follows.

[0103] The display device according to embodiments of this specification may include: a substrate including a display area, a camera hole and a non-display area; a light-emitting element disposed in the display area; a gate driver disposed in the non-display area; and an initialization signal line disposed in the display area.

[0104] In the display device according to embodiments of this specification, the display area may include a left display area, a right display area, and an array pixel area relative to the camera hole, and may include an initialization signal line disposed in each of the left and right display areas.

[0105] In the display device according to embodiments of this specification, the initialization signal line may include a low-resistance initialization signal line and a high-resistance initialization signal line.

[0106] In the display device according to the embodiments of this specification, the low-resistance initialization signal line and the high-resistance initialization signal line can be electrically connected through a contact hole.

[0107] In the display device according to an embodiment of this specification, a low-resistance initialization signal line may be disposed near the camera hole to have a planar curved shape.

[0108] The display device according to embodiments of this specification may further include data lines disposed in the display area, and the data lines may include a first data line and a second data line.

[0109] In the display device according to an embodiment of this specification, the second data line may at least partially overlap with the low-resistance initialization signal line near the camera hole.

[0110] In the display device according to the embodiments of this specification, the low-resistance initialization signal line and the high-resistance initialization signal line may each have a constant length throughout the display area.

[0111] In the display device according to the embodiments of this specification, the low-resistance initialization signal line and the high-resistance initialization signal line may have different lengths in at least a portion of the display area.

[0112] The display device according to embodiments of this specification may include: a substrate including a display area, a camera hole and a non-display area; a light-emitting element disposed in the display area; a gate driver disposed in the non-display area; and an initialization signal line disposed in the display area.

[0113] In the display device according to embodiments of this specification, the display area may include a left display area, a right display area, and an array pixel area relative to the camera hole, and the initialization signal line may include a low-resistance initialization signal line and a high-resistance initialization signal line.

[0114] In the display device according to embodiments of this specification, a low-resistance initialization signal line may be provided in at least a portion of the array pixel area, the left display area, and the right display area.

[0115] In the display device according to the embodiments of this specification, the low-resistance initialization signal line and the high-resistance initialization signal line can be electrically connected through a contact hole.

[0116] In the display device according to the embodiments of this specification, the low-resistance initialization signal line may be disposed near the camera hole to have a planar curved shape.

[0117] The display device according to embodiments of this specification may further include data lines disposed in the display area, and the data lines may include a first data line and a second data line.

[0118] In the display device according to an embodiment of this specification, the second data line may at least partially overlap with the low-resistance initialization signal line near the camera hole.

[0119] In the display device according to the embodiments of this specification, the low-resistance initialization signal line and the high-resistance initialization signal line may each have a constant length throughout the display area.

[0120] In the display device according to the embodiments of this specification, the low-resistance initialization signal line and the high-resistance initialization signal line may have different lengths in at least a portion of the display area.

[0121] The features, structures, and effects described above in the examples of this application are included in at least one example of this application, but this disclosure is not limited to one example. Furthermore, the features, structures, and effects described in at least one example of this application can be implemented by those skilled in the art through combinations or modifications of other examples. Therefore, content associated with combinations and modifications should be interpreted as being within the scope of this application.

[0122] It will be apparent to those skilled in the art that this application is not limited to the embodiments and drawings described above, and that various substitutions, modifications, and variations can be made without departing from the spirit or scope of this application. Therefore, the scope of this application is defined by the claims described below, and this application should be construed as covering all modifications or variations arising from the meaning and scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, the substrate including a display area, a camera hole, a region between the display area and the camera hole, and a non-display area, the non-display area including at least two portions adjacent to the side of the display area; as well as A gate driver, the gate driver being disposed in at least two portions of the non-display area; A data cable is disposed in the display area; A first planarization layer is disposed on the substrate; A light-emitting element, wherein the light-emitting element is disposed on the first planarization layer; as well as An initialization signal line is established, which intersects with the data line in the display area. The display area includes pixels, which are disposed in the area where the data lines and gate lines intersect and include multiple transistors and storage capacitors. The plurality of transistors include a gate electrode, a semiconductor layer, and a source-drain layer therein, wherein a source electrode and a drain electrode are disposed. The initialization signal lines include low-resistance initialization signal lines and high-resistance initialization signal lines. The high-resistance initialization signal line bends in the region between the display area and the camera hole, and connects to a first and a second portion of the low-resistance initialization signal line, or to a first and a second low-resistance initialization signal line adjacent to the left and right sides of the camera hole. The high-resistance initialization signal line comprises the same material as the gate electrode, and the low-resistance initialization signal line comprises the same material as at least one of the source electrode or the drain electrode.

2. The display device according to claim 1, further comprising: A connecting electrode is disposed on the first planarization layer; as well as A second planarization layer is disposed on the connecting electrode. The light-emitting element includes an anode disposed on the second planarization layer.

3. The display device according to claim 1, wherein, The plurality of transistors includes at least one low-temperature polysilicon transistor having a plurality of insulating layers disposed thereon, and at least one oxide transistor, and The at least one oxide transistor is disposed on the plurality of insulating layers.

4. The display device according to claim 3, wherein, At least one of the plurality of insulating layers is disposed between the low-resistance initialization signal line and the high-resistance initialization signal line.

5. The display device according to claim 4, wherein, The low-resistance initialization signal line and the high-resistance initialization signal line are electrically connected through a contact hole passing through the at least one insulating layer.

6. The display device according to claim 5, wherein, The at least one insulating layer includes an interlayer insulating film, a buffer layer, and a gate insulating film disposed on the substrate.

7. The display device according to claim 1, wherein, The data cable includes a first data cable disposed in the display area and a second data cable connected to the first data cable and disposed in the area between the display area and the camera hole.

8. The display device according to claim 7, wherein, The second data line bends in the region between the display area and the camera hole, and connects to a first portion and a second portion of the first data line that are disposed adjacent to the upper and lower sides of the camera hole.

9. The display device according to claim 7, wherein, The first data line includes a data line connected to the second data line, and another data line not connected to the second data line and disposed adjacent to the second data line in the area between the display area and the camera hole.

10. The display device according to claim 7, wherein, The second data line intersects the low-resistance initialization signal line in the region between the display area and the camera hole.

11. The display device according to claim 8, wherein, The second data line is bent such that it extends along the left or right edge of the camera hole.

12. The display device according to claim 1, wherein, The portion of the display area containing the high-resistance initialization signal line overlaps with the data line.

13. The display device according to claim 7, wherein, The high-resistance initialization signal line is bent such that it extends along the upper or lower edge of the camera aperture.

14. The display device according to claim 1, wherein, The initialization signal line is connected to the source electrode of the transistor, including the low-temperature polysilicon transistor, among the plurality of transistors.

15. The display device according to claim 1, wherein, The gate electrode is in the form of a single layer or multiple layers comprising at least one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy comprising at least one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Wherein, at least one of the source electrode or the drain electrode is in the form of a single layer or multiple layers selected from at least one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or at least one alloy including two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

16. The display device according to claim 7, wherein, The second data line at least partially overlaps with the low-resistance initialization signal line near the camera aperture.

17. The display device according to claim 7, wherein, Each of the low-resistance initialization signal line and the high-resistance initialization signal line has a constant length in the display area.

18. The display device according to claim 7, wherein, The low-resistance initialization signal line and the high-resistance initialization signal line have different lengths in at least a portion of the display area.

19. The display device according to claim 7, wherein, The display area includes a left display area, a right display area, and an array pixel area relative to the camera aperture, and The lengths of the low-resistance initialization signal line and the high-resistance initialization signal line in the left display area and the right display area are different from their lengths in the array pixel area.

20. The display device according to claim 1, further comprising a light-blocking layer disposed on at least one of the gate electrode or the semiconductor layer.

Images