MEMS biplanar coil preparation method

Abstract

The invention relates to the technical field of micro electro mechanical system manufacturing, and discloses an MEMS biplanar coil preparation method, which comprises the following steps: carrying out surface cleaning and baking pretreatment on a silicon wafer substrate, and depositing a first insulating layer on the surface of the silicon wafer substrate; forming a first mask pattern, forming a first pre-buried groove, and then performing a metal deposition and stripping process to form a first layer of magnetic field coil; then preparing a connecting hole communicated with the first layer of magnetic field coil; then, forming a second layer of magnetic field coil in the second pre-buried groove through a metal deposition and stripping process; and etching the protective layer to expose the bonding pad area, and cutting the wafer. According to the invention, the first mask pattern is used as the barrier layer to etch the first insulating layer to form the first pre-buried groove, and the metal deposition and stripping process is completed based on the same first mask pattern, so that the first layer of magnetic field coil is formed in the first pre-buried groove, the self-alignment of the coil pattern and the groove is realized, and the overlay error is eliminated.

Description

Technical Field

[0001] This invention relates to the field of microelectromechanical systems (MEMS) manufacturing technology, specifically a method for fabricating MEMS dual-plane coils. Background Technology

[0002] Magnetic sensing technology is applied in fields such as geological exploration and biomedical imaging. With increasing demands for detection accuracy and portability, the chip-based integration of magnetic sensing systems is becoming a trend. Magnetic field coils, as components for achieving magnetic field modulation and compensation, are being manufactured as miniaturized coils on silicon substrates using microelectromechanical systems (MEMS) technology, providing a means to achieve device miniaturization and mass production.

[0003] Current methods for manufacturing micro-coils commonly employ electroplating or dry etching processes. Copper is difficult to etch with high precision using dry etching, while electroplating can easily lead to surface roughness or edge protrusions, reducing wafer flatness. These topographical variations accumulate during the fabrication of double- or multi-layer coil structures, causing difficulties in controlling the depth of focus and alignment errors in photolithography, thus affecting the accuracy of interlayer interconnects and structural stability.

[0004] Meanwhile, during the etching process to expose the pads, conventional methods typically involve an oxygen-containing environment, which can easily lead to oxidation of the copper pad surface, generating high-resistance oxides. This increases the contact resistance of subsequent packaging bonding and reduces the reliability of electrical contacts. Therefore, developing a method for fabricating MEMS dual-planar coils that can ensure wafer surface flatness, improve interlayer alignment accuracy, and reduce pad contact resistance is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for fabricating MEMS dual-plane coils, which solves the problems of low interlayer alignment accuracy due to poor wafer surface flatness and low electrical contact reliability caused by easy oxidation of pads during protective layer etching in existing manufacturing processes.

[0006] To address the above problems, this invention provides a method for fabricating MEMS dual-plane coils, employing the following technical solution:

[0007] A method for fabricating a MEMS dual-plane coil includes the following steps:

[0008] S1. Perform surface cleaning and baking pretreatment on the silicon wafer substrate to obtain a clean substrate;

[0009] S2. A first insulating layer is deposited on the surface of the clean substrate to obtain a substrate with the first insulating layer;

[0010] S3. A first mask pattern is formed on the first insulating layer, and the first insulating layer is etched based on the first mask pattern to form a first pre-embedded groove. Then, a metal deposition and stripping process is performed to form a first layer of magnetic field coil in the first pre-embedded groove, thereby obtaining a semi-finished product with a first layer of magnetic field coil.

[0011] S4. Deposit an interlayer insulating layer on the semi-finished product having the first layer magnetic field coil, and prepare a connection hole with conductive material in the interlayer insulating layer. The connection hole is connected to the first layer magnetic field coil to obtain a semi-finished product with an interlayer interconnection structure.

[0012] S5. On the semi-finished product with interlayer interconnect structure, a second mask pattern is formed on the interlayer insulating layer using an alignment process. Based on the second mask pattern, the interlayer insulating layer is etched to form a second pre-embedded groove. Subsequently, a second magnetic field coil is formed in the second pre-embedded groove through a metal deposition and stripping process to obtain a wafer with a double-layer coil structure.

[0013] S6. A protective layer is deposited on the surface of the wafer with the double-layer coil structure, and the protective layer is etched to expose the pad area, thereby obtaining the processed wafer.

[0014] S7. The processed wafer is cut to obtain a single MEMS dual-plane coil chip.

[0015] By adopting the above technical solution, the embedded growth of coil wires in the insulation layer is achieved by using a process route that combines pre-embedded grooves with metal stripping. The embedded structure ensures that the wafer surface maintains a high degree of flatness after each layer of coil is fabricated, reducing the morphological fluctuations caused by interlayer stacking. This provides a flat process plane for the vertical interconnection of multilayer coils, thereby improving the structural stability and photolithographic alignment accuracy of the dual-plane coil.

[0016] Preferably, the specific implementation of the preparation of the first magnetic field coil in step S3 is as follows: spin-coating photoresist on the first insulating layer and performing photolithography to form the first mask pattern; using the first mask pattern as a barrier layer to perform dry etching on the first insulating layer to form the first pre-embedded groove in the first insulating layer; keeping the first mask pattern intact, directly depositing the first metal layer on the surface of the first mask pattern, and simultaneously depositing the second metal layer inside the first pre-embedded groove; removing the first mask pattern and the first metal layer with a solvent, retaining the second metal layer, and completing the stripping.

[0017] By adopting the above technical solution, the same first mask pattern is continuously used as the blocking layer for etching the insulating layer and the sacrificial layer for the metal stripping process, so as to achieve self-alignment between the first layer magnetic field coil pattern and the first pre-embedded groove, eliminate the overlay error between the metal layer and the pre-embedded groove, and ensure the precise matching between the metal coil and the pre-embedded groove.

[0018] Preferably, in step S3, the etching depth of the first pre-embedded groove is 630 nm to 670 nm; the second metal layer includes a titanium adhesion layer with a thickness of 40 nm to 60 nm and a copper host metal layer with a thickness of 500 nm to 700 nm deposited sequentially.

[0019] Preferably, in step S3, the dry etching employs a reactive ion etching process, and the etching gas is selected from carbon tetrafluoride and trifluoromethane; the metal deposition employs a DC magnetron sputtering process.

[0020] Preferably, in step S1, the baking pretreatment temperature is 110°C to 150°C; in step S2, the material of the first insulating layer is silicon dioxide, the deposition thickness is 700 nm to 900 nm, and the deposition temperature is 250°C to 350°C.

[0021] Preferably, in step S4, the deposition thickness of the interlayer insulating layer is 1050 nm to 1150 nm; the method for preparing the connection hole is as follows: the connection hole pattern is defined using photolithography, the interlayer insulating layer is etched using inductively coupled plasma etching, and a titanium layer and a copper layer are sputtered sequentially to cover the inner wall and bottom of the connection hole.

[0022] Preferably, in step S5, the wiring pattern of the second layer magnetic field coil is configured such that, in the energized operating state, the current direction in the second layer magnetic field coil is opposite to the current direction in the first layer magnetic field coil.

[0023] Preferably, in step S6, the protective layer is made of silicon dioxide and has a thickness of 500 nanometers to 1000 nanometers; the protective layer is etched using an oxygen-free fluorine-based mixed gas for inductively coupled plasma etching.

[0024] Preferably, the fluorine-based mixed gas is a mixture of carbon tetrafluoride and trifluoromethane; and the over-etching time is increased by 10% to 20% during the etching process.

[0025] Preferably, the first insulating layer, the interlayer insulating layer, and the protective layer are all prepared using plasma-enhanced chemical vapor deposition (PECVD) with silane and nitrous oxide as the reaction gases.

[0026] This invention provides a method for fabricating MEMS dual-plane coils. It has the following beneficial effects:

[0027] 1. This invention uses a first mask pattern as a barrier layer to etch a first insulating layer to form a first pre-embedded groove, and completes metal deposition and stripping processes based on the same first mask pattern to form a first layer of magnetic field coil in the first pre-embedded groove. This achieves self-alignment between the coil pattern and the groove and eliminates overlay errors. At the same time, the embedded structure keeps the surface of the semi-finished product with the first layer of magnetic field coil flat, providing a flat process plane for the subsequent deposition of the interlayer insulating layer and the preparation of the second layer of magnetic field coil.

[0028] 2. The present invention deposits a titanium adhesive layer and a copper body metal layer sequentially in the first and second pre-embedded grooves, and sputters titanium and copper layers sequentially on the inner wall and bottom of the connecting hole. The bonding effect between the titanium adhesive layer and the silicon dioxide material enhances the adhesion of the metal layer and prevents the coil from falling off. At the same time, the copper body metal layer provides a low resistivity conductive channel, ensuring the electrical reliability of the interlayer interconnection between the first and second magnetic field coils.

[0029] 3. This invention uses an oxygen-free fluorine-based mixed gas to perform inductively coupled plasma etching on the protective layer to expose the pad area. While removing the protective layer of silicon dioxide material, it avoids the oxidation reaction of the copper metal at the bottom in the plasma environment, thereby maintaining the cleanliness of the exposed pad area metal surface. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of the first layer coil (bottom layer) in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of the second layer coil (top layer) in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the overall structure of the MEMS dual-plane coil chip in an embodiment of the present invention;

[0033] Figure 4 This is a flowchart illustrating the fabrication process of the MEMS dual-plane coil in an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, examples, comparative examples, and test examples. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Example 1:

[0036] See attached document Figure 1 - Appendix Figure 4 This embodiment provides a method for fabricating a MEMS dual-plane coil, including the following steps:

[0037] S1, such as Figure 4 As shown in (1), a 4-inch single-polished silicon wafer was selected as the substrate. Acetone, isopropanol and deionized water were used in sequence for ultrasonic cleaning to remove surface oil and impurities. Then the silicon wafer was placed on a heating table and baked at 110°C for 10 minutes to completely remove surface water vapor.

[0038] S2, such as Figure 4 As shown in (2), a SiO2 layer with a thickness of 800 nm was deposited on the surface of a silicon wafer using a plasma-enhanced chemical vapor deposition (PECVD) device as an insulating and pre-embedded groove substrate. The deposition temperature was controlled at 250 °C, and the reaction gases were SiH4 and N2O.

[0039] S3, such as Figure 4 As shown in (3)-(6), the first layer of magnetic field coils is prepared as follows: First, the wafer surface is treated with O2 plasma, and AZ4620 positive photoresist is spin-coated. The thickness of the photoresist after spin-coating is about 7 μm. It is pre-baked at 90°C, exposed using a contact lithography machine and developed with NaOH solution. After development, it is post-baked at 110°C to harden the film. Then, using the photoresist as a mask, SiO2 is etched using reactive ion etching (RIE) process. The etching gases are CF4 and CHF3, and the etching depth is controlled to be 630 nm to form a pre-embedded groove. Keeping the photoresist mask in place, a 50 nm thick Ti adhesion layer and a 600 nm thick layer are deposited sequentially using DC magnetron sputtering process in an environment with a background vacuum of better than 5 × 10 Pa. -4 A thick Cu main metal layer; finally, the wafer is immersed in acetone and placed in an ultrasonic bath for peeling to remove the photoresist and non-patterned metal areas, retaining the metal in the pre-embedded grooves to form the first layer of coils (structure as follows). Figure 1 (as shown)

[0040] S4, such as Figure 4 As shown in (7)-(10), a 1050nm thick SiO2 layer is deposited at 250℃ using PECVD process as an interlayer insulating layer and a second layer coil pre-embedded substrate. Then, the connection hole pattern is defined using photolithography process. The SiO2 is etched with C4F8 gas using inductively coupled plasma (ICP) etching process until the first layer of Cu metal is exposed. Then, 50nm Ti and 600nm Cu are sputtered using DC magnetron sputtering process to cover the inner wall and bottom of the connection hole to achieve conductivity.

[0041] S5, such as Figure 4 As shown in (11)-(13), a double-sided lithography machine is used for alignment and overlay processes, with alignment accuracy controlled within ±2μm. The spin coating of photoresist, photolithography, RIE etching of pre-embedded grooves, magnetron sputtering of metal and stripping steps in S3 are repeated to prepare a second layer coil complementary to the first layer coil (structure as shown in Figure 13). Figure 2 As shown in the figure, its process parameters are consistent with those of S3;

[0042] S6, such as Figure 4 As shown in (14)-(16), a 500nm thick SiO2 protective layer was deposited on the surface of the coil using PECVD technology. Then, the pad area was exposed by photolithography, and the SiO2 protective layer was etched using ICP etching process. The etching gas selected was a CF4 / CHF3 mixed gas (without O2) with a high selectivity for Cu. The over-etching time was increased by 10% to ensure that the pads were fully exposed without damaging the metal. The resistance between the pads was tested to be 248Ω.

[0043] S7. The processed wafer is diced using a grinding wheel dicing technique to obtain a single MEMS dual-plane coil chip (overall structure as shown in the figure). Figure 3 (As shown).

[0044] Example 2:

[0045] See attached document Figure 1 - Appendix Figure 4 This embodiment provides a method for fabricating a MEMS dual-plane coil, including the following steps:

[0046] S1. Select a 4-inch single-polished silicon wafer as the substrate, and use acetone, isopropanol and deionized water in sequence for ultrasonic cleaning to remove surface oil and impurities. Then place the silicon wafer on a heating table and bake it at 130°C for 20 minutes to completely remove surface water vapor.

[0047] S2. A SiO2 layer with a thickness of 800 nm is deposited on the surface of a silicon wafer using plasma-enhanced chemical vapor deposition (PECVD) equipment as an insulating and pre-embedded groove substrate. The deposition temperature is controlled at 300℃, and the reaction gases are SiH4 and N2O.

[0048] S3. Fabrication of the first magnetic field coil: First, the wafer surface is treated with O2 plasma, and AZ4620 positive photoresist is spin-coated to a thickness of approximately 7 μm. Pre-baking is performed at 100°C, followed by exposure using a contact lithography machine and development with NaOH solution. After development, post-baking is performed at 115°C for hardening. Next, using the photoresist as a mask, reactive ion etching (RIE) is employed to etch SiO2 using CF4 and CHF3 as etching gases, controlling the etching depth to 650 nm to form pre-embedded grooves. The photoresist mask is left in place, and the etching is carried out under a background vacuum better than 5 × 10⁻⁶.-4 In an environment of Pa, a 50 nm thick Ti adhesion layer and a 600 nm thick Cu host metal layer are sequentially deposited using DC magnetron sputtering. Finally, the wafer is immersed in acetone and placed in an ultrasonic bath for peeling to remove the photoresist and metal in the non-patterned area, while retaining the metal in the pre-embedded groove to form the first layer of coil.

[0049] S4. A 1100nm thick SiO2 layer is deposited at 300℃ using PECVD process as an interlayer insulating layer and a second layer coil pre-embedded substrate. Then, the connection hole pattern is defined using photolithography. The SiO2 is etched with C4F8 gas using inductively coupled plasma (ICP) etching process until the first layer of Cu metal is exposed. Then, 50nm Ti and 600nm Cu are sputtered using DC magnetron sputtering process to cover the inner wall and bottom of the connection hole to achieve conductivity.

[0050] S5. Using a double-sided lithography machine, an alignment and overlay process is performed, with the alignment accuracy controlled within ±2μm. Repeat the spin coating of photoresist, lithography, RIE etching of pre-embedded grooves, magnetron sputtering of metal and stripping steps in S3 above to prepare a second layer coil that is complementary to the first layer coil. Its process parameters are consistent with those in S3.

[0051] S6. A SiO2 protective layer with a thickness of 800nm ​​is deposited on the surface of the coil using PECVD technology. Then, the pad area is exposed by photolithography. The SiO2 protective layer is etched using ICP etching process. The etching gas is a CF4 / CHF3 mixed gas (without O2) with a high selectivity for Cu. The over-etching time is increased by 15% to ensure that the pads are fully exposed without damaging the metal. The resistance between the pads is tested to be 252Ω.

[0052] S7. The processed wafer is cut using a grinding wheel dicing technique to obtain a single MEMS dual-plane coil chip.

[0053] Example 3:

[0054] See attached document Figure 1 - Appendix Figure 4 This embodiment provides a method for fabricating a MEMS dual-plane coil, including the following steps:

[0055] S1. Select a 4-inch single-polished silicon wafer as the substrate, and use acetone, isopropanol and deionized water in sequence for ultrasonic cleaning to remove surface oil and impurities. Then place the silicon wafer on a heating table and bake it at 150°C for 30 minutes to completely remove surface water vapor.

[0056] S2. A SiO2 layer with a thickness of 800 nm is deposited on the surface of a silicon wafer using plasma-enhanced chemical vapor deposition (PECVD) equipment as an insulating and pre-embedded groove substrate. The deposition temperature is controlled at 350℃, and the reaction gases are SiH4 and N2O.

[0057] S3. Fabrication of the first magnetic field coil: First, the wafer surface is treated with O2 plasma, and AZ4620 positive photoresist is spin-coated to a thickness of approximately 7 μm. Pre-baking is performed at 110°C, followed by exposure using a contact lithography machine and development with NaOH solution. After development, post-baking is performed at 120°C for hardening. Next, using the photoresist as a mask, reactive ion etching (RIE) is employed to etch SiO2 using CF4 and CHF3 as etching gases, controlling the etching depth to 670 nm to form pre-embedded grooves. The photoresist mask is kept in place, and the etching is performed under a background vacuum better than 5 × 10⁻⁶. -4 In an environment of Pa, a 50 nm thick Ti adhesion layer and a 600 nm thick Cu host metal layer are sequentially deposited using DC magnetron sputtering. Finally, the wafer is immersed in acetone and placed in an ultrasonic bath for peeling to remove the photoresist and metal in the non-patterned area, while retaining the metal in the pre-embedded groove to form the first layer of coil.

[0058] S4. A 1150nm thick SiO2 layer is deposited at 350℃ using PECVD process as an interlayer insulating layer and a second layer coil pre-embedded substrate. Then, the connection hole pattern is defined using photolithography process. The SiO2 is etched with C4F8 gas using inductively coupled plasma (ICP) etching process until the first layer of Cu metal is exposed. Then, 50nm Ti and 600nm Cu are sputtered using DC magnetron sputtering process to cover the inner wall and bottom of the connection hole to achieve conductivity.

[0059] S5. Using a double-sided lithography machine, an alignment and overlay process is performed, with the alignment accuracy controlled within ±2μm. Repeat the spin coating of photoresist, lithography, RIE etching of pre-embedded grooves, magnetron sputtering of metal and stripping steps in S3 above to prepare a second layer coil that is complementary to the first layer coil. Its process parameters are consistent with those in S3.

[0060] S6. A 1000nm thick SiO2 protective layer is deposited on the coil surface using PECVD technology. Then, the pad area is exposed by photolithography. The SiO2 protective layer is etched using ICP etching process. The etching gas is a CF4 / CHF3 mixed gas (without O2) with a high selectivity for Cu. The over-etching time is increased by 20% to ensure that the pads are fully exposed without damaging the metal. The resistance between the pads is tested to be 258Ω.

[0061] S7. The processed wafer is cut using a grinding wheel dicing technique to obtain a single MEMS dual-plane coil chip.

[0062] Comparative Examples 1-3:

[0063] Comparative Example 1:

[0064] Compared with Example 2, the difference is that steps S4 and S5 are omitted. That is, after step S3 of preparing the first layer coil, the interlayer insulation and the preparation of the second layer coil are not performed. Instead, the protective layer deposition and pad exposure in step S6 are performed directly to obtain a single-planar coil structure. All other parameters and steps are the same.

[0065] Comparative Example 2:

[0066] Compared with Example 2, the difference is that the RIE dry etching of the pre-embedded groove is omitted in step S3. After photolithography, development and hardening, the SiO2 layer is not etched. Instead, the Ti / Cu metal layer is sputtered directly on the relatively flat SiO2 substrate and then stripped, so that the first coil protrudes from the substrate surface instead of being embedded in the pre-embedded groove. All other parameters and steps are the same.

[0067] Comparative Example 3:

[0068] Compared with Example 2, the difference lies in the adjustment of the photolithographic mask pattern of the second layer coil used in step S5 and the position of the connecting hole in step S4. The wiring direction and interlayer connection point of the second layer coil are changed so that when the power is applied, the current direction of the second layer coil is the same as that of the first layer coil, while in Example 2 the current directions are opposite. All other parameters and steps are the same.

[0069] Test Examples 1-4:

[0070] Test Example 1:

[0071] Experimental description:

[0072] Independent bare wafers prepared and diced in Examples 1, 2, and 3, as well as Comparative Examples 1, 2, and 3, were selected as test samples. Twenty chip samples were randomly selected from each group for testing to evaluate the consistency and yield of the process.

[0073] The test was conducted using a semi-automatic probe station in conjunction with a precision source meter. The chip was fixed on the test platform, and the chip pads were aligned with a microscope. A tungsten probe was then used to establish electrical contact with the pads.

[0074] A constant DC voltage of 1.0V is applied between the two pads while monitoring the circuit current. The DC resistance of the coil is calculated using Ohm's law. If the detected current is less than 1nA, it is considered an open circuit failure; if the resistance value deviates from the theoretical design value (approximately 250Ω) by more than ±20%, it is considered an abnormal resistance value. The average resistance value and yield of each sample group are recorded.

[0075] Table 1. Summary of test data on DC resistance and conduction yield of coils in each experimental group

[0076]

[0077] Experimental conclusion:

[0078] The data in Table 1 show that the average resistance values ​​of the samples in Examples 1 to 3 are between 241.5Ω and 263.2Ω, with a small standard deviation, and the yield rate is over 90%, indicating that the process parameter range set in this invention can ensure that the device has stable electrical connection performance.

[0079] The comparative data shows a significant deterioration in the test results of Comparative Example 2, with a yield rate of only 30%. Furthermore, the resistance values ​​of the conductive samples exhibit large dispersion, with the average resistance exceeding the design value. This difference stems from the fact that Comparative Example 2 did not employ a pre-embedded groove etching process in step S3. In this comparative example, the first metal coil layer was directly deposited on the substrate surface, forming a raised step of approximately 650 nm. During subsequent deposition of the interlayer insulating layer and fabrication of the second coil layer, the film faced difficulties in covering this step, easily resulting in thinning or breakage, leading to abnormally high resistance or even open circuits.

[0080] Test Example 2:

[0081] Experimental description:

[0082] The MEMS coil chips prepared in Examples 1, 2, and 3, as well as Comparative Examples 2 and 3, were selected as test objects. Twenty chip samples were randomly selected from each group.

[0083] The testing process was conducted on a probe station equipped with a shielded enclosure, using a high-sensitivity picoammeter to measure the weak current. The lead pads of the first and second layer coils were connected to the positive and negative terminals of the testing instrument, respectively. A DC voltage of 100V was applied between the two coils and maintained for 60 seconds to eliminate the effect of capacitor charging. After the reading stabilized, the leakage current flowing through the interlayer insulation was recorded. If the sample broke down or the leakage current exceeded 100nA, it was recorded as insulation failure.

[0084] Table 2. Interlayer insulation leakage current test data for each experimental group

[0085]

[0086] Note: "-" indicates that Comparative Example 1 is a single-layer planar coil structure without interlayer insulation, so this test was not performed.

[0087] Experimental conclusion:

[0088] Table 2 shows the test results, indicating a significant decrease in the insulation performance of Comparative Example 2. Its average leakage current reached 48.73 nA, and a high proportion of samples exhibited insulation failure. Analysis of the failure mechanism reveals that it is primarily attributed to the lack of a pre-embedded planarization process in Comparative Example 2. In Comparative Example 2, the first layer of metal coils was directly formed on the substrate surface, creating a vertical step approximately 650 nm high. When depositing a silicon dioxide insulating layer using PECVD, defects such as discontinuous coverage or keyhole-like gaps easily appear at the edge steps of the metal lines. These microscopic defects become leakage channels for charge carriers under the influence of an electric field, leading to reduced withstand voltage and increased leakage current.

[0089] Test Example 3:

[0090] Experimental description:

[0091] The chips prepared in Example 2, Comparative Example 1, and Comparative Example 3 were selected as test samples. Example 2 represents the dual-plane reverse current structure of the present invention, Comparative Example 1 represents the conventional single-plane structure, and Comparative Example 3 represents the dual-plane unidirectional current structure. Ten samples were randomly selected from each group for testing.

[0092] The chip under test was fixed on a non-magnetic test platform, and a constant operating current of 50mA was supplied to the coil using a high-precision DC power supply. A micron-level stepper motor with three-dimensional movement capability, equipped with a high-resolution Hall probe, was used to scan the magnetic field of a plane 100μm above the central region of the coil. The scanning range was set as a circular area with a diameter of 500μm centered on the geometric center of the coil. The system automatically recorded the maximum and minimum values ​​of magnetic induction intensity within this area. The formula for calculating magnetic field uniformity was set as follows:

[0093] Uniformity = [1 - (maximum value - minimum value) / average value] × 100%;

[0094] The closer the value is to 100%, the flatter and more uniform the magnetic field distribution in that region.

[0095] Table 3. Magnetic field uniformity test data of the central region of each experimental group

[0096]

[0097] Experimental conclusion:

[0098] Referring to Table 3, the magnetic field uniformity of the samples in Example 2 remained above 98% in the central working region, exhibiting extremely high flatness. In contrast, the magnetic field uniformity of the single-planar structure sample in Comparative Example 1 was only about 78%, and the absolute value of the magnetic field strength was low. Although Comparative Example 3 achieved a higher magnetic field strength due to the double-layer superposition effect, its uniformity was approximately 90%, still lower than that of Example 2.

[0099] Example 2 employs the dual-plane structure proposed in this invention, combined with a reverse current design. This topology does not simply cancel out magnetic fields; instead, it shapes the spatial magnetic field distribution using Ampere's law. The upper and lower coils have a small vertical distance in space, and the current directions are opposite. This configuration creates a compensation effect similar to that of a Helmholtz coil in the near-field operating region.

[0100] Test Example 4: Interference Magnetic Field Suppression Test

[0101] Experimental description:

[0102] The MEMS coil chips prepared in Example 2, Comparative Example 1, and Comparative Example 3 were selected as test objects. Example 2 represents the dual-plane reverse current structure of the present invention, Comparative Example 1 represents the single-plane structure, and Comparative Example 3 represents the dual-plane unidirectional current structure. Ten samples were randomly selected from each group.

[0103] The test was conducted in an electromagnetically shielded room to eliminate interference from ambient electromagnetic noise on the measurement results. A 10MHz sinusoidal signal with a peak-to-peak value of 1V was input to the coil under test using a high-frequency signal generator. A calibrated near-field magnetic field probe was vertically fixed 5mm from the edge of the coil and connected to a high-sensitivity spectrum analyzer. After signal output was initiated, the spectrum analyzer read and recorded the radiated magnetic field strength at the fundamental frequency, in dBμA / m. This indicator reflects the level of electromagnetic radiation interference generated by the coil to the external space during operation; a lower value indicates less interference to the surrounding environment.

[0104] Table 4. Test data of edge radiation magnetic field strength for each experimental group

[0105]

[0106] Experimental conclusion:

[0107] Table 4 shows that the radiated magnetic field strength of Example 2 (approximately 42 dBμA / m) is significantly lower than that of Comparative Example 3 (approximately 75 dBμA / m) and Comparative Example 1 (approximately 68 dBμA / m). Comparative Example 3 exhibits higher external radiation due to the superposition of magnetic fields caused by the co-directional currents in the upper and lower layers, and Comparative Example 1, lacking magnetic field confinement due to its single-layer structure. Example 2 employs dual-plane parallel wiring and reverse current drive, resulting in magnetic field vectors generated by the upper and lower layer conductors in opposite directions. This causes interference and destructive forces in the far-field region, confining the magnetic energy within the coil and the near-field region, effectively suppressing leakage magnetic radiation into the external space and improving the electromagnetic compatibility of the device.

Claims

1. A method for fabricating a MEMS dual-plane coil, characterized in that, Includes the following steps: S1. Perform surface cleaning and baking pretreatment on the silicon wafer substrate to obtain a clean substrate; S2. A first insulating layer is deposited on the surface of the clean substrate to obtain a substrate with the first insulating layer; S3. A first mask pattern is formed on the first insulating layer, and the first insulating layer is etched based on the first mask pattern to form a first pre-embedded groove. Then, a metal deposition and stripping process is performed to form a first layer of magnetic field coil in the first pre-embedded groove, thereby obtaining a semi-finished product with a first layer of magnetic field coil. S4. Deposit an interlayer insulating layer on the semi-finished product having the first layer magnetic field coil, and prepare a connection hole with conductive material in the interlayer insulating layer. The connection hole is connected to the first layer magnetic field coil to obtain a semi-finished product with an interlayer interconnection structure. S5. On the semi-finished product with interlayer interconnect structure, a second mask pattern is formed on the interlayer insulating layer using an alignment process. Based on the second mask pattern, the interlayer insulating layer is etched to form a second pre-embedded groove. Subsequently, a second magnetic field coil is formed in the second pre-embedded groove through a metal deposition and stripping process to obtain a wafer with a double-layer coil structure. S6. A protective layer is deposited on the surface of the wafer with the double-layer coil structure, and the protective layer is etched to expose the pad area, thereby obtaining the processed wafer. S7. The processed wafer is cut to obtain a single MEMS dual-plane coil.

2. The method for fabricating a MEMS dual-plane coil according to claim 1, characterized in that, The specific implementation method for preparing the first layer of magnetic field coils in step S3 is as follows: Photoresist is spin-coated onto the first insulating layer and photolithographic development is performed to form the first mask pattern; The first mask pattern is used as a barrier layer to dry etch the first insulating layer to form the first pre-embedded groove in the first insulating layer; Without removing the first mask pattern, a first metal layer is deposited directly on the surface of the first mask pattern, and a second metal layer is deposited simultaneously inside the first pre-embedded groove. The first mask pattern and the first metal layer are removed by solvent, while the second metal layer is retained, thus completing the stripping process.

3. The method for fabricating a MEMS dual-plane coil according to claim 2, characterized in that, In step S3, the etching depth of the first pre-embedded groove is 630nm-670nm; the second metal layer includes a titanium adhesion layer with a thickness of 40nm-60nm and a copper main metal layer with a thickness of 500nm-700nm deposited sequentially.

4. The method for fabricating a MEMS dual-plane coil according to claim 2, characterized in that, In step S3, the dry etching employs a reactive ion etching process, and the etching gases are carbon tetrafluoride and trifluoromethane; the metal deposition employs a DC magnetron sputtering process.

5. The method for fabricating a MEMS dual-plane coil according to claim 1, characterized in that, In step S1, the baking pretreatment temperature is 110℃-150℃; in step S2, the material of the first insulating layer is silicon dioxide, the deposition thickness is 700nm-900nm, and the deposition temperature is 250℃-350℃.

6. The method for fabricating a MEMS dual-plane coil according to claim 1, characterized in that, In step S4, the deposition thickness of the interlayer insulating layer is 1050nm-1150nm; the method for fabricating the connecting holes is as follows: The connection hole pattern is defined using photolithography, the interlayer insulating layer is etched using inductively coupled plasma etching, and titanium and copper layers are sputtered sequentially to cover the inner wall and bottom of the connection hole.

7. The method for fabricating a MEMS dual-plane coil according to claim 1, characterized in that, In step S5, the wiring pattern of the second layer magnetic field coil is configured as follows: When the circuit is powered on, the direction of the current in the second layer magnetic field coil is opposite to the direction of the current in the first layer magnetic field coil.

8. The method for fabricating a MEMS dual-plane coil according to claim 1, characterized in that, In step S6, the protective layer is made of silicon dioxide and has a thickness of 500nm-1000nm; the protective layer is etched using an oxygen-free fluorine-based mixed gas for inductively coupled plasma etching.

9. A method for fabricating a MEMS dual-plane coil according to claim 8, characterized in that, The fluorine-based mixed gas is a mixture of carbon tetrafluoride and trifluoromethane; and it increases the over-etching time by 10%-20% during the etching process.

10. A method for fabricating a MEMS dual-plane coil according to claim 1, characterized in that, The first insulating layer, the interlayer insulating layer, and the protective layer are all prepared using plasma-enhanced chemical vapor deposition (PECVD) with silane and nitrous oxide as the reaction gases.

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