Capacitor structure and manufacturing method thereof

Abstract

The invention relates to a capacitor structure and a manufacturing method thereof. A method includes forming a first electrode including depositing a first layer of conductive material and depositing a second layer of conductive material on the first layer of conductive material; forming a first insulating layer on the second layer of conductive material; and forming a second electrode, including depositing a third layer of conductive material on the first insulating layer and depositing a fourth layer of conductive material on the third layer of conductive material.

Description

Technical Field

[0001] This disclosure relates to capacitor structures and methods of manufacturing thereof. Background Technology

[0002] Metal-insulator-metal (MIM) capacitors are widely used in functional circuits such as mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), embedded DRAM, and logic operation circuits. In system-on-a-chip (SoC) applications, different capacitors for different functional circuits must be integrated on the same chip to serve different purposes. For example, in mixed-signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase shift networks for coupling and / or bypassing purposes. For microprocessors, capacitors are used for decoupling. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method for forming a capacitor structure is provided, comprising: forming a first electrode, comprising: depositing a first layer of conductive material; depositing a second layer of conductive material on the first layer of conductive material; forming a first insulating layer on the second layer of conductive material; and forming a second electrode, comprising: depositing a third layer of conductive material on the first insulating layer; and depositing a fourth layer of conductive material on the third layer of conductive material.

[0004] According to one embodiment of this disclosure, a method for forming a capacitor structure is provided, comprising: performing a first deposition process to deposit a first electrode layer on a substrate, wherein the first electrode layer is a first conductive material; performing a second deposition process to deposit a second electrode layer on the first electrode layer, wherein the second electrode layer is the first conductive material, wherein the second deposition process is different from the first deposition process; depositing an insulating material on the second electrode layer; performing the first deposition process to deposit a third electrode layer on the insulating material, wherein the third electrode layer is the first conductive material; performing the second deposition process to deposit a fourth electrode layer on the third electrode layer, wherein the fourth electrode layer is the first conductive material; and performing a high-voltage annealing (HPA) process on the substrate.

[0005] According to one embodiment of this disclosure, a capacitor structure is provided, comprising: a dielectric layer sandwiched between a first electrode and a second electrode, wherein the first electrode and the second electrode each comprise: a first layer of conductive material; and a second layer of conductive material on the first layer of conductive material, wherein the first layer has a greater density than the second layer; a first contact plug electrically contacting the first electrode; and a second contact plug electrically contacting the second electrode. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 A cross-sectional view of a package assembly comprising one or more metal-insulator-metal (MIM) capacitors according to some embodiments is shown.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 Cross-sectional views of various intermediate stages in the formation of a capacitor according to some embodiments are shown.

[0009] Figure 17 A cross-sectional view of an intermediate stage in the formation of a capacitor according to some embodiments is shown. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, these spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0012] A capacitor and a method for forming the same are provided. According to some embodiments, the formation of a metal-insulator-metal (MIM) capacitor includes forming electrodes as a double-layer structure, the double-layer structure comprising an upper layer on top of a lower layer. The upper and lower layers can be formed from the same material, but deposited using two different deposition techniques. The upper layer material can be deposited using a deposition technique that improves the interface between the upper layer and the overlying insulating layer. In this way, the capacitor's sensitivity to subsequent processing (e.g., hydrogen annealing) can be reduced, thereby improving the capacitor's reliability.

[0013] The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1 A cross-sectional view of a package assembly 100 including one or more capacitors 146 according to some embodiments is shown. In some embodiments, the capacitor 146 may be a metal-insulator-metal (MIM) capacitor, etc. The package assembly 100 may be, for example, a device wafer, an interposer wafer, a package (e.g., an integrated fan-out (InFO) package, etc.). In the embodiments shown below, a device wafer is used as an example structure of the package assembly 100, but the capacitor 146 may be formed in other structures or other regions of the device wafer, such as in a rear-end redistribution structure of the device wafer. Therefore, it will be understood by those skilled in the art that the formation of the capacitor 146 as described herein is not limited to the examples shown and described in this disclosure. Figure 1 Three example capacitors, 146A, 146B, and 146C, are shown. For simplicity, as used herein, "capacitor 146" may refer to any or all of capacitors 146A through C, or... Figure 1 Other capacitors 146 not explicitly shown in the text.

[0015] refer to Figure 1 According to some embodiments, the packaging assembly 100 includes a substrate 110. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 110 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. In an alternative embodiment, substrate 110 is based on an insulating core, such as a glass fiber reinforced resin core or an organic core. The insulating core may include, for example, materials such as glass fiber resin, bismaleimide-triazine (BT) resin, printed circuit board (PCB) materials or films, laminated films such as Ajinomoto laminated film (ABF), other laminated materials, similar materials, or combinations thereof.

[0016] According to some embodiments, device 112 may be formed on or near the surface of substrate 110. Device 112 may be an integrated circuit device and may include active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.). Transistors may be, for example, planar field-effect transistors (FETs), FinFETs, nanostructured field-effect transistors (NSFETs, nanosheet FETs, etc.). Transistors may include n-type transistors (e.g., NFETs) and / or p-type transistors (e.g., PFETs). Other devices or combinations of devices are also possible.

[0017] According to some embodiments, the package assembly 100 may further include an interlayer dielectric (ILD) 114 and an interconnect structure 116 above a substrate 110. In some cases, the ILD 114 may surround and / or cover the device 112. The ILD 114 may include one or more dielectric layers formed of materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and similar materials or combinations thereof.

[0018] In some embodiments, the interconnect structure 116 includes conductive features formed in one or more dielectric layers 118, such as metallization patterns, redistribution layers, etc. In some cases, the one or more dielectric layers 118 may be intermetallic dielectric (IMD) layers. The interconnect structure 116 may be electrically connected to the device 112 to form functional circuitry. In some embodiments, the functional circuitry formed by the interconnect structure 116 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input / output circuitry, image sensor circuitry, and similar circuitry, or combinations thereof.

[0019] The dielectric layer 118 may comprise one or more layers of one or more suitable dielectric materials (e.g., silicon oxide, PSG, BSG, BPSG, USG, low-k materials, fluorosilicate glass (FSG), carbon-doped oxide (CDO), flowable oxide, polymers, and similar materials, or combinations thereof). In some cases, the material of one or more dielectric layers 118 may be similar to the material of ILD 114. The dielectric layer 118 may be deposited using any suitable technique (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), plasma-enhanced CVD (PECVD), flowable CVD (FCVD), spin coating, and similar techniques, or combinations thereof). Other materials or formation techniques are also possible.

[0020] The conductive features of the interconnect structure 116 may include, for example, wires 120, conductive vias 122, conductive pads 128, etc. In some embodiments, the conductive pads 128 are formed in the top dielectric layer 118 of the interconnect structure 116. Figure 1 The interconnect structure 116 shown is an example, and it should be understood that the interconnect structure 116 may include any number of dielectric layers 118 in which various conductive features are disposed. In some embodiments, the interconnect structure 116 may be formed as part of a back-end process (BEOL) or a mid-end process (MEOL). Suitable techniques (e.g., damascene, dual damascene, or other techniques) may be used to form the conductive features. In some embodiments, the conductive features may include a liner (not shown) (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like, or combinations thereof. The conductive material may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, and the like, or combinations thereof. Suitable techniques (e.g., ALD, CVD, PVD, plating, electroless plating, and similar techniques, or combinations thereof) may be used to deposit one or more materials of the conductive features. Other materials or formation techniques are also possible.

[0021] In some embodiments, a metal pad 130 is formed on and electrically coupled to the interconnect structure 116. The metal pad 130 can be electrically coupled to the device 112 via conductive pads 128, wires 120, and vias 122 of the interconnect structure 116. The metal pad 130 can be, for example, an aluminum pad or an aluminum-copper pad, but other materials are also possible. According to some embodiments, the metal pad 130 is in physical contact with conductive features of the underlying interconnect structure 116, which may include the topmost conductive features of the interconnect structure 116. For example, as... Figure 1 As shown, the metal pad 130 has a bottom surface that is in physical and electrical contact with the top surface of the conductive pad 128.

[0022] Still Figure 1 As shown, in some embodiments, a passivation layer 132 may be formed over the interconnect structure 116. In some embodiments, the passivation layer 132 is formed on the conductive pads 128 of the interconnect structure 116 and on the top dielectric layer 118. The passivation layer 132 may comprise one or more layers of dielectric material, such as USG, silicon oxide, silicon nitride, silicon oxynitride, non-porous dielectric material, low-k dielectric material, and similar materials or combinations thereof. Other materials or combinations of materials are also possible. One or more suitable techniques may be used to form the passivation layer 132. The passivation layer 132 is patterned such that the central portion of the metal pads 130 is exposed. In some embodiments, the edge portions of the metal pads 130 may remain covered by the passivation layer 132. In some embodiments, the passivation layer 132 and some top surfaces of the metal pads 130 are flush.

[0023] In some embodiments, a dielectric layer 136 is formed over metal pads 130 and passivation layer 132. In some embodiments, the dielectric layer 136 is formed of one or more polymeric materials, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In some cases, the polymeric material of the dielectric layer 136 may be photosensitive. In alternative embodiments, the dielectric layer 136 may be formed of one or more materials, such as silicon oxide, silicon nitride, PSG, BSG, BPSG, and similar materials, or combinations thereof. For example, the dielectric layer 136 may be formed by spin coating, lamination, CVD, etc. Other materials or techniques are also possible.

[0024] In some embodiments, a post-passivation interconnect (PPI) 138 may be formed on the dielectric layer 136. The PPI 138 may include, for example, a conductor portion on the top surface of the dielectric layer 136 and / or a conductive via portion extending into the dielectric layer 136. In some embodiments, the PPI 138 may be electrically connected to a metal pad 130. The PPI 138 may be formed of one or more conductive materials (e.g., copper, copper alloys, titanium, tungsten, aluminum, etc.). Other materials are also possible.

[0025] In some embodiments, dielectric layer 142 may be formed over dielectric layer 136 and PPI 138. Dielectric layer 142 may be formed of one or more materials similar to those previously described for dielectric layer 136. Dielectric layer 136 and dielectric layer 142 may be formed of the same(one or more) materials, or they may be formed of different materials.

[0026] In some embodiments, PPI 150 is formed over dielectric layer 142. PPI 150 may be electrically connected to PPI 138 and thus electrically connected to device 112. PPI 150 may include conductive features such as redistribution lines, metal pads, under-bump metallization (UBM), etc. According to some embodiments, dielectric layer 152 may be formed over PPI 150. Dielectric layer 152 may cover and / or surround the conductive features of PPI 150, and dielectric layer 152 may be in physical contact with the top surface of dielectric layer 142. Dielectric layer 152 may be formed of one or more materials similar to those previously described with respect to dielectric layer 136, or may be formed of other materials such as molding compounds, sealants, etc. Other materials are also possible.

[0027] According to some embodiments, a conductive connector 154 is formed on a PPI 150. The conductive connector 154 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. The conductive connector 154 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connector 154 is formed by first forming a solder layer through evaporation, electroplating, printing, solder transfer, solder ball placement, etc. After the solder layer is formed on this structure, reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 154 includes metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, and similar materials or combinations thereof, and may be formed by a plating process. In some embodiments, the conductive connector 154 may be surrounded or embedded in the dielectric layer 152. The conductive connector 154 may be formed before or after the deposition of the dielectric layer 152. In some embodiments, a monolithization process (e.g., a sawing process) may be performed to monolithize the structure into a single package assembly 100, each package assembly 100 including at least one capacitor 146. In some embodiments, the monolithized package assembly 100 is a device die, etc. The monolithization process may be performed before or after the formation of the conductive connector 154.

[0028] According to some embodiments, the encapsulation assembly 100 includes one or more capacitors 146. As previously described, the capacitors 146 are in... Figure 1 The capacitors 146A, 146B, and / or 146C are used in the designation. Capacitor 146 may be formed in one or more dielectric layers of the package assembly 100, such as dielectric layer 118 or dielectric layers 136 / 142 of the interconnect structure 116. In this way, capacitor 146 may be formed as part of a MEOL process and / or a BEOL process. Capacitor 146A refers to capacitor 146 formed in the upper dielectric layer 118 of the interconnect structure 116 (e.g., dielectric layer 118 at or near the top of the interconnect structure 116). Capacitor 146A may be formed below passivation layer 132, such as... Figure 1As shown. In some embodiments, capacitor 146A is electrically coupled to conductive pad 128. Capacitor 146B represents capacitor 146 formed in one or more dielectric layers 118 within interconnect structure 116. For example, capacitor 146B may be formed at or near the bottom or middle of interconnect structure 116. In some embodiments, capacitor 146B is electrically coupled to wire 120 or via 122 of interconnect structure 116. Capacitor 146C represents capacitor 146 formed on passivation layer 132 (e.g., in dielectric layer 136 and / or dielectric layer 142). In some embodiments, dielectric layer 136 and / or 142 may be polymer layers, as previously described. In some embodiments, capacitor 146C is electrically coupled to PPI 138 and / or PPI 150.

[0029] In some embodiments, capacitor 146 is electrically coupled to other features of the package assembly via vias or contact plugs that are physically and electrically in contact with one or more top electrodes and one or more bottom electrodes of capacitor 146. In some embodiments, capacitor 146 is a decoupling capacitor, wherein one or more top electrodes and one or more bottom electrodes of capacitor 146 are electrically coupled to power lines (e.g., VDD and VSS). In this way, capacitor 146 can be used to filter or suppress power supply noise, and / or can be used to reduce the effects of power supply voltage variations. According to alternative embodiments of this disclosure, one or more top electrodes and one or more bottom electrodes of capacitor 146 are connected to signal lines, and capacitor 146 is used to filter or suppress signal line noise. In other embodiments, capacitor 146 as described herein can be used in other structures or for other purposes. As a non-limiting example, capacitor 146 can be used in dynamic random access memory (DRAM) cells. Other structures or devices having capacitor 146 as described herein are also possible.

[0030] Figures 2 to 16 A capacitor 146 according to some embodiments is shown (see Figure 15 Cross-sectional views of the various intermediate stages in the formation of ). Figures 2 to 16 The process is similar to the formation Figure 1 The capacitor 146A is shown in the context of the present invention, but it should be understood that the techniques described herein can be applied to the formation of capacitor 146B, capacitor 146C, or other capacitors formed in other layers. In this way, Figures 2 to 16 The cross-sectional view can correspond to Figure 1 An enlarged view of a portion of the encapsulation component 100 (e.g., a portion of the interconnect structure 116).

[0031] Figure 15The capacitor 146 shown includes alternating electrode layers 212 (individually labeled as electrodes 212A, 212B, and 212C) and insulating layers 216 (individually labeled as insulators 216A and 216B). For example, Figure 15 The illustrated embodiment includes a first electrode 212A (e.g., "bottom electrode 212A"), a second electrode 212B (e.g., "middle electrode 212B"), and a third electrode 212C (e.g., "top electrode 212C"). Figure 15 The embodiments also include a first insulator 216A (e.g., "bottom insulator 216A") and a second insulator 216B (e.g., "top insulator 216B"). As used in this disclosure, the term "(one or more) electrodes 212" may refer to any or all of electrodes 212A to C, and the term "(one or more) insulators 216" may refer to any or all of insulators 216A to B. Figures 1 to 16 The capacitor 146 shown is an example, and other capacitors 146 with different configurations, layouts, numbers of layers (e.g., electrodes 212 and / or insulators 216) or different feature arrangements are also possible.

[0032] In some embodiments, each electrode 212 includes an upper electrode layer 211 over a lower electrode layer 210. For example, a first electrode 212A includes a first upper electrode layer 211A over a first lower electrode layer 210A, a second electrode 212B includes a second upper electrode layer 211B over a second lower electrode layer 210B, and a third electrode 212C includes a third upper electrode layer 211C over a third lower electrode layer 210C. As used in this disclosure, the term "(one or more) upper electrode layers 211" may refer to any one or all of the upper electrode layers 211A to C, and the term "(one or more) lower electrode layers 210" may refer to any one or all of the lower electrode layers 210A to C. In this way, the electrode 212 can be considered as a double layer. In some embodiments, the upper electrode layer 211 and the lower electrode layer 210 may comprise the same material. The upper electrode layers 211A to C and the lower electrode layers 210A to C are described in more detail below.

[0033] refer to Figure 2The diagram illustrates a conductive feature 202 in a dielectric layer 204 according to some embodiments. In some embodiments, the conductive feature 202 may resemble a conductive feature of interconnect structure 116, such as wire 120, via 122, or conductive pad 128. In other embodiments, the conductive feature 202 may resemble other features, such as metal pad 130, PPI 138, PPI 150, etc. In some embodiments, the conductive feature 202 may be formed within the dielectric layer 204, which may resemble the dielectric layer 118 of interconnect structure 116. For example, the dielectric layer 204 may include silicon oxide, silicon nitride, etc. In other embodiments, the dielectric layer 204 may resemble another dielectric layer, such as dielectric layer 136, dielectric layer 142, etc. For example, in some embodiments, the dielectric layer 204 may include a polymer. Other materials are also possible. The portion of the package assembly 100 below the conductive feature 202 is indicated as feature 201. Details of feature 201 are not shown and may be similar to those previously indicated for… Figure 1 The described features. For example, feature 201 may include or represent conductive features, active devices, passive devices, and similar features, or combinations thereof.

[0034] According to some embodiments, an etch stop layer 206 and a dielectric layer 208 are formed over the conductive feature 202 and the dielectric layer 204. The etch stop layer 206 is an optional layer and in some cases may comprise one or more layers of dielectric material having a lower etch rate than the underlying dielectric layer 204 and / or the overlying dielectric layer 208. In some embodiments, the etch stop layer 206 may comprise one or more layers of materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and similar materials, or combinations thereof. The etch stop layer 206 can be formed using suitable techniques (e.g., CVD, PECVD, LPCVD, PVD, ALD, etc.). Other materials or formation techniques are also possible.

[0035] The dielectric layer 208 may be formed of one or more materials similar to those previously described for dielectric layers 204, 118, or 136 / 142, and may be formed using similar techniques. For example, in some embodiments, the dielectric layer 208 comprises silicon nitride, silicon oxide, silicon oxynitride, etc. Other materials are also possible. The dielectric layer 208 may be the same material as the underlying dielectric layer 204, or it may be a different material.

[0036] exist Figure 3In some embodiments, a first lower electrode layer 210A is deposited on top of a dielectric layer 208. In some embodiments, prior to the deposition of the first lower electrode layer 210A, the dielectric layer 208 is thinned using a planarization process such as chemical mechanical polishing (CMP). The first lower electrode layer 210A may be formed of one or more conductive materials, such as titanium nitride, tantalum nitride, other metal nitrides, titanium, tungsten, platinum, iridium, ruthenium, ruthenium oxide (e.g., RuO2), and combinations thereof. In some embodiments, the first lower electrode layer 210A is formed of layers of different materials, such as two or more layers including titanium nitride, tantalum nitride, titanium, tungsten, etc. For example, in some embodiments, the first lower electrode layer 210A includes a titanium or tungsten layer on top of a titanium nitride or tantalum nitride layer. Other combinations of layers or materials are also possible.

[0037] The first lower electrode layer 210A can be deposited as a uniform thickness layer and can be deposited using a suitable technique such as PVD. In some embodiments, the first lower electrode layer 210A is deposited using a PVD process having a process temperature in the range of about 250°C to about 350°C, a process pressure in the range of about 10 mTorr to about 250 mTorr, or a bias power in the range of about 50 W to about 80 W. Other process conditions are also possible. For example, in some embodiments, the first lower electrode layer 210A is a titanium nitride layer deposited using a PVD process. In some embodiments, the deposited titanium nitride layer has a thickness of about 5 g / cm³. 3 Approximately 6g / cm 3 The density is within the range of about 80 Ω·m to about 110 Ω·m, the resistivity is within the range of about 6:1 to about 7:1, and the ratio of (200) crystal orientation to (111) crystal orientation is within the range of about 6:1 to about 7:1. However, other material properties are possible, and other materials are also possible. In some embodiments, the first lower electrode layer 210A may have a density within the range of about 80 Ω·m to about 110 Ω·m, the resistivity is within the range of about 80 Ω·m to about 110 Ω·m, and the ratio of (200) crystal orientation to (111) crystal orientation is within the range of about 6:1 to about 7:1. to approximately The thickness T1 is within the range, but other thicknesses are also possible.

[0038] exist Figure 4In some embodiments, a first upper electrode layer 211A is deposited on top of a first lower electrode layer 210A. A first electrode 212A is then formed as a bilayer of the first upper electrode layer 211A and the first lower electrode layer 210A, as will be described in more detail below. The first upper electrode layer 211A may be formed of one or more conductive materials similar to those previously described for the first lower electrode layer 210A. For example, in some embodiments, the first upper electrode layer 211A may be a material such as titanium nitride, tantalum nitride, other metal nitrides, etc. In some embodiments, the first upper electrode layer 211A is formed of the same or similar material as the underlying first lower electrode layer 210A. For example, in some embodiments, both the first upper electrode layer 211A and the first lower electrode layer 210A are titanium nitride, but other materials are also possible. In embodiments where the first lower electrode layer 210A is formed of two or more layers of different materials, in some cases, the first upper electrode layer 211A may be formed of one of the materials of the first lower electrode layer 210A. For example, in an embodiment where the first lower electrode layer 210A comprises a titanium or tungsten layer over a titanium nitride or tantalum nitride layer, the first upper electrode layer 211A may be either a titanium nitride or tantalum nitride layer. Other combinations of layers or materials are also possible. In other embodiments, the first upper electrode layer 211A and the first lower electrode layer 210A may be made of different materials or may have different material compositions.

[0039] In some embodiments, the first upper electrode layer 211A may be deposited as a uniform thickness layer and may be deposited using a suitable technique such as ALD. In some embodiments, the first upper electrode layer 211A is deposited using a different deposition technique than the underlying first lower electrode layer 210A. For example, in some embodiments, the first lower electrode layer 210A is a material deposited using a PVD process, while the first upper electrode layer 211A is the same material deposited using an ALD process. For example, in some embodiments, the first lower electrode layer 210A is a titanium nitride layer deposited using a PVD process, while the first upper electrode layer 211A is a titanium nitride layer deposited using an ALD process. Other materials or deposition techniques are also possible. In some cases, using two deposition processes to deposit the electrode 212 material as a bilayer can improve the reliability of the capacitor 146, as will be described in more detail below.

[0040] In some embodiments, the first upper electrode layer 211A is deposited using an ALD process with a process temperature in the range of about 300°C to about 400°C, but other process conditions are also possible. For example, in some embodiments, the first upper electrode layer 211A is a titanium nitride layer deposited using an ALD process. In some embodiments, the deposited titanium nitride layer has a temperature of about 4 g / cm³. 3 Approximately 5g / cm 3The density is within the range of about 800 Ω·m to about 900 Ω·m, the resistivity is within the range of about 1:1 to about 1.5:1, and the ratio of (200) crystal orientation to (111) crystal orientation is within the range of about 1:1 to about 1.5:1. However, other material properties are possible, and other materials are also possible. The first upper electrode layer 211A may have a thickness T2 that is smaller than the thickness T1 of the first lower electrode layer 210A. In some embodiments, the first upper electrode layer 211A may have a thickness T2 in the range of about 30 to about 50, but other thicknesses are also possible. In some cases, the thickness T2 is between about 30 and 50. The thickness T2 within this range protects the first lower electrode layer 210A and the first upper electrode layer 211A from damage during the subsequent high-pressure annealing (HPA) process, as described in more detail below. In this way, the reliability window of the double-layer electrodes (e.g., electrodes 212A to C described below) can be increased.

[0041] exist Figure 5 In some embodiments, a first lower electrode layer 210A and a first upper electrode layer 211A are patterned to form a first electrode 212A. Suitable photolithography and etching techniques can be used to pattern the first lower electrode layer 210A and the first upper electrode layer 211A. For example, an etching mask (not shown) can be formed over the first upper electrode layer 211A. The etching mask can be formed, for example, by forming a mask layer over the first upper electrode layer 211A and then patterning that mask layer. The mask layer can be, for example, a photoresist, a multilayer photoresist structure, a hard mask material, etc. Suitable photolithography techniques can be used to pattern the mask layer to form the etching mask. The pattern of the etching mask corresponds to the pattern of the subsequently formed first electrode 212A.

[0042] According to some embodiments, an etching mask is then used to etch the first lower electrode layer 210A and the first upper electrode layer 211A to form the first electrode 212A. In other embodiments, two or more first electrodes 212A may be formed from the first lower electrode layer 210A and the first upper electrode layer 211A. Etching may include any acceptable etching process, such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), and similar processes, or combinations thereof. Etching may be anisotropic. In some cases, etching may etch through both the first lower electrode layer 210A and the first upper electrode layer 211A and stop at the dielectric layer 208. Etching may expose the top surface of the dielectric layer 208. After patterning the first lower electrode layer 210A and the first upper electrode layer 211A to form the first electrode 212A, the etching mask may be removed using an acceptable process (e.g., ashing).

[0043] Figure 6The formation of a first insulator 216A over a first electrode 212A according to some embodiments is illustrated. The first insulator 216A may comprise one or more insulating materials having a high dielectric constant (e.g., high k) to achieve a large capacitance value in the resulting capacitor 146. For example, in some embodiments, the first insulator 216A may comprise hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO2, ZrO3, etc.), hafnium zirconium oxide (e.g., HfZrO), aluminum oxide (e.g., Al2O3), and the like, combinations thereof, or multiples thereof. The first insulator 216A may be deposited as a conformal layer (e.g., a uniform thickness layer) using suitable techniques such as ALD, CVD, etc. Thus, in some embodiments, the first insulator 216A is deposited on the top surface of the first electrode 212A and the top surface of the dielectric layer 208.

[0044] exist Figure 7 In some embodiments, a second lower electrode layer 210B and a second upper electrode layer 211B are formed on a first insulator 216A. The second lower electrode layer 210B may be similar to the first lower electrode layer 210A and may be formed using similar materials or techniques. The second upper electrode layer 211B may be similar to the first upper electrode layer 211A and may be formed using similar materials or techniques. In some embodiments, the second lower electrode layer 210B and the second upper electrode layer 211B may be the same material formed using different deposition techniques, similar to the first lower electrode layer 210A and the first upper electrode layer 211A. For example, in some embodiments, the second lower electrode layer 210B may be titanium nitride formed using a PVD process, while the second upper electrode layer 211B may be titanium nitride formed using an ALD process. In other embodiments, the second lower electrode layer 210B may comprise two or more layers of different materials. Other materials or deposition techniques are also possible.

[0045] exist Figure 8 In some embodiments, the second lower electrode layer 210B and the second upper electrode layer 211B are patterned to form the second electrode 212B. Suitable photolithography and etching techniques can be used to pattern the second lower electrode layer 210B and the second upper electrode layer 211B. In other embodiments, two or more second electrodes 212B may be formed from the second lower electrode layer 210B and the second upper electrode layer 211B. Patterning the second lower electrode layer 210B and the second upper electrode layer 211B can expose the top surface of the first insulator 216A.

[0046] exist Figure 9In some embodiments, a second insulator 216B is formed on the second electrode 212B and the first insulator 216A. The second insulator 216B can be similar to the first insulator 216A and can be formed using similar materials or techniques. For example, the second insulator 216B may comprise one or more materials having a high dielectric constant (e.g., high k) and can be formed using conformal deposition techniques.

[0047] exist Figure 10 In some embodiments, a third lower electrode layer 210C and a third upper electrode layer 211C are formed on a second insulator 216B. The third lower electrode layer 210C may be similar to the first lower electrode layer 210A and / or the second lower electrode layer 210B, and may be formed using similar materials or techniques. The third upper electrode layer 211C may be similar to the first upper electrode layer 211A and / or the second upper electrode layer 211B, and may be formed using similar materials or techniques. In some embodiments, the third lower electrode layer 210C and the third upper electrode layer 211C may be the same material formed using different deposition techniques, similar to the first lower electrode layer 210A and the first upper electrode layer 211A. For example, in some embodiments, the third lower electrode layer 210C may be titanium nitride formed using a PVD process, while the third upper electrode layer 211C may be titanium nitride formed using an ALD process. In other embodiments, the third lower electrode layer 210C may comprise two or more layers of different materials. Other materials or deposition techniques are also possible.

[0048] exist Figure 11 In some embodiments, the third lower electrode layer 210C and the third upper electrode layer 211C are patterned to form the third electrode 212C. Suitable photolithography and etching techniques can be used to pattern the third lower electrode layer 210C and the third upper electrode layer 211C. In other embodiments, two or more third electrodes 212C may be formed from the third lower electrode layer 210C and the third upper electrode layer 211C. Patterning the third lower electrode layer 210C and the third upper electrode layer 211C can expose the top surface of the second insulator 216B. In other embodiments, additional insulating layers and / or additional electrode layers may be deposited, which may be similar in materials or deposition techniques to those described above for electrodes 212A to C or insulators 216A to B.

[0049] exist Figure 12In some embodiments, a dielectric layer 220 is deposited on the third electrode 212C and the second insulator 216B. The dielectric layer 220 may be formed of one or more materials similar to those previously described for dielectric layers 204, 118, or 136 / 142, and may be formed using similar techniques. For example, in some embodiments, the dielectric layer 220 includes silicon nitride, silicon oxynitride, polymers, etc. Other materials are also possible. The dielectric layer 220 may be the same material as the dielectric layer 208, or it may be a different material. In some embodiments, a planarization process, such as a CMP process or a polishing process, is performed on the dielectric layer 220.

[0050] Figure 13 , Figure 14 and Figure 15 Cross-sectional views are shown of various intermediate steps in the formation of the contact plug 226 and the wire 228 according to some embodiments. Figure 13 In some embodiments, the contact opening 222 is formed to expose the surfaces of electrodes 212A to C and the surface of conductive feature 202. In other embodiments, the opening 222 may expose only the surfaces of electrodes 212A to C, without exposing the surface of conductive feature 202. The opening 222 may be formed, for example, by performing one or more etching processes using an etching mask 221. The etching mask 221 may be, for example, a photoresist, a photoresist structure, a hard mask, etc. The etching mask 221 may be patterned using suitable photolithography and etching techniques.

[0051] The etching mask 221 can then be used to perform one or more etching processes to form an opening 222 extending through the dielectric layer 220, electrodes 212A to C, and insulators 216A to B. In some embodiments, the opening 222 may also extend through the dielectric layer 208 and the etch stop layer 206. The opening 222 exposes the sidewalls of electrodes 212A to C and may expose the top surface of the conductive feature 202. The one or more etching processes may include wet etching processes and / or dry etching processes. The one or more etching processes may be anisotropic. In some cases, different etching processes may be used to etch different materials. This is an example, and in other embodiments, other techniques or etching processes may be used to form the opening 222. After the opening 222 has been etched, the etching mask 221 may be removed using a suitable process, such as an ashing process or an etching process.

[0052] exist Figure 14In some embodiments, a seed layer 224 and a plating mask 225 are formed. The seed layer 224 is formed over the dielectric layer 220 and in the opening 222. The seed layer 224 can be in physical and electrical contact with the surfaces of the electrodes 212A to C and / or the conductive features 202 exposed by the opening 222. In some embodiments, the seed layer 224 is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer 224 comprises a titanium layer and a copper layer above the titanium layer, but other materials are also possible. The seed layer 224 can be formed using, for example, PVD, CVD, metal-organic chemical vapor deposition (MOCVD), etc. The plating mask 225 is then formed on the seed layer 224 and patterned thereon. The plating mask 225 can be, for example, a photoresist, a photoresist structure, a hard mask, etc. The plating mask 225 can be patterned using a suitable photolithography technique. The pattern of the coating mask 225 can expose the seed layer 224 in and around the opening 222.

[0053] exist Figure 15 In some embodiments, conductive material is deposited in opening 222 to form contact plug 226 and wire 228. The conductive material may be formed on the exposed portion of the patterned plating mask 225 of the seed layer 224. The conductive material may be formed by plating (e.g., electroplating, electroless plating, etc.). The conductive material may include metals such as copper, titanium, nickel, tungsten, aluminum, and their alloys. The combination of the conductive material and the lower portion of the seed layer 224 forms the contact plug 226 and wire 228. The portion of the conductive material and seed layer 224 below the top surface of the dielectric layer 220 may be considered the contact plug 226, and the portion of the conductive material and seed layer 224 above or along the top surface of the dielectric layer 220 may be considered the wire 228. In some cases, the contact plug 226 and wire 228 may be portions of continuous conductive features. In some embodiments, the contact plug 226 and / or the wire 228 may resemble the conductive features or other conductive features of the interconnect structure 116 of the package assembly 100. The contact plug 226 is physically and electrically in contact with the conductive feature 202, and in some cases, the contact plug 226 may be considered a via. The contact plug 226 is also physically and electrically in contact with electrodes 212A to C. In this way, according to some embodiments, a capacitor 146 can be formed. Figure 15 As shown, capacitor 146 may include a stack of interdigitated electrodes 212, wherein each electrode 212 is separated from each adjacent electrode 212 by an insulating layer 216.

[0054] exist Figure 16In some embodiments, plating mask 225 is removed and an optional passivation layer 230 is formed. The plating mask 225 and the underside of seed layer 224 can be removed using, for example, ashing and / or etching processes. In some embodiments, passivation layer 230 can then be deposited over dielectric layer 220 and conductor 228. Passivation layer 230 can be formed of one or more materials similar to those previously described for dielectric layer 220, dielectric layer 204, dielectric layer 118, or dielectric layers 136 / 142, and can be formed using similar techniques. For example, in some embodiments, passivation layer 230 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, polymers, and the like, or combinations thereof. Other materials are also possible. Passivation layer 230 can be the same material as dielectric layer 220, or it can be a different material. In this way, a capacitor 146 with double-layer electrodes 212 can be formed, but the capacitor 146 can have different configurations, or can be formed using other manufacturing steps in other embodiments.

[0055] In some cases, thermal processing can be performed on package assembly 100. Thermal processing can be performed at any suitable process step, such as during the formation of capacitor(s)(146) (e.g., at...). Figures 11 to 15 After any of them), or after the formation of capacitor(s) 146 (e.g., in Figure 16 Afterwards or Figure 1 (Afterwards). In some cases, the thermal process may include a high-pressure annealing (HPA) process, in which the structure is annealed in a pressurized environment. For example, an HPA process may be performed using a 100% hydrogen (e.g., H2) environment at a pressure between about 10 atm and about 30 atm. Other pressures or environmental compositions are also possible. HPA processes may include process temperatures between about 350°C and about 450°C and may have durations between about 15 minutes and about 60 minutes, but other process parameters are also possible. In some cases, an HPA process may be performed, for example, to reduce defects in the channel region of the p-type transistor (e.g., PFET) in device 112 of package assembly 100. However, during the HPA process, hydrogen can displace oxygen at or near the interface between the electrode and insulator in a MIM capacitor. This creates oxygen vacancies at or near the electrode-insulator interface, which can severely degrade capacitor reliability (e.g., reduce lifetime). For example, in some cases, HPA annealing can reduce the capacitor lifetime to less than 1% of its expected lifetime before HPA annealing.

[0056] In some cases, forming capacitor electrodes from a bilayer of a single material as described herein can reduce the impact of the HPA process and improve the reliability of capacitors subjected to the HPA process. As an example, in some cases, the interface between the electrode, comprising titanium nitride, and the insulator (e.g., insulator 216) may include oxygen bonds (e.g., Ti-O bonds), which may be disrupted or broken by hydrogen displacement during the HPA process. In other words, the capacitor may have an interface layer between the electrode and the insulator comprising titanium oxynitride, and the HPA process may damage this interface layer. However, titanium nitride grown using ALD (e.g., "ALD TiN") can form more and / or stronger oxygen bonds with the insulator compared to titanium nitride grown using PVD (e.g., "PVDTiN"). The greater number and / or stronger oxygen bonds formed with ALD TiN compared to PVD TiN can reduce the amount of broken bonds and oxygen vacancies generated by the HPA process. Therefore, since the electrodes described herein are formed from an upper ALD TiN electrode layer on top of a lower PVD TiN electrode layer, the interface between the electrode and the overlying insulator is a relatively more robust interface between the ALD TiN of the electrode and the insulator. In other words, depositing an ALD TiN layer can improve device reliability by improving the electrode-insulator interface. In this way, undesirable effects caused by thermal processes such as HPA processes can be reduced or eliminated in the capacitor, and the reliability window of the capacitor can be increased.

[0057] Figure 17 A capacitor 146' comprising three layers of second electrodes 212B' is shown according to some embodiments. The capacitor 146' is similar to... Figure 16 The capacitor 146' has a second electrode 212B' comprising an intermediate electrode layer 210B' sandwiched between a lower electrode layer 211B-1' and an upper electrode layer 211B-2'. Additionally, the third electrode 212C' of the capacitor 146' comprises an electrode layer 210C' above the electrode layer 211C'. Similar to those used for... Figures 2 to 16 The materials or techniques used to form capacitor 146 are described, and some details may not be repeated.

[0058] In some embodiments, firstly, using a method similar to that used for Figures 1 to 6The steps described are used to form capacitor 146'. For example, the first electrode 212A may be a bilayer formed of a first upper electrode layer 211A over a first lower electrode layer 210A and a first insulator 216A over the first electrode 212A. After forming the first insulator 216A, a lower electrode layer 211B-1' is formed over the first insulator 216A. The lower electrode layer 211B-1' may be similar to the upper electrode layer 211 previously described for capacitor 146. For example, in some embodiments, the lower electrode layer 211B-1' may be an ALD titanium nitride (TiN) layer. An intermediate electrode layer 210B' may then be formed over the lower electrode layer 211B-1'. The intermediate electrode layer 210B' may be similar to the lower electrode layer 210 previously described for capacitor 146. An upper electrode layer 211B-2' is formed over the intermediate electrode layer 210B'. The upper electrode layer 211B-2' can be similar to the lower electrode layer 211b-1'. ​​The upper electrode layer 211B-2', the intermediate electrode layer 210B', and the lower electrode layer 211B-1' can be patterned to form the second electrode 212B'. In this way, the second electrode 212B' can be a three-layer electrode formed by the upper electrode layer 211B-2', the intermediate electrode layer 210B', and the lower electrode layer 211B-1'.

[0059] After forming the second electrode 212B', a second insulator 216B is deposited. The second insulator 216B can be similar to the second insulator 216B of capacitor 146. An electrode layer 211C' can be deposited on the second insulator 216B. The electrode layer 211C' can be similar to a first upper electrode layer 211A, a lower electrode layer 211B-1', or an upper electrode layer 211B-2'. For example, in some embodiments, the electrode layer 211C' can be an ALD titanium nitride (TiN) layer. An electrode layer 210C' can then be formed on the electrode layer 211C'. The electrode layer 210C' can be similar to an intermediate electrode layer 210B' or a first lower electrode layer 210A. The electrode layers 211C' and 210C' can be patterned to form a bilayer third electrode 212C'. In this manner, the first upper electrode layer 211A is located at the interface between the first electrode 212A and the insulator 216A, the lower electrode layer 211B-1' is located at the interface between the second electrode 212B' and the insulator 216A, the upper electrode layer 211B-2' is located at the interface between the second electrode 212B' and the insulator 216B, and the electrode layer 211C' is located at the interface between the third electrode 212C' and the insulator 216B. Therefore, in some embodiments, the ALD TiN layer may be present at the interface between electrodes 212A / 212B' / 212C' and insulators 216A / 216B. Forming the ALD TiN layer at the interface between electrodes 212A / 212B' / 212C' and insulators 216A / 216B can improve device reliability and reduce damage to capacitor 146' during the HPA process.

[0060] Based on time-related dielectric breakdown (TDDB) measurements, using an ALD TiN layer as described herein can improve the reliability of the capacitor after the HPA process. For example, some TDDB measurements indicate that the expected lifetime of the capacitor after the HPA process can range from approximately 80 years to approximately 2500 years. This is an example from experimental results, and other reliability metrics or expected lifetimes are also possible. In some cases, the ALD TiN upper layer can be deposited as a thin layer on top of the PVD TiN lower layer, such that the interfacial properties of the electrode are dominated by the ALD TiN, but the bulk electrical properties of the electrode are dominated by the PVD TiN. Although titanium nitride is used as an example for illustrative purposes, other materials, such as those previously described for electrode 212, can be used in accordance with the teachings of this document.

[0061] In one embodiment, a method includes: forming a first electrode, including depositing a first conductive material layer and depositing a second conductive material layer on the first conductive material layer; forming a first insulating layer on the second conductive material layer; and forming a second electrode, including depositing a third conductive material layer on the first insulating layer and depositing a fourth conductive material layer on the third conductive material layer. In another embodiment, forming the second electrode further includes depositing a fifth conductive material layer on the first insulating layer. In another embodiment, the method includes annealing the first insulating layer in a hydrogen environment. In another embodiment, the second conductive material layer has a higher resistivity than the first conductive material layer. In another embodiment, a first deposition process is used to deposit the first and third conductive material layers, and a second deposition process is used to deposit the second and fourth conductive material layers. In another embodiment, the first deposition process is a physical vapor deposition (PVD) process, and the second deposition process is an atomic layer deposition (ALD) process. In yet another embodiment, the method includes: forming a second insulating layer on the fourth conductive material layer; and forming a third electrode, including depositing a sixth conductive material layer on the second insulating layer; and depositing a seventh conductive material layer on the fifth conductive material layer. In an embodiment, the second conductive material has a thickness in the range of 30 to 50.

[0062] In one embodiment, a method includes: performing a first deposition process to deposit a first electrode layer on a substrate, wherein the first electrode layer is a first conductive material; performing a second deposition process to deposit a second electrode layer on the first electrode layer, wherein the second electrode layer is the first conductive material, wherein the second deposition process is different from the first deposition process; depositing an insulating material on the second electrode layer; performing a first deposition process to deposit a third electrode layer on the insulating material, wherein the third electrode layer is the first conductive material; performing a second deposition process to deposit a fourth electrode layer on the third electrode layer, wherein the fourth electrode layer is the first conductive material; and performing a high-pressure annealing (HPA) process on the substrate. In another embodiment, the method includes depositing a fifth electrode layer between the first and second electrode layers, wherein the fifth electrode layer is a second conductive material. In another embodiment, the second conductive material is tungsten. In another embodiment, the first conductive material is tantalum nitride. In another embodiment, the first deposition process is a physical vapor deposition (PVD) process. In another embodiment, the second deposition process is an atomic layer deposition (ALD) process. In another embodiment, the second electrode layer has a larger (200) crystal orientation ratio than the first electrode layer.

[0063] In one embodiment, a structure includes a dielectric layer sandwiched between a first electrode and a second electrode, wherein each of the first and second electrodes comprises a first conductive material layer and a second conductive material layer on top of the first conductive material layer, wherein the first layer has a higher density than the second layer; a first contact plug electrically contacts the first electrode; and a second contact plug electrically contacts the second electrode. In one embodiment, the second layer is thinner than the first layer. In another embodiment, the structure includes an interface layer between the dielectric layer and the second layer of the first electrode, wherein the interface layer comprises oxygen. In one embodiment, the conductive material is titanium nitride. In one embodiment, the density of the second layer is 4 g / cm³. 3 Up to 5g / cm 3 Within the range.

[0064] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein.

[0065] Example 1 is a method for forming a capacitor structure, comprising: forming a first electrode, including: depositing a first layer of conductive material; and depositing a second layer of conductive material on the first layer of conductive material; forming a first insulating layer on the second layer of conductive material; and forming a second electrode, including: depositing a third layer of conductive material on the first insulating layer; and depositing a fourth layer of conductive material on the third layer of conductive material.

[0066] Example 2 is the method described in Example 1, wherein forming the second electrode further includes depositing a fifth layer of conductive material on top of the first insulating layer.

[0067] Example 3 is the method of Example 1, further comprising: annealing the first insulating layer in a hydrogen environment.

[0068] Example 4 is the method described in Example 1, wherein the second conductive layer has a higher resistivity than the first conductive layer.

[0069] Example 5 is the method described in Example 1, wherein a first deposition process is used to deposit the first conductive layer and the third conductive layer, and wherein a second deposition process is used to deposit the second conductive layer and the fourth conductive layer.

[0070] Example 6 is the method described in Example 1, wherein the first deposition process is a physical vapor deposition (PVD) process, and the second deposition process is an atomic layer deposition (ALD) process.

[0071] Example 7 is the method of Example 1, further comprising: forming a second insulating layer on the fourth conductive material; and forming a third electrode, comprising: depositing a sixth conductive material on the second insulating layer; and depositing a seventh conductive material on the fifth conductive material.

[0072] Example 8 is the method described in Example 1, wherein the second layer of conductive material has in to Thickness within the range.

[0073] Example 9 is a method for forming a capacitor structure, comprising: performing a first deposition process to deposit a first electrode layer on a substrate, wherein the first electrode layer is a first conductive material; performing a second deposition process to deposit a second electrode layer on the first electrode layer, wherein the second electrode layer is the first conductive material, wherein the second deposition process is different from the first deposition process; depositing an insulating material on the second electrode layer; performing the first deposition process to deposit a third electrode layer on the insulating material, wherein the third electrode layer is the first conductive material; performing the second deposition process to deposit a fourth electrode layer on the third electrode layer, wherein the fourth electrode layer is the first conductive material; and performing a high-voltage annealing (HPA) process on the substrate.

[0074] Example 10 is the method of Example 9, further comprising: depositing a fifth electrode layer between the first electrode layer and the second electrode layer, wherein the fifth electrode layer is a second conductive material.

[0075] Example 11 is the method described in Example 10, wherein the second conductive material is tungsten.

[0076] Example 12 is the method described in Example 9, wherein the first conductive material is tantalum nitride.

[0077] Example 13 is the method described in Example 9, wherein the first deposition process is a physical vapor deposition (PVD) process.

[0078] Example 14 is the method described in Example 9, wherein the second deposition process is an atomic layer deposition (ALD) process.

[0079] Example 15 is the method described in Example 9, wherein the second electrode layer has a larger (200) crystal orientation ratio than the first electrode layer.

[0080] Example 16 is a capacitor structure comprising: a dielectric layer sandwiched between a first electrode and a second electrode, wherein the first electrode and the second electrode each comprise: a first layer of conductive material; and a second layer of conductive material on the first layer of conductive material, wherein the first layer has a greater density than the second layer; a first contact plug electrically contacting the first electrode; and a second contact plug electrically contacting the second electrode.

[0081] Example 17 is the structure described in Example 16, wherein the second layer is thinner than the first layer.

[0082] Example 18 is the structure described in Example 16, further comprising: an interface layer between the dielectric layer and the second layer of the first electrode, wherein the interface layer comprises oxygen.

[0083] Example 19 is the structure described in Example 16, wherein the conductive material is titanium nitride.

[0084] Example 20 is the structure described in Example 16, wherein the second layer has a concentration of 4 g / cm³. 3 Up to 5g / cm 3 Density within the range.

Claims

1. A method for forming a capacitor structure, comprising: Forming the first electrode includes: Depositing the first layer of conductive material; and A second layer of conductive material is deposited on the first layer of conductive material; A first insulating layer is formed on the second conductive material; and Forming the second electrode includes: Deposit a third conductive material layer on the first insulating layer; and A fourth layer of conductive material is deposited on the third layer of conductive material.

2. The method according to claim 1, wherein, Forming the second electrode further includes depositing a fifth layer of conductive material on top of the first insulating layer.

3. The method according to claim 1, further comprising: The first insulating layer is annealed in a hydrogen environment.

4. The method according to claim 1, wherein, The second conductive layer has a higher resistivity than the first conductive layer.

5. The method according to claim 1, wherein, A first deposition process is used to deposit the first conductive layer and the third conductive layer, and a second deposition process is used to deposit the second conductive layer and the fourth conductive layer.

6. The method according to claim 1, wherein, The first deposition process is physical vapor deposition (PVD), and the second deposition process is atomic layer deposition (ALD).

7. The method according to claim 1, further comprising: A second insulating layer is formed on the fourth conductive material; as well as Forming the third electrode includes: A sixth layer of conductive material is deposited on the second insulating layer; as well as A seventh layer of conductive material is deposited on the fifth layer of conductive material.

8. The method according to claim 1, wherein, The second layer of conductive material has in to Thickness within the range.

9. A method for forming a capacitor structure, comprising: A first deposition process is performed to deposit a first electrode layer on a substrate, wherein the first electrode layer is a first conductive material; A second deposition process is performed to deposit a second electrode layer on the first electrode layer, wherein the second electrode layer is the first conductive material, and wherein the second deposition process is different from the first deposition process; An insulating material is deposited on the second electrode layer; Perform the first deposition process to deposit a third electrode layer on the insulating material, wherein the third electrode layer is the first conductive material; Perform the second deposition process to deposit a fourth electrode layer on the third electrode layer, wherein the fourth electrode layer is the first conductive material; and The substrate is subjected to a high-pressure annealing (HPA) process.

10. A capacitor structure, comprising: A dielectric layer is sandwiched between a first electrode and a second electrode, wherein the first electrode and the second electrode each comprise: The first layer of conductive material; and A second conductive material on top of a first conductive material, wherein the first layer has a greater density than the second layer; The first contact plug makes electrical contact with the first electrode; and The second contact plug makes electrical contact with the second electrode.

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