LED chip, manufacturing method thereof and semiconductor light-emitting device

Abstract

The invention provides an LED chip, a manufacturing method thereof and a semiconductor light-emitting device, a current confinement layer is formed on the side wall of a semiconductor epitaxial laminated layer, and the current confinement layer at least covers the side wall of an active layer along the stacking direction of the semiconductor epitaxial laminated layer. The current confinement layer can be bonded with the unsaturated bond at the side wall of the semiconductor epitaxial laminated layer to form a heterogeneous interface with a continuous crystal configuration, so that current can be effectively prevented from diffusing to the side wall by regulating and controlling the conductivity of the current confinement layer, carriers are further prevented from diffusing to the side wall of the semiconductor epitaxial laminated layer, and the service life of the semiconductor epitaxial laminated layer is prolonged. According to the micro LED chip, the potential well non-radiation deep energy level generated by unsaturated bonds and impurities on the surface of the side wall of the semiconductor epitaxial lamination layer is greatly reduced, non-radiation recombination of carriers at the defect position of the surface of the side wall is reduced, the carriers are limited in the chip for composite light emitting, the internal quantum efficiency of the micro LED is improved, and the light emitting efficiency of the chip is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more specifically, to an LED chip, a method for manufacturing the same, and a semiconductor light-emitting device. Background Technology

[0002] LED chips have seen rapid development in the lighting field as a light source. Among them, micro LED chips (side length ≤100μm) have been applied in display, optical communication, indoor positioning, biological and medical fields due to their advantages such as self-illumination, high efficiency, low power consumption, high brightness, high stability and long life. They are also being further expanded into wearable / implantable devices, augmented / virtual reality, automotive displays, ultra-large displays, optical communication / optical interconnection, medical detection, smart car lights and spatial imaging.

[0003] As the performance of devices improves, the size of Micro LEDs needs to be continuously reduced. In particular, when the chip size is less than 20 μm, it is difficult to design the N and P electrodes as a horizontal structure on the same side. A vertical structure with upper and lower electrodes is generally adopted. Due to the high absorption of photons by the light-emitting electrode, the photon loss in the normal direction of the light-emitting surface is extremely high. Only a portion of the photons are emitted from the sidewall and the angle is diverged. Therefore, microlenses are often used in the chip process to focus the emitted beam to improve the light extraction efficiency.

[0004] During chip fabrication, processes such as etching and resist removal using plasma and chemical etching solutions can cause irreversible damage to the semiconductor stacked layers on the chip sidewalls. For example, after etching, impurity elements other than those forming the semiconductor stack can be directly introduced into the sidewalls. These impurity elements parasitize the chip sidewalls due to unsaturated bonding on the sidewall surface, forming a series of deep-level defects. Furthermore, for AlGaInP semiconductor stacks with larger carrier diffusion lengths and higher defect recombination rates, the nonradiative recombination of surface defects caused by carriers transported to the chip sidewalls leads to a rapid decrease in the internal quantum efficiency of Micro LEDs, severely affecting their light extraction efficiency.

[0005] Based on the above, in order to address the problem of insufficient luminous efficiency of Micro LEDs, it is necessary to develop an effective sidewall treatment technology to reduce the chip luminous efficiency degradation caused by sidewall defects. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide an LED chip, a method for manufacturing the same, and a semiconductor light-emitting device. The present invention forms an opening extending along the growth direction in a semiconductor epitaxial stack to at least expose the sidewalls of the active layer of the semiconductor epitaxial stack. A current-constraining layer is formed on the exposed sidewalls, which effectively prevents carriers from diffusing to the sidewalls. This confines the carriers within the chip for recombination and light emission, thereby reducing the chip sidewall effect and significantly improving the chip's luminous efficiency.

[0007] To achieve the above and other related objectives, the present invention provides an LED chip comprising at least:

[0008] A semiconductor epitaxial stack, wherein the semiconductor epitaxial stack comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked sequentially from bottom to top;

[0009] A current-constrained layer is located on the sidewall of the semiconductor epitaxial stack along the stacking direction of the semiconductor epitaxial stack. The current-constrained layer at least covers the sidewall of the active layer. The current-constrained layer contains group III elements and group V elements, and has at least two of the same elements as the semiconductor epitaxial stack.

[0010] Another aspect of this application provides a method for manufacturing an LED chip, the method comprising the following steps:

[0011] A semiconductor epitaxial stack is formed on a growth substrate, the semiconductor epitaxial stack comprising a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer formed sequentially.

[0012] The semiconductor epitaxial stack is etched to form a first opening to expose the sidewalls of the semiconductor epitaxial stack. The first opening is formed between adjacent LED chips, and the bottom of the first opening is located in the first conductivity type semiconductor layer.

[0013] The semiconductor epitaxial stack with the first opening is placed in the reaction chamber;

[0014] A reaction gas is introduced into the reaction chamber to form a layer of compound semiconductor material filled in the opening; the reaction gas includes at least two reaction source gases.

[0015] The filling compound semiconductor material layer is etched along the first opening region to form a second opening, thereby dividing the filling compound semiconductor material layer and forming a current confinement layer covering the sidewalls of the semiconductor epitaxial stack.

[0016] Another aspect of this application provides a semiconductor light-emitting device, which includes a circuit board and a plurality of light-emitting elements disposed on the circuit board, wherein the light-emitting elements include the LED chip provided in this application.

[0017] As described above, the LED chip, its manufacturing method, and the semiconductor light-emitting device provided by the present invention have at least the following beneficial technical effects:

[0018] In the LED chip of the present invention, a current confinement layer is formed on the sidewall of the semiconductor epitaxial stack, and along the stacking direction of the semiconductor epitaxial stack, the current confinement layer covers at least to the sidewall of the active layer. The current confinement layer can bond with the unsaturated bonds on the sidewall of the semiconductor epitaxial stack to form a heterojunction with a continuous crystal configuration. Therefore, by controlling the conductivity of the current confinement layer, current diffusion to the sidewall can be effectively prevented, thereby preventing carrier diffusion to the sidewall of the semiconductor epitaxial stack. This significantly reduces the nonradiative deep energy levels of the potential wells generated by unsaturated bonds and impurities on the sidewall surface of the semiconductor epitaxial stack, reduces the nonradiative recombination of carriers at the sidewall surface, and confines carriers within the chip for recombination and light emission, improving the internal quantum efficiency of the Micro LED and significantly increasing the chip's luminous efficiency. Attached Figure Description

[0019] Figure 1 The diagram shows a schematic of the structure of a light-emitting diode in the prior art.

[0020] Figure 2 The diagram shown is a structural schematic of an LED chip provided in Embodiment 1 of the present invention.

[0021] Figure 3 Displayed as Figure 2 The diagram shows a top view of the LED chip.

[0022] Figure 4 Displayed as Figure 2 The diagram shows the structure of the semiconductor epitaxial stack in the LED chip.

[0023] Figure 5 The diagram shows a process flow chart of the LED chip manufacturing method as shown in Example 1.

[0024] Figure 6 The diagram shows a structure in which a semiconductor epitaxial stack is formed on a growth substrate and a first mask layer is formed on top of the semiconductor epitaxial stack.

[0025] Figure 7 Displayed as along Figure 6 The diagram shows a structure in which the first mask layer etches the semiconductor epitaxial stack to form an opening.

[0026] Figure 8 Displayed as in Figure 7The diagram shows a structure in which a layer of compound semiconductor material is formed in the opening.

[0027] Figure 9 Showing as formation Figure 8 The image shown is a TEM image of a layer filled with a compound semiconductor material.

[0028] Figure 10 Displayed as in Figure 8 A schematic diagram of a structure in which a second mask layer is formed on top of the structure shown.

[0029] Figure 11 The diagram shows a structure for forming a current confinement layer by etching and filling a compound semiconductor material layer.

[0030] Figure 12 The diagram shown is a schematic diagram of the semiconductor light-emitting device provided in Embodiment 2 of the present invention.

[0031] Figure Labels

[0032] 10. Light-emitting diode; 11. Sidewall.

[0033] 100. LED chip; 110. Semiconductor epitaxial stack; 111. First conductivity type semiconductor layer; 1111. N-type ohmic contact layer; 1112. N-type window layer; 1113. N-type confinement layer; 1114. N-type space layer; 112. Active layer; 1121. Potential well layer; 1122. Potential barrier layer; 113. Second conductivity type semiconductor layer; 1131. P-type ohmic contact layer; 1132. P-type confinement layer; 1133. P-type space layer; 114. Buffer layer; 115. Etch stop layer; 120. Current confinement layer; 131. First electrode; 132. Second electrode; 140. Transparent conductive layer; 150. Insulating protective layer.

[0034] 200, growth substrate; 201, first opening; 202, first mask layer; 2020, first opening pattern; 203, filling compound semiconductor material layer; 204, second mask layer; 2040, second opening pattern; 205, second opening.

[0035] 300, Semiconductor light-emitting device; 301, Circuit board; 302, Die-bonding area; 400, Light-emitting element. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0038] like Figure 1 As shown, in the prior art, the manufacturing of a light-emitting diode (LED) 1 typically involves etching and resist removal processes. At this time, the sidewall 11 of the LED 1 is the semiconductor layer exposed after etching. The plasma and chemical etching solutions used in the etching and resist removal processes can cause irreversible damage to the semiconductor stacked layer of the LED, directly introducing impurity elements other than those constituting the semiconductor stacked layer. These impurity elements parasitize the sidewall of the LED under the influence of unsaturated bonds on the etched sidewall surface, especially at the sidewall 11 of the etched semiconductor stacked layer, forming a series of defect deep energy levels at the sidewall of the LED. For AlGaInP semiconductor stacked layers with larger carrier diffusion lengths and higher defect recombination rates, the nonradiative recombination of surface defects caused by carriers transported to the LED sidewall leads to a rapid decrease in the internal quantum efficiency of the LED. Therefore, this invention provides a novel chip structure and its manufacturing method, and also provides a semiconductor light-emitting device including this chip, to reduce the defect effect of the LED chip sidewall and improve the luminous efficiency of the LED chip.

[0039] An embodiment of the present invention provides an LED chip, which includes at least:

[0040] A semiconductor epitaxial stack, wherein the semiconductor epitaxial stack comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked sequentially from bottom to top;

[0041] A current-constrained layer is located on the sidewall of the semiconductor epitaxial stack along the stacking direction of the semiconductor epitaxial stack. The current-constrained layer at least covers the sidewall of the active layer. The current-constrained layer contains group III elements and group V elements, and has at least two of the same elements as the semiconductor epitaxial stack.

[0042] As described above, the current confinement layer contains Group III and Group V elements, and has at least two of the same elements as the semiconductor epitaxial stack. With the participation of Group IIA and IIB elements, it can bond with the unsaturated bonds on the sidewalls of the semiconductor epitaxial stack to form a heterogeneous interface with a continuous crystal structure. Therefore, it can effectively prevent current from diffusing to the sidewalls, and thus effectively prevent charge carriers from diffusing to the sidewalls of the semiconductor epitaxial stack. This significantly reduces the nonradiative deep energy levels of the potential wells generated by unsaturated bonds and impurities on the sidewall surface of the semiconductor epitaxial stack, reduces the nonradiative recombination of charge carriers at the sidewall surface, and confines the charge carriers within the chip for recombination and light emission, thereby improving the internal quantum efficiency of Micro LED and significantly increasing the chip's luminous efficiency.

[0043] Optionally, the ratio of the width of the current constraint layer to the side length of a single side of the LED chip is between 1:100 and 1:4.

[0044] Optionally, the width of the current constraint layer is between 0.01 μm and 1 μm.

[0045] The width of the current confinement layer is set to ensure that it can establish a relatively complete periodic potential field and independent energy band, effectively increasing the barrier height of the sidewalls of the semiconductor epitaxial stack and effectively preventing nonradiative recombination of charge carriers at the sidewalls.

[0046] Optionally, both the semiconductor epitaxial stack and the current confinement layer contain Al elements, and the Al content in the current confinement layer is different from the Al content in the active layer of the semiconductor epitaxial stack.

[0047] The introduction of Al gives the current confinement layer a lower conductivity and a higher potential barrier, preventing charge carriers from overflowing to the sidewalls.

[0048] Optionally, the current confinement layer is a material layer composed of at least two elements selected from Al, Ga, In, and P.

[0049] The aforementioned current confinement layer and bonding auxiliary elements can be some or all of the elements forming the semiconductor epitaxial stack, thus reducing the selection or adjustment of the source gas and auxiliary source gas, which helps to simplify the process flow.

[0050] Optionally, along the stacking direction of the semiconductor epitaxial stack, the current confinement layer covers the sidewalls of the second conductivity type semiconductor layer and the active layer, as well as at least a portion of the sidewalls of the first conductivity type semiconductor layer.

[0051] A current-constrained layer is formed on the sidewall of the first conductivity type semiconductor layer to ensure that the sidewall at the active layer location is completely covered by the current-constrained layer, preventing the carriers therein from overflowing to the sidewall.

[0052] Optionally, the current constraint layer further includes bonding auxiliary elements.

[0053] Optionally, the bonding auxiliary element includes any one or more elements from Group IIA and Group IIB.

[0054] The introduction of bonding auxiliary elements ensures that the lattice configuration of atoms at the sidewalls of the semiconductor epitaxial layer stack does not change, and can also play a role in repairing the atomic lattice configuration. This makes it easier for the unsaturated bonds of the atoms on the sidewall surface of the etched semiconductor epitaxial layer stack to bond with the atoms forming the current confinement layer, forming a heterogeneous interface with a continuous crystal configuration, improving the crystal quality of the current confinement layer, effectively preventing carrier diffusion, and enhancing the confinement of carriers.

[0055] Optionally, the semiconductor epitaxial stack is an AlGaInP-based material layer, wherein the second conductivity type semiconductor layer is a P-type doped material layer, and in the direction toward the active layer, the second conductivity type semiconductor layer includes a P-type ohmic contact layer, a P-type confinement layer and a P-type space layer stacked sequentially, wherein the P-type ohmic contact layer is an AlGaAs layer or an AlGaInP layer.

[0056] As shown above, the P-type ohmic contact layer is an AlGaAs layer or an AlGaInP layer. The material forming the second conductivity type semiconductor layer is the same as the material forming the current confinement layer or the crystal structure matches. Therefore, the crystal configuration of the sidewall current confinement layer and the epitaxial layer sidewall interface is highly consistent, which makes the confinement effect of the sidewall current confinement layer on the charge carriers better.

[0057] Optionally, the first conductivity type semiconductor layer is an N-type doped material layer. In the direction toward the active layer, the first conductivity type semiconductor layer includes at least an N-type ohmic contact layer, an N-type window layer, an N-type confinement layer and an N-type space layer stacked sequentially, wherein the N-type space layer is adjacent to the active layer.

[0058] Optionally, along the stacking direction of the semiconductor epitaxial stack, the current confinement layer covers the sidewalls of the second conductivity type semiconductor layer and the active layer, and at least covers the sidewalls of the N-type space layer in the first conductivity type semiconductor layer.

[0059] The current confinement layer covers at least the sidewalls of the N-type space layer. It works in conjunction with the N-type confinement layer and the semiconductor layer on the P side to confine the charge carriers (electrons and holes) within the active layer, reducing the overflow of charge carriers to the sidewalls and improving the internal quantum efficiency of the LED chip.

[0060] Optionally, the LED chip further includes an insulating protective layer covering the exposed surfaces of the current constraint layer and the semiconductor epitaxial stack.

[0061] The insulating protective layer provides physical insulation and protection, preventing short circuits and other phenomena, while also preventing damage to the LED chip from external moisture and impurities.

[0062] Another aspect of this application provides a method for manufacturing an LED chip, which includes the following steps:

[0063] Epitaxial growth gas is introduced into the reaction chamber to form a semiconductor epitaxial stack on the growth substrate. The semiconductor epitaxial stack includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer formed sequentially.

[0064] The semiconductor epitaxial stack is etched to form a first opening to expose the sidewalls of the semiconductor epitaxial stack. The first opening is formed between adjacent LED chips, and the bottom of the first opening is located in the first conductivity type semiconductor layer.

[0065] The semiconductor epitaxial stack with the first opening is placed in the reaction chamber;

[0066] A reaction source gas is introduced into the reaction chamber to form a layer of compound semiconductor material filled in the opening. The reaction gas includes group III and group V elements and has at least two of the same elements as the epitaxial growth gas.

[0067] The filling compound semiconductor material layer is etched along the first opening region to form a second opening, thereby dividing the filling compound semiconductor material layer and forming a current confinement layer covering the sidewalls of the semiconductor epitaxial stack.

[0068] As described above, a current confinement layer is deposited in the growth chamber of the semiconductor epitaxial stack to form a current confinement layer that is highly consistent with the crystal configuration of the semiconductor epitaxial stack, thereby improving the confinement effect of the sidewall current confinement layer on the charge carriers.

[0069] Optionally, before introducing the reaction source gas into the reaction chamber, the semiconductor epitaxial stack with the opening formed thereon is further subjected to heat treatment.

[0070] This heat treatment process enables oxide decomposition at the sidewalls of the semiconductor epitaxial stack after etching, effectively removing impurity oxides and exposing the unsaturated bonds on the sidewalls of the semiconductor epitaxial stack. This facilitates the bonding of the subsequent current confinement layer with the unsaturated bonds, forming a heterostructure interface with a continuous crystal configuration.

[0071] Optionally, during the process of introducing the reaction source gas into the reaction chamber, a bonding auxiliary source gas may also be introduced into the reaction chamber.

[0072] Optionally, the reaction source gas includes at least two of Al source gas, Ga source gas, In source gas, and P source gas.

[0073] Optionally, the auxiliary source gas contains any one or more elements from Group IIA and Group IIB.

[0074] Choosing the same source gas as the one used to form the semiconductor epitaxial stack, and introducing the aforementioned bonding auxiliary elements, reduces the selection and adjustment of the source gas, simplifying the process flow. Furthermore, it makes it easier for the unsaturated bonds of the sidewall surface atoms of the etched semiconductor epitaxial stack to bond with the atoms forming the current confinement layer, forming a heterogeneous interface with a continuous crystal structure. This improves the crystal quality of the current confinement layer and enhances the confinement of charge carriers.

[0075] Another aspect of this application provides a semiconductor light-emitting device, which includes a circuit board and a plurality of light-emitting elements disposed on the circuit board, wherein the light-emitting elements include the LED chip provided in this application.

[0076] Semiconductor light-emitting devices include the aforementioned LED chips, thus achieving the same high light output brightness and lower manufacturing costs.

[0077] The LED chip, its manufacturing method, and semiconductor light-emitting device of this application will now be described in detail through the following specific embodiments.

[0078] Example 1

[0079] This embodiment provides an LED chip, such as Figure 2 As shown, the LED chip 100 includes at least a semiconductor epitaxial stack 110 and a current confinement layer 120 located on the sidewall of the semiconductor epitaxial stack 110. The semiconductor epitaxial stack 110 includes a first conductivity type semiconductor layer 111, an active layer 112 and a second conductivity type semiconductor layer 113 stacked sequentially.

[0080] In this embodiment, the material of the semiconductor epitaxial stack 110 includes Al. a In b Ga (1-a-b) N or Al a In b Ga (1-a-b) P or Al a In b Ga (1-a-b)As a group III-V semiconductor material, where 0 ≤ a, b ≤ 1; a + b ≤ 1. The emitted light wavelength and color of the LED chip can be adjusted by changing the material composition of the active layer 112. For example, when the material of the semiconductor epitaxial stack 110 is AlInGaP series, it can emit red light with a wavelength between 610 nm and 750 nm or yellow light with a wavelength between 550 nm and 610 nm. When the material of the semiconductor epitaxial stack 110 is InGaN series, it can emit blue or dark blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm. When the material of the semiconductor epitaxial stack 110 is AlGaN series, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.

[0081] Compared to AlGaInN-based materials, AlGaInP-based materials have a longer carrier diffusion length and a higher defect recombination rate. Therefore, the nonradiative recombination of surface defects caused by carriers transported to the chip sidewalls leads to a more significant decrease in the internal quantum efficiency of AlGaInP-based red Micro LEDs. Accordingly, this embodiment uses the AlInGaP series material of the aforementioned semiconductor epitaxial stack 110 as an example, emitting red light with a wavelength between 610 nm and 750 nm. In other embodiments, the aforementioned semiconductor epitaxial stack 110 can also be made of other material systems.

[0082] The active layer 112 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiquantum well (MQW). (See reference...) Figure 3 In this embodiment, the multi-well layer structure is formed by alternating stacking of well layers 1121 and barrier layers 1122. The barrier layer 1122 can be a GaN layer, an AlGaN layer, or an AlGaInP layer. Optionally, the active layer 112 can include multi-well layer structures such as GaN / AlGaN, InAlGaN / InAlGaN, InGaN / AlGaN, GaInP / AlGaInP, GaInP / AlInP, or InGaAs / AlInGaAs. To improve the luminous efficiency of the active layer 112, the depth of the well layers 1121, the number of paired well layers 1121 and barrier layers 1122, the thickness, and / or other characteristics can be changed in the active layer 112.

[0083] like Figure 2As shown, the LED chip 100 in this embodiment is formed in a vertical structure. The side of the second conductivity type semiconductor layer 113 away from the active layer 112 is the front side 1001 of the LED chip 100, and the side of the first conductivity type semiconductor layer 111 away from the active layer 112 is the back side 1002 of the LED chip 100. The back side 1002 serves as the light-emitting side of the LED chip 100. Furthermore, in order to improve the light extraction efficiency of the LED chip 100, the surface of the back side 1002, which serves as the light-emitting side, is formed as a roughened surface.

[0084] like Figure 2 As shown, the semiconductor epitaxial stack 110 of this embodiment has a current confinement layer 120 on its sidewall. Along the direction from the front side 1001 to the back side 1002 of the LED chip 100, the current confinement layer 120 extends from the sidewall of the second conductivity type semiconductor layer 111 to at least cover the sidewall of the active layer 112, and further extends to cover a portion of the sidewall of the first conductivity type semiconductor layer 111. This current confinement layer 120 contains Group III and Group V elements, and has at least two of the same elements as the semiconductor epitaxial stack 110. As described above, when the semiconductor epitaxial stack 110 is an AlGaInAsP-based material layer, the current confinement layer 120 of this embodiment contains at least two elements from the aforementioned material system, for example, it can be an AlGaP layer, a GaInP layer, or AlGaInP and AlGaAsP, or it can be GaP or AlP. Both the current confinement layer 120 and the semiconductor epitaxial stack 110 contain group III and group V elements, and have at least two of the same elements as the semiconductor epitaxial stack 110. Therefore, they can bond with unsaturated bonds at the sidewalls of the semiconductor epitaxial stack 119 to form a heterogeneous interface with a continuous crystal structure. This effectively prevents current from diffusing to the sidewalls, and thus effectively prevents charge carriers from diffusing to the sidewalls of the semiconductor epitaxial stack.

[0085] In an optional example, the current confinement layer 120 and the semiconductor epitaxial stack 110 have different Al content. Specifically, the Al content in the current confinement layer 120 is greater than that in the epitaxial stack 110, and especially greater than that in the active layer 112. This configuration results in a band gap of the current confinement layer 120 that is much larger than the band gap of the quantum well layer 1121 at the active layer 112. The increased band gap of the current confinement layer 120 helps to reduce conductivity, prevents carrier overflow into this region, and confines carriers within the semiconductor epitaxial stack 110 surrounded by the current confinement layer 120. This avoids abnormal radiative recombination at the sidewalls, improves radiative recombination efficiency, and thus improves the light extraction performance of the LED chip.

[0086] In an optional example, the current confinement layer 120 further contains bonding auxiliary elements, which include any one or more elements from Group IIA and Group IIB, such as, but not limited to, Zn, Mg, Ca, Be, or Cd. Compared to AlGaInAsP material layers, these bonding auxiliary atoms ensure that the lattice configuration and periodicity of atoms at the sidewalls of the semiconductor epitaxial stack 110 remain unchanged, and can repair the atomic lattice configuration. This makes it easier for the unsaturated bonds of the atoms on the sidewall surface of the semiconductor epitaxial stack 110 exposed after etching to bond with the atoms of the subsequently grown current confinement layer 120, forming a heterogeneous interface with a continuous crystal configuration. This improves the crystal quality of the current confinement layer, significantly reduces the nonradiative deep energy levels of the potential wells generated by unsaturated bonds and impurities on the sidewall surface of the semiconductor epitaxial stack 110, effectively prevents carrier diffusion, increases carrier confinement, reduces nonradiative recombination of carriers at defects on the sidewall surface of the semiconductor epitaxial stack 110, and improves the internal quantum efficiency of Micro LEDs.

[0087] like Figure 2 and Figure 3 As shown, along the direction from the sidewall of the semiconductor epitaxial stack 110 towards the central region, the current confinement layer 120 has a width D. In the same extension direction as the width D, the side of the LED chip 100 has a side length W. Optionally, the ratio D:W of the width D of the current confinement layer 120 to the side length W of the LED chip 100 is between 1:100 and 1:4, further between 1:50 and 1:4, or between 1:100 and 1:20, or between 1:50 and 1:20, or between 1:30 and 1:20. More specifically, the width D of the current confinement layer 120 is between 0.01 μm and 1 μm, further between 0.1 μm and 1 μm, or between 0.5 μm and 1 μm, or between 0.1 μm and 0.5 μm. The width of the current confinement layer 120 ensures that it can establish a relatively complete periodic potential field and independent energy band, thereby increasing the barrier height at the sidewall of the semiconductor epitaxial stack 110 and effectively preventing nonradiative recombination of charge carriers at the sidewall.

[0088] Refer again Figure 2In the stacking direction of the semiconductor epitaxial stack 110, the current confinement layer 120 has a height H, and the semiconductor epitaxial stack has a height H0, wherein H is less than or equal to H0. Further, the height of the current confinement layer 120 is greater than the sum of the heights H1 of the second conductivity type semiconductor layer 113 and the active layer 112, and less than or equal to the height H0 of the semiconductor epitaxial stack 110. As described above, the current confinement layer 120 extends from the sidewall of the second conductivity type semiconductor layer 113 to completely cover the sidewall of the active layer 112, thus effectively preventing carrier overflow from the active layer 112 to the sidewall by utilizing the difference in conductivity and potential barrier between the current confinement layer 120 and the active layer 112. Furthermore, the height H of the current confinement layer 120 is greater than the sum of the heights H1 of the second conductivity type semiconductor layer 113 and the active layer 112, covering a portion of the sidewalls of the first conductivity type semiconductor layer 111, for example, at least covering the sidewalls of the N-type space layer 1114 in the first conductivity type semiconductor layer 111. The current confinement layer 120 at least covers the sidewalls of the N-type space layer 1114, and works in conjunction with the N-type confinement layer 1113 and the P-side semiconductor layer to confine charge carriers (electrons and holes) within the active layer 112 of the semiconductor epitaxial stack 110, reducing the overflow of charge carriers to the sidewalls, improving the internal quantum efficiency of the LED chip, and reducing the risk of leakage.

[0089] Reference Figure 2 In this embodiment, the sidewalls and surface of the LED chip 100 also have an insulating protective layer 150, which may be, for example, SiO2, SiN, or SiO2. x N y TiO x The insulating protective layer 150 can protect the semiconductor epitaxial stack 110 from external moisture, impurities, etc., which is beneficial to improving the reliability and yield of the LED chip 100.

[0090] Refer again Figure 2 The LED chip in this embodiment also includes an electrode structure, specifically including a first electrode 131 electrically connected to a first conductivity type semiconductor layer 111, and a second electrode 132 electrically connected to a second conductivity type semiconductor layer 113. Taking the vertical structure LED chip 100 of this application as an example, the first electrode 131 is formed above the first conductivity type semiconductor layer 111 on the back side 1102 of the semiconductor epitaxial stack 110. The second electrode 132 is formed above the second conductivity type semiconductor layer 113 on the front side 1101 of the semiconductor epitaxial stack 110. Figure 2As shown, a transparent conductive layer 140 is formed between the second electrode 132 and the second conductivity type semiconductor layer 113. This transparent conductive layer 140 can be a transparent conductive material layer with good current diffusion effects, such as ITO or IZO, which can form an ohmic contact with the second electrode 132 and improve current diffusion. The first electrode 131 and the second electrode 132 can be one or more alloys of Ag, Al, Cu, Sn, Au, etc., and they can be the same or different. In this embodiment, the longest side length of the LED chip is less than or equal to 100 μm, and further less than or equal to 50 μm, 20 μm, or even less than or equal to 5 μm. Although this embodiment shows the LED chip as a vertical structure, it can be understood that it can be formed as a horizontal structure with the first electrode 131 and the second electrode 132 located on the same side.

[0091] Reference Figure 4 In an optional example of this application, the semiconductor epitaxial stack 110 is based on the AlGaInAsP material system. Specifically, the first conductivity type semiconductor layer 111 is an N-type semiconductor layer, and the second conductivity type semiconductor layer 113 is a P-type semiconductor layer. Specifically, in the direction toward (i.e., gradually approaching) the active layer 112, the first conductivity type semiconductor layer 111 includes, for example, a sequentially stacked N-type ohmic contact layer 1111, an N-type window layer 1112, an N-type confinement layer 1113, and an N-type space layer 1114. Similarly, in the direction toward (i.e., gradually approaching) the active layer 112, the second conductivity type semiconductor layer 113 includes, for example, a sequentially stacked P-type ohmic contact layer 1131, a P-type confinement layer 1132, and a P-type space layer 1133.

[0092] Furthermore, the aforementioned N-type ohmic contact layer 1111 is an N-type doped AlGaAs layer or an AlGaInP layer, and the N-type window layer 1112 is an N-type doped AlGaInP layer or a superlattice structure formed by multiple layers of semiconductor materials (e.g., AlInP / AlGaInP). The N-type window layer 1112 can be a single-layer structure, such as an N-type AlGaInP single-layer structure; or a multi-layer structure, such as a superlattice structure formed by AlInP / AlGaInP. The N-type confinement layer 1113 is an N-type doped AlInP or an N-type doped AlGaInP layer, and the N-type space layer 1114 is an unintentionally doped AlGaInP layer.

[0093] Similarly, Figure 4As shown, the P-type ohmic contact layer 1131 is a P-type AlGaAs layer or an AlGaInP layer, the P-type confinement layer 1132 is a P-type AlInP layer, and the P-type space layer 1133 is an unintentionally doped AlGaInP layer. As described above, in this embodiment, the second conductivity type semiconductor layer 113 does not have a separate window layer. Instead, an AlGaAs layer or an AlGaInP layer replaces the GaP material layer as the P-type ohmic contact layer. Since the P-type ohmic contact layer has a high lattice matching degree with the underlying P-type confinement layer, the transition layer between the two can also be omitted, thereby simplifying the semiconductor epitaxial stack formation process.

[0094] The active layer 112 includes alternately stacked potential well layers 1121 and potential barrier layers 1122. The number of stacked pairs of potential well layers 1121 and potential barrier layers 1122 is between 1 and 200 pairs, such as 3 pairs, 5 pairs, 8 pairs, 10 pairs, 15 pairs, 20 pairs, 100 pairs, etc. In this embodiment, the potential well layer 1121 is specifically [(Al a Ga 1-a ) b In 1-b ] c P 1-c The material layer has values ​​where 0.1 ≤ a ≤ 0.3, 0 < b < 1, and 0 < c < 1, the specific values ​​depending on the wavelength of the light emitted by the LED chip. The barrier layer 1122 is specifically [(Al x Ga 1-x ) y In 1-y ] z P 1-z The material layer has x ≥ 0.5, 0 < y < 1, 0 < z < 1; further, x ≥ 0.6. As described above, the barrier layer 1122 has a relatively high aluminum content compared to the well layer 1121, thereby enabling it to confine charge carriers.

[0095] This embodiment also provides a method for manufacturing the above-mentioned LED chip, such as... Figure 5 As shown, the method includes the following steps:

[0096] S1: Introduce epitaxial growth gas into the reaction chamber to form a semiconductor epitaxial stack on the growth substrate. The semiconductor epitaxial stack includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer formed sequentially.

[0097] S2: Etch the semiconductor epitaxial stack to form a first opening to expose the sidewalls of the semiconductor epitaxial stack, the first opening being formed between adjacent LED chips, the bottom of the first opening being located in the first conductivity type semiconductor layer;

[0098] S3: Place the semiconductor epitaxial stack with the first opening in the reaction chamber;

[0099] S4: Introduce a reaction source gas into the reaction chamber to form a layer of compound semiconductor material in the opening. The reaction gas includes group III and group V elements and has at least two of the same elements as the epitaxial growth gas.

[0100] S5: Etch the filled compound semiconductor material layer along the first opening region to form a second opening, thereby dividing the filled compound semiconductor material layer and forming a current confinement layer covering the sidewalls of the semiconductor epitaxial stack.

[0101] Taking the aforementioned semiconductor epitaxial stack 110 as an AlGaInAsP material system as an example, such as Figure 6 As shown, a growth substrate 200 is first provided, such as a sapphire substrate or a gallium arsenide substrate. In this embodiment, a gallium arsenide substrate is used as the growth substrate 200. The growth substrate 200 is placed in a reaction chamber, and an epitaxial growth gas is introduced into the reaction chamber. This epitaxial growth gas contains a group III metal-organic source and a group V hydride source. The group III metal-organic source includes, for example, any two or three of trimethylaluminum (TMAl), trimethylgallium (TMGa), and trimethylindium (TMIn) to provide the three group III elements Al, Ga, and In required for epitaxial growth. The group V hydride source includes arsine (AsH3) and / or phosphine (PH3) to provide the group V elements As and / or P, which react with the group III elements to form a semiconductor compound. It is understood that the growth process also includes the introduction of a p-type dopant source or an n-type dopant source to form an n-type semiconductor layer or a p-type semiconductor layer. A carrier gas, such as hydrogen, may also be introduced as a dilution and transport gas to ensure uniform distribution of the reaction gas, maintain stable chamber atmosphere and pressure, and improve the quality of epitaxial growth. In this embodiment, by controlling the flow rate ratio of the aforementioned source gas and carrier gas, and controlling parameters such as the reaction chamber temperature and pressure within the reaction chamber, a first conductivity type semiconductor layer 111, an active layer 112, and a second conductivity type semiconductor layer 113 are sequentially formed on a gallium arsenide substrate to form a semiconductor epitaxial stack 110. The aforementioned first conductivity type semiconductor layer 111, active layer 112, and second conductivity type semiconductor layer 113 can be referred to the description regarding the LED chip section above.

[0102] Similarly, Figure 6 As shown, a first mask layer 202 is formed above the semiconductor epitaxial stack 110, specifically above the second conductivity type semiconductor layer 113. The first mask layer 202 has a first opening pattern 2020. The area surrounded by the first opening pattern 2020 (i.e. the area covered by the first mask layer 202) is the main light-emitting area of ​​the LED chip.

[0103] The first mask layer 202 may optionally be an insulating material layer, such as SiN. x The first mask layer 202 can be a single or multiple layer of material such as SiO2. It can also be a multilayer structure formed by an insulating layer and a sacrificial layer. For example, in an optional embodiment, the first mask layer 202 includes a sacrificial layer formed above the second conductivity type semiconductor layer 113 and an insulating layer formed above the sacrificial layer. The sacrificial layer can be a material layer such as ITO that is not dry-etched, and the insulating layer can be SiN. x Material layers such as SiO2 that are easily removed by dry etching.

[0104] like Figure 7 As shown, the semiconductor epitaxial stack 110 is etched downwards through the first opening pattern 2020 in the first mask layer 202 to form the first opening 201. In this embodiment, under the action of the first mask layer 202, the semiconductor epitaxial stack 110 is etched through the first opening pattern 2020, sequentially etching the second conductivity type semiconductor layer 113, the active layer 112, and part of the first conductivity type semiconductor layer 111, for example, at least etching the N-type space layer 1114, forming the first opening 201 that exposes the sidewalls of the semiconductor epitaxial stack 110. The first opening 201 exposes the sidewalls of the semiconductor epitaxial stack 110, which contain a certain number of unsaturated bonds. At the same time, the exposed sidewalls may be damaged during the etching process, or the unsaturated bonds may be affected by gases in the environment to generate undesirable oxides, etc.

[0105] Therefore, before step S4, in which the reaction source gas is introduced into the reaction chamber and the filling compound semiconductor material layer 203 is formed in the first opening 201, the structure forming the first opening 201 is first placed in the reaction chamber, and the sidewall surface of the semiconductor epitaxial stack 110 exposed after etching is subjected to heat treatment for a certain period of time. During the heat treatment process, impurities such as oxides at the sidewall of the semiconductor epitaxial stack 110 can be decomposed and removed, exposing the unsaturated bonds on the sidewall of the semiconductor epitaxial stack 110, which is conducive to the subsequent bonding of the filling compound semiconductor material layer 203 with the unsaturated bonds, forming a heterogeneous interface with a continuous crystal structure.

[0106] After heat treatment, a reaction source gas is introduced into the reaction chamber to form a compound semiconductor material layer 203 filled in the first opening 201. The reaction gas includes Group III and Group V elements, and has at least two of the same elements as the epitaxial growth gas. For example, the epitaxial growth gas includes any two or three of trimethylaluminum (TMAl), trimethylgallium (TMGa), and trimethylindium (TMIn), and also includes arsine (AsH3) and / or phosphine (PH3) to form a compound semiconductor material layer 203 in the opening 202. Figure 8 The shown is a filled compound semiconductor material layer 203.

[0107] Optionally, during the process of introducing the reaction source gas into the reaction chamber, a bonding auxiliary source gas is also introduced into the reaction chamber. The auxiliary source gas includes any element from Group IIA and Group IIB, such as, but not limited to, Zn, Mg, Ca, Be, or Cd. Selecting the same reaction source gas as that used to form the semiconductor epitaxial stack 110, and simultaneously introducing the aforementioned bonding auxiliary elements, reduces the selection and adjustment of the source gas, simplifying the process flow. Furthermore, it makes it easier for the unsaturated bonds of the sidewall surface atoms of the etched semiconductor epitaxial stack 110 to bond with the atoms forming the current confinement layer, such as… Figure 9 As shown in the TEM (Transmission Electron Microscope) image, the aforementioned filled compound semiconductor material layer 203 and the semiconductor epitaxial stack 110 form a heterogeneous interface with a continuous crystal configuration. Therefore, by controlling the conductivity of the filled compound semiconductor material layer 203, current diffusion to the heterogeneous interface (i.e., the sidewall of the semiconductor epitaxial stack 110) can be effectively prevented, thereby preventing carriers from diffusing to the sidewall of the semiconductor epitaxial stack 110, improving the crystal quality of the current confinement layer, and increasing the confinement of carriers.

[0108] It is understandable that during the growth of the compound semiconductor material layer 203, a disordered polycrystalline semiconductor layer will also be deposited on the upper surface of the semiconductor epitaxial stack 110. This disordered polycrystalline semiconductor layer can be removed using processes such as dry etching, wet etching, and CMP planarization, while simultaneously removing the aforementioned first mask layer 202, ultimately forming… Figure 8 The shown is a filled compound semiconductor material layer 203.

[0109] After that, as Figure 10 As shown, in Figure 8 A second mask layer 204 is formed above the structure shown. A second opening pattern 2040 is formed in this second mask layer 204, located above the filled compound semiconductor material layer 203, such that the second mask layer 204 covers the semiconductor epitaxial stack 110 and the filled compound semiconductor material layer 203 adjacent to the sidewalls of the semiconductor epitaxial stack 110. Then, as... Figure 11As shown, the compound semiconductor material layer 203 is etched along the second opening pattern 2040 until the growth substrate 200 is exposed, forming the second opening 205. By forming the second opening 205, the compound semiconductor material layer 203 is divided, forming a current confinement layer 120 covering the sidewalls of the semiconductor epitaxial stack 110, and simultaneously dividing the semiconductor epitaxial stack 110 to form independent chips. As described above, the current confinement layer 120 is grown in the growth chamber of the semiconductor epitaxial stack 110, forming a current confinement layer 120 with a high degree of consistency with the crystal configuration of the semiconductor epitaxial stack 110, so that the current confinement layer 120 on the sidewalls has a better confinement effect on charge carriers.

[0110] Understandably, the process then includes steps such as removing the second mask layer 204, forming the insulating protective layer 150, and subsequently forming the electrode structure, ultimately forming... Figure 2 The LED chip shown.

[0111] Example 2

[0112] This embodiment provides a semiconductor light-emitting device, which can be, for example, a display device. Figure 12 As shown, the semiconductor light-emitting device 300 includes a circuit board 301 and a plurality of light-emitting elements 400 disposed on the circuit board 301. A die-bonding region 302 is provided on one side of the circuit board 301 where the light-emitting elements 400 are disposed. This die-bonding region 302 is used to mount LED chips. The die-bonding region 302 includes two spaced-apart portions, which are electrically connected to the circuit board 301 respectively. The aforementioned light-emitting unit 400 can be any one type of LED chip or a combination of multiple LED chips provided in Embodiment 1. The LED chip is connected to the die-bonding region 302 via an electrode structure and achieves electrical connection with the circuit board 301. When the LED chip is formed in a vertical structure as described in Embodiment 1, the semiconductor light-emitting device including the LED chip with this vertical structure can be used in AR display devices, etc.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LED chip, characterized in that, At least including: A semiconductor epitaxial stack, wherein the semiconductor epitaxial stack comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked sequentially from bottom to top; A current-constrained layer is located on the sidewall of the semiconductor epitaxial stack along the stacking direction of the semiconductor epitaxial stack. The current-constrained layer at least covers the sidewall of the active layer. The current-constrained layer contains group III elements and group V elements, and has at least two of the same elements as the semiconductor epitaxial stack.

2. The LED chip according to claim 1, characterized in that, The ratio of the width of the current constraint layer to the side length of one side of the LED chip is between 1:100 and 1:

4.

3. The LED chip according to claim 1, characterized in that, The width of the current constraint layer is between 0.01μm and 1μm.

4. The LED chip according to claim 1, characterized in that, Both the semiconductor epitaxial stack and the current confinement layer contain Al elements, and the Al content in the current confinement layer is different from the Al content in the active layer of the semiconductor epitaxial stack.

5. The LED chip according to claim 1, characterized in that, The current confinement layer is a material layer composed of at least two elements selected from Al, Ga, In, and P.

6. The LED chip according to claim 1, characterized in that, Along the stacking direction of the semiconductor epitaxial stack, the current confinement layer covers the sidewalls of the second conductivity type semiconductor layer and the active layer, as well as at least a portion of the sidewalls of the first conductivity type semiconductor layer.

7. The LED chip according to claim 1, characterized in that, The current constraint layer also includes bonding auxiliary elements.

8. The LED chip according to claim 7, characterized in that, The bonding auxiliary element includes any one or more elements from groups IIA and IIB.

9. The LED chip according to claim 1, characterized in that, The semiconductor epitaxial stack is an AlGaInP-based material layer, wherein the second conductivity type semiconductor layer is a P-type doped material layer. In the direction toward the active layer, the second conductivity type semiconductor layer includes a P-type ohmic contact layer, a P-type confinement layer and a P-type space layer stacked sequentially, wherein the P-type ohmic contact layer is an AlGaAs layer or an AlGaInP layer.

10. The LED chip according to claim 9, characterized in that, The first conductivity type semiconductor layer is an N-type doped material layer. In the direction toward the active layer, the first conductivity type semiconductor layer includes at least an N-type ohmic contact layer, an N-type window layer, an N-type confinement layer and an N-type space layer stacked in sequence, with the N-type space layer adjacent to the active layer.

11. The LED chip according to claim 9, characterized in that, Along the stacking direction of the semiconductor epitaxial stack, the current confinement layer covers the sidewalls of the second conductivity type semiconductor layer and the active layer, and at least covers the sidewalls of the N-type space layer in the first conductivity type semiconductor layer.

12. The LED chip according to claim 1, characterized in that, It also includes an insulating protective layer that covers the exposed surfaces of the current-constraining layer and the semiconductor epitaxial stack.

13. A method for manufacturing an LED chip, characterized in that, Includes the following steps: Epitaxial growth gas is introduced into the reaction chamber to form a semiconductor epitaxial stack on the growth substrate. The semiconductor epitaxial stack includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer formed sequentially. The semiconductor epitaxial stack is etched to form a first opening to expose the sidewalls of the semiconductor epitaxial stack. The first opening is formed between adjacent LED chips, and the bottom of the first opening is located in the first conductivity type semiconductor layer. The semiconductor epitaxial stack with the first opening is placed in the reaction chamber; A reaction source gas is introduced into the reaction chamber to form a layer of compound semiconductor material in the first opening. The reaction gas includes group III and group V elements and has at least two of the same elements as the epitaxial growth gas. The filling compound semiconductor material layer is etched along the first opening region to form a second opening, thereby dividing the filling compound semiconductor material layer and forming a current confinement layer covering the sidewalls of the semiconductor epitaxial stack.

14. The method for manufacturing an LED chip according to claim 13, characterized in that, Before introducing the reaction source gas into the reaction chamber, the semiconductor epitaxial stack with the opening is subjected to heat treatment.

15. The method for manufacturing an LED chip according to claim 13, characterized in that, The process of introducing the reaction source gas into the reaction chamber also includes introducing a bonding auxiliary source gas into the reaction chamber.

16. The method for manufacturing an LED chip according to claim 13, characterized in that, The reaction source gas includes at least two of Al source gas, Ga source gas, In source gas, and P source gas.

17. The method for manufacturing an LED chip according to claim 13, characterized in that, The auxiliary source gas contains any one or more elements from Group IIA and Group IIB.

18. A semiconductor light-emitting device, characterized in that, It includes a circuit board and a plurality of light-emitting elements disposed on the circuit board, wherein the light-emitting elements include the LED chip according to any one of claims 1 to 12.

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