Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate comprises a first region and a second region; patterning the first core material layer to form a first core layer which comprises a first sub-core layer and two adjacent second sub-core layers which are alternately distributed and arranged; forming a first side wall covering the side wall of the first core layer; performing modification treatment on the first sub-core layer to form a third sub-core layer; forming a first protective layer on the second core material layer in the second region; patterning the second core material layer by taking the first protective layer, the first side wall and the third sub-core layer as masks to form a second core layer; forming a second side wall covering the side wall of the second core layer; and patterning the target material layer by taking the second side wall and the remaining second core layer as a mask to form a first target structure located in the first region and a second target structure located in the second region. The SAQP process and the SALELE process are formed at the same time, and the design freedom degree in the patterning process is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Photolithography is a commonly used patterning method and one of the most critical production technologies in semiconductor manufacturing. As the critical dimension (CD) and pitch of patterns continue to shrink, self-aligned double patterning (SADP) can no longer meet current process requirements, leading to the development of self-aligned quadruple patterning (SAQP). Generally, the smallest pitch that SADP can achieve under DUV technology is about half the single-exposure pitch limit of 76nm, or 38nm. Similarly, the limit of SAQP under DUV technology is a pitch of 19nm. While maintaining good yield, the typical SADP limit is around 40nm, and the SAQP limit is around 24nm. In the back-end process, instead of SADP or SAQP processes, self-aligned lithography (SALELE, Spacer Assisted Litho-Etch) is often used to form metal patterns. SALELE has the advantage of greater design freedom compared to SADP, but the metal pitch limit is similar to SADP, with a minimum pitch of about 40nm.

[0003] However, with the miniaturization of transistors and chip sizes, the back-end metal pitch also needs to reach less than 40nm to 30nm or even smaller. Traditional Self-Aligned Quadruple Patterning (SAQP) can achieve smaller pitches, but like SADP, it has significant limitations in metal line layout design. Metal line layout generally needs to balance smaller and larger pitches on the same chip, as well as the freedom to freely place metal lines—something that SAQP alone struggles to provide. However, without extreme ultraviolet (EUV) lithography for exposure, achieving both pitch miniaturization and design freedom using only DUV lithography-based SAQP is relatively difficult, which also significantly limits the production of more advanced chips. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming semiconductor structures, thereby increasing the degree of design freedom in patterning processes.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a target material layer located on the substrate, wherein a second core material layer and a first core material layer are formed on the substrate, and the substrate includes a first region and a second region; patterning the first core material layer to form a first core layer discretely located in the first region, the first core layer including a plurality of first sub-core layers and second sub-core layers extending along a first direction and arranged parallel to each other along a second direction, wherein along the second direction, one first sub-core layer and two adjacent second sub-core layers are alternately distributed, the width of the second sub-core layer is greater than the width of the first sub-core layer, and the first direction is perpendicular to the second direction; forming a first sidewall covering the sidewall of the first core layer; modifying the first sub-core layer to form a third sub-core layer having an etching selectivity ratio with the second sub-core layer; removing the second sub-core layer; and forming a first protective layer on the second core material layer located in the second region. The first protective layer has multiple discrete openings extending along a first direction and arranged parallel to a second direction. A second core material layer is patterned using the first protective layer, first sidewall, and third sub-core layer as a mask to form a second core layer. The third sub-core layer, first protective layer, and first sidewall are removed. A second sidewall covering the sidewall of the second core layer is formed. The second core layer in the first region and a portion of the second core layer in the second region are removed. A target material layer is patterned using the second sidewall and the remaining second core layer as a mask to form a first target structure in the first region and a second target structure in the second region. The intervals between adjacent second sub-core layers and the first target structure corresponding to the first sub-core layer are considered first sub-target structures. The first target structure between adjacent first sub-target structures is a second sub-target structure. Both the first and second target structures extend along the first direction, and the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] In the forming method provided by this embodiment of the invention, the substrate includes a first region for forming multiple first target structures and a second region for forming multiple second target structures. The pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures. Target material layers are patterned using a second sidewall and a third core layer as masks to form first target structures located in the first region and second target structures located in the second region. In this embodiment of the invention, for the first region, a first core layer is formed discretely within the first region. Along a second direction, multiple first core layers are arranged in an alternating pattern of one first sub-core layer and two adjacent second sub-core layers. The width of the second sub-core layer is greater than the width of the first sub-core layer. Each pair of adjacent second sub-core layers and one first sub-core layer constitutes a repeating unit of the first core layer, forming a first sidewall covering the sidewall of the first core layer. The first sub-core layer is modified to form a third sub-core layer with an etching selectivity ratio to the second sub-core layer. The second core material layer of the first region is patterned using the first sidewall and the third sub-core layer as a mask, forming a second core layer discrete in the first region. The width of the second core layer corresponding to the first sidewall of the third sub-core layer and its sidewall is relatively large, forming a second sidewall covering the sidewall of the second core layer. The target material layer is patterned using the second sidewall as a mask. Since the SAQP process is adopted, the width of the first target structure corresponding to the third sub-core layer is relatively large. The SAQP process can form a first target structure with a small pitch. Simultaneously, the first target structure corresponding to the interval between adjacent second sub-core layers and the first sub-core layer is the first sub-target structure, and the first target structure between adjacent first sub-target structures is the second sub-target structure. By modifying the first sub-core layer, a first sub-target structure with a larger width can be formed. Furthermore, five second sidewalls are formed in the interval between adjacent second sub-core layers and in the region between the first sub-core layers, allowing four second sub-target structures to be formed between adjacent first sub-target structures. This results in a high integration density of the device unit composed of the first and second sub-target structures. For the second region, the second core material layer is patterned using the first protective layer as a mask to form the second core layer. Second sidewalls are formed covering the sidewalls of the second core layer. The second sidewalls and the remaining second core layer are used as mask patterning target material layers, enabling the formation of a second target structure with a larger pitch using the SALELE process. In other words, the embodiments of the present invention can effectively integrate the SAQP process and the SALELE process, enabling the formation of both a first target structure with a small pitch and a second target structure with a large pitch on the same substrate. This facilitates process integration, meets more semiconductor process requirements, and increases the design freedom in patterning processes. Attached Figure Description

[0008] Figures 1 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0009] As the background technology indicates, a common approach in back-end patterning is self-aligned lithography (also known as Spacer-Assisted Litho-Etch or SALELE process), which offers two core advantages in patterning. The first advantage is that the spacing between the metal lines defined by the two lithography steps is determined by the sidewall thickness during the process. These sidewalls are typically formed using a highly uniform atomic layer deposition (ALD) process. This ensures that the overlay between the two lithography steps does not cause changes in the spacing between adjacent metal lines, resulting in a very uniform and consistent spacing. This opens a larger process window for reliability testing, such as time-dependent dielectric breakdown (TDDB) and breakdown voltage (VBD). The second advantage is that the tip-to-tip cut of the metal lines defined by the two Lithos can be formed very small by using other photomasks to create patterning cuts, and the cuts corresponding to the first Litho and the second Litho can be made without interfering with each other. This is also known in the industry as the self-aligned block process.

[0010] The above two advantages are why SALELE balances process difficulty and provides a high degree of design freedom in the later-stage patterning. There are various similar solutions for the SALELE process, such as the process solution shown in CN111640668B, and the process solution disclosed in US10991596B2.

[0011] However, in general, the smallest pattern feature pitch formed by a single immersion DUV (ArFi) lithography is about 80nm. Therefore, SALELE can achieve a minimum pattern pitch of 38nm to 40nm using DUV equipment, while more advanced chips require smaller pitches, such as 32nm, 28nm, 24nm, etc.

[0012] In traditional fin patterning, SAQP (Self-Regulating Qt) is typically used when the pitch reaches around 30nm. This is because SADP (Self-Regulating Difference) can only form fins with a minimum pitch of 38nm, requiring a repeat of SADP to become SAQP. SAQP technology effectively meets the needs of fin patterning because the fin patterns are relatively regular, the fin pitch within a chip region is generally fixed and regular, and the differences between regions are not significant. However, SAQP has significant limitations in back-end processes where metal lines have higher degrees of freedom. For example, in SRAM metal patterning, the metal lines formed by SAQP are difficult to match with the pattern of the first metal layer of traditional SRAM. Furthermore, the relatively fixed width of the metal lines formed by SAQP makes the design of other bypass circuits more difficult.

[0013] Therefore, it can be concluded that in the current semiconductor structure, in the same area, the back-end patterning is difficult to balance smaller pitch and design freedom, making it difficult to meet more semiconductor process requirements and consequently difficult to improve the design freedom in the patterning process.

[0014] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a target material layer located on the substrate, wherein a second core material layer and a first core material layer are formed on the substrate, and the substrate includes a first region and a second region; patterning the first core material layer to form a first core layer discretely located in the first region, the first core layer including a plurality of first sub-core layers and second sub-core layers extending along a first direction and arranged in parallel along a second direction, wherein along the second direction, one first sub-core layer and two adjacent second sub-core layers are alternately distributed, the width of the second sub-core layer is greater than the width of the first core layer, and the first direction is perpendicular to the second direction; forming a first sidewall covering the sidewall of the first core layer; modifying the first sub-core layer to form a third sub-core layer having an etching selectivity ratio with the second sub-core layer; removing the second sub-core layer; and forming a first protective layer on the second core material layer located in the second region. The process involves: forming a first protective layer with multiple discrete openings extending in a first direction and arranged parallel to a second direction; patterning a second core material layer using the first protective layer, first sidewalls, and third sub-core layer as a mask to form a second core layer; removing the third sub-core layer, first protective layer, and first sidewalls; forming a second sidewall covering the sidewalls of the second core layer; removing the second core layer in the first region and a portion of the second core layer in the second region; patterning a target material layer using the second sidewalls and the remaining second core layer as a mask to form a first target structure in the first region and a second target structure in the second region, wherein the intervals corresponding to adjacent second sub-core layers and the first target structures corresponding to the first sub-core layers are first sub-target structures, and the first target structures between adjacent first sub-target structures are second sub-target structures. Both the first target structures and the second target structures extend in the first direction, and the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures.

[0015] In this embodiment of the invention, for the first region, a first core layer is formed discretely in the first region. Along the second direction, multiple first core layers are arranged in an alternating pattern of a first sub-core layer and two adjacent second sub-core layers. The width of the second sub-core layer is greater than the width of the first sub-core layer. That is, every two adjacent second sub-core layers and one first sub-core layer constitute a repeating unit of the first core layer, forming a first sidewall covering the sidewall of the first core layer. The first sub-core layer is modified to form a third sub-core layer with an etching selectivity ratio to the second sub-core layer. The second core material layer of the first region is patterned using the first sidewall and the third sub-core layer as a mask, forming a second core layer discretely in the first region. The width of the second core layer corresponding to the first sidewall of the third sub-core layer and its sidewall is relatively large, forming a second sidewall covering the sidewall of the second core layer. The target material layer is patterned using the second sidewall as a mask. Since the SAQP process is adopted, the width of the first target structure corresponding to the third sub-core layer is relatively large. The SAQP process can form a first target structure with a small pitch. Simultaneously, the first target structure corresponding to the interval between adjacent second sub-core layers and the first sub-core layer is the first sub-target structure, and the first target structure between adjacent first sub-target structures is the second sub-target structure. By modifying the first sub-core layer, a wider first sub-target structure can be formed. Furthermore, five second sidewalls are formed in the interval between adjacent second sub-core layers and in the region between the first sub-core layers, allowing four second sub-target structures to be formed between adjacent first sub-target structures. This results in a high integration density of the device unit composed of the first and second sub-target structures. For the second region, the first protective layer is used as a mask to pattern the second core material layer, forming the second core layer. Second sidewalls are formed covering the sidewalls of the second core layer. The second sidewalls and the remaining second core layer are used as mask patterning target material layers, enabling the formation of a second target structure with a larger pitch using the SALELE process. In other words, the embodiments of the present invention can effectively integrate the SAQP process and the SALELE process, enabling the formation of both a first target structure with a small pitch and a second target structure with a large pitch on the same substrate. This facilitates process integration, meets more semiconductor process requirements, and increases the design freedom in patterning processes.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0017] Figures 1 to 23 This is a schematic diagram of the structure corresponding to each step in an embodiment of the semiconductor structure formation method of the present invention, wherein, Figure 1 It's a 3D image. Figures 2 to 22 Based on Figure 1 A sectional view.

[0018] Reference Figure 1 and Figure 2 A substrate 100 is provided, including a substrate 180 and a target material layer 170 located on the substrate 180. A second core material layer 200 is formed on the substrate 100, and a first core material layer 400 is located on the second core material layer 200. The substrate 100 includes a first region 100a for forming a plurality of first target structures and a second region 100b for forming a plurality of second target structures, wherein the first target structures and the second target structures are both along a first direction (e.g., Figure 1 Extending in the X direction, the pitch of the adjacent first target structure is less than or equal to the pitch of the adjacent second target structure.

[0019] The substrate 100 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include metal interconnects, barrier layers, adhesion layers, and cap layers.

[0020] In this embodiment, the substrate 180 is a wafer on which transistors and some interconnects are formed.

[0021] It should be noted that during the formation of a semiconductor structure, a relatively dense first target structure and a relatively sparse second target structure need to be formed. That is, the pitch between adjacent first target structures is less than or equal to the pitch between adjacent second target structures. While the SAQP process can form a relatively dense target structure, it is difficult to form a relatively sparse one. Furthermore, the pitch between target structures is relatively fixed and difficult to adjust freely according to the layout requirements. The SALELE process can define the pitch between target structures according to the layout, and the pitch is easily adjustable. It also enables self-aligned block lithography, but it is difficult to form a relatively dense target structure (pitch less than 38nm). Specifically, this embodiment uses the SAQP process to realize the first region 100a, and simultaneously uses a self-aligned lithography (SALELE) process to realize the second region 100b. Therefore, in this embodiment, the substrate 100 includes a first region 100a for forming a plurality of first target structures and a second region 100b for forming a plurality of second target structures. This means that this embodiment can simultaneously form a first target structure with a small pitch that is difficult to form by the SALELE process and a second target structure with a large pitch that is difficult to form by the SAQP process on the same substrate 100 (e.g., the same wafer), allowing for more flexible design.

[0022] In this embodiment, the first region 100a includes a logic device region, and the second region 100b includes a peripheral device region. The graphics in the logic device region are denser, while the graphics in the peripheral device region are sparser. Specifically, the logic device region includes device regions such as a central processing unit (CPU) and a graphics processing unit (GPU), while the peripheral device region includes device regions such as static random-access memory (SRAM) and input / output (IO) devices.

[0023] In this embodiment, the pitch of adjacent first target structures is 24nm to 38nm; the pitch of adjacent second target structures is 38nm to 200nm.

[0024] Therefore, it can be seen that the first target structure can be formed by SAQP process and the second target structure can be formed by SALELE process, forming the first target structure with a pitch of 24nm to 38nm and the second target structure with a pitch of 38nm to 200nm in the same substrate 100.

[0025] In this embodiment, the thickness of the gate oxide layer in the logic device region is less than the thickness of the gate oxide layer in the peripheral device region. Generally, the operating voltage of CPU or GPU transistors is lower than that of transistors in the I / O device region; for example, the operating voltage of a CPU transistor is 0.75V, while the operating voltage of transistors in the I / O device region is 1.2V or even 1.8V. Therefore, typically, for the sake of reliability and electrical performance of transistors in the I / O device region, the gate oxide layer of transistors in the I / O device region is thicker than that in the logic device region. This difference in thickness mainly comes from the thickness of the interface layer (i.e., silicon oxide layer) between the high-k dielectric (High-K, HK) dielectric layer and the transistor channel in the High-K Metal Gate (HKMG). In other words, the interface layer in the gate oxide layer of the logic device region is thinner than the interface layer in the I / O device region, while the HK dielectric layer above the interface layer in both regions is the same thickness. The interface layer and the HK dielectric layer together form the gate dielectric layer of the corresponding transistor, thus the thickness of the gate oxide layer in the logic device region is less than that in the peripheral device region.

[0026] The target material layer 170 is used to provide a process platform for forming the first target structure and the second target structure.

[0027] In this embodiment, in the step of providing the substrate 100, the target material layer 170 is a dielectric layer, the first target structure is a first trench, and the second target structure is a second trench.

[0028] The first and second trenches provide space for subsequent processes, and the target material layer 170 is a dielectric layer used to isolate the structures formed in the first and second trenches.

[0029] In this embodiment, the dielectric layer material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, LK (low-K dielectric layer) and ULK (ultralow-K dielectric layer).

[0030] In this embodiment, during the step of providing the substrate 100, a mask material layer 110 is also formed between the target material layer 170 and the second core material layer 200.

[0031] The mask material layer 110 is used to subsequently form the second pattern transfer layer.

[0032] Specifically, in this embodiment, the mask material layer 110 has a stacked structure, including a titanium nitride layer and a silicon oxide layer located on the titanium nitride layer.

[0033] The second core material layer 200 is used to form the second core layer and the third core layer in the future.

[0034] In this embodiment, after the second and third core layers are formed, the second core layer will be removed subsequently. Therefore, the material of the second core material layer 200 is an easily removable material, thereby reducing the difficulty of removing the second core layer and minimizing damage to other film layers located below the second core material layer 200. Therefore, the material of the second core material layer 200 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the material of the second core material layer 200 is amorphous silicon (a-Si).

[0035] In this embodiment, during the step of providing the substrate 100, an etch stop layer 300 is also formed between the first core material layer 200 and the second core material layer 400.

[0036] The etch stop layer 300 is used to form the first pattern transfer layer in the future. The etch stop layer 300 is also used as an etch stop layer when the first core material layer 400 is patterned in the future, and protects the second core material layer 200 from damage.

[0037] In this embodiment, the etching stop layer 300 is made of one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, and tungsten nitride. In this embodiment, the etching stop layer 300 is made of silicon oxide.

[0038] The first core material layer 400 is used to form the first core layer in the subsequent process.

[0039] In this embodiment, after the first core layer is formed, it will be removed subsequently. Therefore, the material of the first core material layer 400 is one that is easy to remove, thereby reducing the difficulty of removing the first core layer and minimizing damage to other film layers located below the first core material layer 400. Therefore, the material of the first core material layer 400 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the material of the first core material layer 400 is amorphous silicon (a-Si).

[0040] Reference Figure 3 and Figure 4 The first core material layer 400 is graphically represented to form a first core layer 410 discretely located in the first region 100a. The first core layer 410 includes multiple layers along a first direction (e.g., ...). Figure 4 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 4 The first sub-core layer 411 and the second sub-core layer 412 are arranged in parallel along the Y direction. Along the second direction, one first sub-core layer 411 and two adjacent second sub-core layers 412 are alternately distributed. The width of the second sub-core layer 412 is greater than the width of the first sub-core layer 411. The first direction is perpendicular to the second direction.

[0041] The first core layer 410 is used to provide support for the subsequent formation of the first sidewall. One first sub-core layer 411 and two adjacent second sub-core layers 412 form a cycle. The first core layer 410 is composed of multiple cycles along the second direction. The width of the second sub-core layer 412 is greater than the width of the first sub-core layer 411, so that the second sub-core layer 412 forms multiple first target structures with smaller widths in the target material layer 170. The first sub-core layer 411 is used to transfer together with the first sidewall to form the first target structures with larger widths in the target material layer 170.

[0042] In this embodiment, a dry etching process is used to pattern the first core material layer 400. Dry etching of amorphous silicon is relatively easy to stop on the silicon oxide material, which serves as the first etching stop layer 300 in this embodiment.

[0043] Dry etching is a dry etching process with anisotropic etching characteristics. Its longitudinal etching rate is much greater than its transverse etching rate. Therefore, by selecting the dry etching process, it is beneficial to improve the pattern transfer accuracy. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the first core layer 410.

[0044] Accordingly, in this embodiment, the material of the first core layer 410 is amorphous silicon (a-Si), which reduces damage to the etch stop layer 300 during the patterning of the first core material layer 400. After the first core material layer 400 is patterned, the etch stop layer 300 still maintains good dimensional and morphological accuracy. Furthermore, the first core layer 410 is made of an easy-to-remove material, and the subsequent removal of the first core layer 410 has little impact on the etch stop layer 300.

[0045] It should be noted that in this embodiment, the size and pitch of the first core layer 410 are set according to the size and pitch of the first target structure subsequently formed in the first region 100a.

[0046] refer to Figure 3 The step of graphically representing the first core material layer 400 and forming the first core layer 410 discretely located in the first region 100a includes forming a first mask layer 320 discretely located on the first core material layer 400 in the first region 100a.

[0047] The first mask layer 320 is used as an etching mask for patterning the first core material layer 400.

[0048] In this embodiment, the first mask layer 320 includes a SOC layer, an anti-reflective coating (Si-ARC) on the SOC, and a photoresist layer on the anti-reflective coating (Si-ARC). The first mask layer 320 can be formed by photolithography and several etching steps.

[0049] refer to Figure 4 The first core material layer 400 is patterned along the first mask layer 320 to form the first core layer 410 discrete in the first region 100a.

[0050] In this embodiment, after forming the first core layer 410, the method further includes removing the first mask layer 320.

[0051] Remove the first mask layer 320 to prepare for the subsequent formation of the first sidewall.

[0052] Reference Figure 5 and Figure 6 This forms the first sidewall 510, which covers the sidewall of the first core layer 410.

[0053] The first sidewall 510 is used as an etching mask for the subsequent patterning of the second core material layer 200.

[0054] In this embodiment, the material of the first sidewall 510 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0055] Titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide can form a good etching selectivity with the first core layer 410, thereby reducing damage to the first sidewall 510 in the subsequent step of removing the first core layer 410.

[0056] Specifically, refer to Figure 5 The step of forming a first sidewall 510 covering the sidewalls of the first core layer 410 includes forming a first sidewall material layer 500 covering the sidewalls and top of the first core layer 410 and above the second core material layer 200.

[0057] Specifically, in this embodiment, the first sidewall material layer 500 covers the sidewalls and top of the first core layer 410, as well as the top of the etching stop layer 300.

[0058] The first sidewall material layer 500 is used to directly form the first sidewall 510. Accordingly, the material of the first sidewall material layer 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0059] In this embodiment, an atomic layer deposition process is used to form a first sidewall material layer 500 covering the sidewalls and top of the first core layer 410 and the top of the etch stop layer 300.

[0060] The first sidewall material layer 500 formed by atomic layer deposition has good thickness uniformity and good step coverage, which enables the first sidewall material layer 500 to cover the sidewalls and top of the first core layer 410 and the top of the second core material layer 200 in good conformal manner.

[0061] refer to Figure 6 Remove the first sidewall material layer 500 located on top of the first core layer 410 and the second core material layer 200, and retain the first sidewall material layer 500 located on the sidewall of the first core layer 410 as the first sidewall 510.

[0062] Specifically, in this embodiment, the first sidewall material layer 500 located on top of the first core layer 410 and the etching stop layer 300 is removed.

[0063] In this embodiment, a dry etching process is used to remove the first sidewall material layer 500 at the top of the first core layer 410 and the top of the etching stop layer 300.

[0064] Dry etching is an anisotropic dry etching process. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the first core layer 410 and the etching stop layer 300. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the first sidewall 510.

[0065] Reference Figure 7 and Figure 8 The first sub-core layer 411 is modified to form a third sub-core layer 413 with an etching selectivity ratio to the second sub-core layer 412.

[0066] A third sub-core layer 413 with an etching selectivity ratio to the second sub-core layer 412 is formed, such that when the second sub-core layer 412 is subsequently removed, the third sub-core layer 413 is retained for pattern transfer to the second core material layer 200 together with the first sidewall 510.

[0067] In this embodiment, before the second sub-core layer 412 is subsequently removed, the method further includes: modifying a portion of the second core material layer 200 in the second region 100b to form a third core material layer 210 with an etching selectivity ratio to the remaining second core material layer 200. The remaining second core material layer 200 is separated in the second region 100b and surrounded by the third core material layer 210 in the second region 100b.

[0068] A portion of the second core material layer 200 in the second region 100b is modified to obtain a third core material layer 210 with an etching selectivity ratio to the second core material layer 200. This makes it easier to remove the remaining second core material layer 200 in the future. At the same time, the damage to the third core material layer 210 is reduced during the removal of the remaining second core material layer 200. The third core material layer 210 is used to prepare for the subsequent patterning of the target material layer 170 in the second region 100b.

[0069] In this embodiment, in the same step, the first sub-core layer 411 and a portion of the second core material layer 200 of the second region 100b are modified.

[0070] In the same step, modifying the first sub-core layer 411 and part of the second core material layer 200 of the second region 100b is beneficial to simplifying the process flow and improving process efficiency.

[0071] In this embodiment, during the step of modifying the first sub-core layer 411 and a portion of the second core material layer 200 in the second region 100b, ion implantation is performed on the first sub-core layer 411 and a portion of the second core material layer 200 in the second region 100b to form a corresponding third sub-core layer 413 and a third core material layer 210.

[0072] Ion implantation technology has the advantages of uniform large-area ion implantation, more accurate control of ion doping depth and high repeatability. Using ion implantation to obtain the third sub-core layer 413 and the third core material layer 210 is beneficial for accurately controlling the doping concentration and distribution of the third sub-core layer 413 and the third core material layer 210, as well as the penetration depth into the second core material layer 200, so that the ion distribution in the third core material layer 210 is more uniform.

[0073] In this embodiment, in the step of performing ion implantation on the first sub-core layer 411 and a portion of the second core material layer 200 of the second region 100b, the implanted ions include one or more of boron, phosphorus, arsenic, boron chloride, boron dichloride and carbon.

[0074] In this embodiment, the materials of the second core material layer 200 and the first sub-core layer 411 are amorphous silicon. Implanting one or more ions of boron, phosphorus, arsenic, boron chloride, boron dichloride and carbon into the second core material layer 200 and the first sub-core layer 411 can transform the amorphous silicon into a material with a higher etch selectivity than the amorphous silicon, thereby obtaining a third core material layer 210 with a higher etch selectivity than the second core material layer 200, and a third sub-core layer 413 with a higher etch selectivity than the first sub-core layer 411.

[0075] refer to Figure 7 The modification process includes forming a second protective layer 610 that is separate on the second core material layer 200 of the second region 100b and covers the second core material layer 200, the second sub-core layer 412 and the first sidewall 510 of the first region 100a and exposes the first sub-core layer 411.

[0076] The second protective layer 610 of the first region 100a is used to protect the first sidewall 510, the second sub-core layer 412 and the second core material layer 200 of the first region 100a from damage. The first sub-core layer 411 is exposed in the first region 100a, so that the first sub-core layer 411 can be modified. The second protective layer 610 of the second region 100b is used as a mask for modifying the second core material layer 200 of the second region 100b.

[0077] In this embodiment, the material of the second protective layer 610 includes spin-on carbon (SOC) material.

[0078] Specifically, in this embodiment, the step of forming a second protective layer 610 that is separate on the second core material layer 200 of the second region 100b and covers the second core material layer 200, the second sub-core layer 412 and the first sidewall 510 of the first region 100a and exposes the first sub-core layer 411 includes: forming a first protective material layer that covers the second core material layer 200, the first core layer 410 and the first sidewall 510.

[0079] The first protective material layer is used to form the second protective layer 610.

[0080] Accordingly, in this embodiment, the first protective material layer is a planarization layer, and the material of the first protective material layer includes spin-on carbon (SOC) material. Spin-on carbon is formed by a spin coating process, which has a low process cost; moreover, by using spin-on carbon, it is beneficial to improve the flatness of the top surface of the first protective material layer, thereby providing a good interface for the formation of the first protective layer.

[0081] Accordingly, in this embodiment, the first protective material layer covers the etching stop layer 300.

[0082] In this embodiment, a second mask layer is also formed on the first protective material layer. The second mask layer covers the first protective material layer of the first region 100a and exposes the first protective material layer above the first sub-core layer 411, and is separate from the first protective material layer of the second region 100b.

[0083] The second mask layer is used to pattern the first protective material layer.

[0084] In this embodiment, the second mask layer includes an anti-reflective coating (Si-ARC) and a photoresist layer located on the anti-reflective coating (Si-ARC).

[0085] In this embodiment, the first protective material layer located in the second region 100b is graphically represented, forming a first protective material layer that is separate from the second region 100b and a first protective material layer that retains the second core material layer 200 covering the first region 100a and exposes the first sub-core layer 411, which together serve as the second protective layer 610.

[0086] Specifically, in this embodiment, the second mask layer is used as the etching mask patterning first protective material layer.

[0087] In this embodiment, after patterning the first protective material layer located in the second region 100b, the method further includes: removing the second mask layer.

[0088] refer to Figure 8Using the second protective layer 610 as a mask, the first sub-core layer 411 and part of the second core material layer 200 of the second region 100b are modified to form the corresponding third sub-core layer 413 and third core material layer 210.

[0089] Specifically, in this embodiment, the first sub-core layer 411 and a portion of the second core material layer 200 in the second region 100b are subjected to ion implantation using the second protective layer 610 as a mask to form the corresponding third sub-core layer 413 and third core material layer 210.

[0090] It should be noted that in this embodiment, a photomask and photolithography etching process are used to pattern the second mask layer located in the second region 100b and the second mask layer located in the first region 100a. The first protective material layer is patterned using the second mask layer to form the second protective layer 610. Then, the second protective layer 610 is used as a mask to perform ion implantation on the second core material layer 200 and the first sub-core layer 411 to form the corresponding third core material layer 210 and the third sub-core layer 413. The process of forming the second protective layer 610 has high flexibility. The width and pitch of the second protective layer 610 are easy to adjust. Correspondingly, the width and pitch of the remaining second core material layers 200 located in the second region 100b are easy to adjust. Thus, it is possible to obtain some second target structures with larger pitches in the second region 100b and improve the design freedom of patterning.

[0091] Specifically, in this embodiment, in the step of modifying a portion of the second core material layer 200 in the second region 100b to form a third core material layer 210 having an etching selectivity ratio with the remaining second core material layer 200, the remaining second core material layer 200 is along the second direction (e.g., Figure 8 The dimensions of the third core material layer 210 (shown in the Y direction) are 35nm to 200nm and the pitch is 76nm to 200nm. The dimensions of the third core material layer 210 along the second direction are 35nm to 200nm and the pitch is 76nm to 200nm.

[0092] refer to Figure 9 After forming the corresponding third sub-core layer 210 and third core material layer 210, the process also includes: removing the second protective layer 610.

[0093] Remove the second protective layer 610 to prepare for the subsequent formation of the first protective layer.

[0094] In this embodiment, the second protective layer 610 is removed by etching.

[0095] In this embodiment, either isotropic or anisotropic etching processes can be used. It is only necessary to ensure the etching selectivity of the etching process so that the etching process has a large etching selectivity for the second protective layer 610 and the first sidewall 510, thereby reducing the damage to the first sidewall 510 during the removal of the second protective layer 610.

[0096] refer to Figure 10 Remove the second sub-core layer 412.

[0097] The second sub-core layer 412 is removed to prepare for the subsequent patterning etching of the stop layer 300 and the second core material layer 200 using the first sidewall 510 and the third sub-core layer 413 as masks.

[0098] In this embodiment, a wet etching process is used to remove the second sub-core layer 412.

[0099] Wet etching has the characteristics of isotropic etching, which is beneficial for completely removing the second sub-core layer 412. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the first sidewall 510 during the removal of the second sub-core layer 412.

[0100] refer to Figure 11 Before the second core material layer 200 is patterned using the first protective layer, the first sidewall 510 and the third sub-core layer 413 as a mask, the process also includes: patterning an etching stop layer 300 using the first sidewall 510 and the third sub-core layer 413 as a mask to form the first pattern transfer layer 310.

[0101] The first pattern transfer layer 310 is used as an etching mask for the second core material layer 200 of the subsequent patterning of the first region 100a.

[0102] refer to Figure 12 A first protective layer 710 is formed on the second core material layer 200 located in the second region 100b, and a first protective layer opening 720 is formed in the first protective layer 710 extending in the first direction and arranged in parallel in the second direction.

[0103] The first protective layer 710 is used as an etching mask for the subsequent patterning of the second core material layer 200.

[0104] In this embodiment, in the step of forming the first protective layer 710 on the second core material layer 200 located in the second region 100b, the first protective layer 710 is separated on the second core material layer 200 and the third core material layer 210.

[0105] Correspondingly, the first protective layer 710 is also used as an etching mask for the subsequent patterning of the third core material layer 210.

[0106] In this embodiment, the first protective layer 710 is patterned from the planarization layer. The material of the first protective layer 710 includes spin-on carbon (SOC) material or spin-on carbon and a residual portion of the third mask layer. Whether the third mask layer remains is related to the process selection and does not affect subsequent steps. Spin-on carbon is formed by a spin coating process, which has a low process cost. Moreover, by using spin-on carbon, the flatness of the top surface of the planarization layer is improved, thereby providing a good interface for the formation of the first protective layer 710.

[0107] In this embodiment, the step of forming a first protective layer 710 on the second core material layer 200 and the third core material layer 210 located in the second region 100b includes: forming a first protective material layer covering the second core material layer 200, the third core material layer 210, the third sub-core layer 413, the first sidewall 510 and the sidewall of the first graphic transfer layer 310.

[0108] In this embodiment, a third mask layer is also formed on the first protective material layer. The third mask layer exposes the first protective material layer in the first region 100a and is located on the first protective material layer in the second region 100b.

[0109] The third mask layer is used to pattern the first protective material layer.

[0110] In this embodiment, the third mask layer includes an anti-reflective coating (Si-ARC) and a photoresist layer located on the anti-reflective coating (Si-ARC).

[0111] In this embodiment, the first protective material layer is graphically represented, the first protective material layer in the first region 100a is removed, the first sidewall 510 in the first region 100a is exposed, and multiple portions of the first protective material layer extending along the first direction and the portion of the first protective material layer along the second direction in the second region 100b are removed, and the remaining first protective material layer in the second region 100b is retained as the first protective layer 710.

[0112] Specifically, in this embodiment, the third mask layer is used as the first protective material layer for etching mask patterning.

[0113] In this embodiment, after forming the first protective layer 710 on the second core material layer 200 and the third core material layer 210 of the second region 100b, the method further includes removing the third mask layer.

[0114] refer to Figure 13 The second core material layer 200 is patterned using the first protective layer 710, the first sidewall 510 and the third sub-core layer 513 as a mask to form the second core layer 210.

[0115] In this embodiment, in the step of patterning the second core material layer 200 using the first protective layer 710 and the first sidewall 510 as a mask to form the second core layer 220, the third core material layer 210 is also patterned using the first protective layer 710 as a mask to form the third core layer 230 corresponding to the third core material layer 210.

[0116] It should be noted that the second core layer 220 is patterned from the second core material layer 200, while the third core layer 230 is patterned from the third core material layer 210. The etching selectivity of the original second core material layer 200 and third core material layer 210 due to the modification treatment will not disappear due to the patterning process. In other words, the second core layer 220 and the third core layer 230 still retain a high etching selectivity. For example, during etching with KOH or SCl solution, the second core layer 220 will be removed at a relatively fast etching rate, while the third core layer 230 will be almost unaffected.

[0117] It should also be noted that in this embodiment, a single photomask and related lithography and etching processes are used to pattern the third mask layer located in the first region 100a and the second region 100b. The first protective material layer is then patterned using the third mask layer to form the first protective layer 710. Next, the first protective layer 710 located in the second region 100b and the first sidewall 510 located in the first region are used as masks to pattern the second core material layer 200 and the third core material layer 210, forming the third core layer 230 with an etching selectivity ratio to the second core layer 220, and the second core layer 220 located below the first sidewall 510 in the first region. Because the process of defining the third mask layer using a single photomask offers high flexibility and diverse patterns, the design is relatively free within the limits allowed by a single lithography operation. That is, the size and pitch of the first protective layer opening 720 within the first protective layer 710 are relatively free, as long as they meet the limits of single DUV lithography and the pitch is greater than approximately 76 nm. This allows for greater freedom in the design of the relative size and pitch of the groove formed by the second sidewall material layer supported by the sidewalls of the second core layer 220 and the third core layer 230, thereby enabling the acquisition of a second target structure with a larger pitch in the second region 100b and increasing the degree of freedom in the graphical design.

[0118] After the second core layer 220 is removed, the third core layer 230 serves as part of the etching mask for the target material layer 170 of the subsequent patterned second region 100b, and also provides support for the subsequent formation of the second sidewall.

[0119] Accordingly, in this embodiment, the material of the second core layer 220 is amorphous silicon (a-Si), and the material of the third core layer 230 is amorphous silicon doped with boron, phosphorus or arsenic.

[0120] In this embodiment, in the step of patterning the second core material layer 200 using the first sidewall 510 and the third sub-core layer 413 as a mask, the second core material layer 200 of the first region 100a is patterned using the first pattern transfer layer 310 as a mask, forming a second core layer 220 discrete in the first region 100a.

[0121] Using the first pattern transfer layer 310 as a mask to pattern the second core material layer 200 of the first region 100a, forming the second core layer 220 discrete in the first region 100a, is beneficial to improving the pattern transfer accuracy, thereby improving the pattern size accuracy of the second core layer 220.

[0122] It should be noted that the second core layer 220 of the first region 100a is derived from the first sidewall 510. The pitch of the first sidewall 510 has been halved based on the pitch of the first mask layer 320. This is also a SADP process, achieving a reduction from the single DUV lithography etching limit of approximately 80nm to approximately 40nm. This prepares for the subsequent formation of the second sidewall on the sidewall of the second core layer, achieving a further halving of the second sidewall pitch compared to the first sidewall 510. This is also a characteristic of the SAQP process, and the reason why SAQP can form patterns with a pitch of approximately 24nm.

[0123] In this embodiment, in the step of patterning the third core material layer 210 using the first protective layer 710 as a mask, the third sub-core layer 413 is also removed.

[0124] refer to Figure 15 Remove the first protective layer 710.

[0125] Remove the first protective layer 710 to prepare for the subsequent removal of the second core layer 220.

[0126] In this embodiment, a dry etching process is used to remove the first protective layer 710.

[0127] In this embodiment, either isotropic or anisotropic etching processes can be used. It is only necessary to ensure the etching selectivity of the etching process so that the etching process has a large etching selectivity for the first protective layer 710 and the third core layer 230, thereby reducing the damage to the third core layer 230 during the removal of the first protective layer 710.

[0128] refer to Figure 15 Remove the first side wall 510.

[0129] Remove the first side wall 510 to prepare for the subsequent formation of the second side wall.

[0130] In this embodiment, after forming the second core layer 220, the method further includes removing the first graphics transfer layer 310.

[0131] Remove the first graphic transfer layer 310 to prepare for the subsequent formation of the second sidewall.

[0132] In this embodiment, a wet etching process is used to remove the first sidewall 510 and the first pattern transfer layer 310.

[0133] Wet etching has the characteristics of isotropic etching, which is beneficial for completely removing the first sidewall 510 and the first pattern transfer layer 310. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the second core layer 220 and the third core layer 230 during the removal of the first sidewall 510 and the first pattern transfer layer 310.

[0134] Reference Figure 16 and Figure 17 This forms a second sidewall 810 that covers the sidewall of the second core layer 220.

[0135] The second sidewall 810 is used as a partial etching mask for the target material layer 170 of the subsequent patterning of the first region 100a and the second region 100b.

[0136] Specifically, in this embodiment, in the step of forming the second sidewall 810 covering the sidewall of the second core layer 220, the second sidewall 810 is formed covering the sidewalls of the second core layer 220 and the third core layer 230.

[0137] In this embodiment, the material of the second sidewall 810 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0138] Titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide can form a good etching selectivity with the second core layer 220, thereby reducing damage to the second sidewall 810 in the subsequent step of removing the second core layer 220.

[0139] Specifically, refer to Figure 16 The step of forming a second sidewall 810 covering the sidewalls of the second core layer 220 and the third core layer 230 includes forming a second sidewall material layer 800 covering the sidewalls and top of the second core layer 220 and the third core layer 230, and the top of the base 100.

[0140] The second sidewall material layer 800 is used to directly form the second sidewall 810. Accordingly, the material of the second sidewall material layer 800 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0141] In this embodiment, an atomic layer deposition process is used to form a second sidewall material layer 800 covering the sidewalls and top of the second core layer 220 and the third core layer 230, as well as the top of the substrate 100.

[0142] The second sidewall material layer 800 formed by atomic layer deposition has good thickness uniformity and good step coverage, which enables the second sidewall material layer 800 to cover the sidewalls and top of the second core layer 220 and the third core layer 230, as well as the top of the substrate 100 in good conformal manner.

[0143] refer to Figure 17 Remove the second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230, as well as on top of the base 100, and retain the second sidewall material layer 800 located on the sidewalls of the second core layer 220 and the third core layer 230 as the second sidewall 810.

[0144] In this embodiment, a dry etching process is used to remove the second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230, as well as on top of the substrate 100.

[0145] Dry etching is an anisotropic dry etching process. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the second core layer 220 and the third core layer 230. At the same time, dry etching is more directional, which is beneficial to improve the sidewall morphology quality and dimensional accuracy of the second sidewall 810.

[0146] In this embodiment, the second sidewall material layer 800 located on top of the second core layer 220 and the third core layer 230, as well as on top of the base 100, is removed to expose the top of the second core layer 220 and the third core layer 230.

[0147] refer to Figure 18 Remove the second core layer 220 of the first zone 100a and part of the second core layer 220 of the second zone 100b.

[0148] The second core layer 220 of the first region 100a and part of the second core layer 220 of the second region 100b are removed to prepare for the subsequent patterning of the target material layer 170 of the first region 100a and the second region 100b using the second sidewall 810 and the remaining second core layer 220 as a mask.

[0149] Specifically, in this embodiment, in the step of removing the second core layer 220 of the first region 100a and part of the second core layer 220 of the second region 100b, the second core layer 220 of the first region 100a and the second region 100b is removed, and the third core layer 230 is retained.

[0150] The second core layer 220 is removed to prepare for the subsequent patterning of the target material layer 170 of the first region 100a and the second region 100b using the second sidewall 810 and the third core layer 230 as masks.

[0151] In this embodiment, a wet etching process is used to remove the second core layer 220 of the first region 100a and part of the second core layer 220 of the second region 100b.

[0152] Specifically, in this embodiment, a wet etching process is used to remove the second core layer 220.

[0153] Wet etching has the characteristics of isotropic etching, which is beneficial for completely removing the second core layer 220. Moreover, wet etching has relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the second sidewall 810 during the removal of the second core layer 220.

[0154] In this embodiment, in the step of removing the second core layer 220 using a wet etching process, the etching solution of the wet etching process includes one or more of KOH solution, THMA solution and SC1 solution.

[0155] In this embodiment, the second core layer 220 is undoped silicon, while the third core layer 230 is doped silicon. KOH or THMA solutions have a high etching rate for undoped silicon but almost no etching rate for doped silicon (especially doped with boron ions). Therefore, using KOH or THMA solutions as etching solutions can effectively remove the second core layer 220 while minimizing damage to the third core layer 230. This ensures that the removal of the second core layer 220 has almost no impact on other components during the pattern transfer process.

[0156] Reference Figure 19 and Figure 20 Using the second sidewall 810 and the remaining second core layer 220 as a mask, a target material layer 170 is patterned to form a first target structure 131 located in the first region 100a and a second target structure 141 located in the second region 100b. The first target structure 131 corresponding to the interval between adjacent second sub-core layers 412 and corresponding to the first sub-core layer 411 is the first sub-target structure 130a, and the first target structure 131 between adjacent first sub-target structures 120a is the second sub-target structure 130b. Both the first target structure 131 and the second target structure 141 extend along a first direction, and the pitch of adjacent first target structures 131 is less than or equal to the pitch of adjacent second target structures 141.

[0157] In this embodiment, for the first region 100a, a first core layer 410 is formed separately in the first region 100a. Along the second direction, multiple first core layers 410 are arranged in an alternating pattern of a first sub-core layer 411 and two adjacent second sub-core layers 412. The width of the second sub-core layer 412 is greater than the width of the first sub-core layer 411. That is, every two adjacent second sub-core layers 412 and one first sub-core layer 411 constitute a repeating unit of the first core layer 410, forming a first sidewall 510 covering the sidewall of the first core layer 410. The first sub-core layer 411 is modified to form a structure similar to the first core layer. The third sub-core layer 413 with etching selectivity is used as a mask to pattern the second core material layer 200 of the first region 100a, forming the second core layer 220 discretely located in the first region 100a. The width of the second core layer 220 corresponding to the first sidewall 510 of the third sub-core layer 413 and its sidewall is relatively large, forming the second sidewall 810 covering the sidewall of the second core layer 220. The target material layer 170 is patterned using the second sidewall 810 as a mask. Since the SAQP process is adopted, the width of the first target structure 131 corresponding to the third sub-core layer 413 is relatively large. The SAQP process can form a first target structure 131 with a small pitch. At the same time, the first target structure 131 corresponding to the interval of the adjacent second sub-core layer 412 and the first sub-core layer 411 is a first sub-target structure 130a. The first target structure 131 between adjacent first sub-target structures 130a is a second sub-target structure 130b. By modifying the first sub-core layer 411, a first sub-target structure 130a with a larger width can be formed. At the same time, five second sidewalls 810 are formed in the interval of the adjacent second sub-core layer 412 and the area between the first sub-core layer 411. Thus, four second sub-target structures 130b can be formed between adjacent first sub-target structures 130a, so that the device unit composed of the first sub-target structure 130a and the second sub-target structure 130b has a high integration degree. For the second region 100b, the second core material layer 200 is patterned using the first protective layer 710 as a mask to form the second core layer 220. A second sidewall 810 is formed covering the sidewalls of the second core layer 220. The second sidewall 810 and the remaining second core layer 220 are used as a mask to pattern the target material layer 170, which is a second target structure 141 with a larger pitch that can be formed using the SALELE process. In other words, this embodiment can effectively integrate the SAQP process and the SALELE process, and can form both the first target structure 131 with a smaller pitch and the second target structure 141 with a larger pitch on the same substrate 100. This is beneficial for meeting more semiconductor process requirements through process integration and improving the design freedom in the patterning process.

[0158] Specifically, in this embodiment, in the step of using the second sidewall 810 and the remaining second core layer 220 as the mask patterning target material layer 170, the second sidewall 810 and the third core layer 230 are used as the mask patterning target material layer 170.

[0159] It should be noted that, in this embodiment, as mentioned above, the width of the first sub-core layer 411 and the width of the first sidewalls 510 on both sides are the areas used to form the first sub-target structure 130a, and the spacing between adjacent second sub-core layers 412 is the area used to form the first sub-target structure 130a. Therefore, in this embodiment, in the step of graphically representing the first core material layer 400 to form the first core layer 410 separated in the first region 100a, the width of the first sub-core layer 411 is equal to the difference between the preset width of the first sub-target structure 130a and twice the preset width of the first sidewall 510, and the width of the second sub-core layer 412 is equal to the sum of the preset width of the first sub-target structure 130a, twice the preset width of the second sidewall 810, and twice the preset width of the first sidewall 510.

[0160] It should also be noted that, in this embodiment, as mentioned above, in the region between the adjacent first sub-core layer 411 and the second sub-core layer 412, and in the region where the width of the second sub-core layer 412 is used to form the second sub-target structure 130b, in this embodiment, in the step of graphically forming the first core material layer 400 to form the first core layer 410 separated in the first region 100a, the width of the second sub-core layer 412 is equal to the sum of the preset width of the second sub-target structure 130b and twice the preset width of the second sidewall 810, and the distance between the adjacent first sub-core layer 411 and the second sub-core layer 412 is equal to the sum of the preset width of the second sub-target structure 130b, twice the preset width of the second sidewall 810, and twice the preset width of the first sidewall 510.

[0161] In this embodiment, in the step of forming a first target structure 131 located in the first region 100a and a second target structure 141 located in the second region 100b by using the second sidewall 810 and the remaining second core layer 220 (third core layer 230) as mask patterning target material layer 170, a first trench 130 and a second trench 140 located in the medium layer are formed by using the second sidewall 810 and the third core layer 230 as mask patterning medium layer.

[0162] The first trench 130 provides space for the subsequent formation of the first metal line, and the second trench 140 provides space for the subsequent formation of the second metal line.

[0163] The second trench 140 can also be divided into type A second trench 140a and type B second trench 140b. Type A second trench 140a is the second trench 140 corresponding to the second core layer 220, and type B second trench 140b is the second trench 140 corresponding to the groove formed by the second sidewall material layer 800 of the sidewall of the second core layer 220 and the third core layer 230.

[0164] Specifically, refer to Figure 19 The step of patterning the target material layer 170 using the second sidewall 810 and the remaining second core layer 220 (third core layer 230) as a mask includes: patterning the mask material layer 110 using the second sidewall 810 and the third core layer 230 as a mask to form a second pattern transfer layer 120.

[0165] The second pattern transfer layer 120 is used as an etching mask for the patterning target material layer 170.

[0166] In this embodiment, after the second pattern transfer layer 120 is formed, before the target material layer 170 is patterned using the second pattern transfer layer 120 as a mask, the method further includes: removing the second sidewall 810 and the third core layer 230 to prepare for the subsequent patterning of the target material layer 170 using the second pattern transfer layer 120 as a mask.

[0167] refer to Figure 20 The second pattern transfer layer 120 is used as a mask to pattern the target material layer 170.

[0168] The second graphic transfer layer 120 transfers the graphics of the second sidewall 810 and the third core layer 230 to the target material layer 170, which helps to improve the graphic transfer accuracy and makes the dimensional accuracy of the first target structure 131 and the second target structure 141 higher.

[0169] It should be noted that the second pattern transfer layer 120 is used as a mask to pattern the target material layer 170 using an etching process, thereby thinning the second pattern transfer layer 120 in the step of patterning the target material layer 170, for example, by removing the silicon oxide layer in the second pattern transfer layer 120.

[0170] refer to Figure 21 After forming the first target structure 131 and the second target structure 141, the process also includes: removing the second graphics transfer layer 120.

[0171] Remove the second pattern transfer layer 120 to prepare for the subsequent formation of the first and second metal lines.

[0172] refer to Figure 22After forming the first target structure 131 located in the first region 100a and the second target structure 141 located in the second region 100b, the forming method further includes: forming a first metal line 150 in the first trench 130; and forming a second metal line 160 in the second trench 140.

[0173] The first metal line 150 and the second metal line 160 are metal interconnects used in subsequent process steps.

[0174] Specifically, the first metal wire 150 can be divided into type A first metal wires 150a with a larger width and type B first metal wires 150b with a smaller width. Four type B first metal wires 150b are formed between adjacent type A first metal wires 150a.

[0175] Similarly, the second metal wire can also be divided into type A second metal wire 160a and type B second metal wire 160b. Type A second metal wire 160a is the metal wire corresponding to the second core layer 220, and type B second metal wire 160b is the metal wire corresponding to the groove formed by the second sidewall material layer 800 of the sidewall of the second core layer 220 and the third core layer 230. Type A second metal wire 160a and type B second metal wire 160b can be arranged alternately, and the pitch, width and length between them can be adjusted, so the design is more flexible than that of the first metal wire 150.

[0176] The dielectric layer is an inter-metal dielectric (IMD) layer, which is used to achieve electrical isolation between metal interconnects in the back end of line (BEOL) process.

[0177] As an example, such as Figure 23 The present invention illustrates the formation method of simultaneously forming a 6T Standard Cell, a 7.5T Standard Cell, and a memory / input / output (SRAM / IO) region on a substrate, wherein the black areas indicate the corresponding device regions.

[0178] Specifically, such as Figure 23 (a) In a 6T standard cell region, the metal pitch reaches approximately 30nm, and uniform metal lines are required for routing, along with wide power rails. Therefore, the SAQP process is used for fabrication. Figure 23(b) In the 7.5T standard cell area, the metal pitch is around 40nm, and uniform metal lines are required for routing, along with wide power rails. Therefore, the SALELE process is used for fabrication. Figure 23 (c) In the memory / input / output area, if the metal pitch is greater than 50nm and metal wiring without a clear layout rule is required, the SALELE process is used for formation. It can be seen that by using the method of this embodiment, combining SAQP and SALELE, it is possible to simultaneously realize the formation of 6T standard cell area, 7.5T standard cell area and memory / input / output area with different pitch requirements on the same substrate.

[0179] It should be noted that in this embodiment, in the first region 100a, the wider A-type first metal line 150a is used as the power line of the standard unit, and the narrower B-type first metal line 150b is used as the device structure line of the standard unit. Thus, this embodiment utilizes the SAQP process, that is, four device structure lines are formed between adjacent power lines in the standard unit, which helps to reduce the area occupied by the standard unit and improve the integration of the standard unit.

[0180] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a target material layer located on the substrate, wherein a second core material layer is formed on the substrate and a first core material layer is located on the second core material layer, and the substrate includes a first region and a second region; The first core material layer is graphically represented to form a first core layer separate from the first region. The first core layer includes multiple first sub-core layers and second sub-core layers that extend along a first direction and are arranged in parallel along a second direction. Along the second direction, one first sub-core layer and two adjacent second sub-core layers are alternately distributed. The width of the second sub-core layer is greater than the width of the first sub-core layer. The first direction is perpendicular to the second direction. A first sidewall is formed that covers the sidewall of the first core layer; The first sub-core layer is modified to form a third sub-core layer with an etch selectivity ratio to the second sub-core layer; Remove the second sub-core layer; A first protective layer is formed on the second core material layer in the second region, and a plurality of separate first protective layer openings are formed in the first protective layer extending along the first direction and arranged in parallel along the second direction. The second core material layer is patterned using the first protective layer, the first sidewall, and the third sub-core layer as a mask to form the second core layer; Remove the third sub-core layer, the first protective layer, and the first sidewall; A second sidewall is formed that covers the sidewall of the second core layer; Remove the second core layer of the first region and part of the second core layer of the second region; Using the second sidewall and the remaining second core layer as a mask, the target material layer is patterned to form a first target structure located in the first region and a second target structure located in the second region. The first target structure corresponding to the interval between adjacent second sub-core layers and the first target structure corresponding to the first sub-core layer are the first sub-target structures, and the first target structure between adjacent first sub-target structures is the second sub-target structure. Both the first target structure and the second target structure extend along a first direction, and the pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the target material layer is a dielectric layer, the first target structure is a first trench, and the second target structure is a second trench; In the step of patterning the target material layer using the second sidewall and the remaining second core layer as a mask, the dielectric layer is patterned using the second sidewall and the remaining second core layer as a mask to form a first trench and a second trench located in the dielectric layer; After forming the first target structure located in the first region and the second target structure located in the second region, the forming method further includes: forming a first metal wire in the first trench; A second metal wire is formed in the second trench.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the first region includes a logic device region, and the second region includes a peripheral device region; the thickness of the gate oxide layer in the logic device region is less than the thickness of the gate oxide layer in the peripheral device region.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The pitch between adjacent first target structures is 24 nm to 38 nm; the pitch between adjacent second target structures is 38 nm to 200 nm.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of graphically representing the first core material layer to form a first core layer separate from the first region, the width of the first sub-core layer is equal to the difference between the preset width of the first sub-target structure and twice the preset width of the first sidewall, and the spacing between adjacent second sub-core layers is equal to the sum of the preset width of the first sub-target structure, twice the preset width of the second sidewall, and twice the preset width of the first sidewall.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of graphically representing the first core material layer to form a first core layer separate from the first region, the width of the second sub-core layer is equal to the sum of the preset width of the second sub-target structure and twice the preset width of the second sidewall, and the distance between adjacent first sub-core layers and second sub-core layers is equal to the sum of the preset width of the second sub-target structure, twice the preset width of the second sidewall, and twice the preset width of the first sidewall.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first sidewall covering the sidewall of the first core layer includes: forming a first sidewall material layer covering the sidewall and top of the first core layer, and above the second core material layer; Remove the first sidewall material layer located on top of the first core layer and above the second core material layer, and retain the first sidewall material layer located on the sidewall of the first core layer as the first sidewall.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before removing the second sub-core layer, the process further includes: modifying a portion of the second core material layer in the second region to form a third core material layer with an etching selectivity ratio to the remaining second core material layer, wherein the remaining second core material layer is separated in the second region and surrounded by the third core material layer in the second region; In the step of forming a first protective layer on the second core material layer located in the second region, the first protective layer is separated on the second core material layer and the third core material layer. In the step of patterning the second core material layer using the first protective layer and the first sidewall as a mask to form the second core layer, the third core material layer is also patterned using the first protective layer as a mask to form the third core layer corresponding to the third core material layer. In the step of forming a second sidewall covering the sidewall of the second core layer, a second sidewall covering the sidewalls of the second core layer and the third core layer is formed. In the step of removing the second core layer of the first region and part of the second core layer of the second region, the second core layers of the first region and the second region are removed, while the third core layer is retained; In the step of patterning the target material layer using the second sidewall and the remaining second core layer as a mask, the target material layer is patterned using the second sidewall and the third core layer as a mask.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the same step, the modification treatment is performed on the first sub-core layer and a portion of the second core material layer in the second region.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The modification process includes: forming a second protective layer on the second core material layer of the second region and covering the second core material layer, the second sub-core layer and the first sidewall of the first region, while exposing the first sub-core layer; Using the second protective layer as a mask, the first sub-core layer and a portion of the second core material layer in the second region are modified to form the corresponding third sub-core layer and third core material layer. After forming the corresponding third sub-core layer and third core material layer, the process also includes: removing the second protective layer.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of modifying the first sub-core layer and a portion of the second core material layer in the second region, ion implantation is performed on the first sub-core layer and a portion of the second core material layer in the second region to form a corresponding third sub-core layer and a third core material layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the material of the second core material layer includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide; In the step of performing ion implantation on the first sub-core layer and a portion of the second core material layer in the second region, the ions implanted in the ion implantation process include one or more of boron, phosphorus, arsenic, boron chloride, boron dichloride, and carbon.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of modifying a portion of the second core material layer in the second region to form a third core material layer with an etching selectivity ratio to the remaining second core material layer, the remaining second core material layer has a dimension of 35nm to 200nm and a pitch of 76nm to 200nm along the second direction, and the third core material layer has a dimension of 35nm to 200nm and a pitch of 76nm to 200nm along the second direction.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first protective layer on the second core material layer located in the second region includes: forming a first protective material layer covering the second core material layer, the third sub-core layer and the first sidewall; The first protective material layer is graphically represented. The first protective material layer in the first region is removed. In the second region, multiple first protective material layers with lengths extending along the first direction and widths extending along the second direction are removed. The remaining first protective material layer in the second region is retained as the first protective layer.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second sidewall covering the sidewall of the second core layer includes: forming a second sidewall material layer covering the sidewall and top of the second core layer, and the top of the substrate; Remove the second sidewall material layer located on top of the second core layer and on top of the base, and retain the second sidewall material layer located on the sidewall of the second core layer as the second sidewall.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, an etch stop layer is also formed between the first core material layer and the second core material layer; Before patterning the second core material layer using the first protective layer, the first sidewall, and the third sub-core layer as a mask, the method further includes: patterning an etching stop layer using the first sidewall and the third sub-core layer as a mask to form a first pattern transfer layer. In the step of patterning the second core material layer using the first sidewall and the third sub-core layer as a mask, the second core material layer of the first region is patterned using the first pattern transfer layer as a mask to form a second core layer separate from the first region. After forming the second core layer, the process also includes: removing the first graphics transfer layer.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second core layer of the first region and part of the second core layer of the second region are removed by a wet etching process.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, In the step of removing the second core layer of the first region and a portion of the second core layer of the second region using a wet etching process, the etching solution of the wet etching process includes one or more of KOH solution, THMA solution and SC1 solution.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a mask material layer is also formed between the target material layer and the second core material layer; The step of patterning the target material layer using the second sidewall and the remaining second core layer as a mask includes: patterning the mask material layer using the second sidewall and the remaining second core layer as a mask to form a second pattern transfer layer; The target material layer is patterned using the second pattern transfer layer as a mask; After forming the first target structure and the second target structure, the method further includes: removing the second graphics transfer layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, After the second pattern transfer layer is formed, before patterning the target material layer using the second pattern transfer layer as a mask, the method further includes: removing the second sidewall and the remaining second core layer.

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