Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises an SOI substrate which is provided with a substrate plate, a buried oxide layer located on the substrate plate, and an element layer located on the buried oxide layer; a circuit element disposed on the element layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit element; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer. The buried power rail is isolated from the element layer by the buried oxide layer and the trench fill oxide of the trench isolation region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an improved silicon-on-insulator (SOI) semiconductor structure and its fabrication method. Background Technology

[0002] Back-of-disk (BPD) technology is one of the key technologies for achieving sub-3nm wafer sizes. BPD eliminates the need for signal and power lines to compete for interconnect resources on the front side of the wafer. Instead, as the name suggests, power signals are transmitted from the back side of the wafer, so only signals are transmitted via front-side interconnects. BPD also allows for the optimal fabrication of these different metal layers, including wider lines for Vdd and Vss signal transmission, and finer lines for carrying high-frequency signals. Nevertheless, BPD still faces many fabrication challenges that need to be overcome. Summary of the Invention

[0003] The main objective of this invention is to provide an improved silicon-on-insulator (SOI) semiconductor structure and its fabrication method to overcome the shortcomings or disadvantages of the prior art.

[0004] One aspect of the present invention provides a semiconductor structure comprising a silicon-on-insulator (SOI) substrate having a substrate, a buried oxide layer on the substrate, and a component layer on the buried oxide layer; a circuit component disposed on the component layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit component; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer, wherein the buried power rail is isolated from the component layer by a trench-filled oxide layer in the buried oxide layer and the trench isolation region.

[0005] According to an embodiment of the present invention, the embedded power rail is electrically connected to a through-hole in the base plate.

[0006] According to an embodiment of the present invention, the through-hole is isolated from the substrate by an oxide liner layer.

[0007] According to an embodiment of the present invention, the through-hole includes a conductive layer.

[0008] According to an embodiment of the present invention, the embedded power rail includes a work function metal layer and an integral metal layer.

[0009] According to an embodiment of the present invention, the conductive layer is in direct contact with the work function metal layer.

[0010] According to an embodiment of the present invention, the conductive layer is in direct contact with the bulk metal layer.

[0011] According to an embodiment of the present invention, the circuit element is a transistor, wherein the transistor includes a metal gate, and the metal gate includes the work function metal layer and the body metal layer.

[0012] According to an embodiment of the present invention, a top surface of the metal gate, a top surface of the embedded power rail, and a top surface of the first dielectric layer are coplanar.

[0013] According to an embodiment of the present invention, the semiconductor structure further includes: a second dielectric layer covering the top surface of the first dielectric layer, the top surface of the metal gate, and the top surface of the buried power rail; and a partial interconnect disposed in the second dielectric layer to electrically connect the buried power rail to a source / drain doped region of the transistor or the metal gate.

[0014] Another aspect of the present invention provides a method for forming a semiconductor structure. A silicon-on-insulator (SOI) substrate is provided, having a substrate, a buried oxide layer on the substrate, and a component layer on the buried oxide layer; a circuit component is formed on the component layer, and the circuit component is surrounded by a trench isolation region in the SOI substrate; an etch stop layer is formed around the circuit component; a first dielectric layer is formed on the etch stop layer; and a buried power rail is formed in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer, wherein the buried power rail is isolated from the component layer by a trench-filled oxide layer in the buried oxide layer and the trench isolation region.

[0015] According to an embodiment of the present invention, the embedded power rail is electrically connected to a through-hole in the base plate.

[0016] According to an embodiment of the present invention, the through-hole is isolated from the substrate by an oxide liner layer.

[0017] According to an embodiment of the present invention, the through-hole includes a conductive layer.

[0018] According to an embodiment of the present invention, the embedded power rail includes a work function metal layer and an integral metal layer.

[0019] According to an embodiment of the present invention, the conductive layer is in direct contact with the work function metal layer.

[0020] According to an embodiment of the present invention, the conductive layer is in direct contact with the bulk metal layer.

[0021] According to an embodiment of the present invention, the circuit element is a transistor, wherein the transistor includes a metal gate, and the metal gate includes the work function metal layer and the body metal layer.

[0022] According to an embodiment of the present invention, a top surface of the metal gate, a top surface of the embedded power rail, and a top surface of the first dielectric layer are coplanar.

[0023] According to an embodiment of the present invention, the method further includes: forming a second dielectric layer on the top surface of the first dielectric layer, the top surface of the metal gate, and the top surface of the buried power rail; and forming a partial interconnect in the second dielectric layer to electrically connect the buried power rail to a source / drain doped region of the transistor or the metal gate. Attached Figure Description

[0024] Figures 1 to 10 This is a schematic diagram illustrating a method for forming a semiconductor structure according to an embodiment of the present invention.

[0025] Symbol Explanation

[0026] 10 Semiconductor Structure

[0027] 100 Silicon-coated Insulating Substrate

[0028] 110 Active (Active) Region

[0029] 111 Base Plate

[0030] 112 Embedded oxide layer

[0031] 113 Component Layer

[0032] 120 Trench-filled oxide

[0033] 210 Gate oxide layer

[0034] 220 High-k dielectric constant material layer

[0035] 230 Barrier Layer

[0036] 242 Work Function Metals

[0037] 244 Body Metal Layer

[0038] 250 polycrystalline silicon layers

[0039] 280 Etching Stop Layer

[0040] 310 dielectric layer

[0041] 320 dielectric layer

[0042] 400 conductive layer

[0043] 420 oxide liner

[0044] BPR Embedded Power Rail

[0045] D circuit elements

[0046] DR doped region

[0047] IT trench isolation area

[0048] Connections within the LI area

[0049] MG metal gate

[0050] TG gate trench

[0051] TSV Through Hole Detailed Implementation

[0052] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0053] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0054] like Figures 1 to 10 As shown, it is a schematic diagram illustrating a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, firstly, a silicon-on-insulator (SOI) substrate 100 is provided, comprising a base substrate 111, a buried oxide layer 112 on the base substrate 111, and a device layer 113 on the buried oxide layer 112. According to an embodiment of the invention, the base substrate 111 is, for example, a silicon substrate with a thickness of, for example, 7 to 100 micrometers. According to an embodiment of the invention, the thickness of the buried oxide layer 112 is, for example, 2000 angstroms. According to an embodiment of the invention, the device layer 113 is, for example, an epitaxial silicon layer with a thickness of, for example, 1400 angstroms.

[0055] Next, a shallow trench insulation fabrication process is performed to form a trench isolation region IT and a plurality of active regions 110 isolated by the trench isolation region IT in the component layer 113. According to an embodiment of the present invention, the trench isolation region IT includes a trench-filling oxide 120, such as silicon dioxide, but not limited thereto.

[0056] like Figure 2As shown, next, an oxidation fabrication process is performed to form a gate oxide layer 210 on the active region 110. Then, a deposition fabrication process is performed, for example, a chemical vapor deposition (CVD) process, to deposit a high-k material layer 220 and a barrier layer 230 over the entire SOI substrate 100. According to an embodiment of the present invention, the high-k material layer 220 is, for example, HfO2, but is not limited thereto. According to an embodiment of the present invention, the barrier layer 230 is, for example, TiN, but is not limited thereto.

[0057] like Figure 3 As shown, subsequent photolithography and etching processes are performed to form a trench PT that penetrates the barrier layer 230, the high-k material layer 220, the trench-filling oxide 120, and the embedded oxide layer 112. According to an embodiment of the present invention, the trench PT is located in the trench isolation region IT, and the bottom portion of the substrate 111 is exposed.

[0058] like Figure 4 As shown, a deposition process is then performed to deposit a polysilicon layer 250 over the entire SOI substrate 100, filling the trench PT with the polysilicon layer 250. Another deposition process, such as chemical vapor deposition (CVD), is then performed to form a hard mask layer 260 on the polysilicon layer 250. According to an embodiment of the present invention, the hard mask layer 260 is, for example, a silicon nitride layer, but is not limited thereto.

[0059] Next, as Figure 5 As shown, photolithography and etching processes are performed to pattern the hard mask layer 260, polysilicon layer 250, barrier layer 230, and high-k material layer 220 into a dummy gate structure DP. Simultaneously, a dummy polysilicon track DPR is formed within the trench PT. According to an embodiment of the present invention, the dummy polysilicon track DPR extends downward into the trench-filling oxide 120 and the buried oxide layer 112, and directly contacts the substrate 111.

[0060] like Figure 6 As shown, an ion implantation process is then performed to form a doped region DR within the active region 110. According to an embodiment of the invention, the doped region DR can be, for example, an N-type or P-type doped region, serving as the source / drain doped region of a transistor. Next, a deposition process, such as chemical vapor deposition (CVD), is performed to deposit an etch stop layer 280, for example, a silicon nitride layer, over the entire SOI substrate 100. According to an embodiment of the invention, the etch stop layer 280 is conformally deposited on the trench isolation region IT, the dummy polysilicon track DPR, and the dummy gate structure DP. Then, another deposition process, such as chemical vapor deposition (CVD), is performed to deposit a dielectric layer 310 over the entire SOI substrate 100.

[0061] Then, as Figure 7 As shown, a replacement metal gate (RMG) fabrication process is performed. For example, a chemical mechanical polishing process is first performed to polish the dielectric layer 310 until the hard mask layer 260 is exposed. Then, a photolithography and etching process is performed to form a trench T in the dielectric layer 310 and the etch stop layer 280, exposing the dummy polysilicon track DPR. The dummy gate structure DP and the dummy polysilicon track DPR are then removed together to form the gate trench TG and the trench PT is cleared.

[0062] like Figure 8 As shown, next, a work function metal layer 242 and a body metal layer 244 are deposited over the entire SOI substrate 100, followed by planarization using a chemical mechanical polishing (CMP) process, thus simultaneously forming the metal gate MG and the buried power rail BPR. The metal gate MG and the doped region DR can constitute a circuit element D, such as a MOS transistor element, wherein the doped region DR is a source / drain doped region. The buried power rail BPR includes the work function metal layer 242 and the body metal layer 244.

[0063] like Figure 9 As shown, next, a dielectric layer 320 is deposited on the dielectric layer 310, the buried power rail BPR, and the metal gate MG. Then, a metallization process is performed to form regional interconnects LI within the dielectric layer 320 and dielectric layer 310, which electrically connect the doped region DR and the buried power rail BPR. According to embodiments of the present invention, the dielectric layer 310 and dielectric layer 320 may be a single layer or a combination of multiple dielectric layers stacked together.

[0064] like Figure 10 As shown, photolithography, etching, and metallization processes are then performed to form a through-plate via (TSV) in the substrate 111. A power rail (BPR) is embedded and electrically connected to the TSV in the substrate 111. According to an embodiment of the invention, the TSV includes a conductive layer 400, for example, a copper layer. According to an embodiment of the invention, the TSV is electrically isolated from the substrate 111 via an oxide pad layer 420. According to an embodiment of the invention, the conductive layer 400, for example, a copper layer, of the TSV is in direct contact with the work function metal layer 242. According to an embodiment of the invention, the conductive layer 400, for example, a copper layer, of the TSV is in direct contact with the body metal layer 244.

[0065] Structurally, such as Figure 10As shown, the semiconductor structure 10 of the present invention includes a silicon-on-insulator (SOI) substrate 100, having a substrate 111, a buried oxide layer 112 on the substrate 111, and a component layer 113 on the buried oxide layer 112; a circuit element D disposed on the component layer 113 and surrounded by a trench isolation region IT in the SOI substrate 100; an etch stop layer 280 disposed around the circuit element D; a dielectric layer 310 disposed on the etch stop layer 280; and a buried power rail BPR embedded in the dielectric layer 310, the etch stop layer 280, the trench isolation region IT, and the buried oxide layer 112, wherein the buried power rail BPR is isolated from the component layer 113 by a trench-filled oxide 120 in the buried oxide layer 112 and the trench isolation region IT.

[0066] According to an embodiment of the present invention, the embedded power rail (BPR) is electrically connected to a through-plate via (TSV) in the substrate 111. According to an embodiment of the present invention, the through-plate via (TSV) is isolated from the substrate 111 by an oxide liner layer 420. According to an embodiment of the present invention, the through-plate via (TSV) includes a conductive layer 400.

[0067] According to an embodiment of the present invention, the embedded power rail (BPR) includes a work function metal layer 242 and a bulk metal layer 244. According to an embodiment of the present invention, the conductive layer 400 is in direct contact with the work function metal layer 242. According to an embodiment of the present invention, the conductive layer 400 is in direct contact with the bulk metal layer 244.

[0068] According to an embodiment of the present invention, circuit element D is a transistor and includes a metal gate MG. According to an embodiment of the present invention, the top surface of the metal gate MG, the top surface of the buried power rail BPR, and the top surface of the dielectric layer 310 are coplanar.

[0069] According to an embodiment of the present invention, the semiconductor structure further includes: a dielectric layer 320 covering the top surface of the dielectric layer 310, the top surface of the metal gate MG, and the top surface of the buried power rail BPR; and a local interconnect LI disposed in the dielectric layer 320 to electrically connect the buried power rail BPR to the doped region DR (source / drain doped region) of the circuit element D (transistor). In other embodiments, the local interconnect LI can electrically connect the buried power rail BPR to the gate of the circuit element D (transistor).

[0070] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising: A silicon-on-insulator (SOI) substrate having a substrate, a buried oxide layer on the substrate, and a component layer on the buried oxide layer; Circuit elements are disposed on the element layer and surrounded by trench isolation regions in the SOI substrate; An etch stop layer is disposed around the circuit element; A first dielectric layer is disposed on the etch stop layer; as well as An embedded power rail is embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the embedded oxide layer, wherein the embedded power rail is isolated from the component layer by the trench-filled oxide of the embedded oxide layer and the trench isolation region.

2. The semiconductor structure as described in claim 1, wherein, The embedded power rail is electrically connected to the through-hole in the base plate.

3. The semiconductor structure as described in claim 2, wherein, The through-hole is isolated from the substrate by an oxide liner.

4. The semiconductor structure as described in claim 2, wherein, The through-hole contains a conductive layer.

5. The semiconductor structure as described in claim 4, wherein, The embedded power rail consists of a work function metal layer and a bulk metal layer.

6. The semiconductor structure as described in claim 5, wherein, The conductive layer is in direct contact with the work function metal layer.

7. The semiconductor structure as claimed in claim 5, wherein, The conductive layer is in direct contact with the bulk metal layer.

8. The semiconductor structure as claimed in claim 5, wherein, The circuit element is a transistor, wherein the transistor includes a metal gate, wherein the metal gate includes a work function metal layer and a body metal layer.

9. The semiconductor structure as claimed in claim 8, wherein, The top surface of the metal gate, the top surface of the embedded power rail, and the top surface of the first dielectric layer are coplanar.

10. The semiconductor structure as claimed in claim 9, wherein, Also includes: The second dielectric layer covers the top surface of the first dielectric layer, the top surface of the metal gate, and the top surface of the embedded power rail; and Local interconnects are provided in the second dielectric layer to electrically connect the buried power rail to the source / drain doped region of the transistor or the metal gate.

11. A method for forming a semiconductor structure, comprising: A silicon-on-insulator (SOI) substrate is provided, having a substrate, a buried oxide layer on the substrate, and a component layer on the buried oxide layer. A circuit element is formed on this element layer, and the circuit element is surrounded by a trench isolation region in the SOI substrate; An etch stop layer is formed around the circuit element; A first dielectric layer is formed on the etch stop layer; as well as Buried power rails are formed in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer, wherein the buried power rails are isolated from the component layer by the trench-filled oxide of the buried oxide layer and the trench isolation region.

12. The method of claim 11, wherein, The embedded power rail is electrically connected to the through-hole in the base plate.

13. The method of claim 12, wherein, The through-hole is isolated from the substrate by an oxide liner.

14. The method of claim 12, wherein, The through-hole contains a conductive layer.

15. The method of claim 14, wherein, The embedded power rail consists of a work function metal layer and a bulk metal layer.

16. The method of claim 15, wherein, The conductive layer is in direct contact with the work function metal layer.

17. The method of claim 15, wherein, The conductive layer is in direct contact with the bulk metal layer.

18. The method of claim 15, wherein, The circuit element is a transistor, wherein the transistor includes a metal gate, wherein the metal gate includes a work function metal layer and a body metal layer.

19. The method of claim 18, wherein, The top surface of the metal gate, the top surface of the embedded power rail, and the top surface of the first dielectric layer are coplanar.

20. The method of claim 19, wherein, Also includes: A second dielectric layer is formed on the top surface of the first dielectric layer, the top surface of the metal gate, and the top surface of the embedded power rail; and Local interconnects are formed in the second dielectric layer to electrically connect the buried power rail to the source / drain doped region of the transistor or the metal gate.

Images