Data voltage supply circuit, display device and driving method

Abstract

The invention provides a data voltage providing circuit, a display device and a driving method. The data voltage supply circuit is applied to the display device, the display device comprises a data driver, a plurality of columns of pixels and a plurality of columns of data lines, and each column of pixels comprises M columns of sub-pixels; m is an integer greater than or equal to 3; the data driver comprises a plurality of data voltage supply ends; the data voltage supply circuit comprises a plurality of supply circuits; the providing circuit is used for controlling the M columns of sub-pixels included in the corresponding columns of pixels to receive the data voltages provided by the corresponding data voltage providing ends, or controlling the M columns of sub-pixels included in the corresponding columns of pixels to obtain the data voltages provided for the M columns of sub-pixels according to the data voltages provided for at least one other column of pixels. The data voltage providing circuit is capable of driving a high-resolution display screen with a low-resolution signal.

Description

Data voltage supply circuit, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a data voltage supply circuit, a display device, and a driving method. Background Art

[0002] The related display device cannot drive a high-resolution display screen with a low-resolution signal and cannot meet the low-profile screen consumption.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a data voltage supply circuit, applied to a display device, the display device including a data driver, a plurality of columns of pixels, and a plurality of columns of data lines, the columns of pixels including M columns of sub-pixels; M is an integer greater than or equal to 3; the data driver including a plurality of data voltage supply terminals; the data voltage supply circuit including a plurality of supply circuits;

[0005] The providing circuit is used to control the M columns of sub-pixels included in the corresponding column of pixels to respectively receive data voltages provided by corresponding data voltage providing terminals, or to control the M columns of sub-pixels included in the corresponding column of pixels to obtain data voltages provided to the M columns of sub-pixels based on the data voltage provided for at least one other column of pixels.

[0006] Optionally, the providing circuit includes a first gating circuit and a second gating circuit; the column of sub-pixels is electrically connected to a corresponding column data line, and receives a data voltage through the corresponding column data line;

[0007] The first gating circuit is electrically connected to M data voltage supply terminals and the current M columns of data lines, respectively, and is used to control the connection or disconnection between the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines; the mth data line is electrically connected to the mth column of sub-pixels among the M columns of sub-pixels included in the corresponding column of pixels; m is a positive integer less than or equal to M;

[0008] The second gating circuit is electrically connected to the current M column data lines, a first group of M column data lines electrically connected to M columns of sub-pixels included in a first target column of pixels, and a second group of M column data lines electrically connected to M columns of sub-pixels included in a second target column of pixels, respectively, and is configured to control a data voltage received by the current M column data lines based on a data voltage received by the first group of M column data lines and a data voltage received by the second group of M column data lines;

[0009] The first target column of pixels is a column of pixels other than the corresponding column of pixels, the second target column of pixels is a column of pixels other than the corresponding column of pixels, and the first target column of pixels and the second target column of pixels are different column pixels;

[0010] The current M columns of data lines are data lines electrically connected to the M columns of sub-pixels included in the corresponding column of pixels;

[0011] The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals, and the data lines electrically connected to the M columns of sub-pixels in the second target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

[0012] Optionally, the providing circuit includes a first gating circuit and a third gating circuit; the column of sub-pixels is electrically connected to a corresponding column data line, and receives a data voltage through the corresponding column data line;

[0013] The first gating circuit is electrically connected to M data voltage supply terminals and the current M columns of data lines, respectively, and is used to control the connection or disconnection between the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines; the mth data line is electrically connected to the mth column of sub-pixels among the M columns of sub-pixels included in the corresponding column of pixels; m is a positive integer less than or equal to M;

[0014] The third gating circuit is electrically connected to the current M column data lines and a first group of M column data lines electrically connected to M columns of sub-pixels included in the first target column of pixels, respectively, and is used to control the data voltage received by the current M column data lines according to the data voltage received by the first group of M column data lines;

[0015] The first target column of pixels is a column of pixels other than the corresponding column of pixels;

[0016] The current M columns of data lines are data lines electrically connected to the M columns of sub-pixels included in the corresponding column of pixels;

[0017] The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

[0018] Optionally, the first gating circuit includes M first switching circuits;

[0019] The mth first switch circuit is electrically connected to the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines, and is used to control the connection or disconnection between the mth data voltage supply terminal and the mth data line.

[0020] Optionally, the second gating circuit includes M second switch circuits, M first resistors, M third switch circuits and M second resistors;

[0021] an mth second switch circuit electrically connected to the mth column data line in the first group of M columns of data lines and the first end of the mth first resistor, respectively, for controlling connection or disconnection between the mth column data line in the first group of M columns of data lines and the first end of the mth first resistor; and a second end of the mth first resistor electrically connected to the mth column data line in the current M columns of data lines;

[0022] The first end of the mth second resistor is electrically connected to the mth column data line in the current M columns of data lines, and the mth third switching circuit is electrically connected to the second end of the mth second resistor and the mth column data line in the second group of M columns of data lines, respectively, and is used to control the connection or disconnection between the second end of the mth second resistor and the mth column data line in the second group of M columns of data lines.

[0023] Optionally, the third gating circuit includes M third resistors and M fourth switch circuits;

[0024] an m-th fourth switch circuit electrically connected to the first end of the m-th third resistor and the m-th data line in the first group of M columns of data lines, respectively, for controlling connection or disconnection between the first end of the m-th third resistor and the m-th data line in the first group of M columns of data lines;

[0025] The second end of the mth third resistor is electrically connected to the mth column data line among the current M columns of data lines;

[0026] The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

[0027] Optionally, the data driver includes at least one data driving circuit; the column of pixels includes three columns of sub-pixels;

[0028] The data driving circuit includes N data voltage supply terminals; N is a positive integer;

[0029] The a-th providing circuit includes an a-th first gating circuit and an a-th second gating circuit; a is a positive integer;

[0030] The first column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a-2 column, the second column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a-1 column, and the third column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a column.

[0031] The first column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-5 column, the second column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-4 column, and the third column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-3 column.

[0032] The first column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+1 column, the second column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+2 column, and the third column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+3 column.

[0033] The ath first gating circuit is electrically connected to the 6a-2th column data line, the 6a-1th column data line, the 6ath column data line, the 6a-2th data voltage supply terminal, the 6a-1th data voltage supply terminal, and the 6ath data voltage supply terminal, respectively, and is used to control the connection or disconnection between the 6a-2th column data line and the 6a-2th data voltage supply terminal, control the connection or disconnection between the 6a-1th column data line and the 6a-1th data voltage supply terminal, and control the connection or disconnection between the 6ath column data line and the 6ath data voltage supply terminal;

[0034] the ath second gating circuit being electrically connected to the 6a-5th column data line, the 6a-4th column data line, the 6a-3th column data line, the 6a+1th column data line, the 6a+2th column data line and the 6a+3th column data line, the 6a-2th column data line, the 6a-1th column data line and the 6a column data line, respectively, and being configured to control the data voltage received by the 6a-2th column data line according to the data voltage received by the 6a-5th column data line and the data voltage received by the 6a+1th column data line, control the data voltage received by the 6a-1th column data line according to the data voltage received by the 6a-4th column data line and the data voltage received by the 6a+2th column data line, and control the data voltage received by the 6a column data line according to the data voltage received by the 6a-3th column data line and the data voltage received by the 6a+3th column data line;

[0035] The data line in the 6a-5 column is directly electrically connected to the 6a-5 data voltage supply terminal, the data line in the 6a-4 column is directly electrically connected to the 6a-4 data voltage supply terminal, the data line in the 6a-3 column is directly electrically connected to the 6a-3 data voltage supply terminal, the data line in the 6a+1 column is directly electrically connected to the 6a+1 data voltage supply terminal, the data line in the 6a+2 column is directly electrically connected to the 6a+2 data voltage supply terminal, and the data line in the 6a+3 column is directly electrically connected to the 6a+3 data voltage supply terminal.

[0036] Optionally, N is a multiple of 6;

[0037] The data voltage supply circuit includes a fourth gating circuit;

[0038] The fourth selection circuit is electrically connected to the Nth column data line, the N-1th column data line, the N-2th column data line, the N-3th column data line, the N-4th column data line and the N-5th column data line, respectively, and is used to control the connection or disconnection between the Nth column data line and the N-3rd column data line, control the connection or disconnection between the N-1th column data line and the N-4th column data line, and control the connection or disconnection between the N-2th column data line and the N-5th column data line.

[0039] Optionally, N is a multiple of 6, the data driver includes B data driving circuits; B is an integer greater than 1;

[0040] The bth data driving circuit is electrically connected to the bth group of N columns of data lines, and the b+1th data circuit is electrically connected to the b+1th group of N columns of data lines, where b is a positive integer and b+1 is less than or equal to B;

[0041] The data voltage supply circuit includes a fifth gating circuit;

[0042] The fifth gating circuit is electrically connected to the N-5th data line in the b-th group of N column data lines, the N-4th data line in the b-th group of N column data lines, the N-3th data line in the b-th group of N column data lines, the N-2th data line in the b-th group of N column data lines, the N-1th data line in the b-th group of N column data lines, the N data line in the b-th group of N column data lines, the first column data line in the b+1-th group of N column data lines, the second column data line in the b+1-th group of N column data lines and the third column data line in the b+1-th group of N column data lines, respectively, for selecting the data line according to the data voltage received by the N-5th data line in the b-th group of N column data lines and the data voltage received by the b+1-th group of N column data lines. The data voltage received by the first column of N column data lines controls the data voltage received by the N-2th data line in the b-th group of N column data lines; the data voltage received by the N-1th data line in the b-th group of N column data lines is controlled based on the data voltage received by the N-4th data line in the b-th group of N column data lines and the data voltage received by the second column of N column data lines in the b+1-th group of N column data lines; the data voltage received by the N-3th data line in the b-th group of N column data lines and the data voltage received by the third column of N column data lines in the b+1-th group of N column data lines is controlled.

[0043] Optionally, the data driver includes at least one data driving circuit; the column of pixels includes three columns of sub-pixels;

[0044] The data driving circuit includes N data voltage supply terminals; N is a positive integer;

[0045] The a-th providing circuit includes an a-th first gating circuit and an a-th third gating circuit; a is a positive integer;

[0046] The ath first gating circuit is electrically connected to the 6a-2th column data line, the 6a-1th column data line, the 6ath column data line, the 6a-2th data voltage supply terminal, the 6a-1th data voltage supply terminal, and the 6ath data voltage supply terminal, respectively, and is used to control the connection or disconnection between the 6a-2th column data line and the 6a-2th data voltage supply terminal, control the connection or disconnection between the 6a-1th column data line and the 6a-1th data voltage supply terminal, and control the connection or disconnection between the 6ath column data line and the 6ath data voltage supply terminal.

[0047] The ath third selection circuit is electrically connected to the 6a-5th column data line, the 6a-4th column data line, the 6a-3th column data line, the 6a-2th column data line, the 6a-1th column data line and the 6a column data line, respectively, and is used to control the data voltage on the 6a-2th column data line according to the data voltage on the 6a-5th column data line, control the data voltage on the 6a-1th column data line according to the data voltage on the 6a-4th column data line, and control the data voltage on the 6a column data line according to the data voltage on the 6a-3th column data line.

[0048] Optionally, the mth first switching circuit includes an mth first switching transistor;

[0049] The gate of the mth first switch transistor is electrically connected to the first control voltage terminal, the first electrode of the mth first switch transistor is electrically connected to the mth data voltage supply terminal, and the second electrode of the mth first switch transistor is electrically connected to the mth data line;

[0050] The data voltage providing circuit includes a first control circuit;

[0051] The first control circuit is used to provide a first control voltage to the first control voltage terminal to control the mth first switching transistor to be turned on or off.

[0052] Optionally, the mth second switching circuit includes an mth second switching transistor, and the mth third switching circuit includes an mth third switching transistor;

[0053] The gate of the mth second switch transistor is electrically connected to the second control voltage terminal, the first electrode of the mth second switch transistor is electrically connected to the mth column data line in the first group of M columns of data lines, and the second electrode of the mth second switch transistor is electrically connected to the first end of the mth first resistor;

[0054] a gate of the mth third switch transistor being electrically connected to the second control voltage terminal, a first electrode of the mth third switch transistor being electrically connected to the second end of the mth second resistor, and a second electrode of the mth third switch transistor being electrically connected to the mth column data line of the second group of M columns of data lines;

[0055] The data voltage providing circuit includes a second control circuit;

[0056] The second control circuit is used to provide a second control voltage to the second control voltage terminal to control the mth second switching transistor to be turned on or off, and to control the mth third switching transistor to be turned on or off.

[0057] In a second aspect, an embodiment of the present disclosure provides a display device comprising a plurality of rows of gate lines, a plurality of columns of data lines, a plurality of rows and columns of pixels, a driving module, and the aforementioned data voltage supply circuit; the driving module is electrically connected to the plurality of rows of gate lines and is configured to provide driving signals to the gate lines;

[0058] The pixels located in the same row are electrically connected to the corresponding row gate line and are used to receive the driving signal provided by the corresponding row gate line;

[0059] Pixels located in the same column are electrically connected to the corresponding column data line and are used to receive data voltages from the corresponding column data line.

[0060] In a third aspect, an embodiment of the present disclosure provides a driving method, applied to the above-mentioned display device, the driving method comprising:

[0061] During the driving cycle, the driving module provides a driving signal to the gate line to control the multiple scan lines to turn on in sequence;

[0062] In the driving cycle, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scanning signals provided by at least two adjacent gate lines in the plurality of rows of gate lines turned on sequentially;

[0063] During at least a portion of the overlapping time period, the data line receives a data voltage that is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0064] In a fourth aspect, an embodiment of the present disclosure provides a driving method, applied to the above-mentioned display device, wherein a driving cycle includes a plurality of driving phases arranged in sequence; a 2n-1th row scanning signal provided by a 2n-1th row scanning line is the same as a 2nth row scanning signal provided by a 2nth row scanning line; the driving method includes:

[0065] In the nth driving phase, the 2n-1th scan line and the 2nth scan line are turned on, and the sub-pixels located in the 2n-1th row and the sub-pixels located in the 2nth row receive data voltages provided by corresponding data lines;

[0066] n is a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] FIG1 is a structural diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0068] FIG2 is a structural diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0069] FIG3 is a structural diagram of at least one embodiment of a first gating circuit;

[0070] FIG4 is a structural diagram of at least one embodiment of a second gating circuit;

[0071] FIG5A is a structural diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0072] FIG5B is a circuit diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0073] FIG5C is a circuit diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0074] FIG6 is a circuit diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0075] FIG7 is a circuit diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0076] FIG8 is a circuit diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0077] FIG9 is a circuit diagram of a data voltage providing circuit according to at least one embodiment of the present disclosure;

[0078] FIG10 is a waveform diagram corresponding to the driving method according to at least one embodiment of the present disclosure;

[0079] FIG. 11 is a waveform diagram corresponding to the driving method according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0081] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0082] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0083] The data voltage supply circuit according to an embodiment of the present disclosure is applied to a display device, wherein the display device includes a data driver, a plurality of columns of pixels, and a plurality of columns of data lines, wherein the columns of pixels include M columns of sub-pixels; M is an integer greater than or equal to 3; the data driver includes a plurality of data voltage supply terminals; and the data voltage supply circuit includes a plurality of supply circuits;

[0084] The providing circuit is used to control the M columns of sub-pixels included in the corresponding column of pixels to respectively receive data voltages provided by corresponding data voltage providing terminals, or to control the M columns of sub-pixels included in the corresponding column of pixels to obtain data voltages provided to the M columns of sub-pixels based on the data voltage provided for at least one other column of pixels.

[0085] When the data voltage providing circuit described in the embodiment of the present disclosure is in operation, the providing circuit can control the M columns of sub-pixels included in the corresponding column of pixels to obtain the data voltage provided to the M columns of sub-pixels based on the data voltage provided for at least one other column of pixels, thereby enabling a high-resolution display screen to be driven by a low-resolution signal, thereby meeting low-profile screen consumption.

[0086] In at least one embodiment of the present disclosure, the providing circuit includes a first gating circuit and a second gating circuit; the column of sub-pixels is electrically connected to a corresponding column data line and receives a data voltage through the corresponding column data line;

[0087] The first gating circuit is electrically connected to M data voltage supply terminals and the current M columns of data lines, respectively, and is used to control the connection or disconnection between the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines; the mth data line is electrically connected to the mth column of sub-pixels among the M columns of sub-pixels included in the corresponding column of pixels; m is a positive integer less than or equal to M;

[0088] The second gating circuit is electrically connected to the current M column data lines, a first group of M column data lines electrically connected to M columns of sub-pixels included in a first target column of pixels, and a second group of M column data lines electrically connected to M columns of sub-pixels included in a second target column of pixels, respectively, and is configured to control a data voltage received by the current M column data lines based on a data voltage received by the first group of M column data lines and a data voltage received by the second group of M column data lines;

[0089] The first target column of pixels is a column of pixels other than the corresponding column of pixels, the second target column of pixels is a column of pixels other than the corresponding column of pixels, and the first target column of pixels and the second target column of pixels are different column pixels;

[0090] The current M columns of data lines are data lines electrically connected to the M columns of sub-pixels included in the corresponding column of pixels;

[0091] The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals, and the data lines electrically connected to the M columns of sub-pixels in the second target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

[0092] In a specific implementation, the providing circuit may include a first gating circuit and a second gating circuit. The first gating circuit can control the connection or disconnection between the current M column data lines and the corresponding data voltage providing terminals. The second gating circuit can control the data voltages provided respectively according to the M columns of sub-pixels included in the two target columns of pixels, and provide data voltages for the current M column data lines.

[0093] In at least one embodiment of the present disclosure, M is equal to 3 as an example for description, but the present invention is not limited thereto. In actual operation, M can be an integer greater than 3.

[0094] As shown in FIG1 , a circuit P0 is provided including a first gating circuit 11 and a second gating circuit 12; a first column of pixels including a first red sub-pixel R01, a second green sub-pixel G2, a third blue sub-pixel B3, a fourth red sub-pixel R04, a fifth green sub-pixel G5, a sixth blue sub-pixel B6, a seventh red sub-pixel R07, an eighth green sub-pixel G8, and a ninth blue sub-pixel B9;

[0095] The first column of red sub-pixels R01 is electrically connected to the first column of data line DL1, the second column of green sub-pixels G2 is electrically connected to the second column of data line DL2, the third column of blue sub-pixels B3 is electrically connected to the third column of data line DL3, the fourth column of red sub-pixels R04 is electrically connected to the fourth column of data line DL4, the fifth column of green sub-pixels G5 is electrically connected to the fifth column of data line DL5, the sixth column of blue sub-pixels B6 is electrically connected to the sixth column of data line DL6, the seventh column of red sub-pixels R07 is electrically connected to the seventh column of data line DL7, the eighth column of green sub-pixels G8 is electrically connected to the eighth column of data line DL8, and the ninth column of blue sub-pixels B9 is electrically connected to the ninth column of data line DL9;

[0096] Among them, the current M columns of data lines are: the fourth column of data line DL4, the fifth column of data line DL5 and the sixth column of data line SL6;

[0097] The first target column of pixels is the first column of pixels, and the second target column of pixels is the second column of pixels;

[0098] The first gating circuit 11 is electrically connected to the fourth data voltage supply terminal Y4, the fifth data voltage supply terminal Y5, the sixth data voltage supply terminal Y6, the fourth column data line DL4, the fifth column data line DL5 and the sixth column data line DL6, respectively, and is used to control the connection or disconnection between the fourth data voltage supply terminal Y4 and the fourth column data line DL4, control the connection or disconnection between the fifth data voltage supply terminal Y5 and the fifth column data line DL5, and control the connection or disconnection between the sixth data voltage supply terminal Y6 and the sixth column data line DL6;

[0099] the second gating circuit 12 being electrically connected to the fourth column data line DL4, the fifth column data line DL5, the sixth column data line DL6, the first column data line DL1, the second column data line DL2, the third column data line DL3, the seventh column data line DL7, the eighth column data line DL8, and the ninth column data line DL9, respectively, and being configured to control the data voltage provided by the fourth column data line DL4 according to the data voltage provided by the first column data line DL1 and the data voltage provided by the seventh column data line DL7, control the data voltage provided by the fifth column data line DL5 according to the data voltage provided by the second column data line DL2 and the data voltage provided by the eighth column data line DL8, and control the data voltage provided by the sixth column data line DL6 according to the data voltage provided by the third column data line DL3 and the data voltage provided by the ninth column data line DL9;

[0100] The first column data line DL1 is electrically connected to the first data voltage supply terminal Y1, the second column data line DL2 is electrically connected to the second data voltage supply terminal Y2, the third column data line DL3 is electrically connected to the third data voltage supply terminal Y3, the seventh column data line DL7 is electrically connected to the seventh data voltage supply terminal Y7, the eighth column data line DL8 is electrically connected to the eighth data voltage supply terminal Y8, and the ninth column data line DL9 is electrically connected to the ninth data voltage supply terminal Y9.

[0101] When at least one embodiment shown in FIG. 1 is in operation,

[0102] When the first gating circuit 11 controls the fourth data voltage supply terminal Y4 to be connected to the fourth column data line DL4, controls the fifth data voltage supply terminal Y5 to be connected to the fifth column data line DL5, and controls the sixth data voltage supply terminal Y6 to be connected to the sixth column data line DL6, DL4 directly receives the data voltage provided by Y4, DL5 directly receives the data voltage provided by Y5, and DL6 directly receives the data voltage provided by Y6;

[0103] When the first selection circuit 11 controls the disconnection between the fourth data voltage supply terminal Y4 and the fourth column data line DL4, controls the disconnection between the fifth data voltage supply terminal Y5 and the fifth column data line DL5, and controls the disconnection between the sixth data voltage supply terminal Y6 and the sixth column data line DL6, the second selection circuit 12 controls the data voltage provided by the fourth column data line DL4 according to the data voltage provided by the first column data line DL1 and the data voltage provided by the seventh column data line DL7, controls the data voltage provided by the fifth column data line DL5 according to the data voltage provided by the second column data line DL2 and the data voltage provided by the eighth column data line DL8, and controls the data voltage provided by the sixth column data line DL6 according to the data voltage provided by the third column data line DL3 and the data voltage provided by the ninth column data line DL9. In this way, a low-resolution data voltage signal can be used to drive a high-resolution display screen.

[0104] In at least one embodiment shown in FIG. 1 , each row of sub-pixels in each column of sub-pixels is electrically connected to a corresponding scan line to receive a scan signal provided by the scan line.

[0105] In at least one embodiment of the present disclosure, the providing circuit may be provided on a Driver IC (driver integrated circuit).

[0106] In at least one embodiment of the present disclosure, the providing circuit includes a first gating circuit and a third gating circuit; the column of sub-pixels is electrically connected to a corresponding column data line and receives a data voltage through the corresponding column data line;

[0107] The first gating circuit is electrically connected to M data voltage supply terminals and the current M columns of data lines, respectively, and is used to control the connection or disconnection between the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines; the mth data line is electrically connected to the mth column of sub-pixels among the M columns of sub-pixels included in the corresponding column of pixels; m is a positive integer less than or equal to M;

[0108] The third gating circuit is electrically connected to the current M column data lines and a first group of M column data lines electrically connected to M columns of sub-pixels included in the first target column of pixels, respectively, and is used to control the data voltage received by the current M column data lines according to the data voltage received by the first group of M column data lines;

[0109] The first target column of pixels is a column of pixels other than the corresponding column of pixels;

[0110] The current M columns of data lines are data lines electrically connected to the M columns of sub-pixels included in the corresponding column of pixels;

[0111] The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

[0112] In a specific implementation, the providing circuit may include a first gating circuit and a third gating circuit. The first gating circuit can control the connection or disconnection between the current M column data lines and the corresponding data voltage providing terminals, and the third gating circuit can control the data voltage received by the current M column data lines according to the data voltage provided for the first target column pixels.

[0113] As shown in FIG2 , the providing circuit P0 includes a first gating circuit 11 and a third gating circuit 13 ;

[0114] The first column of pixels has a red subpixel R01, a green subpixel G2, a blue subpixel B3, a red subpixel R04, a green subpixel G5, and a blue subpixel B6;

[0115] The first column of red sub-pixels R01 is electrically connected to the first column of data line DL1, the second column of green sub-pixels G2 is electrically connected to the second column of data line DL2, the third column of blue sub-pixels B3 is electrically connected to the third column of data line DL3, the fourth column of red sub-pixels R04 is electrically connected to the fourth column of data line DL4, the fifth column of green sub-pixels G5 is electrically connected to the fifth column of data line DL5, and the sixth column of blue sub-pixels B6 is electrically connected to the sixth column of data line DL6;

[0116] Among them, the current M columns of data lines are: the fourth column of data line DL4, the fifth column of data line DL5 and the sixth column of data line SL6;

[0117] The first gating circuit 11 is electrically connected to the fourth data voltage supply terminal Y4, the fifth data voltage supply terminal Y5, the sixth data voltage supply terminal Y6, the fourth column data line DL4, the fifth column data line DL5 and the sixth column data line DL6, respectively, and is used to control the connection or disconnection between the fourth data voltage supply terminal Y4 and the fourth column data line DL4, control the connection or disconnection between the fifth data voltage supply terminal Y5 and the fifth column data line DL5, and control the connection or disconnection between the sixth data voltage supply terminal Y6 and the sixth column data line DL6;

[0118] The first column of data line DL1 is electrically connected to the first data voltage supply terminal Y1, the second column of data line DL2 is electrically connected to the second data voltage supply terminal Y2, and the third column of data line DL3 is electrically connected to the third data voltage supply terminal Y3;

[0119] The third selection circuit 13 is electrically connected to the first column data line DL1, the second column data line DL2, the third column data line DL3, the fourth column data line DL4, the fifth column data line DL5 and the sixth column data line DL6, respectively, and is used to control the data voltage controlled by the fourth column data line DL4 according to the data voltage provided by the first column data line DL1, control the data voltage controlled by the fifth column data line DL5 according to the data voltage provided by the second column data line DL2, and control the data voltage controlled by the sixth column data line DL6 according to the data voltage provided by the third column data line DL3.

[0120] When at least one embodiment shown in FIG. 2 is in operation,

[0121] When the first gating circuit 11 controls the fourth data voltage supply terminal Y4 to be connected to the fourth column data line DL4, controls the fifth data voltage supply terminal Y5 to be connected to the fifth column data line DL5, and controls the sixth data voltage supply terminal Y6 to be connected to the sixth column data line DL6, DL4 receives the data voltage provided by Y4, DL5 receives the data voltage provided by Y5, and DL6 receives the data voltage provided by Y6;

[0122] When the first selection circuit 11 controls the fourth data voltage supply terminal Y4 and the fourth column data line DL4 to be disconnected, controls the fifth data voltage supply terminal Y5 and the fifth column data line DL5 to be disconnected, and controls the sixth data voltage supply terminal Y6 and the sixth column data line DL6 to be disconnected, the third selection circuit 13 controls the data voltage controlled by the fourth column data line DL4 according to the data voltage provided by the first column data line DL1, controls the data voltage controlled by the fifth column data line DL5 according to the data voltage provided by the second column data line DL2, and controls the data voltage controlled by the sixth column data line DL6 according to the data voltage provided by the third column data line DL3, thereby realizing the use of low-resolution data voltage signals to drive a high-resolution display screen.

[0123] In at least one embodiment shown in FIG. 2 , when the first gating circuit 11 controls the fourth data voltage supply terminal Y4 to be disconnected from the fourth column data line DL4, controls the fifth data voltage supply terminal Y5 to be disconnected from the fifth column data line DL5, and controls the sixth data voltage supply terminal Y6 to be disconnected from the sixth column data line DL6, and the second gating circuit 12 controls the data voltage of the fourth column data line DL4 according to the data voltage provided by the first column data line DL1, controls the data voltage of the fifth column data line DL5 according to the data voltage provided by the second column data line DL2, and controls the data voltage of the sixth column data line DL6 according to the data voltage provided by the third column data line DL3,

[0124] When the sub-pixels in row A are turned on, the data voltage received by the sub-pixels in row A and row B is the average of the data voltage received by the sub-pixels in row A and row B and row B;

[0125] The data voltage received by the sub-pixel in the fifth column of row A is the average of the data voltage received by the sub-pixel in the second column of row A and the data voltage received by the sub-pixel in the eighth column of row A;

[0126] The data voltage received by the sub-pixel in the sixth column of row A is the average of the data voltage received by the sub-pixel in the third column of row A and the data voltage received by the sub-pixel in the ninth column of row A;

[0127] A is a positive integer;

[0128] That is, the transmittance of the sub-pixel in the fourth column of the Ath row is the average of the transmittance of the sub-pixel in the first column of the Ath row and the transmittance of the sub-pixel in the seventh column of the Ath row;

[0129] The transmittance of the sub-pixel in the fifth column of row A is the average of the transmittance of the sub-pixel in the second column of row A and the transmittance of the sub-pixel in the eighth column of row A;

[0130] The transmittance of the sub-pixel in the sixth column of row A is the average of the transmittance of the sub-pixel in the third column of row A and the transmittance of the sub-pixel in the ninth column of row A;

[0131] The above approach can achieve a uniform horizontal transition of the picture.

[0132] Optionally, the first gating circuit includes M first switching circuits;

[0133] The mth first switch circuit is electrically connected to the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines, and is used to control the connection or disconnection between the mth data voltage supply terminal and the mth data line.

[0134] In a specific implementation, the first gating circuit may include M first switch circuits, and the mth first switch circuit controls the connection or disconnection between the mth data voltage supply terminal and the mth data line.

[0135] As shown in FIG3 , at least one embodiment of the first gating circuit may include a first first switch circuit 31 , a second first switch circuit 32 , and a third first switch circuit 33 ;

[0136] The first first switch circuit 31 is electrically connected to the fourth data voltage supply terminal Y4 and the fourth column data line DL4 respectively, and is used to control the connection or disconnection between the fourth data voltage supply terminal Y4 and the fourth column data line DL4;

[0137] The second first switch circuit 32 is electrically connected to the fifth data voltage supply terminal Y5 and the fifth column data line DL5, respectively, and is used to control the connection or disconnection between the fifth data voltage supply terminal Y5 and the fifth column data line DL5;

[0138] The third first switch circuit 33 is electrically connected to the sixth data voltage supply terminal Y6 and the sixth column data line DL6 respectively, and is used to control the connection or disconnection between the sixth data voltage supply terminal Y6 and the sixth column data line DL6.

[0139] In at least one embodiment of the present disclosure as shown in FIG3 , when in operation, the sub-pixels in row A are all electrically connected to the scan lines in row A. When the scan lines in row A are turned on,

[0140] When the first first switch circuit 31 controls the connection between the fourth data voltage supply terminal Y4 and the fourth column data line DL4, the second first switch circuit 32 controls the connection between the fifth data voltage supply terminal Y5 and the fifth column data line DL5, and the third first switch circuit 33 controls the connection between the sixth data voltage supply terminal Y6 and the sixth column data line DL6, the sub-pixel in the fourth column of the A-th row directly receives the data voltage provided by Y4, the sub-pixel in the fifth column of the A-th row directly receives the data voltage provided by Y5, and the sub-pixel in the sixth column of the A-th row directly receives the data voltage provided by Y6;

[0141] A is a positive integer.

[0142] Optionally, the second gating circuit includes M second switch circuits, M first resistors, M third switch circuits and M second resistors;

[0143] an mth second switch circuit electrically connected to the mth column data line in the first group of M columns of data lines and the first end of the mth first resistor, respectively, for controlling connection or disconnection between the mth column data line in the first group of M columns of data lines and the first end of the mth first resistor; and a second end of the mth first resistor electrically connected to the mth column data line in the current M columns of data lines;

[0144] The first end of the mth second resistor is electrically connected to the mth column data line in the current M columns of data lines, and the mth third switching circuit is electrically connected to the second end of the mth second resistor and the mth column data line in the second group of M columns of data lines, respectively, and is used to control the connection or disconnection between the second end of the mth second resistor and the mth column data line in the second group of M columns of data lines.

[0145] In a specific implementation, the second selection circuit may include M second switching circuits, M first resistors, M third switching circuits and M second resistors, the mth second switching circuit controls the connection or disconnection between the mth column data line in the first group of M column data lines and the first end of the mth first resistor; each third switching circuit controls the connection or disconnection between the second end of the mth second resistor and the mth column data line in the second group of M column data lines.

[0146] As shown in FIG4 , at least one embodiment of the second gating circuit includes a first second switch circuit 41, a second second switch circuit 42, a third second switch circuit 43, a first first resistor R11, a second first resistor R21, a third first resistor R31, a first third switch circuit 51, a second third switch circuit 52, a third third switch circuit 53, a first second resistor R12, a second second resistor R22, and a third second resistor R32;

[0147] The first second switch circuit 41 is electrically connected to the first column data line DL1 and the first end of the first first resistor R11, respectively, and is used to control the connection or disconnection between the first column data line DL1 and the first end of the first first resistor R11, and the second end of the first first resistor R11 is electrically connected to the fourth column data line DL4;

[0148] The second second switch circuit 42 is electrically connected to the second column data line DL2 and the first end of the second first resistor R21, respectively, and is used to control the connection or disconnection between the second column data line DL2 and the first end of the second first resistor R21. The second end of the second first resistor R21 is electrically connected to the fifth column data line DL5.

[0149] The third second switch circuit 43 is electrically connected to the third column data line DL3 and the first end of the third first resistor R31, respectively, and is used to control the connection or disconnection between the third column data line DL3 and the first end of the third first resistor R31. The second end of the third first resistor R31 is electrically connected to the sixth column data line DL6.

[0150] A first end of the first second resistor R12 is electrically connected to the fourth column data line DL4;

[0151] The first third switch circuit 51 is electrically connected to the second end of the first second resistor R12 and the seventh column data line DL7, respectively, and is used to control the connection or disconnection between the second end of the first second resistor R12 and the seventh column data line DL7;

[0152] A first end of the second resistor R22 is electrically connected to the fifth column data line DL5;

[0153] The second third switch circuit 52 is electrically connected to the second end of the second second resistor R22 and the eighth column data line DL8 respectively, and is used to control the connection or disconnection between the second end of the second second resistor R22 and the eighth column data line DL8;

[0154] A first end of the third second resistor R32 is electrically connected to the sixth column data line DL6;

[0155] The third third switch circuit 53 is electrically connected to the second end of the third second resistor R32 and the ninth column data line DL9 respectively, and is used to control the connection or disconnection between the second end of the third second resistor R32 and the ninth column data line DL9.

[0156] In at least one embodiment shown in FIG. 4 of the present disclosure, when working, the sub-pixels in row A are all electrically connected to the scan lines in row A. When the scan lines in row A are turned on (A is a positive integer),

[0157] When the first second switch circuit 41 controls the connection between the first column data line DL1 and the first end of the first first resistor R11, the second second switch circuit 42 controls the connection between the second column data line DL2 and the first end of the second first resistor R21, the third second switch circuit 43 controls the connection between the third column data line DL3 and the first end of the third first resistor R31, the first third switch circuit 51 controls the connection between the second end of the first second resistor R12 and the seventh column data line DL7, the second third switch circuit 52 controls the connection between the second end of the second second resistor R22 and the eighth column data line DL8, and the third third switch circuit 53 controls the connection between the second end of the third second resistor R32 and the ninth column data line DL9,

[0158] The data voltage received by the sub-pixel in the fourth column of row A is the average of the data voltage received by the sub-pixel in the first column of row A and the data voltage received by the sub-pixel in the seventh column of row A;

[0159] The data voltage received by the sub-pixel in the fifth column of row A is the average of the data voltage received by the sub-pixel in the second column of row A and the data voltage received by the sub-pixel in the eighth column of row A;

[0160] The data voltage received by the sub-pixel in the sixth column of the A row is an average of the data voltage received by the sub-pixel in the third column of the A row and the data voltage received by the sub-pixel in the ninth column of the A row.

[0161] In FIG4 , the first first switch circuit is labeled 31 , the second first switch circuit is labeled 32 , and the third first switch circuit is labeled 33 .

[0162] In at least one embodiment of the present disclosure, the third gating circuit includes M third resistors and M fourth switch circuits;

[0163] an m-th fourth switch circuit electrically connected to the first end of the m-th third resistor and the m-th data line in the first group of M columns of data lines, respectively, for controlling connection or disconnection between the first end of the m-th third resistor and the m-th data line in the first group of M columns of data lines;

[0164] The second end of the mth third resistor is electrically connected to the mth column data line among the current M columns of data lines;

[0165] The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

[0166] In a specific implementation, the third selection circuit includes M third resistors and M fourth switch circuits; the mth fourth switch controls the connection or disconnection between the first end of the mth third resistor and the mth column data line in the first group of M columns of data lines.

[0167] As shown in FIG5A , the third gating circuit includes a first third resistor R13 , a second third resistor R23 , a third third resistor R33 , a first fourth switch circuit 51 , a second fourth switch circuit 52 , and a third fourth switch circuit 53 ;

[0168] The first fourth switch circuit 51 is electrically connected to the first end of the first third resistor R13 and the first column data line DL1, respectively, and is used to control the connection or disconnection between the first end of the first third resistor R13 and the first column data line DL1; the second end of the first third resistor R13 is electrically connected to the fourth column data line DL4;

[0169] The second fourth switch circuit 52 is electrically connected to the first end of the second third resistor R23 and the second column data line DL2, respectively, for controlling the connection or disconnection between the first end of the second third resistor R23 and the second column data line DL2; the second end of the second third resistor R23 is electrically connected to the fifth column data line DL5;

[0170] The third fourth switch circuit 53 is electrically connected to the first end of the third third resistor R33 and the third column data line DL3 respectively, and is used to control the connection or disconnection between the first end of the third third resistor R33 and the third column data line DL3; the second end of the third third resistor R33 is electrically connected to the sixth column data line DL6.

[0171] In at least one embodiment shown in FIG. 5A of the present disclosure, when in operation, the sub-pixels in row A are all electrically connected to the scan lines in row A. When the scan lines in row A are turned on (A is a positive integer),

[0172] When the first fourth switch circuit 51 controls the first end of the first third resistor R13 to be connected to the first column data line DL1, the second fourth switch circuit 52 controls the first end of the second third resistor R23 to be connected to the second column data line DL2, and the third fourth switch circuit 53 controls the first end of the third third resistor R33 to be connected to the third column data line DL3,

[0173] The data voltage received by the sub-pixel in the fourth column of row A is slightly smaller than the data voltage received by the sub-pixel in the first column of row A, the data voltage received by the sub-pixel in the fifth column of row A is slightly smaller than the data voltage received by the sub-pixel in the second column of row A, and the data voltage received by the sub-pixel in the sixth column of row A is slightly smaller than the data voltage received by the sub-pixel in the first column of row A.

[0174] In FIG5A , the first first switch circuit is labeled 31 , the second first switch circuit is labeled 32 , and the third first switch circuit is labeled 33 .

[0175] When at least one embodiment shown in FIG. 5A of the present disclosure is in operation, when the first fourth switch circuit 51 controls the first end of the first third resistor R13 to be connected to the first column data line DL1, the second fourth switch circuit 52 controls the first end of the second third resistor R23 to be connected to the second column data line DL2, and the third fourth switch circuit 53 controls the first end of the third third resistor R33 to be connected to the third column data line DL3, it is in V-HSR (V-Hardware Super Resolution) mode, and there is no need to separately apply data voltages to DL4, DL5, and DL6.

[0176] As shown in FIG5B , a circuit P0 is provided including a first gating circuit and a second gating circuit; a first column of pixels includes a first red sub-pixel R01, a second green sub-pixel G2, a third blue sub-pixel B3, a fourth red sub-pixel R04, a fifth green sub-pixel G5, a sixth blue sub-pixel B6, a seventh red sub-pixel R07, an eighth green sub-pixel G8, and a ninth blue sub-pixel B9;

[0177] The first column of red sub-pixels R01 is electrically connected to the first column of data line DL1, the second column of green sub-pixels G2 is electrically connected to the second column of data line DL2, the third column of blue sub-pixels B3 is electrically connected to the third column of data line DL3, the fourth column of red sub-pixels R04 is electrically connected to the fourth column of data line DL4, the fifth column of green sub-pixels G5 is electrically connected to the fifth column of data line DL5, the sixth column of blue sub-pixels B6 is electrically connected to the sixth column of data line DL6, the seventh column of red sub-pixels R07 is electrically connected to the seventh column of data line DL7, the eighth column of green sub-pixels G8 is electrically connected to the eighth column of data line DL8, and the ninth column of blue sub-pixels B9 is electrically connected to the ninth column of data line DL9;

[0178] The first gating circuit includes a first switch K1, a second switch K2 and a third switch K3;

[0179] The second gating circuit includes a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0180] The first data voltage supply terminal Y1 is directly electrically connected to DL1, the second data voltage supply terminal Y2 is directly electrically connected to DL2, the third data voltage supply terminal Y3 is directly electrically connected to DL3, the seventh data voltage supply terminal Y7 is directly electrically connected to DL7, the eighth data voltage supply terminal Y8 is directly electrically connected to DL8, and the ninth data voltage supply terminal Y9 is directly electrically connected to DL9;

[0181] The first end of K1 is electrically connected to DL4, and the second end of K1 is electrically connected to Y4;

[0182] The first end of K2 is electrically connected to DL5, and the second end of K2 is electrically connected to Y5;

[0183] The first end of K3 is electrically connected to DL6, and the second end of K3 is electrically connected to Y6;

[0184] The first end of K4 is electrically connected to DL1, and the second end of K4 is electrically connected to DL4 via R1;

[0185] A first end of K5 is electrically connected to DL2, and a second end of K5 is electrically connected to DL5 via R3;

[0186] A first end of K6 is electrically connected to DL3, and a second end of K6 is electrically connected to DL6 via R5;

[0187] A first end of K7 is electrically connected to DL7, and a second end of K7 is electrically connected to DL4 via R2;

[0188] A first end of K8 is electrically connected to DL8, and a second end of K8 is electrically connected to DL5 via R4;

[0189] A first end of K9 is electrically connected to DL9 , and a second end of K9 is electrically connected to DL6 through R6 .

[0190] As shown in FIG5C , the circuit P0 is provided to include a first gating circuit and a third gating circuit;

[0191] The first column of pixels has a red subpixel R01, a green subpixel G2, a blue subpixel B3, a red subpixel R04, a green subpixel G5, and a blue subpixel B6;

[0192] The first column of red sub-pixels R01 is electrically connected to the first column of data line DL1, the second column of green sub-pixels G2 is electrically connected to the second column of data line DL2, the third column of blue sub-pixels B3 is electrically connected to the third column of data line DL3, the fourth column of red sub-pixels R04 is electrically connected to the fourth column of data line DL4, the fifth column of green sub-pixels G5 is electrically connected to the fifth column of data line DL5, and the sixth column of blue sub-pixels B6 is electrically connected to the sixth column of data line DL6;

[0193] The first gating circuit includes a first switch K1, a second switch K2 and a third switch K3;

[0194] The first end of K1 is electrically connected to DL4, and the second end of K1 is electrically connected to Y4;

[0195] The first end of K2 is electrically connected to DL5, and the second end of K2 is electrically connected to Y5;

[0196] The first end of K3 is electrically connected to DL6, and the second end of K3 is electrically connected to Y6;

[0197] The first data voltage supply terminal Y1 is directly electrically connected to DL1, the second data voltage supply terminal Y2 is directly electrically connected to DL2, and the third data voltage supply terminal Y3 is directly electrically connected to DL3;

[0198] The third gating circuit includes a fourth switch K4, a fifth switch K5, a sixth switch K6, a first resistor R1, a second resistor R2 and a third resistor R3;

[0199] The first end of K4 is electrically connected to DL1, and the second end of K4 is electrically connected to DL4 via R1;

[0200] A first end of K5 is electrically connected to DL2, and a second end of K5 is electrically connected to DL5 via R2;

[0201] A first end of K6 is electrically connected to DL3 , and a second end of K6 is electrically connected to DL6 via R3 .

[0202] In at least one embodiment of the present disclosure, the data driver includes at least one data driving circuit; the column of pixels includes three columns of sub-pixels;

[0203] The data driving circuit includes N data voltage supply terminals; N is a positive integer;

[0204] The a-th providing circuit includes an a-th first gating circuit and an a-th second gating circuit; a is a positive integer;

[0205] The first column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a-2 column, the second column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a-1 column, and the third column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a column.

[0206] The first column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-5 column, the second column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-4 column, and the third column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-3 column.

[0207] The first column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+1 column, the second column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+2 column, and the third column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+3 column.

[0208] The ath first gating circuit is electrically connected to the 6a-2th column data line, the 6a-1th column data line, the 6ath column data line, the 6a-2th data voltage supply terminal, the 6a-1th data voltage supply terminal, and the 6ath data voltage supply terminal, respectively, and is used to control the connection or disconnection between the 6a-2th column data line and the 6a-2th data voltage supply terminal, control the connection or disconnection between the 6a-1th column data line and the 6a-1th data voltage supply terminal, and control the connection or disconnection between the 6ath column data line and the 6ath data voltage supply terminal;

[0209] the ath second gating circuit being electrically connected to the 6a-5th column data line, the 6a-4th column data line, the 6a-3th column data line, the 6a+1th column data line, the 6a+2th column data line and the 6a+3th column data line, the 6a-2th column data line, the 6a-1th column data line and the 6a column data line, respectively, and being configured to control the data voltage received by the 6a-2th column data line according to the data voltage received by the 6a-5th column data line and the data voltage received by the 6a+1th column data line, control the data voltage received by the 6a-1th column data line according to the data voltage received by the 6a-4th column data line and the data voltage received by the 6a+2th column data line, and control the data voltage received by the 6a column data line according to the data voltage received by the 6a-3th column data line and the data voltage received by the 6a+3th column data line;

[0210] The data line in the 6a-5 column is directly electrically connected to the 6a-5 data voltage supply terminal, the data line in the 6a-4 column is directly electrically connected to the 6a-4 data voltage supply terminal, the data line in the 6a-3 column is directly electrically connected to the 6a-3 data voltage supply terminal, the data line in the 6a+1 column is directly electrically connected to the 6a+1 data voltage supply terminal, the data line in the 6a+2 column is directly electrically connected to the 6a+2 data voltage supply terminal, and the data line in the 6a+3 column is directly electrically connected to the 6a+3 data voltage supply terminal.

[0211] In a specific implementation, the data voltage providing circuit may include a plurality of providing circuits;

[0212] Each providing circuit includes a first gating circuit and a second gating circuit;

[0213] the ath first gating circuit controls the connection or disconnection between the 6a-2th column data line and the 6a-2th data voltage supply terminal, controls the connection or disconnection between the 6a-1th column data line and the 6a-1th data voltage supply terminal, and controls the connection or disconnection between the 6ath column data line and the 6ath data voltage supply terminal;

[0214] The ath second selection circuit controls the data voltage received by the 6a-2 column data line according to the data voltage received by the 6a-5 column data line and the data voltage received by the 6a+1 column data line, controls the data voltage received by the 6a-1 column data line according to the data voltage received by the 6a-4 column data line and the data voltage received by the 6a+2 column data line, and controls the data voltage received by the 6a column data line according to the data voltage received by the 6a-3 column data line and the data voltage received by the 6a+3 column data line.

[0215] Optionally, N is a multiple of 6;

[0216] The data voltage supply circuit includes a fourth gating circuit;

[0217] The fourth selection circuit is electrically connected to the Nth column data line, the N-1th column data line, the N-2th column data line, the N-3th column data line, the N-4th column data line and the N-5th column data line, respectively, and is used to control the connection or disconnection between the Nth column data line and the N-3rd column data line, control the connection or disconnection between the N-1th column data line and the N-4th column data line, and control the connection or disconnection between the N-2th column data line and the N-5th column data line.

[0218] In a specific implementation, when the number N of data voltage supply terminals included in the data driving circuit is a multiple of 6, the data voltages provided by the last three data voltage supply terminals included in the data driving circuit cannot be provided by other data voltage supply terminals. Therefore, at least one embodiment of the present disclosure provides a fourth selection circuit; the fourth selection circuit controls the connection or disconnection between the Nth column data line and the N-3th column data line, controls the connection or disconnection between the N-1th column data line and the N-4th column data line, and controls the connection or disconnection between the N-2nd column data line and the N-5th column data line, so that the Nth column data line can share the data voltage on the N-3rd column data line, the N-1st column data line can share the data voltage on the N-4th data line, and the N-2nd column data line can share the data voltage on the N-5th column data line.

[0219] As shown in FIG6 , Y949 is the 949th data voltage supply terminal, Y950 is the 950th data voltage supply terminal, Y951 is the 951st data voltage supply terminal, Y952 is the 952nd data voltage supply terminal, Y953 is the 953rd data voltage supply terminal, Y954 is the 954th data voltage supply terminal, Y955 is the 955th data voltage supply terminal, Y956 is the 956th data voltage supply terminal, Y957 is the 957th data voltage supply terminal, Y958 is the 958th data voltage supply terminal, Y959 is the 959th data voltage supply terminal, and Y960 is the 960th data voltage supply terminal.

[0220] The data line labeled DL949 is the 949th column, the data line labeled DL950 is the 950th column, the data line labeled DL951 is the 951st column, the data line labeled DL952 is the 952nd column, the data line labeled DL953 is the 953rd column, the data line labeled DL954 is the 954th column, the data line labeled DL955 is the 955th column, the data line labeled DL956 is the 956th column, the data line labeled DL957 is the 957th column, the data line labeled DL958 is the 958th column, the data line labeled DL959 is the 959th column, and the data line labeled DL960 is the 960th column;

[0221] The 949th red sub-pixel is labeled R949, the 950th green sub-pixel is labeled G950, the 951st blue sub-pixel is labeled B951, the 952nd red sub-pixel is labeled G953, the 953rd green sub-pixel is labeled B954, the 954th blue sub-pixel is labeled R955, the 955th red sub-pixel is labeled G956, the 956th green sub-pixel is labeled B957, the 957th blue sub-pixel is labeled R958, the 958th red sub-pixel is labeled G959, the 959th green sub-pixel is labeled B960, and the 960th blue sub-pixel is labeled B960.

[0222] In at least one embodiment shown in FIG6 , N is equal to 960;

[0223] The data voltage supply circuit includes a fourth gating circuit 60;

[0224] The fourth selection circuit 60 is electrically connected to the 960th column data line DL960, the 959th column data line DL959, the 958th column data line DL958, the 957th column data line DL957, the 956th column data line DL956 and the 955th column data line DL955, respectively, and is used to control the connection or disconnection between the 960th column data line DL960 and the 957th column data line DL957, control the connection or disconnection between the 959th column data line DL959 and the 956th column data line DL956, and control the connection or disconnection between the 958th column data line DL958 and the 955th column data line DL955.

[0225] In FIG6 , a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a ninth switch K9, a tenth switch K10, an eleventh switch K11, and a twelfth switch K12 are further provided;

[0226] Y952 is electrically connected to DL952 via K1, Y953 is electrically connected to DL953 via K2, and Y954 is electrically connected to DL954 via K3;

[0227] Y949 is electrically connected to DL949, R949 is electrically connected to DL949; Y949 is electrically connected to DL952 through K4 and R1;

[0228] Y950 is electrically connected to DL950, G950 is electrically connected to DL950, and Y950 is electrically connected to DL953 through K5 and R2;

[0229] Y951 is electrically connected to DL951, B951 is electrically connected to DL951, and Y951 is electrically connected to DL954 through K6 and R3;

[0230] R952 is electrically connected to DL952, and DL952 is electrically connected to DL955 through K7 and R4;

[0231] G953 is electrically connected to DL953, and DL953 is electrically connected to DL956 via K8 and R5;

[0232] B954 is electrically connected to DL954, and DL954 is electrically connected to DL957 through K9 and R6;

[0233] Y958 is electrically connected to DL958 via K10, Y959 is electrically connected to DL959 via K11, and Y960 is electrically connected to DL960 via K12;

[0234] The fourth gating circuit 60 includes a thirteenth switch K13, a fourteenth switch K14 and a fifteenth switch K15;

[0235] The first end of K13 is electrically connected to DL955, and the second end of K13 is electrically connected to DL958;

[0236] The first end of K14 is electrically connected to DL956, and the second end of K13 is electrically connected to DL959;

[0237] The first end of K15 is electrically connected to DL957, and the second end of K13 is electrically connected to DL960.

[0238] When at least one embodiment shown in Figure 6 of the present disclosure is in operation, the fourth selection circuit 60 can control the connection between the 960th column data line DL960 and the 957th column data line DL957, control the connection between the 959th column data line DL959 and the 956th column data line DL956, and control the connection between the 958th column data line DL958 and the 955th column data line DL955, so that the data voltage received by DL960 is the same as the data voltage received by DL957, the data voltage received by DL959 is the same as the data voltage received by DL956, and the data voltage received by DL958 is the same as the data voltage received by DL955.

[0239] Optionally, N is a multiple of 6, the data driver includes B data driving circuits; B is an integer greater than 1;

[0240] The bth data driving circuit is electrically connected to the bth group of N columns of data lines, and the b+1th data circuit is electrically connected to the b+1th group of N columns of data lines, where b is a positive integer and b+1 is less than or equal to B;

[0241] The data voltage supply circuit includes a fifth gating circuit;

[0242] The fifth gating circuit is electrically connected to the N-5th data line in the b-th group of N column data lines, the N-4th data line in the b-th group of N column data lines, the N-3th data line in the b-th group of N column data lines, the N-2th data line in the b-th group of N column data lines, the N-1th data line in the b-th group of N column data lines, the N data line in the b-th group of N column data lines, the first column data line in the b+1-th group of N column data lines, the second column data line in the b+1-th group of N column data lines and the third column data line in the b+1-th group of N column data lines, respectively, for selecting the data line according to the data voltage received by the N-5th data line in the b-th group of N column data lines and the data voltage received by the b+1-th group of N column data lines. The data voltage received by the first column of N column data lines controls the data voltage received by the N-2th data line in the b-th group of N column data lines; the data voltage received by the N-1th data line in the b-th group of N column data lines is controlled based on the data voltage received by the N-4th data line in the b-th group of N column data lines and the data voltage received by the second column of N column data lines in the b+1-th group of N column data lines; the data voltage received by the N-3th data line in the b-th group of N column data lines and the data voltage received by the third column of N column data lines in the b+1-th group of N column data lines is controlled.

[0243] In a specific implementation, when the data driver includes multiple data driving circuits, when the number of data voltage supply terminals included in the data driving circuit is a multiple of 6, the data voltages provided by the last three data voltage supply terminals included in a data driving circuit can be obtained based on the sixth to fourth data voltage supply terminals included in a data driving circuit, and the first three data voltage supply terminals included in another data driving circuit.

[0244] In FIG7 , the circuit labeled F1 is a first data driving circuit, and the circuit labeled F2 is a second data driving circuit;

[0245] Y952 is the 952nd data voltage supply terminal of the first data driving circuit, Y953 is the 953rd data voltage supply terminal of the first data driving circuit, Y954 is the 954th data voltage supply terminal of the first data driving circuit, Y955 is the 955th data voltage supply terminal of the first data driving circuit, Y956 is the 956th data voltage supply terminal of the first data driving circuit, Y957 is the 957th data voltage supply terminal of the first data driving circuit, Y958 is the 958th data voltage supply terminal of the first data driving circuit, Y959 is the 959th data voltage supply terminal of the first data driving circuit, and Y960 is the 960th data voltage supply terminal of the first data driving circuit;

[0246] DL952 is the 952nd column data line electrically connected to the first data driving circuit, DL953 is the 953rd column data line electrically connected to the first data driving circuit, DL954 is the 954th column data line electrically connected to the first data driving circuit, DL955 is the 955th column data line electrically connected to the first data driving circuit, DL956 is the 956th column data line electrically connected to the first data driving circuit, DL957 is the 957th column data line electrically connected to the first data driving circuit, DL958 is the 958th column data line electrically connected to the first data driving circuit, DL959 is the 959th column data line electrically connected to the first data driving circuit, and DL960 is the 960th column data line electrically connected to the first data driving circuit;

[0247] Y1 is a first data voltage supply terminal of the second data driving circuit, Y2 is a second data voltage supply terminal of the second data driving circuit, Y3 is a third data voltage supply terminal of the second data driving circuit, Y4 is a fourth data voltage supply terminal of the second data driving circuit, Y5 is a fifth data voltage supply terminal of the second data driving circuit, Y6 is a sixth data voltage supply terminal of the second data driving circuit, Y7 is a seventh data voltage supply terminal of the second data driving circuit, Y8 is an eighth data voltage supply terminal of the second data driving circuit, and Y9 is a ninth data voltage supply terminal of the second data driving circuit;

[0248] DL1 is a first column data line electrically connected to the second data driving circuit, DL2 is a second column data line electrically connected to the second data driving circuit, DL3 is a third column data line electrically connected to the second data driving circuit, DL4 is a fourth column data line electrically connected to the second data driving circuit, DL5 is a fifth column data line electrically connected to the second data driving circuit, DL6 is a sixth column data line electrically connected to the second data driving circuit, DL7 is a seventh column data line electrically connected to the second data driving circuit, DL8 is an eighth column data line electrically connected to the second data driving circuit, and DL9 is a ninth column data line electrically connected to the second data driving circuit;

[0249] R952 is a column of red sub-pixels electrically connected to DL952, G953 is a column of green sub-pixels electrically connected to DL953, B954 is a column of blue sub-pixels electrically connected to DL954, R955 is a column of red sub-pixels electrically connected to DL955, G956 is a column of green sub-pixels electrically connected to DL956, B957 is a column of blue sub-pixels electrically connected to DL957, R958 is a column of red sub-pixels electrically connected to DL958, G959 is a column of green sub-pixels electrically connected to DL959, and B960 is a column of blue sub-pixels electrically connected to DL960.

[0250] R1 is a column of red sub-pixels electrically connected to DL1, G2 is a column of green sub-pixels electrically connected to DL2, B3 is a column of blue sub-pixels electrically connected to DL3, R04 is a column of red sub-pixels electrically connected to DL4, G5 is a column of green sub-pixels electrically connected to DL5, B6 is a column of blue sub-pixels electrically connected to DL6, R07 is a column of red sub-pixels electrically connected to DL7, G8 is a column of green sub-pixels electrically connected to DL8, and B9 is a column of blue sub-pixels electrically connected to DL9.

[0251] K1 is the first switch, K2 is the second switch, K3 is the third switch, K4 is the fourth switch, K5 is the fifth switch, K6 is the sixth switch, K7 is the seventh switch, K8 is the eighth switch, K9 is the ninth switch, K10 is the tenth switch, K11 is the eleventh switch, K12 is the twelfth switch, K13 is the thirteenth switch, K14 is the fourteenth switch, K15 is the fifteenth switch, K16 is the sixteenth switch, K17 is the seventeenth switch, K18 is the eighteenth switch, K19 is the nineteenth switch, K20 is the twentieth switch, and K21 is the twenty-first switch.

[0252] The first resistor is labeled R1, the second resistor is labeled R2, the third resistor is labeled R3, the fourth resistor is labeled R4, the fifth resistor is labeled R5, the sixth resistor is labeled R6, the seventh resistor is labeled R7, the eighth resistor is labeled R8, the ninth resistor is labeled R9, the tenth resistor is labeled R10, the eleventh resistor is labeled R11, and the twelfth resistor is labeled R12; the thirteenth resistor is labeled R13, the fourteenth resistor is labeled R14, and the fifteenth resistor is labeled R15;

[0253] Y958 is electrically connected to Y955 via K1 and R1, Y959 is electrically connected to Y956 via K2 and R2, and Y960 is electrically connected to Y957 via K3 and R3;

[0254] Y958 is electrically connected to Y1 through R4 and K4, Y959 is electrically connected to Y2 through R5 and K5, and Y960 is electrically connected to Y3 through R6 and K6;

[0255] Y955 is electrically connected to DL955 via K7, Y956 is electrically connected to DL956 via K8, and Y957 is electrically connected to DL957 via K9;

[0256] DL955 is electrically connected to Y952 via R7 and K10, DL956 is electrically connected to Y953 via R8 and K11, and DL957 is electrically connected to Y954 via R9 and K12;

[0257] Y1 is electrically connected to Y4 via K13 and R10, Y2 is electrically connected to Y5 via K14 and R11, and Y3 is electrically connected to Y6 via K15 and R12;

[0258] DL4 is electrically connected to Y4 via K16, DL5 is electrically connected to Y5 via K17, and DL6 is electrically connected to Y6 via K18;

[0259] Y7 is electrically connected to Y4 via K19 and R13, Y8 is electrically connected to Y5 via K20 and R14, and Y9 is electrically connected to Y6 via K21 and R15;

[0260] Y958 is directly electrically connected to DL958, Y959 is directly electrically connected to DL959, Y960 is directly electrically connected to DL960, Y1 is directly electrically connected to DL1, Y2 is directly electrically connected to DL2, and Y3 is directly electrically connected to DL3.

[0261] When at least one embodiment shown in FIG. 7 of the present disclosure is in operation, when K1, K2, K3, K4, K5, and K6 are all closed, Y958 is connected to Y955 through R1, Y959 is connected to Y956 through R2, Y960 is connected to Y957 through R3, Y958 is connected to Y1 through R4, Y959 is connected to Y2 through R5, and Y960 is connected to Y3 through R6. The data voltage provided by Y958 can be controlled according to the data voltage provided by Y955 and the data voltage provided by Y1, the data voltage provided by Y959 can be controlled according to the data voltage provided by Y956 and the data voltage provided by Y2, and the data voltage provided by Y960 can be controlled according to the data voltage provided by Y957 and the data voltage provided by Y3.

[0262] In at least one embodiment of the present disclosure, the data driver includes at least one data driving circuit; the column of pixels includes three columns of sub-pixels;

[0263] The data driving circuit includes N data voltage supply terminals; N is a positive integer;

[0264] The a-th providing circuit includes an a-th first gating circuit and an a-th third gating circuit; a is a positive integer;

[0265] The ath first gating circuit is electrically connected to the 6a-2th column data line, the 6a-1th column data line, the 6ath column data line, the 6a-2th data voltage supply terminal, the 6a-1th data voltage supply terminal, and the 6ath data voltage supply terminal, respectively, and is used to control the connection or disconnection between the 6a-2th column data line and the 6a-2th data voltage supply terminal, control the connection or disconnection between the 6a-1th column data line and the 6a-1th data voltage supply terminal, and control the connection or disconnection between the 6ath column data line and the 6ath data voltage supply terminal;

[0266] The ath third selection circuit is electrically connected to the 6a-5th column data line, the 6a-4th column data line, the 6a-3th column data line, the 6a-2th column data line, the 6a-1th column data line and the 6a column data line, respectively, and is used to control the data voltage on the 6a-2th column data line according to the data voltage on the 6a-5th column data line, control the data voltage on the 6a-1th column data line according to the data voltage on the 6a-4th column data line, and control the data voltage on the 6a column data line according to the data voltage on the 6a-3th column data line.

[0267] In a specific implementation, the data driver may include at least one data driving circuit, the ath supply circuit includes the ath first selection circuit and the ath third selection circuit, the ath first selection circuit controls the connection or disconnection between the 6a-2 column data line and the 6a-2 data voltage supply end, controls the connection or disconnection between the 6a-1 column data line and the 6a-1 data voltage supply end, and controls the connection or disconnection between the 6a column data line and the 6a data voltage supply end; the ath third selection circuit controls the data voltage on the 6a-2 column data line according to the data voltage on the 6a-5 column data line, controls the data voltage on the 6a-1 column data line according to the data voltage on the 6a-4 column data line, and controls the data voltage on the 6a column data line according to the data voltage on the 6a-3 column data line.

[0268] Optionally, the mth first switching circuit includes an mth first switching transistor;

[0269] The gate of the mth first switch transistor is electrically connected to the first control voltage terminal, the first electrode of the mth first switch transistor is electrically connected to the mth data voltage supply terminal, and the second electrode of the mth first switch transistor is electrically connected to the mth data line;

[0270] The data voltage providing circuit includes a first control circuit;

[0271] The first control circuit is used to provide a first control voltage to the first control voltage terminal to control the mth first switching transistor to be turned on or off.

[0272] Optionally, the mth second switching circuit includes an mth second switching transistor, and the mth third switching circuit includes an mth third switching transistor;

[0273] The gate of the mth second switch transistor is electrically connected to the second control voltage terminal, the first electrode of the mth second switch transistor is electrically connected to the mth column data line in the first group of M columns of data lines, and the second electrode of the mth second switch transistor is electrically connected to the first end of the mth first resistor;

[0274] a gate of the mth third switch transistor being electrically connected to the second control voltage terminal, a first electrode of the mth third switch transistor being electrically connected to the second end of the mth second resistor, and a second electrode of the mth third switch transistor being electrically connected to the mth column data line of the second group of M columns of data lines;

[0275] The data voltage providing circuit includes a second control circuit;

[0276] The second control circuit is used to provide a second control voltage to the second control voltage terminal to control the mth second switching transistor to be turned on or off, and to control the mth third switching transistor to be turned on or off.

[0277] As shown in FIG8 , the data line labeled DL1 is the first column, the data line labeled DL2 is the second column, the data line labeled DL3 is the third column, the data line labeled DL4 is the fourth column, the data line labeled DL5 is the fifth column, the data line labeled DL6 is the sixth column, the data line labeled DL7 is the seventh column, the data line labeled DL8 is the eighth column, and the data line labeled DL9 is the ninth column;

[0278] The data line labeled DLM-8 is the M-8th column data line, the data line labeled DLM-7 is the M-7th column data line, the data line labeled DLM-6 is the M-6th column data line, the data line labeled DLM-5 is the M-5th column data line, the data line labeled DLM-4 is the M-4th column data line, the data line labeled DLM-3 is the M-3rd column data line, the data line labeled DLM-2 is the M-2nd column data line, the data line labeled DLM-1 is the M-1st column data line, and the data line labeled DLM is the Mth column data line; M is a positive integer;

[0279] In FIG8 , M11 is the first first switch transistor, M21 is the second first switch transistor, M31 is the third first switch transistor, M41 is the fourth first switch transistor, M51 is the fifth first switch transistor, and M61 is the sixth first switch transistor;

[0280] The first second switch transistor is labeled M12, the second second switch transistor is labeled M22, the third second switch transistor is labeled M32, the fourth second switch transistor is labeled M42, the fifth second switch transistor is labeled M52, and the sixth second switch transistor is labeled M62;

[0281] The first third switch transistor is labeled M13, the second third switch transistor is labeled M23, the third third switch transistor is labeled M33, the fourth third switch transistor is labeled M43, the fifth third switch transistor is labeled M53, and the sixth third switch transistor is labeled M63;

[0282] The first resistor is labeled R1, the second resistor is labeled R2, the third resistor is labeled R3, the fourth resistor is labeled R4, the fifth resistor is labeled R5, the sixth resistor is labeled R6, the seventh resistor is labeled R7, the eighth resistor is labeled R8, the ninth resistor is labeled R9, the tenth resistor is labeled R10, the eleventh resistor is labeled R11, and the twelfth resistor is labeled R12;

[0283] The resistor labeled R13 is the thirteenth resistor, the resistor labeled R14 is the fourteenth resistor, the resistor labeled R15 is the fifteenth resistor, and the resistor labeled R16 is the sixteenth resistor;

[0284] Y1 is a first data voltage supply terminal, Y2 is a second data voltage supply terminal, Y3 is a third data voltage supply terminal, Y4 is a fourth data voltage supply terminal, Y5 is a fifth data voltage supply terminal, Y6 is a sixth data voltage supply terminal, Y7 is a seventh data voltage supply terminal, Y8 is an eighth data voltage supply terminal, and Y9 is a ninth data voltage supply terminal;

[0285] The terminal labeled YM-8 is the M-8th data voltage supply terminal, the terminal labeled YM-7 is the M-7th data voltage supply terminal, the terminal labeled YM-6 is the M-6th data voltage supply terminal, the terminal labeled YM-5 is the M-5th data voltage supply terminal, the terminal labeled YM-4 is the M-4th data voltage supply terminal, the terminal labeled YM-3 is the M-3rd data voltage supply terminal, the terminal labeled YM-2 is the M-2nd data voltage supply terminal, the terminal labeled YM-1 is the M-1th data voltage supply terminal, and the terminal labeled YM is the Mth data voltage supply terminal;

[0286] The first column of red sub-pixels is labeled R01, the second column of green sub-pixels is labeled G2, the third column of blue sub-pixels is labeled B3, the fourth column of red sub-pixels is labeled R04, the fifth column of green sub-pixels is labeled G5, the sixth column of blue sub-pixels is labeled B6, the seventh column of red sub-pixels is labeled R07, the eighth column of green sub-pixels is labeled G8, and the ninth column of blue sub-pixels is labeled B9;

[0287] The red sub-pixel labeled RM-8 is the M-8th column, the green sub-pixel labeled GM-7 is the M-7th column, the blue sub-pixel labeled BM-6 is the M-6th column, the red sub-pixel labeled RM-5 is the M-5th column, the green sub-pixel labeled GM-4 is the M-4th column, the blue sub-pixel labeled BM-3 is the M-3rd column, the red sub-pixel labeled RM-2 is the M-2nd column, the green sub-pixel labeled GM-1 is the M-1th column, and the blue sub-pixel labeled BM is the Mth column;

[0288] The gate of M11, the gate of M21, the gate of M31, the gate of M41, the gate of M51 and the gate of M61 are all electrically connected to the first control voltage terminal VC1;

[0289] The source of M11 is electrically connected to Y4, and the drain of M11 is electrically connected to DL4;

[0290] The source of M21 is electrically connected to Y5, and the drain of M21 is electrically connected to DL5;

[0291] The source of M31 is electrically connected to Y6, and the drain of M31 is electrically connected to DL6;

[0292] The source of M41 is electrically connected to YM-5, and the drain of M41 is electrically connected to DLM-5;

[0293] The source of M51 is electrically connected to YM-4, and the drain of M51 is electrically connected to DLM-4;

[0294] The source of M61 is electrically connected to YM-3, and the drain of M61 is electrically connected to DLM-3;

[0295] The gate of M12, the gate of M22, the gate of M32, the gate of M42, the gate of M52, the gate of M62, the gate of M13, the gate of M23, the gate of M33, the gate of M43, the gate of M53 and the gate of M63 are all electrically connected to the second control voltage terminal VC2;

[0296] The source of M12 is electrically connected to Y1, and the drain of M12 is electrically connected to DL4 through R1;

[0297] Y1 is directly electrically connected to DL1;

[0298] The source of M22 is electrically connected to Y2, and the drain of M22 is electrically connected to DL5 via R2;

[0299] Y2 is directly electrically connected to DL2;

[0300] The source of M32 is electrically connected to Y3, and the drain of M32 is electrically connected to DL6 via R3;

[0301] Y3 is directly electrically connected to DL3;

[0302] The source of M13 is electrically connected to DL4 through R4, and the drain of M13 is electrically connected to Y7;

[0303] Y7 is directly electrically connected to DL7;

[0304] The source of M23 is electrically connected to DL5 through R5, and the drain of M23 is electrically connected to Y8;

[0305] Y8 is directly electrically connected to DL8;

[0306] The source of M33 is electrically connected to DL6 through R6, and the drain of M33 is electrically connected to Y9;

[0307] Y9 is directly electrically connected to DL9;

[0308] The source of M42 is electrically connected to YM-8, and the drain of M42 is electrically connected to DLM-5 through R7;

[0309] YM-8 is directly electrically connected to DLM-8;

[0310] The source of M52 is electrically connected to YM-7, and the drain of M52 is electrically connected to DLM-4 through R8;

[0311] YM-7 is directly electrically connected to DLM-7;

[0312] The source of M62 is electrically connected to YM-6, and the drain of M62 is electrically connected to DLM-3 through R9;

[0313] YM-6 is directly electrically connected to DLM-6;

[0314] The source of M43 is electrically connected to DLM-5 through R10, and the drain of M43 is electrically connected to YM-2;

[0315] YM-2 is directly electrically connected to DLM-2;

[0316] The source of M53 is electrically connected to DLM-4 through R11, and the drain of M53 is electrically connected to YM-1;

[0317] YM-1 is directly electrically connected to DLM-1;

[0318] The source of M63 is electrically connected to R12 and DLM-3, and the drain of M63 is electrically connected to YM;

[0319] YM is directly electrically connected to DLM.

[0320] At least one embodiment shown in FIG. 8 of the present disclosure can control the on / off of each transistor by hardware gating during operation, wherein R13 - R16 can be arranged on a circuit board;

[0321] When R13 and R14 are on, that is, when R13 and R14 are enabled, the high voltage terminal VDD is electrically connected to the first control voltage terminal VC1 through R13, the first control voltage terminal VC1 is electrically connected to the ground terminal GD through R14, M11, M21, M31, M41, M51 and M61 are turned on, and are in a normal data voltage supply mode;

[0322] When R15 and R16 are on, that is, when R15 and R16 are enabled, the high voltage terminal VDD is electrically connected to the second control voltage terminal VC2 through R15, the second control voltage terminal VC2 is electrically connected to the ground terminal GD through R16, and M12, M22, M32, M42, M52, M62, M13, M23, M33, M43, M53 and M63 are all turned on and are in V-HSR mode.

[0323] In at least one embodiment shown in FIG. 8 , all transistors may be n-type transistors, but the present invention is not limited thereto.

[0324] The difference between at least one embodiment shown in FIG9 and at least one embodiment shown in FIG8 is that R13, R14, R15 and R16 are not included;

[0325] In at least one embodiment shown in FIG9 , the first control circuit includes a first control transistor T1 , a second control transistor T2 , and a seventeenth resistor R17 , and the second control circuit includes a third control transistor T3 , a fourth control transistor T4 , and an eighteenth resistor R18 ;

[0326] The gate of T1 is electrically connected to the control signal terminal SC, the source of T1 is electrically connected to the first control voltage terminal VC1 through R17, and the drain of T1 is electrically connected to the ground terminal GD;

[0327] The gate of T2 is electrically connected to the control signal terminal SC, the source of T2 is electrically connected to the high voltage terminal VDD, and the drain of T2 is electrically connected to the first control voltage terminal VC1;

[0328] T1 is a p-type transistor and T2 is an n-type transistor;

[0329] The gate of T3 is electrically connected to the control signal terminal SC, the source of T3 is electrically connected to the second control voltage terminal VC2 via R18, and the drain of T3 is electrically connected to the ground terminal GD;

[0330] The gate of T4 is electrically connected to the control signal terminal SC, the source of T4 is electrically connected to the high voltage terminal VDD, and the drain of T4 is electrically connected to the second control voltage terminal VC2;

[0331] T3 is an n-type transistor, and T4 is a p-type transistor.

[0332] In at least one embodiment shown in FIG9 , when in operation, the control signal terminal SC is used to provide a square wave control signal, and the square wave control signal can be provided by a timing controller chip;

[0333] When the control signal terminal SC provides a high voltage signal, T1 is turned off, T2 is turned on, VDD is connected to VC1, M11, M21, M31, M41, M51 and M61 are turned on, and the system is in a normal data voltage supply mode; T3 is turned on, T4 is turned off, GD is connected to VC2, and the second and third switch transistors are turned off;

[0334] When the control signal terminal SC provides a low voltage signal, T1 is turned on, T2 is turned off, GD is connected to VC1, and each first switch transistor is turned on; T3 is turned off, T4 is turned on, each second switch transistor and each third switch transistor are turned on, and it is in V-HSR mode.

[0335] The display device according to the embodiment of the present disclosure includes a plurality of rows of gate lines, a plurality of columns of data lines, a plurality of rows and columns of pixels, a driving module, and the above-mentioned data voltage supply circuit; the driving module is electrically connected to the plurality of rows of gate lines, and is used to provide driving signals to the gate lines;

[0336] The pixels located in the same row are electrically connected to the corresponding row gate line and are used to receive the driving signal provided by the corresponding row gate line;

[0337] Pixels located in the same column are electrically connected to the corresponding column data line and are used to receive data voltages from the corresponding column data line.

[0338] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned display device, and the driving method includes:

[0339] During the driving cycle, the driving module provides a driving signal to the gate line to control the multiple scan lines to turn on in sequence;

[0340] In the driving cycle, there are overlapping time periods and non-overlapping time periods between the effective time periods of the scanning signals provided by at least two adjacent gate lines in the plurality of rows of gate lines turned on sequentially;

[0341] During at least a portion of the overlapping time period, the data line receives a data voltage that is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0342] As shown in FIG10 , when the display device according to at least one embodiment of the present disclosure includes M rows of sub-pixels and M rows of scan lines, and the sub-pixels in the mth row are electrically connected to the mth row of scan lines (M is an integer greater than 1, and m is a positive integer less than or equal to M),

[0343] The display period may include a first overlapping period J1, a first non-overlapping period B1, a second overlapping period J2, a second non-overlapping period B2, an ath overlapping period Ja and an ath non-overlapping period Ba (a is a positive integer);

[0344] In the first overlapping period J1, the data line DT provides the first row data voltage D1, GT1 and GT2 are turned on, and the first row sub-pixels and the second row sub-pixels receive the first row data voltage D1;

[0345] In the first non-overlapping period B1, the data line DT provides the first row data voltage D1, GT2 is turned on, and the second row of sub-pixels receives the first row data voltage D1;

[0346] In the second overlapping period J2, the data line DT provides the third row data voltage D3, GT3 and GT4 are turned on, and the third row sub-pixels and the fourth row sub-pixels receive the third row data voltage D3;

[0347] In the second non-overlapping period B2, the data line DT provides the third row data voltage D3, GT4 is turned on, and the fourth row of sub-pixels receives the third row data voltage D3;

[0348] In the ath overlapping period Ja, the data line DT provides the M-1th row data voltage DM-1; GTM-1 and GTM are turned on, the M-1th row sub-pixels and the M-th row sub-pixels are turned on, and the M-1th row sub-pixels and the M-th row sub-pixels receive the M-1th row data voltage DM-1;

[0349] In the ath non-overlapping period Ba, the data line DT provides the M-1th row data voltage DM; the GTM is turned on, the Mth row sub-pixels are turned on, and the Mth row sub-pixels receive the M-1th row data voltage DM-1.

[0350] In at least one embodiment shown in FIG. 10 , J1 is a partially overlapping period between a high voltage period of the first scan signal and a high voltage period of the second scan signal;

[0351] B1 is a non-overlapping period between the high voltage period of the first scanning signal and the high voltage period of the second scanning signal;

[0352] J2 is a partially overlapping period between the high voltage period of the third scan signal and the high voltage period of the fourth scan signal;

[0353] B2 is a non-overlapping period between the high voltage period of the third scan signal and the high voltage period of the fourth scan signal;

[0354] Ja is a partially overlapping period between the high voltage period of the M-1th scan signal and the high voltage period of the Mth scan signal;

[0355] Ba is a non-overlapping period between the high voltage period of the M-1th scan signal and the high voltage period of the Mth scan signal.

[0356] In at least one embodiment as shown in FIG. 10 , the display device operates in the HSR mode.

[0357] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned display device. The driving cycle includes a plurality of driving phases arranged in sequence. The 2n-1th row scanning signal provided by the 2n-1th row scanning line is the same as the 2nth row scanning signal provided by the 2nth row scanning line. The driving method includes:

[0358] In the nth driving phase, the 2n-1th scan line and the 2nth scan line are turned on, and the sub-pixels located in the 2n-1th row and the sub-pixels located in the 2nth row receive data voltages provided by corresponding data lines;

[0359] n is a positive integer.

[0360] As shown in FIG11 , when the array substrate according to at least one embodiment of the present disclosure includes M rows of sub-pixels and M rows of scan lines, and the sub-pixels in the mth row are electrically connected to the mth row of scan lines (M is an integer greater than 1, and m is a positive integer less than or equal to M),

[0361] The first scan signal provided by the first scan line GT1 is the same as the second scan signal provided by the second scan line GT2, the third scan signal provided by the third scan line GT3 is the same as the fourth scan signal provided by the fourth scan line GT4, and the M-1th scan signal provided by the M-1th scan line GTM-1 is the same as the M-th scan signal provided by the M-th scan line GTM;

[0362] The display cycle includes a plurality of driving stages arranged in sequence; the first driving stage is labeled S1, the second driving stage is labeled S2, and the Mth driving stage is labeled SM;

[0363] The first driving stage S1 is an overlapping period between a high voltage period of the second scanning signal and a high voltage period of the third scanning signal;

[0364] The second driving stage S2 is an overlapping period of the high voltage period of the fourth scanning signal and the high voltage period of the fifth scanning signal provided by the fifth row of scanning lines;

[0365] The a-th driving stage Sa is the last 2H time included in the M-th scanning signal (a is a positive integer);

[0366] In the first driving phase S1, the data line DT provides the first row data voltage D1, GT1, GT2, GT3 and GT4 are turned on, and the sub-pixels in the first row, the second row, the third row and the fourth row are turned on to receive the first row data voltage D1;

[0367] In the second driving phase S2, the data line DT provides the third row data voltage D3, GT3, GT4, the fifth row scan line and the sixth row scan line are turned on, and the sub-pixels in the third row, the fourth row, the fifth row and the sixth row are turned on to receive the third row data voltage D3;

[0368] In the a-th driving phase Sa, the data line DT provides the M-1-th row data voltage DM-1, GTM-1 and GTM are turned on, and the sub-pixels in the M-1-th row and the sub-pixels in the M-th row are turned on and receive the M-1-th row data voltage DM-1.

[0369] In at least one embodiment shown in FIG. 11 , the display device operates in a DLG (dual-line gate) mode.

[0370] To achieve refresh rate doubling, the refresh rate of the driving signal is doubled, and two rows of pixels are given the same data signal, which can enable the display device to operate in HSR mode or DLG mode.

[0371] In a specific implementation, when the data signal of the even-numbered rows is the same as the data signal of the odd-numbered rows, the data signal amount is halved, and a double refresh rate can be achieved;

[0372] When even columns do not need data signal input, the data signal of the even columns is obtained by averaging the data signals of adjacent columns. The data signal amount is halved, and a double refresh rate can be achieved.

[0373] When the data signals of even rows are the same as those of odd rows, even columns do not require data signal input, and even column data signals are obtained by averaging adjacent column data signals, a 4x refresh rate can be achieved.

[0374] At least one embodiment of the present disclosure can enable a low-resolution signal to drive a high-resolution screen.

[0375] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A data voltage supply circuit, applied to a display device, the display device comprising a data driver, a plurality of columns of pixels and a plurality of columns of data lines, the column of pixels comprising M columns of sub-pixels; M is an integer greater than or equal to 3; the data driver comprising a plurality of data voltage supply terminals; the data voltage supply circuit comprising a plurality of supply circuits; The providing circuit is used to control the M columns of sub-pixels included in the corresponding column of pixels to respectively receive data voltages provided by corresponding data voltage providing terminals, or to control the M columns of sub-pixels included in the corresponding column of pixels to obtain data voltages provided to the M columns of sub-pixels based on data voltages provided for at least one other column of pixels.

2. The data voltage supply circuit according to claim 1, wherein: The providing circuit includes a first gating circuit and a second gating circuit; the column sub-pixels are electrically connected to corresponding column data lines and receive data voltages through the corresponding column data lines; The first gating circuit is electrically connected to M data voltage supply terminals and the current M-column data lines respectively, and is used to control the connection or disconnection between the m-th data voltage supply terminal among the M data voltage supply terminals and the m-th data line among the current M-column data lines; the m-th data line is electrically connected to the m-th column of sub-pixels among the M columns of sub-pixels included in the corresponding column of pixels; m is a positive integer less than or equal to M; The second gating circuit is electrically connected to the current M column data lines, a first group of M column data lines electrically connected to the M columns of sub-pixels included in the first target column pixel, and a second group of M column data lines electrically connected to the M columns of sub-pixels included in the second target column pixel, respectively, and is used to control the data voltage received by the current M column data lines according to the data voltage received by the first group of M column data lines and the data voltage received by the second group of M column data lines; The first target column of pixels is a column of pixels other than the corresponding column of pixels, the second target column of pixels is a column of pixels other than the corresponding column of pixels, and the first target column of pixels and the second target column of pixels are different column pixels; The current M columns of data lines are data lines electrically connected to the M columns of sub-pixels included in the corresponding column of pixels; The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly connected to the corresponding data lines. The data lines electrically connected to the M columns of sub-pixels in the second target column of pixels are directly electrically connected to the corresponding data voltage supplying end.

3. The data voltage supply circuit according to claim 1, wherein: The providing circuit includes a first gating circuit and a third gating circuit; the column sub-pixels are electrically connected to corresponding column data lines and receive data voltages through the corresponding column data lines; The first gating circuit is electrically connected to M data voltage supply terminals and the current M-column data lines respectively, and is used to control the connection or disconnection between the m-th data voltage supply terminal among the M data voltage supply terminals and the m-th data line among the current M-column data lines; the m-th data line is electrically connected to the m-th column of sub-pixels among the M columns of sub-pixels included in the corresponding column of pixels; m is a positive integer less than or equal to M; The third gating circuit is electrically connected to the current M column data lines and the first group of M column data lines electrically connected to the M columns of sub-pixels included in the first target column of pixels, respectively, and is used to control the data voltage received by the current M column data lines according to the data voltage received by the first group of M column data lines; The first target column of pixels is a column of pixels other than the corresponding column of pixels; The current M columns of data lines are data lines electrically connected to the M columns of sub-pixels included in the corresponding column of pixels; The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

4. The data voltage supply circuit according to claim 2 or 3, wherein: The first gating circuit includes M first switch circuits; The mth first switch circuit is electrically connected to the mth data voltage supply terminal among the M data voltage supply terminals and the mth data line among the current M columns of data lines, respectively, and is used to control the connection or disconnection between the mth data voltage supply terminal and the mth data line.

5. The data voltage supply circuit according to claim 2, wherein: The second gating circuit includes M second switch circuits, M first resistors, M third switch circuits and M second resistors; The mth second switch circuit is electrically connected to the mth column data line in the first group of M column data lines and the first end of the mth first resistor, respectively, and is used to control the connection or disconnection between the mth column data line in the first group of M column data lines and the first end of the mth first resistor; the second end of the mth first resistor is electrically connected to the mth column data line in the current M column data lines; The first end of the mth second resistor is electrically connected to the mth column data line in the current M column data lines, and the mth third switch circuit is electrically connected to the second end of the mth second resistor and the mth column data line in the second group of M column data lines, respectively, and is used to control the connection or disconnection between the second end of the mth second resistor and the mth column data line in the second group of M column data lines.

6. The data voltage supply circuit according to claim 3, wherein: The third gating circuit includes M third resistors and M fourth switch circuits; The mth fourth switch circuit is electrically connected to the first end of the mth third resistor and the mth column data line in the first group of M columns of data lines, respectively, and is used to control the connection or disconnection between the first end of the mth third resistor and the mth column data line in the first group of M columns of data lines; The second end of the mth third resistor is electrically connected to the mth column data line among the current M columns of data lines; The data lines electrically connected to the M columns of sub-pixels in the first target column of pixels are directly electrically connected to corresponding data voltage supply terminals.

7. The data voltage supply circuit according to claim 1, wherein: The data driver comprises at least one data driving circuit; the column of pixels comprises three columns of sub-pixels; The data driving circuit includes N data voltage supply terminals; N is a positive integer; The a-th providing circuit includes an a-th first gating circuit and an a-th second gating circuit; a is a positive integer; The first column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a-2 column, the second column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a-1 column, and the third column of sub-pixels included in the pixels in the 3a-1 column is electrically connected to the data line in the 6a column; The first column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-5 column, the second column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-4 column, and the third column of sub-pixels included in the pixels in the 3a-2 column is electrically connected to the data line in the 6a-3 column; The first column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+1 column, the second column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+2 column, and the third column of sub-pixels included in the pixels in the 3a column is electrically connected to the data line in the 6a+3 column; The ath first gating circuit is respectively connected to the 6a-2th column data line, the 6a-1th column data line, the 6a column data line, the 6a-2th data voltage supply terminal, the 6a-1th data voltage supply terminal and the 6a data line. The voltage supply terminal is electrically connected to control the connection or disconnection between the 6a-2 column data line and the 6a-2 data voltage supply terminal, control the connection or disconnection between the 6a-1 column data line and the 6a-1 data voltage supply terminal, and control the connection or disconnection between the 6a column data line and the 6a data voltage supply terminal; The ath second gating circuit is electrically connected to the 6a-5th column data line, the 6a-4th column data line, the 6a-3th column data line, the 6a+1th column data line, the 6a+2th column data line and the 6a+3th column data line, the 6a-2th column data line, the 6a-1th column data line and the 6a column data line, respectively, and is used to control the data voltage received by the 6a-2th column data line according to the data voltage received by the 6a-5th column data line and the data voltage received by the 6a+1th column data line, control the data voltage received by the 6a-1th column data line according to the data voltage received by the 6a-4th column data line and the data voltage received by the 6a+2th column data line, and control the data voltage received by the 6a-3th column data line and the data voltage received by the 6a+3th column data line; The data lines in the 6a-5 column are directly electrically connected to the 6a-5 data voltage supply terminal, the data lines in the 6a-4 column are directly electrically connected to the 6a-4 data voltage supply terminal, the data lines in the 6a-3 column are directly electrically connected to the 6a-3 data voltage supply terminal, the data lines in the 6a+1 column are directly electrically connected to the 6a+1 data voltage supply terminal, the data lines in the 6a+2 column are directly electrically connected to the 6a+2 data voltage supply terminal, and the data lines in the 6a+3 column are directly electrically connected to the 6a+3 data voltage supply terminal.

8. The data voltage supply circuit according to claim 7, wherein: N is a multiple of 6; The data voltage supply circuit includes a fourth gating circuit; The fourth selection circuit is electrically connected to the Nth column data line, the N-1th column data line, the N-2th column data line, the N-3th column data line, the N-4th column data line and the N-5th column data line, respectively, and is used to control the connection or disconnection between the Nth column data line and the N-3rd column data line, control the connection or disconnection between the N-1th column data line and the N-4th column data line, and control the connection or disconnection between the N-2th column data line and the N-5th column data line.

9. The data voltage supply circuit according to claim 7, wherein: N is a multiple of 6, the data driver includes B data driving circuits; B is an integer greater than 1; The bth data driving circuit is electrically connected to the bth group of N columns of data lines, the b+1th data circuit is electrically connected to the b+1th group of N columns of data lines, b is a positive integer, and b+1 is less than or equal to B; The data voltage supply circuit includes a fifth gating circuit; The fifth gating circuit is respectively electrically connected to the N-5th data line in the b-th group of N column data lines, the N-4th data line in the b-th group of N column data lines, the N-3th data line in the b-th group of N column data lines, the N-2th data line in the b-th group of N column data lines, the N-1th data line in the b-th group of N column data lines, the N data line in the b-th group of N column data lines, the first column data line in the b+1-th group of N column data lines, the second column data line in the b+1-th group of N column data lines and the third column data line in the b+1-th group of N column data lines, and is used for selecting the data line according to the data voltage received by the N-5th data line in the b-th group of N column data lines and the data voltage received by the b+1-th group of N column data lines. The data voltage received by the first column of N data lines controls the data voltage received by the N-2 data line in the b-th group of N column data lines; the data voltage received by the N-1 data line in the b-th group of N column data lines is controlled based on the data voltage received by the N-4 data line in the b-th group of N column data lines and the data voltage received by the second column of N column data lines in the b+1-th group of N column data lines; the data voltage received by the N data line in the b-th group of N column data lines is controlled based on the data voltage received by the N-3 data line in the b-th group of N column data lines and the data voltage received by the third column of N column data lines in the b+1-th group of N column data lines.

10. The data voltage supply circuit according to claim 1, wherein: The data driver comprises at least one data driving circuit; the column of pixels comprises three columns of sub-pixels; The data driving circuit includes N data voltage supply terminals; N is a positive integer; The a-th providing circuit includes an a-th first gating circuit and an a-th third gating circuit; a is a positive integer; The ath first selection circuit is electrically connected to the 6a-2th column data line, the 6a-1th column data line, the 6a column data line, the 6a-2th data voltage supply terminal, the 6a-1th data voltage supply terminal and the 6a data voltage supply terminal, respectively, and is used to control the connection or disconnection between the 6a-2th column data line and the 6a-2th data voltage supply terminal, control the connection or disconnection between the 6a-1th column data line and the 6a-1th data voltage supply terminal, and control the connection or disconnection between the 6a column data line and the 6a data voltage supply terminal. The ath third gating circuit is electrically connected to the 6a-5th column data line, the 6a-4th column data line, the 6a-3th column data line, the 6a-2th column data line, the 6a-1th column data line and the 6a column data line, respectively, and is used to control the data voltage on the 6a-2th column data line according to the data voltage on the 6a-5th column data line, control the data voltage on the 6a-1th column data line according to the data voltage on the 6a-4th column data line, and control the data voltage on the 6a-3th column data line according to the data voltage on the 6a-2th column data line. The data voltage on the column data line.

11. The data voltage supply circuit according to claim 4, wherein: The mth first switch circuit comprises an mth first switch transistor; The gate of the mth first switch transistor is electrically connected to the first control voltage terminal, the first electrode of the mth first switch transistor is electrically connected to the mth data voltage supply terminal, and the second electrode of the mth first switch transistor is electrically connected to the mth data line; The data voltage providing circuit includes a first control circuit; The first control circuit is used to provide a first control voltage to the first control voltage terminal to control the mth first switch transistor to be turned on or off.

12. The data voltage supply circuit according to claim 5, wherein: The mth second switch circuit includes an mth second switch transistor, and the mth third switch circuit includes an mth third switch transistor; The gate of the mth second switch transistor is electrically connected to the second control voltage terminal, the first electrode of the mth second switch transistor is electrically connected to the mth column data line in the first group of M columns of data lines, and the second electrode of the mth second switch transistor is electrically connected to the first end of the mth first resistor; The gate of the mth third switch transistor is electrically connected to the second control voltage terminal, the first electrode of the mth third switch transistor is electrically connected to the second end of the mth second resistor, and the second electrode of the mth third switch transistor is electrically connected to the mth column data line of the second group of M columns of data lines; The data voltage providing circuit includes a second control circuit; The second control circuit is used to provide a second control voltage to the second control voltage terminal to control the mth second switch transistor to be turned on or off, and to control the mth third switch transistor to be turned on or off.

13. A display device, comprising a plurality of rows of gate lines, a plurality of columns of data lines, a plurality of rows and columns of pixels, a driving module, and a data voltage supply circuit according to any one of claims 1 to 12; the driving module is electrically connected to the plurality of rows of gate lines, and is used to provide driving signals for the gate lines; The pixels located in the same row are electrically connected to the corresponding row gate line, and are used to receive the driving signal provided by the corresponding row gate line; The pixels located in the same column are electrically connected to the corresponding column data line and are used to receive the data voltage from the corresponding column data line.

14. A driving method, applied to the display device according to claim 13, the driving method comprising: During the driving cycle, the driving module provides a driving signal to the gate line to control the multiple scanning lines to be turned on in sequence; In the driving cycle, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent gate lines among the plurality of rows of gate lines that are sequentially turned on; During at least a portion of the overlapping time period, the data line receives a data voltage that is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

15. A driving method, applied to the display device according to claim 13, wherein a driving cycle comprises a plurality of driving phases arranged in sequence; a 2n-1th row scanning signal provided by a 2n-1th row scanning line is the same as a 2nth row scanning signal provided by a 2nth row scanning line; the driving method comprises: In the nth driving stage, the 2n-1th scan line and the 2nth scan line are turned on, and the sub-pixels located in the 2n-1th row and the sub-pixels located in the 2nth row receive data voltages provided by corresponding data lines; n is a positive integer.

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