Driving method, display panel and display device

Abstract

The invention provides a driving method, a display panel and a display device. The driving method is applied to the display panel, the display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a data voltage access end. The display time of the display panel comprises a plurality of display periods; the display period comprises a reset stage and a data writing stage which are set in sequence; the driving method comprises the following steps: providing reset data voltage for a data voltage access end in at least part of time periods included in a reset stage; and providing corresponding display data voltage to the data voltage access end in at least part of time periods included in the data writing stage. The display accuracy is improved.

Description

Driving method, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a driving method, display panel, and display device. Background Technology

[0002] In related technologies, the display panel may include a data voltage supply module, which may include multiple data voltage supply circuits. These circuits operate under the control of N data multiplexing terminals. Under the control of the nth data multiplexing control signal, they connect the data lines to the data voltage input terminal of the nth pixel circuit among the N pixel circuits. When the data voltage provided by the same data line differs significantly from one another, or when the difference between adjacent data lines is large, the signals on the data lines will couple with each other, resulting in a difference in the final signal input to the pixel circuit, causing display abnormalities. N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a driving method applied to a display panel, the display panel including a plurality of pixel circuits, each pixel circuit including a data voltage access terminal; the display time of the display panel includes a plurality of display cycles; the display cycle includes a reset phase and a data writing phase set sequentially; the driving method includes:

[0005] During at least a portion of the time period included in the reset phase, a reset data voltage is provided to the data voltage access terminal;

[0006] During at least a portion of the time period included in the data writing phase, a corresponding display data voltage is provided to the data voltage access terminal.

[0007] Optionally, during at least a portion of the time period included in the reset phase, the same reset data voltage is provided to the data voltage access terminals of the plurality of pixel circuits.

[0008] Optionally, the display panel includes a data voltage supply module, which includes multiple data voltage supply circuits. Each data voltage supply circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively. Under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal, it controls the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The reset phase includes N sequentially set reset time periods. The driving method includes:

[0009] During the reset phase, the data line provides the reset data voltage;

[0010] During the nth reset time period included in the reset phase, the data voltage supply circuit, under the control of the nth data multiplexing control signal, controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0011] Optionally, the display panel includes a data voltage providing module, which includes multiple data voltage providing circuits. Each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively. Under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The driving method includes:

[0012] During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0013] Optionally, the display panel includes a data voltage providing module, which includes multiple data voltage providing circuits. Each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively. Under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal, it controls the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The display cycle includes a first multiplexing time period. The data writing stage includes N sequentially set data writing time periods. The first multiplexing time period includes the reset stage and the first data writing time period included in the data writing stage. The driving method includes:

[0014] During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal of the nth pixel circuit.

[0015] During the first multiplexing time period, the data voltage providing circuit, under the control of the first data multiplexing control signal provided by the first data multiplexing terminal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits.

[0016] During the nth data writing time period included in the data writing phase, the data line provides the nth display data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits, and writes the nth display data voltage into the nth pixel circuit.

[0017] Optionally, the pixel circuit includes a data writing circuit, a first writing control circuit, and a second writing control circuit. The data writing circuit is electrically connected to the scanning end and the data voltage access end, respectively, and is used to receive the display data voltage provided by the data voltage access end under the control of the scanning signal provided by the scanning end. The first writing control circuit is electrically connected to the first reset control end, the data voltage access end, the light emission control end, and the light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the light emission control end according to the first control data voltage provided by the data voltage access end under the control of the first reset control signal provided by the first reset control end. The second writing control circuit is electrically connected to the second reset control end, the data voltage access end, the light emission control end, and the light emission control node, respectively. The data voltage access terminal, display control terminal, and light emission control node are electrically connected, and are used to control the connection or disconnection between the light emission control node and the display control terminal according to the second control data voltage provided by the data voltage access terminal under the control of the second reset control signal provided by the second reset control terminal; the display cycle includes a first control phase and a second control phase set before the reset phase, the first control phase includes a first write phase and a first set phase set sequentially, and the second control phase includes a second write phase and a second set phase set sequentially; the first write phase includes N first write time periods set sequentially, and the second write phase includes N second write time periods set sequentially; the driving method includes:

[0018] During the nth first write time period, the data line provides the nth first control data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the data line to connect with the data voltage access terminal in the nth pixel circuit among the N pixel circuits, and writes the nth first control data voltage into the first write control circuit of the nth pixel circuit.

[0019] During the first setting phase, the first write control circuit in each pixel circuit controls the connection or disconnection between the light emission control node and the light emission control terminal according to the first control data voltage received.

[0020] During the nth second write time period, the data line provides the nth second control data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the data line to connect with the data voltage access terminal in the nth pixel circuit among the N pixel circuits, and writes the nth second control data voltage into the second write control circuit in the nth pixel circuit.

[0021] During the second setting phase, the second write control circuit in each pixel circuit controls the connection or disconnection between the light-emitting control node and the display control terminal according to the received second control data voltage.

[0022] Optionally, the driving method described in at least one embodiment of this disclosure further includes:

[0023] During at least a portion of the time period between two display cycles, the display control terminal provides a valid display control signal.

[0024] Optionally, the driving method described in at least one embodiment of this disclosure further includes:

[0025] During the first setting phase, the display control terminal provides a valid display control signal.

[0026] Optionally, the driving method described in at least one embodiment of this disclosure further includes:

[0027] In the first control phase, the display control terminal provides effective display control signals.

[0028] In a second aspect, embodiments of this disclosure provide a display panel including multiple pixel circuits, each pixel circuit including a data voltage access terminal; the display panel further includes a data voltage supply module; the display time of the display panel includes multiple display cycles; the display cycle includes a reset phase and a data writing phase set sequentially.

[0029] The data voltage providing module is used to provide a reset data voltage to the data voltage access terminal during at least a portion of the time period included in the reset phase, and to provide a corresponding display data voltage to the data voltage access terminal during at least a portion of the time period included in the data writing phase.

[0030] Optionally, the data voltage providing module is used to control the reset data voltage provided to the data voltage access terminals of the plurality of pixel circuits to be the same during at least a portion of the time period included in the reset phase.

[0031] Optionally, the data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively, and is used to control the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit in the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; the reset phase includes N reset time periods set sequentially;

[0032] The data line is used to provide the reset data voltage during the reset phase;

[0033] The data voltage providing circuit is used, under the control of the nth data multiplexing control signal, during the nth reset time period included in the reset phase, to control the connection between the data line and the data voltage access terminal in the nth pixel circuit, and to write the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0034] Optionally, the data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals included in the N pixel circuits, respectively, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0035] The data line is used to provide the reset data voltage during the reset phase;

[0036] The data voltage providing circuit is used during the reset phase to control the connection between the data line and the data voltage access terminal in the nth pixel circuit under the control of the nth data multiplexing control signal, and to write the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0037] Optionally, the data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals included in the N pixel circuits, respectively, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; the display cycle includes a first multiplexing time period; the data writing stage includes N data writing time periods set sequentially; the first multiplexing time period includes the reset stage and the first data writing time period included in the data writing stage; the driving method includes:

[0038] During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal of the nth pixel circuit.

[0039] During the first multiplexing time period, the data voltage providing circuit, under the control of the first data multiplexing control signal provided by the first data multiplexing terminal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits.

[0040] During the nth data writing time period included in the data writing phase, the data line provides the nth display data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits, and writes the nth display data voltage into the nth pixel circuit.

[0041] Optionally, the pixel circuit includes a data writing circuit, a first writing control circuit, and a second writing control circuit. The data writing circuit is electrically connected to the scanning end and the data voltage access end, respectively, and is used to receive the display data voltage provided by the data voltage access end under the control of the scanning signal provided by the scanning end. The first writing control circuit is electrically connected to the first reset control end, the data voltage access end, the light emission control end, and the light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the light emission control end according to the first control data voltage provided by the data voltage access end under the control of the first reset control signal provided by the first reset control end. The second writing control circuit is electrically connected to the second reset control end, the data voltage access end, the display control end, and the light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the display control end according to the second control data voltage provided by the data voltage access end under the control of the second reset control signal provided by the second reset control end.

[0042] The display cycle includes a first control phase and a second control phase set before the reset phase. The first control phase includes a first write phase and a first set phase set sequentially. The second control phase includes a second write phase and a second set phase set sequentially. The first write phase includes N first write time periods set sequentially. The second write phase includes N second write time periods set sequentially.

[0043] The data line is used to provide the nth first control data voltage during the nth first write time period. The data voltage providing circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit of the N pixel circuits during the nth first write time period under the control of the nth data multiplexing control signal, so as to write the nth first control data voltage into the first write control circuit in the nth pixel circuit.

[0044] The first write control circuit in each pixel circuit is used to control the connection or disconnection between the light emission control node and the light emission control terminal according to the first control data voltage received during the first setting phase.

[0045] The data line is used to provide the nth second control data voltage during the nth second write time period. The data voltage providing circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits during the nth second write time period under the control of the nth data multiplexing control signal, so as to write the nth second control data voltage into the second write control circuit in the nth pixel circuit.

[0046] The second write control circuit in each pixel circuit is used to control the connection or disconnection between the light-emitting control node and the display control terminal according to the second control data voltage received during the second setting phase.

[0047] Optionally, the display control terminal is used to provide an effective display control signal for at least a portion of the time period between two display cycles.

[0048] Optionally, the display control terminal is used to provide an effective display control signal during the first setting phase.

[0049] Optionally, the display control terminal is used to provide effective display control signals during the first control phase.

[0050] In a third aspect, embodiments of this disclosure provide a display device including the display panel described above. Attached Figure Description

[0051] Figure 1 is a structural diagram of at least one embodiment of the pixel circuit;

[0052] Figure 2 is a structural diagram of at least one embodiment of the pixel circuit;

[0053] Figure 3 is a circuit diagram of at least one embodiment of the pixel circuit;

[0054] Figure 4 is a structural diagram of at least one embodiment of the pixel circuit;

[0055] Figure 5 is a circuit diagram of at least one embodiment of the pixel circuit;

[0056] Figure 6A is a circuit diagram of at least one embodiment of the data voltage supply circuit;

[0057] Figure 6B is a circuit diagram of at least one embodiment of the data voltage providing circuit;

[0058] Figure 7 is a circuit diagram of at least one embodiment of the data voltage supply module;

[0059] Figure 8 is a timing diagram of the operation of at least one embodiment shown in Figure 6A when the structure of the pixel circuit is as shown in Figure 5.

[0060] Figure 9 is a timing diagram of the operation of at least one embodiment shown in Figure 6B when the structure of each pixel circuit is as shown in Figure 5.

[0061] Figure 10 is a timing diagram of the operation of at least one embodiment shown in Figure 6A when the structure of the pixel circuit is as shown in Figure 3.

[0062] Figure 11 is a timing diagram of the operation of at least one embodiment shown in Figure 6B when the structure of the pixel circuit is as shown in Figure 3.

[0063] Figure 12 is a timing diagram of the operation of at least one embodiment shown in Figure 6B when the pixel circuit structure is as shown in Figure 3.

[0064] Figure 13 is a timing diagram of the operation of at least one embodiment shown in Figure 6B when the structure of the pixel circuit is as shown in Figure 3.

[0065] Figure 14 is a timing diagram of the display control signals provided by the display control terminal in at least one embodiment of this disclosure;

[0066] Figure 15 is a timing diagram of the display control signals provided by the display control terminal in at least one embodiment of this disclosure;

[0067] Figure 16 is a timing diagram of the display control signals provided by the display control terminal in at least one embodiment of this disclosure. Detailed Implementation

[0068] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0069] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0070] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0071] The driving method described in at least one embodiment of this disclosure is applied to a display panel, the display panel including multiple pixel circuits, each pixel circuit including a data voltage input terminal; the display time of the display panel includes multiple display cycles; each display cycle includes a reset phase and a data writing phase set sequentially; the driving method includes:

[0072] During at least a portion of the time period included in the reset phase, a reset data voltage is provided to the data voltage access terminal;

[0073] During at least a portion of the time period included in the data writing phase, a corresponding display data voltage is provided to the data voltage access terminal.

[0074] In the driving method described in at least one embodiment of this disclosure, a reset phase for signal reset is set before the data writing phase. During at least a portion of the time period included in the reset phase, a reset data voltage is provided to the pixel circuits included in the display panel through the data voltage access terminal. Then, during at least a portion of the time period included in the data writing phase, a corresponding display data voltage is provided to the pixel circuits through the data voltage access terminal. This eliminates coupling caused by excessive differences in signals with the previous frame or the previous data writing phase, avoids signal coupling between adjacent data lines, and prevents uneven column display of the display screen, especially uneven column display before and after correction, thereby increasing the accuracy of the final display.

[0075] In at least one embodiment of this disclosure, the same reset data voltage is provided to the data voltage access terminals of the plurality of pixel circuits during at least a portion of the time period included in the reset phase.

[0076] In practice, during at least a portion of the time period included in the reset phase, the reset data voltage to all pixel circuits included in the display panel is controlled to be the same to improve display uniformity.

[0077] In at least one embodiment of this disclosure, the display panel includes a data voltage providing module, which includes multiple data voltage providing circuits. Each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively. Under the control of an nth data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the data line to connect with the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The reset phase includes N sequentially set reset time periods. The driving method includes:

[0078] During the reset phase, the data line provides the reset data voltage;

[0079] During the nth reset time period included in the reset phase, the data voltage supply circuit, under the control of the nth data multiplexing control signal, controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0080] In related technologies, the display panel may include a data voltage providing module, which may include multiple data voltage providing circuits. These circuits operate under the control of N data multiplexing terminals. Under the control of the nth data multiplexing control signal, they connect the data lines to the data voltage access terminal of the nth pixel circuit among the N pixel circuits. When the data voltage provided by the same data line before and after a large difference, or when the difference between adjacent data lines is large, the signals on the data lines will couple with each other, resulting in differences in the signals ultimately input to the pixel circuit, causing display abnormalities. To solve the problems in related technologies and reduce signal coupling, at least one embodiment of this disclosure designs a reset stage (the reset stage can be a signal reset stage). In the reset stage, the data lines provide the reset data voltage. During the nth reset time period included in the reset stage, the data voltage providing circuit, under the control of the nth data multiplexing control signal, writes the reset data voltage into the data voltage access terminal of the nth pixel circuit, resetting the signals on the data lines and the signals provided to the pixel circuit, reducing signal coupling and increasing the accuracy of the final display.

[0081] In at least one embodiment of this disclosure, the display panel includes a data voltage providing module, which includes multiple data voltage providing circuits. Each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively. Under the control of an nth data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the data line to connect with the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The driving method includes:

[0082] During the reset phase, the data line provides the reset data voltage, and the data voltage providing circuit provides the reset data voltage to the corresponding data voltage access terminal under the control of the data multiplexing control signal provided by the corresponding data multiplexing terminal.

[0083] At least one embodiment of this disclosure includes a reset stage (which may be a signal reset stage). In the reset stage, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit writes the reset data voltage into the data voltage access terminal of the nth pixel circuit, thereby resetting the signals on the data line and the signals provided to the pixel circuit, reducing the coupling between signals, and increasing the accuracy of the final display.

[0084] In at least one embodiment of this disclosure, the display panel includes a data voltage providing module, which includes multiple data voltage providing circuits. Each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits, respectively. Under the control of an nth data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The display cycle includes a first multiplexing time period. The data writing phase includes N data writing time periods set sequentially. The first multiplexing time period includes the reset phase and the first data writing time period included in the data writing phase. The driving method includes:

[0085] During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal of the nth pixel circuit.

[0086] During the first multiplexing time period, the data voltage providing circuit, under the control of the first data multiplexing control signal provided by the first data multiplexing terminal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits.

[0087] During the nth data writing time period included in the data writing phase, the data line provides the nth display data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits, and writes the nth display data voltage into the nth pixel circuit.

[0088] At least one embodiment of this disclosure includes a reset stage (which may be a signal reset stage). In the reset stage, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit writes the reset data voltage into the data voltage access terminal of the nth pixel circuit, thereby resetting the signals on the data line and the signals provided to the pixel circuit, reducing the coupling between signals, and increasing the accuracy of the final display.

[0089] Furthermore, a data writing phase is set after the reset phase. The data writing phase includes N data writing time periods set sequentially. During the nth data writing time period, the data voltage supply circuit provides the nth display data voltage provided by the data line to the nth pixel circuit.

[0090] The first reset time period is set to include the reset phase and the data writing phase. During the first reset time period, the data voltage supply circuit, under the control of the first data multiplexing control signal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits, so as to reduce the time between the falling edge of the first data multiplexing control signal in the reset phase and the rising edge of the first data multiplexing control signal in the data writing phase.

[0091] In at least one embodiment of this disclosure, the pixel circuit includes a data writing circuit, a first writing control circuit, and a second writing control circuit. The data writing circuit is electrically connected to a scanning end and a data voltage access end, respectively, and is used to receive a display data voltage provided by the data voltage access end under the control of a scanning signal provided by the scanning end. The first writing control circuit is electrically connected to a first reset control end, the data voltage access end, a light emission control end, and a light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the light emission control end according to a first control data voltage provided by the data voltage access end under the control of a first reset control signal provided by the first reset control end. The second writing control circuit is used to perform a second reset control. The terminal, the data voltage access terminal, the display control terminal, and the light-emitting control node are electrically connected, and are used to control the connection or disconnection between the light-emitting control node and the display control terminal according to the second control data voltage provided by the data voltage access terminal under the control of the second reset control signal provided by the second reset control terminal; the display cycle includes a first control stage and a second control stage set before the reset stage, the first control stage includes a first write stage and a first set stage set sequentially, and the second control stage includes a second write stage and a second set stage set sequentially; the first write stage includes N first write time periods set sequentially, and the second write stage includes N second write time periods set sequentially; the driving method includes:

[0092] During the nth first write time period, the data line provides the nth first control data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the data line to connect with the data voltage access terminal in the nth pixel circuit among the N pixel circuits, and writes the nth first control data voltage into the first write control circuit of the nth pixel circuit.

[0093] During the first setting phase, the first write control circuit in each pixel circuit controls the connection or disconnection between the light emission control node and the light emission control terminal according to the first control data voltage received.

[0094] During the nth second write time period, the data line provides the nth second control data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the data line to connect with the data voltage access terminal in the nth pixel circuit among the N pixel circuits, and writes the nth second control data voltage into the second write control circuit in the nth pixel circuit.

[0095] During the second setting phase, the second write control circuit in each pixel circuit controls the connection or disconnection between the light-emitting control node and the display control terminal according to the received second control data voltage.

[0096] In specific implementation, when the pixel circuit is a PAM (Pulse Amplitude Modulation) + PWM (Pulse Width Modulation) pixel circuit, a first control stage and a second control stage can be set before the reset stage. The first control stage includes a first write stage and a first set stage set sequentially, and the second control stage includes a second write stage and a second set stage set sequentially. The first write stage includes N first write time periods set sequentially, and the second write stage includes N second write time periods set sequentially. In the nth first write time period, the data voltage providing circuit writes the nth first control data voltage into the first write control circuit in the nth pixel circuit. In the first set stage, the first write control circuit in each pixel circuit controls the connection or disconnection between the light-emitting control node and the light-emitting control terminal according to the received first control data voltage. In the first set stage, when the first write control circuit in the pixel circuit controls the connection between the light-emitting control node and the light-emitting control terminal according to the received first control data voltage, the pixel circuit enters PAM mode.

[0097] During the nth second write time period, the data line provides the nth second control data voltage, and the data voltage providing circuit writes the nth second control data voltage into the second write control circuit in the nth pixel circuit; during the second set phase, the second write control circuit in each pixel circuit controls the connection or disconnection between the light-emitting control node and the display control terminal according to the received second control data voltage; when the second write control circuit in the pixel circuit controls the connection between the light-emitting control node and the display control terminal according to the received second control data voltage, the pixel circuit enters PWM mode.

[0098] As shown in Figure 1, at least one embodiment of the pixel circuit includes a light-emitting element E1, a driving circuit 20, a first light-emitting control circuit 21, a data writing circuit 10, a first writing control circuit 11, and a second writing control circuit 12.

[0099] The data writing circuit 10 is electrically connected to the scanning end GT, the data voltage access end DT and the first end of the driving circuit 20 respectively, and is used to write the display data voltage provided by the data voltage access end DT into the first end of the driving circuit 20 under the control of the scanning signal provided by the scanning end GT.

[0100] The first write control circuit 11 is electrically connected to the first reset control terminal RSTB, the data voltage access terminal DT, the light emission control terminal EM, and the light emission control node NE, respectively. Under the control of the first reset control signal provided by the first reset control terminal RSTB, the light emission control node NE is connected or disconnected from the light emission control terminal EM according to the first control data voltage Db provided by the data voltage access terminal DT.

[0101] The second write control circuit 12 is electrically connected to the second reset control terminal RSTA, the data voltage access terminal DT, the display control terminal HF, and the light emission control node NE, respectively. Under the control of the second reset control signal provided by the second reset control terminal RSTA, it controls the connection or disconnection between the light emission control node NE and the display control terminal HF according to the second control data voltage Da provided by the data voltage access terminal DT.

[0102] The control terminal of the drive circuit 20 is electrically connected to the first node N1, the first terminal of the drive circuit 20 is electrically connected to the second node N2, and the second terminal of the drive circuit 20 is electrically connected to the third node N3.

[0103] The first light-emitting control circuit 21 is electrically connected to the light-emitting control node NE, the third node N3 and the first electrode of the light-emitting element E1 respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the potential of the light-emitting control node NE;

[0104] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0105] Optionally, the first voltage terminal can be a low voltage terminal.

[0106] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a second light emission control circuit 22, a first initialization circuit 23, a second initialization circuit 24, an energy storage circuit 25, and a compensation control circuit 26.

[0107] The second light-emitting control circuit 22 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0108] The first initialization circuit 23 is electrically connected to the second reset control terminal RA, the initial voltage terminal I1 and the first node N1 respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RA.

[0109] The second initialization circuit 24 is electrically connected to the second reset control terminal RA, the initial voltage terminal I1, and the first pole of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first pole of the light-emitting element E1 under the control of the second reset control signal.

[0110] The energy storage circuit 25 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0111] The compensation control circuit 26 is electrically connected to the scanning end GT, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the scanning signal provided by the scanning end GT.

[0112] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 2, the data writing circuit includes a first transistor M1, the first writing control circuit includes a second transistor M2, a third transistor M3 and a first capacitor C1, the second writing control circuit includes a fourth transistor M4, a fifth transistor M5 and a second capacitor C2; the driving circuit includes a driving transistor M0, the first light-emitting control circuit includes a sixth transistor M6; and the light-emitting element is an organic light-emitting diode O1.

[0113] The gate of M1 is electrically connected to the scan terminal GT, the source of M1 is electrically connected to the data voltage input terminal DT, and the drain of M1 is electrically connected to the source of M0.

[0114] The gate of M2 is electrically connected to the first reset control terminal RSTB, the source of M2 is electrically connected to the data voltage access terminal DT, and the drain of M2 is electrically connected to the gate of M3.

[0115] The source of M3 is electrically connected to the light-emitting control terminal EM, and the drain of M3 is electrically connected to the light-emitting control node NE.

[0116] The first terminal of C1 is electrically connected to the gate of M3, and the second terminal of C1 is electrically connected to the initial voltage terminal I1.

[0117] The gate of M4 is electrically connected to the second reset control terminal RSTA, the source of M4 is electrically connected to the data voltage access terminal DT, and the drain of M4 is electrically connected to the gate of M5.

[0118] The source of M5 is electrically connected to the display control terminal HF, and the drain of M5 is electrically connected to the light-emitting control node NE.

[0119] The first terminal of C2 is electrically connected to the gate of M5, and the second terminal of C2 is electrically connected to the initial voltage terminal I1.

[0120] The gate of DT is electrically connected to the first node N1, the source of DT is electrically connected to the second node N2, and the drain of DT is electrically connected to the third node N3.

[0121] The gate of M6 is electrically connected to the light-emitting control node NE, the source of M6 is electrically connected to the third node N3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0122] The second light-emitting control circuit includes a seventh transistor M7, the first initialization circuit includes an eighth transistor M8, the second initialization circuit includes a ninth transistor M9, the compensation control circuit includes a tenth transistor M10, and the energy storage circuit includes a third capacitor C3.

[0123] The gate of M7 is electrically connected to the light-emitting control terminal EM, the source of M7 is electrically connected to the power supply voltage terminal VDD, and the drain of M7 is electrically connected to the second node N2.

[0124] The gate of M8 is electrically connected to the second reset control terminal RSTA, the source of M8 is electrically connected to the initial voltage terminal I1, and the drain of M8 is electrically connected to the first node N1.

[0125] The gate of M9 is electrically connected to the second reset control terminal RSTA, the source of M9 is electrically connected to the initial voltage terminal I1, and the drain of M9 is electrically connected to the anode of O1.

[0126] The gate of M10 is electrically connected to the scanning terminal GT, the source of M10 is electrically connected to the first node N1, and the drain of M10 is electrically connected to the third node N3.

[0127] The first terminal of C3 is electrically connected to the first node N1, and the second terminal of C3 is electrically connected to the power supply voltage terminal VDD.

[0128] In at least one embodiment shown in Figure 3, all transistors are p-type transistors.

[0129] As shown in Figure 4, at least one embodiment of the pixel circuit may include a light-emitting element E1, a driving circuit 20, a first light-emitting control circuit 21, a data writing circuit 10, a second light-emitting control circuit 22, a first initialization circuit 23, a second initialization circuit 24, an energy storage circuit 25, and a compensation control circuit 26.

[0130] The control terminal of the driving circuit 20 is electrically connected to the first node N1, the first terminal of the driving circuit 20 is electrically connected to the second node N2, and the second terminal of the driving circuit 20 is electrically connected to the third node N3. The driving circuit 20 is used to generate a driving current under the control of the potential of the first node N1.

[0131] The data writing circuit 10 is electrically connected to the scanning end GT, the data voltage access end DT and the first end of the driving circuit 20 respectively, and is used to write the display data voltage provided by the data voltage access end DT into the first end of the driving circuit 20 under the control of the scanning signal provided by the scanning end GT.

[0132] The first light-emitting control circuit 21 is electrically connected to the light-emitting control node NE, the third node N3 and the first electrode of the light-emitting element E1 respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the potential of the light-emitting control node NE;

[0133] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1;

[0134] The second light-emitting control circuit 22 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0135] The first initialization circuit 23 is electrically connected to the second reset control terminal RA, the initial voltage terminal I1 and the first node N1 respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RA.

[0136] The second initialization circuit 24 is electrically connected to the second reset control terminal RA, the initial voltage terminal I1, and the first pole of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first pole of the light-emitting element E1 under the control of the second reset control signal.

[0137] The energy storage circuit 25 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0138] The compensation control circuit 26 is electrically connected to the scanning end GT, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the scanning signal provided by the scanning end GT.

[0139] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 4, the data writing circuit includes a first transistor M1, the driving circuit includes a driving transistor M0, and the first light-emitting control circuit includes a sixth transistor M6; the light-emitting element is an organic light-emitting diode O1.

[0140] The gate of M1 is electrically connected to the scan terminal GT, the source of M1 is electrically connected to the data voltage input terminal DT, and the drain of M1 is electrically connected to the source of M0.

[0141] The gate of DT is electrically connected to the first node N1, the source of DT is electrically connected to the second node N2, and the drain of DT is electrically connected to the third node N3.

[0142] The gate of M6 is electrically connected to the light-emitting control node NE, the source of M6 is electrically connected to the third node N3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0143] The second light-emitting control circuit includes a seventh transistor M7, the first initialization circuit includes an eighth transistor M8, the second initialization circuit includes a ninth transistor M9, the compensation control circuit includes a tenth transistor M10, and the energy storage circuit includes a third capacitor C3.

[0144] The gate of M7 is electrically connected to the light-emitting control terminal EM, the source of M7 is electrically connected to the power supply voltage terminal VDD, and the drain of M7 is electrically connected to the second node N2.

[0145] The gate of M8 is electrically connected to the second reset control terminal RSTA, the source of M8 is electrically connected to the initial voltage terminal I1, and the drain of M8 is electrically connected to the first node N1.

[0146] The gate of M9 is electrically connected to the second reset control terminal RSTA, the source of M9 is electrically connected to the initial voltage terminal I1, and the drain of M9 is electrically connected to the anode of O1.

[0147] The gate of M10 is electrically connected to the scanning terminal GT, the source of M10 is electrically connected to the first node N1, and the drain of M10 is electrically connected to the third node N3.

[0148] The first terminal of C3 is electrically connected to the first node N1, and the second terminal of C3 is electrically connected to the power supply voltage terminal VDD.

[0149] In at least one embodiment shown in Figure 5, all transistors are p-type transistors.

[0150] As shown in Figure 6A, at least one embodiment of the data voltage providing circuit may include a first multiplexed transistor MX1, a second multiplexed transistor MX2, and a third multiplexed transistor MX3;

[0151] The gate of the first multiplexed transistor MX1 ​​is electrically connected to the first data multiplexing terminal SX1, the source of the first multiplexed transistor MX1 ​​is electrically connected to the data line DL, and the drain of the first multiplexed transistor MX1 ​​is electrically connected to the first data voltage access terminal DT1.

[0152] The gate of the second multiplexing transistor MX2 is electrically connected to the second data multiplexing terminal SX2, the source of the second multiplexing transistor MX2 is electrically connected to the data line DL, and the drain of the second multiplexing transistor MX2 is electrically connected to the second data voltage input terminal DT2.

[0153] The gate of the third multiplexing transistor MX3 is electrically connected to the third data multiplexing terminal SX3, the source of the third multiplexing transistor MX3 is electrically connected to the data line DL, and the drain of the third multiplexing transistor MX3 is electrically connected to the third data voltage access terminal DT3.

[0154] In at least one embodiment shown in Figure 6A, N equals 3.

[0155] In at least one embodiment shown in FIG6A, each multiplexed transistor is a p-type transistor.

[0156] In at least one embodiment shown in Figure 6A, DT1 can be electrically connected to the first red pixel circuit R1, DT2 can be electrically connected to the second red pixel circuit R2, and DT3 can be electrically connected to the third red pixel circuit R3, but is not limited thereto.

[0157] As shown in Figure 6B, at least one embodiment of the data voltage providing circuit may include a first multiplexed transistor MX1, a second multiplexed transistor MX2, and a third multiplexed transistor MX3;

[0158] The gate of the first multiplexed transistor MX1 ​​is electrically connected to the first data multiplexing terminal SX1, the source of the first multiplexed transistor MX1 ​​is electrically connected to the data line DL, and the drain of the first multiplexed transistor MX1 ​​is electrically connected to the first data voltage access terminal DT1.

[0159] The gate of the second multiplexing transistor MX2 is electrically connected to the second data multiplexing terminal SX2, the source of the second multiplexing transistor MX2 is electrically connected to the data line DL, and the drain of the second multiplexing transistor MX2 is electrically connected to the second data voltage input terminal DT2.

[0160] The gate of the third multiplexing transistor MX3 is electrically connected to the third data multiplexing terminal SX3, the source of the third multiplexing transistor MX3 is electrically connected to the data line DL, and the drain of the third multiplexing transistor MX3 is electrically connected to the third data voltage access terminal DT3.

[0161] In at least one embodiment shown in Figure 6B, N equals 3.

[0162] In at least one embodiment shown in FIG6B, each multiplexed transistor is a p-type transistor.

[0163] In at least one embodiment shown in FIG6B, DT1 may be electrically connected to the first red pixel circuit R1, DT2 may be electrically connected to the first green pixel circuit G1, and DT3 may be electrically connected to the first blue pixel circuit B1, but is not limited thereto.

[0164] As shown in Figure 7, at least one embodiment of the data voltage providing module may include a first data voltage providing circuit, a second data voltage providing circuit and a third data voltage providing circuit;

[0165] The first data voltage providing circuit may include a first multiplexed transistor MX1, a second multiplexed transistor MX2, and a third multiplexed transistor MX3;

[0166] The gate of the first multiplexed transistor MX1 ​​is electrically connected to the first data multiplexing terminal SX1, the source of the first multiplexed transistor MX1 ​​is electrically connected to the first data line DL1, and the drain of the first multiplexed transistor MX1 ​​is electrically connected to the first data voltage access terminal DT1.

[0167] The gate of the second multiplexing transistor MX2 is electrically connected to the second data multiplexing terminal SX2, the source of the second multiplexing transistor MX2 is electrically connected to the second data line DL2, and the drain of the second multiplexing transistor MX2 is electrically connected to the second data voltage input terminal DT2.

[0168] The gate of the third multiplexing transistor MX3 is electrically connected to the third data multiplexing terminal SX3, the source of the third multiplexing transistor MX3 is electrically connected to the third data line DL3, and the drain of the third multiplexing transistor MX3 is electrically connected to the third data voltage access terminal DT3.

[0169] The second data voltage providing circuit may include a fourth multiplexed transistor MX4, a fifth multiplexed transistor MX5, and a sixth multiplexed transistor MX6;

[0170] The gate of the fourth multiplexing transistor MX4 is electrically connected to the first data multiplexing terminal SX1, the source of the fourth multiplexing transistor MX4 is electrically connected to the first data line DL1, and the drain of the fourth multiplexing transistor MX4 is electrically connected to the fourth data voltage access terminal DT4.

[0171] The gate of the fifth multiplexed transistor MX5 is electrically connected to the second data multiplexing terminal SX2, the source of the fifth multiplexed transistor MX5 is electrically connected to the second data line DL2, and the drain of the fifth multiplexed transistor MX5 is electrically connected to the fifth data voltage access terminal DT5.

[0172] The gate of the sixth multiplexed transistor MX6 is electrically connected to the third data multiplexing terminal SX3, the source of the sixth multiplexed transistor MX6 is electrically connected to the third data line DL3, and the drain of the sixth multiplexed transistor MX6 is electrically connected to the sixth data voltage access terminal DT6.

[0173] The third data voltage providing circuit may include a seventh multiplexed transistor MX7, an eighth multiplexed transistor MX8, and a ninth multiplexed transistor MX9;

[0174] The gate of the seventh multiplexed transistor MX7 is electrically connected to the first data multiplexing terminal SX1, the source of the seventh multiplexed transistor MX7 is electrically connected to the first data line DL1, and the drain of the seventh multiplexed transistor MX7 is electrically connected to the seventh data voltage access terminal DT7.

[0175] The gate of the eighth multiplexed transistor MX8 is electrically connected to the second data multiplexing terminal SX2, the source of the eighth multiplexed transistor MX8 is electrically connected to the second data line DL2, and the drain of the eighth multiplexed transistor MX8 is electrically connected to the eighth data voltage access terminal DT8.

[0176] The gate of the ninth multiplexed transistor MX9 is electrically connected to the third data multiplexing terminal SX3, the source of the ninth multiplexed transistor MX9 is electrically connected to the third data line DL3, and the drain of the ninth multiplexed transistor MX9 is electrically connected to the ninth data voltage access terminal DT9.

[0177] In at least one embodiment shown in Figure 7, all transistors may be p-type transistors.

[0178] In at least one embodiment shown in Figure 7, DT1, DT2, and DT3 can be electrically connected to the first red pixel circuit, the second red pixel circuit, and the third red data circuit, respectively; DT4, DT5, and DT6 can be electrically connected to the first green pixel circuit, the second green pixel circuit, and the third green data circuit, respectively; and DT7, DT8, and DT9 can be electrically connected to the first blue pixel circuit, the second blue pixel circuit, and the third blue data circuit, respectively; or...

[0179] DT1, DT2 and DT3 can be electrically connected to the first red pixel circuit, the first green pixel circuit and the first blue data circuit respectively; DT4, DT5 and DT6 can be electrically connected to the second red pixel circuit, the second green pixel circuit and the second blue data circuit respectively; DT7, DT8 and DT9 can be electrically connected to the third red pixel circuit, the third green pixel circuit and the third blue data circuit respectively.

[0180] As shown in Figure 8, when at least one embodiment shown in Figure 6A is in operation, and the structure of the pixel circuit is as shown in Figure 5, the first display cycle may include a first initialization stage S1, a first reset stage SR1, a first data writing stage SW1, a first compensation stage SC1, and a first light emission stage SE1 set sequentially; the second display cycle may include a second initialization stage S2, a second reset stage SR2, a second data writing stage SW2, a second compensation stage SC2, and a second light emission stage SE2 set sequentially.

[0181] The first reset phase SR1 includes a first reset time period Sf1, a second reset time period Sf2, and a third reset time period Sf3 set sequentially; the first data write phase SW1 includes a first data write time period Sd1, a second data write time period Sd2, and a third data write time period Sd3 set sequentially.

[0182] In the first initialization phase S1, RSTA provides a low voltage signal, M8 and M9 are turned on, and I1 provides the initial voltage Vinit to the anodes of N1 and O1;

[0183] During the first reset phase SR1, DL provides the reset data voltage Vdataf;

[0184] During the first reset time period, Sf1 and SX1 provide a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1.

[0185] During the second reset period, Sf2 and SX2 provide a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2.

[0186] During the third reset time period, Sf3 and SX3 provide a low voltage signal, MX3 is turned on, and DL provides the reset data voltage Vdataf to DT3.

[0187] By operating in the first reset phase SR1, before the first data write phase SW1, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar1 to DT1, DL provides Vdatar2 to DT2, and DL provides Vdatar3 to DT3 in the first data write phase SW1.

[0188] During the first data write time period Sd1, DL provides the first red data voltage Vdatar1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar1 to DT1;

[0189] During the second data write period Sd2, DL provides the second red data voltage Vdatar2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatar2 to DT2;

[0190] During the third data write period Sd3, DL provides the third red data voltage Vdatar3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatar3 to DT3.

[0191] In the first compensation stage SC1, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0192] The second reset phase SR2 includes a fourth reset time period Sf4, a fifth reset time period Sf5, and a sixth reset time period Sf6 set sequentially; the second data write phase SW2 includes a fourth data write time period Sd4, a fifth data write time period Sd5, and a sixth data write time period Sd6 set sequentially.

[0193] In the second initialization phase S2, RSTA provides a low voltage signal, M8 and M9 are turned on, and I1 provides the initial voltage Vinit to the anodes of N1 and O1;

[0194] During the second reset phase SR2, DL provides the reset data voltage Vdataf;

[0195] During the fourth reset time period Sf4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1;

[0196] During the fifth reset time period Sf5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2;

[0197] During the sixth reset time period Sf6, SX3 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT3;

[0198] The second reset phase SR2 is set before the second data write phase SW2 so that the data voltage on each data voltage access terminal in the first data write phase SW1 will not affect the data voltage written on each data voltage access terminal in the second data write phase SW2, and reduce the coupling of signals written first on the data line with other signals, ensuring the accuracy of the written signal and the correctness of the display.

[0199] By operating in the second reset phase SR2, before the second data write phase SW2, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar4 to DT1, Vdatar5 to DT2 and Vdatar6 to DT3 in the second data write phase SW2.

[0200] During the fourth data write period Sd4, DL provides the fourth red data voltage Vdatar4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar4 to DT1;

[0201] During the fifth data write period Sd5, DL provides the fifth red data voltage Vdatar5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatar5 to DT2;

[0202] During the sixth data write period Sd6, DL provides the sixth red data voltage Vdatar6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatar6 to DT3.

[0203] In the second compensation stage SC2, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0204] In Figure 8, the duration of each time period can be freely set. Furthermore, the second reset control signal provided by RSTA and the scan signal provided by GT can be provided by adjacent GOA circuits in the same GOA (Gate On Array, gate drive circuit disposed on the array substrate) module. That is, the scan signal of the previous row is the second reset control signal of the next row. Therefore, the duration of S1 and the duration of SC1 can be the same. In specific implementation, the second reset control signal and the scan signal can also be provided by two different GOA modules.

[0205] The duration of the first reset phase SR1 and the second reset phase SR2 is mainly determined by the front-end signal transmission rate, the turn-on time of a single multiplexed transistor, and the number of data multiplexing terminals.

[0206] The duration of the first data writing phase SW1 is determined by the sum of the durations of Sd1, Sd2, and Sd3, the minimum interval between Sd1 and Sd2, and the minimum interval between Sd2 and Sd3.

[0207] In at least one embodiment of this disclosure, when each data voltage is greater than or equal to 2.5V and less than or equal to 6V,

[0208] Vdataf can be equal to 2.5V, or Vdataf can be equal to 6V;

[0209] Alternatively, in a preferred embodiment, Vdataf can take an intermediate value between 2.5V and 6V; for example, Vdataf can be equal to 4.8V, 4.5V, or 5V.

[0210] As shown in Figure 9, when at least one embodiment shown in Figure 6B is in operation, and the structure of each pixel circuit is as shown in Figure 5, the first display cycle may include a first initialization stage S1, a first reset stage SR1, a first data writing stage SW1, a first compensation stage SC1, and a first light emission stage SE1 set sequentially; the second display cycle may include a second initialization stage S1, a second reset stage SR2, a second data writing stage SW2, a second compensation stage SC2, and a second light emission stage SE2 set sequentially.

[0211] The first reset phase SR1 includes a first reset time period Sf1, a second reset time period Sf2, and a third reset time period Sf3 set sequentially; the first data write phase SW1 includes a first data write time period Sd1, a second data write time period Sd2, and a third data write time period Sd3 set sequentially.

[0212] In the first initialization phase S1, RSTA provides a low voltage signal, M8 and M9 are turned on, and I1 provides the initial voltage Vinit to the anodes of N1 and O1;

[0213] During the first reset phase SR1, DL provides the reset data voltage Vdataf;

[0214] During the first reset time period, Sf1 and SX1 provide a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1.

[0215] During the second reset period, Sf2 and SX2 provide a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2.

[0216] During the third reset time period, Sf3 and SX3 provide a low voltage signal, MX3 is turned on, and DL provides the reset data voltage Vdataf to DT3.

[0217] By operating in the first reset phase SR1, before the first data write phase SW1, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This reduces the coupling interference between different signals on the data lines when DL provides Vdatar1 to DT1, DL provides Vdatag1 to DT2, and DL provides Vdatab1 to DT3 in the first data write phase SW1.

[0218] During the first data write time period Sd1, DL provides the first red data voltage Vdatar1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar1 to DT1;

[0219] During the second data writing period Sd2, DL provides the first green data voltage Vdatag1, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatag1 to DT2.

[0220] During the third data write period Sd3, DL provides the first blue data voltage Vdatab3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatab1 to DT3.

[0221] In the first compensation stage SC1, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0222] The second reset phase SR2 includes a fourth reset time period Sf4, a fifth reset time period Sf5, and a sixth reset time period Sf6 set sequentially; the second data write phase SW2 includes a fourth data write time period Sd4, a fifth data write time period Sd5, and a sixth data write time period Sd6 set sequentially.

[0223] In the second initialization phase S2, RSTA provides a low voltage signal, M8 and M9 are turned on, and I1 provides the initial voltage Vinit to the anodes of N1 and O1;

[0224] During the second reset phase SR2, DL provides the reset data voltage Vdataf;

[0225] During the fourth reset time period Sf4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1;

[0226] During the fifth reset time period Sf5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2;

[0227] During the sixth reset time period Sf6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides the reset data voltage Vdataf.

[0228] The second reset phase SR2 is set before the second data write phase SW2 so that the data voltage on each data voltage access terminal in the first data write phase SW1 will not affect the data voltage written on each data voltage access terminal in the second data write phase SW2, and reduce the coupling of signals written first on the data line with other signals, ensuring the accuracy of the written signal and the correctness of the display.

[0229] By operating in the second reset phase SR2, before the second data write phase SW2, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar2 to DT1, Vdatag2 to DT2, and Vdatab2 to DT3 in the second data write phase SW2.

[0230] During the fourth data write period Sd4, DL provides two red data voltages Vdatar2, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar2 to DT1;

[0231] During the fifth data write period Sd5, DL provides the second green data voltage Vdatag2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatag2 to DT2.

[0232] During the sixth data write period Sd6, DL provides the second blue data voltage Vdatab2, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatab2 to DT3.

[0233] In the second compensation stage SC2, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0234] In at least one embodiment shown in Figure 6B of this disclosure, during operation, in the first display cycle, in the first data writing phase, Vdatar1 is written to DT1, Vdatag1 is written to DT2, and Vdatab1 is written to DT3; in the second reset phase SR2, Vdataf is written to DT1, DT2, and DT3. The second reset phase SR2 is set before the second data writing phase SW2 so that the previous frame data voltage retained on the data line and data voltage access terminal in the first data writing phase SW1 will not affect the writing of the next frame data voltage, reducing the coupling of the written data voltage with other signals, and ensuring the accuracy of the written data voltage and the correctness of the display.

[0235] As shown in Figure 10, when at least one embodiment shown in Figure 6A is in operation, and the structure of the pixel circuit is as shown in Figure 3, the first display cycle may include a first first control stage S11, a first second control stage S12, a first reset stage SR1, a first data writing stage SW1, a first compensation stage SC1, and a first light emission stage SE1, which are set sequentially; the second display cycle may include a second first control stage S21, a second second control stage S22, a second reset stage SR2, a second data writing stage SW2, a second compensation stage SC2, and a second light emission stage SE2, which are set sequentially.

[0236] The first first control phase S11 includes a first first write phase and a first first set phase SZ11 set sequentially; the first second control phase S12 includes a first second write phase and a second set phase SZ12 set sequentially.

[0237] The first first write phase includes the first first write time period t11, the second first write time period t21, and the third first write time period t31;

[0238] The first second write phase includes the first second write time period t12, the second second write time period t22, and the third second write time period t32;

[0239] During the first write time period t11, DL provides the first control data voltage Db1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Db1 to DT1.

[0240] During the second first write time period t21, DL provides the second first control data voltage Db2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Db2 to DT2;

[0241] During the third first write time period t31, DL provides the third first control data voltage Db3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Db3 to DT3.

[0242] In the first first setting phase SZ11, RSTB provides a low voltage signal to control whether M2 in the first red pixel circuit R1 is turned on according to Db1; to control whether M2 in the second red pixel circuit R2 is turned on according to Db2; and to control whether M2 in the third red pixel circuit R3 is turned on according to Db3.

[0243] During the first second write time period t12, DL provides the first second control data voltage Da1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Da1 to DT1;

[0244] During the second write time period t22, DL provides the second control data voltage Da2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Da2 to DT2;

[0245] During the third second write time period t32, DL provides the third second control data voltage Da3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Da3 to DT3;

[0246] During the first second setting phase SZ12, RSTA provides a low voltage signal to control whether M4 in the first red pixel circuit R1 is turned on according to Da1; to control whether M4 in the second red pixel circuit R2 is turned on according to Da2; and to control whether M4 in the third red pixel circuit R3 is turned on according to Da3.

[0247] The first reset phase SR1 includes a first reset time period Sf1, a second reset time period Sf2, and a third reset time period Sf3 set sequentially; the first data write phase SW1 includes a first data write time period Sd1, a second data write time period Sd2, and a third data write time period Sd3 set sequentially.

[0248] During the first reset phase SR1, DL provides the reset data voltage Vdataf;

[0249] During the first reset time period, Sf1 and SX1 provide a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1.

[0250] During the second reset period, Sf2 and SX2 provide a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2.

[0251] During the third reset time period, Sf3 and SX3 provide a low voltage signal, MX3 is turned on, and DL provides the reset data voltage Vdataf to DT3.

[0252] By operating in the first reset phase SR1, before the first data write phase SW1, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar1 to DT1, DL provides Vdatar2 to DT2, and DL provides Vdatar3 to DT3 in the first data write phase SW1.

[0253] During the first data write time period Sd1, DL provides the first red data voltage Vdatar1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar1 to DT1;

[0254] During the second data write period Sd2, DL provides the second red data voltage Vdatar2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatar2 to DT2;

[0255] During the third data write period Sd3, DL provides the third red data voltage Vdatar3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatar3 to DT3.

[0256] In the first compensation stage SC1, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0257] The second first control stage S21 includes a second first write stage and a second first set stage SZ21 set sequentially; the second second control stage S22 includes a second second write stage and a second second set stage SZ22 set sequentially.

[0258] The second first write phase includes the fourth first write time period t41, the fifth first write time period t51, and the sixth first write time period t61;

[0259] The second second write time period includes the fourth second write time period t42, the fifth second write time period t52, and the sixth second write time period t62;

[0260] During the fourth first write time period t41, DL provides the fourth first control data voltage Db4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Db4 to DT1;

[0261] During the fifth first write time period t51, DL provides the fifth first control data voltage Db5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Db5 to DT2;

[0262] During the sixth first write time period t61, DL provides the sixth first control data voltage Db6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Db6 to DT3;

[0263] In the second first setting phase SZ21, RSTB provides a low voltage signal to control whether M2 in the first red pixel circuit R1 is turned on according to Db4; to control whether M2 in the second red pixel circuit R2 is turned on according to Db5; and to control whether M2 in the third red pixel circuit R3 is turned on according to Db6.

[0264] During the fourth second write time period t42, DL provides the fourth second control data voltage Da4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Da4 to DT1;

[0265] During the fifth second write time period t52, DL provides the fifth second control data voltage Da5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Da5 to DT2;

[0266] During the sixth second write time period t62, DL provides the sixth second control data voltage Da6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Da6 to DT3;

[0267] In the second second setting phase SZ22, RSTA provides a low voltage signal, and according to Da4, controls whether M4 in the first red pixel circuit R1 is turned on; according to Da5, controls whether M4 in the second red pixel circuit R2 is turned on; according to Da6, controls whether M4 in the third red pixel circuit R3 is turned on.

[0268] During the second reset phase SR2, DL provides the reset data voltage Vdataf;

[0269] During the fourth reset time period Sf4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1;

[0270] During the fifth reset time period Sf5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2;

[0271] During the sixth reset time period Sf6, SX3 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT3;

[0272] The second reset phase SR2 is set before the second data write phase SW2 so that the data voltage on each data voltage access terminal in the first data write phase SW1 will not affect the data voltage written on each data voltage access terminal in the second data write phase SW2, and reduce the coupling of signals written first on the data line with other signals, ensuring the accuracy of the written signal and the correctness of the display.

[0273] By operating in the second reset phase SR2, before the second data write phase SW2, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar4 to DT1, Vdatar5 to DT2 and Vdatar6 to DT3 in the second data write phase SW2.

[0274] During the fourth data write period Sd4, DL provides the fourth red data voltage Vdatar4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar4 to DT1;

[0275] During the fifth data write period Sd5, DL provides the fifth red data voltage Vdatar5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatar5 to DT2;

[0276] During the sixth data write period Sd6, DL provides the sixth red data voltage Vdatar6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatar6 to DT3.

[0277] In the second compensation stage SC2, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0278] As shown in Figure 10, at least one embodiment shown in Figure 6A includes a first reset stage SR1 and a second reset stage SR2 during operation. Since each second control data voltage is a maximum or minimum value, without a reset stage, the display data voltage written in the first data writing stage SW1 and the second data writing stage SW2 would be significantly affected. Therefore, at least one embodiment of this disclosure includes a first reset stage SR1 and a second reset stage SR2 to ensure that the second control data voltage does not affect the display data voltage written in each data writing stage. Furthermore, by setting a reset stage, differences in the written signal caused by discrepancies between calibration and actual display can be avoided, preventing the formation of regular brightness and darkness display anomalies. As shown in Figure 11, when at least one embodiment shown in Figure 6B is in operation, and the structure of the pixel circuit is as shown in Figure 3, the first display cycle may include a first first control stage S11, a first second control stage S12, a first reset stage SR1, a first data writing stage SW1, a first compensation stage SC1, and a first light emission stage SE1, which are set sequentially; the second display cycle may include a second first control stage S21, a second second control stage S22, a second reset stage SR2, a second data writing stage SW2, a second compensation stage SC2, and a second light emission stage SE2, which are set sequentially.

[0279] The first first control phase S11 includes a first first write phase and a first first set phase SZ11 set sequentially; the first second control phase S12 includes a first second write phase and a second set phase SZ12 set sequentially.

[0280] The first first write phase includes the first first write time period t11, the second first write time period t21, and the third first write time period t31;

[0281] The first second write phase includes the first second write time period t12, the second second write time period t22, and the third second write time period t32;

[0282] During the first write time period t11, DL provides the first control data voltage Db1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Db1 to DT1.

[0283] During the second first write time period t21, DL provides the second first control data voltage Db2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Db2 to DT2;

[0284] During the third first write time period t31, DL provides the third first control data voltage Db3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Db3 to DT3.

[0285] In the first first setting phase SZ11, RSTB provides a low voltage signal to control whether M2 in the first red pixel circuit R1 is turned on according to Db1; to control whether M2 in the second red pixel circuit R2 is turned on according to Db2; and to control whether M2 in the third red pixel circuit R3 is turned on according to Db3.

[0286] During the first second write time period t12, DL provides the first second control data voltage Da1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Da1 to DT1;

[0287] During the second write time period t22, DL provides the second control data voltage Da2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Da2 to DT2;

[0288] During the third second write time period t32, DL provides the third second control data voltage Da3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Da3 to DT3;

[0289] During the first second setting phase SZ12, RSTA provides a low voltage signal to control whether M4 in the first red pixel circuit R1 is turned on according to Da1; to control whether M4 in the second red pixel circuit R2 is turned on according to Da2; and to control whether M4 in the third red pixel circuit R3 is turned on according to Da3.

[0290] The first reset phase SR1 includes a first reset time period Sf1, a second reset time period Sf2, and a third reset time period Sf3 set sequentially; the first data write phase SW1 includes a first data write time period Sd1, a second data write time period Sd2, and a third data write time period Sd3 set sequentially.

[0291] During the first reset phase SR1, DL provides the reset data voltage Vdataf;

[0292] During the first reset time period, Sf1 and SX1 provide a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1.

[0293] During the second reset period, Sf2 and SX2 provide a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2.

[0294] During the third reset time period, Sf3 and SX3 provide a low voltage signal, MX3 is turned on, and DL provides the reset data voltage Vdataf to DT3.

[0295] By operating in the first reset phase SR1, before the first data write phase SW1, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar1 to DT1, DL provides Vdatar2 to DT2, and DL provides Vdatar3 to DT3 in the first data write phase SW1.

[0296] During the first data write time period Sd1, DL provides the first red data voltage Vdatar1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar1 to DT1;

[0297] During the second data writing period Sd2, DL provides the first green data voltage Vdatag1, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatag1 to DT2.

[0298] During the third data write period Sd3, DL provides the first blue data voltage Vdatab1, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatab1 to DT3;

[0299] In the first compensation stage SC1, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0300] The second first control stage S21 includes a second first write stage and a second first set stage SZ21 set sequentially; the second second control stage S22 includes a second second write stage and a second second set stage SZ22 set sequentially.

[0301] The second first write phase includes the fourth first write time period t41, the fifth first write time period t51, and the sixth first write time period t61;

[0302] The second second write time period includes the fourth second write time period t42, the fifth second write time period t52, and the sixth second write time period t62;

[0303] During the fourth first write time period t41, DL provides the fourth first control data voltage Db4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Db4 to DT1;

[0304] During the fifth first write time period t51, DL provides the fifth first control data voltage Db5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Db5 to DT2;

[0305] During the sixth first write time period t61, DL provides the sixth first control data voltage Db6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Db6 to DT3;

[0306] In the second first setting phase SZ21, RSTB provides a low voltage signal to control whether M2 in the first red pixel circuit R1 is turned on according to Db4; to control whether M2 in the second red pixel circuit R2 is turned on according to Db5; and to control whether M2 in the third red pixel circuit R3 is turned on according to Db6.

[0307] During the fourth second write time period t42, DL provides the fourth second control data voltage Da4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Da4 to DT1;

[0308] During the fifth second write time period t52, DL provides the fifth second control data voltage Da5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Da5 to DT2;

[0309] During the sixth second write time period t62, DL provides the sixth second control data voltage Da6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Da6 to DT3;

[0310] In the second second setting phase SZ22, RSTA provides a low voltage signal, and according to Da4, controls whether M4 in the first red pixel circuit R1 is turned on; according to Da5, controls whether M4 in the second red pixel circuit R2 is turned on; according to Da6, controls whether M4 in the third red pixel circuit R3 is turned on.

[0311] During the second reset phase SR2, DL provides the reset data voltage Vdataf;

[0312] During the fourth reset time period Sf4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1;

[0313] During the fifth reset time period Sf5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2;

[0314] During the sixth reset time period Sf6, SX3 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT3;

[0315] The second reset phase SR2 is set before the second data write phase SW2 so that the data voltage on each data voltage access terminal in the first data write phase SW1 will not affect the data voltage written on each data voltage access terminal in the second data write phase SW2, and reduce the coupling of signals written first on the data line with other signals, ensuring the accuracy of the written signal and the correctness of the display.

[0316] By operating in the second reset phase SR2, before the second data write phase SW2, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar4 to DT1, Vdatar5 to DT2 and Vdatar6 to DT3 in the second data write phase SW2.

[0317] During the fourth data write period Sd4, DL provides the second red data voltage Vdatar2, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar2 to DT1;

[0318] During the fifth data write period Sd5, DL provides the second green data voltage Vdatag2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatag2 to DT2.

[0319] During the sixth data write period Sd6, DL provides the second blue data voltage Vdatab2, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatab2 to DT3.

[0320] In the second compensation stage SC2, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0321] As shown in Figure 11, at least one embodiment shown in Figure 6B includes a first reset stage SR1 and a second reset stage SR2 during operation. Since each second control data voltage is a maximum or minimum value, without a reset stage, the display data voltage written in the first data writing stage SW1 and the second data writing stage SW2 would be significantly affected. Therefore, at least one embodiment of this disclosure includes a first reset stage SR1 and a second reset stage SR2 to ensure that the second control data voltage does not affect the display data voltage written in each data writing stage. Furthermore, by setting a reset stage, differences in the written signal caused by discrepancies between calibration and actual display can be avoided, preventing the formation of regular brightness and darkness display anomalies.

[0322] As shown in Figure 12, when at least one embodiment shown in Figure 6B is in operation, and the structure of the pixel circuit is as shown in Figure 3, the first display cycle may include a first first control stage S11, a first second control stage S12, a first reset stage SR1, a first data writing stage SW1, and a first compensation stage SC1 set sequentially; the second display cycle may include a second first control stage S21, a second second control stage S22, a second reset stage SR2, a second data writing stage SW2, and a second compensation stage SC2 set sequentially.

[0323] The first first control phase S11 includes a first first write phase and a first first set phase SZ11 set sequentially; the first second control phase S12 includes a first second write phase and a second set phase SZ12 set sequentially.

[0324] The first first write phase includes the first first write time period t11, the second first write time period t21, and the third first write time period t31;

[0325] The first second write phase includes the first second write time period t12, the second second write time period t22, and the third second write time period t32;

[0326] During the first write time period t11, DL provides the first control data voltage Db1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Db1 to DT1.

[0327] During the second first write time period t21, DL provides the second first control data voltage Db2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Db2 to DT2;

[0328] During the third first write time period t31, DL provides the third first control data voltage Db3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Db3 to DT3.

[0329] In the first first setting phase SZ11, RSTB provides a low voltage signal to control whether M2 in the first red pixel circuit R1 is turned on according to Db1; to control whether M2 in the second red pixel circuit R2 is turned on according to Db2; and to control whether M2 in the third red pixel circuit R3 is turned on according to Db3.

[0330] During the first second write time period t12, DL provides the first second control data voltage Da1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Da1 to DT1;

[0331] During the second write time period t22, DL provides the second control data voltage Da2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Da2 to DT2;

[0332] During the third second write time period t32, DL provides the third second control data voltage Da3, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Da3 to DT3;

[0333] During the first second setting phase SZ12, RSTA provides a low voltage signal to control whether M4 in the first red pixel circuit R1 is turned on according to Da1; to control whether M4 in the second red pixel circuit R2 is turned on according to Da2; and to control whether M4 in the third red pixel circuit R3 is turned on according to Da3.

[0334] The first data writing phase SW1 includes the first data writing time period Sd1, the second data writing time period Sd2, and the third data writing time period Sd3, which are set sequentially.

[0335] In the first reset phase SR1, DL provides the reset data voltage Vdataf; SX1 provides a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1; SX2 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2; SX3 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT3.

[0336] By operating in the first reset phase SR1, before the first data write phase SW1, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar1 to DT1, DL provides Vdatar2 to DT2, and DL provides Vdatar3 to DT3 in the first data write phase SW1.

[0337] During the first data write time period Sd1, DL provides the first red data voltage Vdatar1, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar1 to DT1;

[0338] During the second data writing period Sd2, DL provides the first green data voltage Vdatag1, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatag1 to DT2.

[0339] During the third data write period Sd3, DL provides the first blue data voltage Vdatab1, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatab1 to DT3;

[0340] In the first compensation stage SC1, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0341] The second first control stage S21 includes a second first write stage and a second first set stage SZ21 set sequentially; the second second control stage S22 includes a second second write stage and a second second set stage SZ22 set sequentially.

[0342] The second first write phase includes the fourth first write time period t41, the fifth first write time period t51, and the sixth first write time period t61;

[0343] The second second write time period includes the fourth second write time period t42, the fifth second write time period t52, and the sixth second write time period t62;

[0344] During the fourth first write time period t41, DL provides the fourth first control data voltage Db4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Db4 to DT1;

[0345] During the fifth first write time period t51, DL provides the fifth first control data voltage Db5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Db5 to DT2;

[0346] During the sixth first write time period t61, DL provides the sixth first control data voltage Db6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Db6 to DT3;

[0347] In the second first setting phase SZ21, RSTB provides a low voltage signal to control whether M2 in the first red pixel circuit R1 is turned on according to Db4; to control whether M2 in the second red pixel circuit R2 is turned on according to Db5; and to control whether M2 in the third red pixel circuit R3 is turned on according to Db6.

[0348] During the fourth second write time period t42, DL provides the fourth second control data voltage Da4, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Da4 to DT1;

[0349] During the fifth second write time period t52, DL provides the fifth second control data voltage Da5, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Da5 to DT2;

[0350] During the sixth second write time period t62, DL provides the sixth second control data voltage Da6, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Da6 to DT3;

[0351] In the second second setting phase SZ22, RSTA provides a low voltage signal, and according to Da4, controls whether M4 in the first red pixel circuit R1 is turned on; according to Da5, controls whether M4 in the second red pixel circuit R2 is turned on; according to Da6, controls whether M4 in the third red pixel circuit R3 is turned on.

[0352] In the second reset phase SR2, DL provides the reset data voltage Vdataf; SX1 provides a low voltage signal, MX1 is turned on, and DL provides the reset data voltage Vdataf to DT1; SX2 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT2; SX3 provides a low voltage signal, MX2 is turned on, and DL provides the reset data voltage Vdataf to DT3.

[0353] The second reset phase SR2 is set before the second data write phase SW2 so that the data voltage on each data voltage access terminal in the first data write phase SW1 will not affect the data voltage written on each data voltage access terminal in the second data write phase SW2, and reduce the coupling of signals written first on the data line with other signals, ensuring the accuracy of the written signal and the correctness of the display.

[0354] By operating in the second reset phase SR2, before the second data write phase SW2, all signals on the data lines, as well as the signals on DT1, DT2 and DT3, are Vdataf. This will reduce the coupling interference between different signals on the data lines when DL provides Vdatar4 to DT1, Vdatar5 to DT2 and Vdatar6 to DT3 in the second data write phase SW2.

[0355] During the fourth data write period Sd4, DL provides the second red data voltage Vdatar2, SX1 provides a low voltage signal, MX1 is turned on, and DL provides Vdatar2 to DT1;

[0356] During the fifth data write period Sd5, DL provides the second green data voltage Vdatag2, SX2 provides a low voltage signal, MX2 is turned on, and DL provides Vdatag2 to DT2.

[0357] During the sixth data write period Sd6, DL provides the second blue data voltage Vdatab2, SX3 provides a low voltage signal, MX3 is turned on, and DL provides Vdatab2 to DT3.

[0358] In the second compensation stage SC2, GT provides a low voltage signal, M1 and M10 in the pixel circuit are turned on, and the data voltages provided by DT1, DT2 and DT3 are written into the first node of each pixel circuit respectively; N1 and N3 are connected to perform threshold voltage compensation.

[0359] As shown in Figure 12, at least one embodiment shown in Figure 6B includes a first reset stage SR1 and a second reset stage SR2 during operation. Since each second control data voltage is a maximum or minimum value, without a reset stage, the display data voltage written in the first data writing stage SW1 and the second data writing stage SW2 would be significantly affected. Therefore, at least one embodiment of this disclosure includes a first reset stage SR1 and a second reset stage SR2 to ensure that the second control data voltage does not affect the display data voltage written in each data writing stage. Furthermore, by setting a reset stage, differences in the written signal caused by discrepancies between calibration and actual display can be avoided, preventing the formation of regular brightness and darkness display anomalies.

[0360] As shown in Figure 12, to reduce the duration of a display cycle, in the first reset phase R1 and the second reset phase R2, SX1, SX2, and SX3 simultaneously provide low-voltage signals to write Vdataf to DT1, DT2, and DT3 simultaneously. This reduces the time it takes for each multiplexed transistor to turn on sequentially, reduces the interval between the falling edge of the signal provided by SX1 and the rising edge of the signal provided by SX2, and reduces the interval between the falling edge of the signal provided by SX2 and the rising edge of the signal provided by SX3. Similarly, for the 7T1C pixel circuit shown in Figure 5, the duration of the display cycle can be reduced by compressing the duration of the reset phase, thereby reducing the overall scan time.

[0361] When the pixel circuit has a 7T1C structure, the duration of the display cycle can be reduced by compressing the duration of the reset phase, thereby reducing the overall scanning time.

[0362] As shown in Figure 13, based on the timing diagram shown in Figure 12, SR1 and Sd1 can be merged to reduce the duration of the display cycle and reduce the interval between the falling edge and the rising edge of the signal provided by SX1.

[0363] In at least one embodiment of the pixel circuit shown in Figure 3, when M5 is turned on, the on and off of M6 can be controlled by the display control signal provided by HF to achieve light emission with a fixed duty cycle in PWM (pulse width modulation) mode.

[0364] When the driving method described in at least one embodiment of this disclosure is applied to the 7T1C pixel circuit, the problem of uneven display caused by coupling between data lines can be reduced;

[0365] When the driving method described in at least one embodiment of this disclosure is applied to the 11T1C pixel circuit, the problem of uneven column display caused by different mode selections before and after correction can be avoided.

[0366] The driving method described in at least one embodiment of this disclosure further includes:

[0367] During at least a portion of the time period between two display cycles, the display control terminal provides a valid display control signal.

[0368] In practical implementation, the display control terminal can provide an effective display control signal for at least a portion of the time period between two display cycles. This display control signal is activated independently between the two display cycles. When the scan time is sufficient, the timing shown in Figure 14 can be selected. The timing of the display control signal provided by HF is independently adjustable with the scan time of each line, eliminating the risk of potential signal interference. It offers the greatest flexibility and applicability. However, adjusting the duty cycle of the display control signal provided by HF requires increasing the overall scan time.

[0369] As shown in Figure 14, SA1 is the first row scan time, SA2 is the second row scan time, and a display control time period SH is set between the first row scan time SA1 and the second row scan time SA2.

[0370] During the display control period, HF provides a low voltage signal.

[0371] In practice, when the display control terminal is activated (generally every n rows) for at least a portion of the time between two display cycles (which can be the scan time of one row), the total screen scan time will be increased. For a display product with M columns and N rows, the scan time of one row is H, the activation time of HF is thf, and the total screen scan time is N×H+N×thf / n, where n and thf together determine the duty cycle of the display control signal provided by HF. Setting a larger duty cycle will increase the total screen scan time, which may affect the implementation of a high refresh rate. Here, N, M, and n are all positive integers.

[0372] To improve the above problems, the effective time period of the display control signal can be placed in a single scan time and can be adjusted within a certain range, thereby reducing the scan time and ensuring that a high refresh rate can be achieved.

[0373] The driving method described in at least one embodiment of this disclosure further includes:

[0374] During the first setting phase, the display control terminal provides a valid display control signal.

[0375] In practical implementation, the display control signal provided by HF and the first reset control signal provided by RSTB can be set to be enabled simultaneously. That is, during the first setting phase, RSTB provides a valid first reset control signal and the display control terminal provides a valid display control signal, so that the display control signal can be set without increasing the overall scan time.

[0376] As shown in Figure 15, SA1 represents the first row scan time, and SA2 represents the second row scan time. During the first set phase SZ11 and the second set phase SZ21, the display control terminal HF provides a low voltage signal.

[0377] The driving method described in at least one embodiment of this disclosure further includes:

[0378] In the first control phase, the display control terminal provides effective display control signals.

[0379] In practical implementation, during the first control phase, the display control signal provided by the HF terminal can be made effective, allowing adjustment of the duty cycle of the display control signal without increasing the overall scan time. When a shorter overall scan time is required, the timing shown in Figure 15 can be used.

[0380] As shown in Figure 16, SA1 represents the first row scan time, and SA2 represents the second row scan time. In the first control phase S11 and the second control phase S21, HF provides a low voltage signal.

[0381] In Figure 16, the effective time period of the display control signal provided by HF may include a first control phase. At the first falling edge of the display control signal provided by HF, the light-emitting control terminal EM provides a high voltage signal. The second falling edge of the display control signal provided by HF is set before the effective time period of the second reset control signal provided by SA1 and RSTA (that is, the time period during which RSTA outputs a low voltage signal) so as to adjust the duty cycle of the display control signal provided by HF.

[0382] The display panel described in this embodiment includes multiple pixel circuits, each pixel circuit including a data voltage input terminal; the display panel also includes a data voltage supply module; the display time of the display panel includes multiple display cycles; each display cycle includes a reset phase and a data writing phase set sequentially.

[0383] The data voltage providing module is used to provide a reset data voltage to the data voltage access terminal during at least a portion of the time period included in the reset phase, and to provide a corresponding display data voltage to the data voltage access terminal during at least a portion of the time period included in the data writing phase.

[0384] In at least one embodiment of this disclosure, a reset phase for signal reset is provided before the data writing phase. During at least a portion of the time period included in the reset phase, a reset data voltage is provided to the pixel circuits included in the display panel through the data voltage access terminal. Then, during at least a portion of the time period included in the data writing phase, a corresponding display data voltage is provided to the pixel circuits through the data voltage access terminal. This eliminates coupling caused by excessive differences in signals from the previous frame or the previous data writing phase, avoids signal coupling between adjacent data lines, and prevents uneven column display on the display screen, especially uneven column display before and after correction, thereby increasing the accuracy of the final display.

[0385] In at least one embodiment of this disclosure, the data voltage providing module is configured to control the reset data voltage provided to the data voltage access terminals of the plurality of pixel circuits to be the same during at least a portion of the time period included in the reset phase.

[0386] In practice, during at least a portion of the time period included in the reset phase, the reset data voltage to all pixel circuits included in the display panel is controlled to be the same to improve display uniformity.

[0387] In at least one embodiment of this disclosure, the data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal included in N pixel circuits, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; the reset phase includes N reset time periods set sequentially;

[0388] The data line is used to provide the reset data voltage during the reset phase;

[0389] The data voltage providing circuit is used, under the control of the nth data multiplexing control signal, during the nth reset time period included in the reset phase, to control the connection between the data line and the data voltage access terminal in the nth pixel circuit, and to write the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0390] In at least one embodiment of this disclosure, the data voltage providing module includes a plurality of data voltage providing circuits; the data voltage providing circuits are electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal included in N pixel circuits, respectively, and are used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0391] The data line is used to provide the reset data voltage during the reset phase;

[0392] The data voltage providing circuit is used during the reset phase to control the connection between the data line and the data voltage access terminal in the nth pixel circuit under the control of the nth data multiplexing control signal, and to write the reset data voltage into the data voltage access terminal in the nth pixel circuit.

[0393] In at least one embodiment of this disclosure, the data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal included in N pixel circuits, respectively, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; the display cycle includes a first multiplexing time period; the data writing stage includes N data writing time periods set sequentially; the first multiplexing time period includes the reset stage and the first data writing time period included in the data writing stage; the driving method includes:

[0394] During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal of the nth pixel circuit.

[0395] During the first multiplexing time period, the data voltage providing circuit, under the control of the first data multiplexing control signal provided by the first data multiplexing terminal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits.

[0396] During the nth data writing time period included in the data writing phase, the data line provides the nth display data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits, and writes the nth display data voltage into the nth pixel circuit.

[0397] In at least one embodiment of this disclosure, the pixel circuit includes a data writing circuit, a first writing control circuit, and a second writing control circuit. The data writing circuit is electrically connected to a scanning end and a data voltage access end, respectively, and is used to receive a display data voltage provided by the data voltage access end under the control of a scanning signal provided by the scanning end. The first writing control circuit is electrically connected to a first reset control end, the data voltage access end, a light emission control end, and a light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the light emission control end according to a first control data voltage provided by the data voltage access end under the control of a first reset control signal provided by the first reset control end. The second writing control circuit is electrically connected to a second reset control end, the data voltage access end, a display control end, and a light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the display control end according to a second control data voltage provided by the data voltage access end under the control of a second reset control signal provided by the second reset control end.

[0398] The display cycle includes a first control phase and a second control phase set before the reset phase. The first control phase includes a first write phase and a first set phase set sequentially. The second control phase includes a second write phase and a second set phase set sequentially. The first write phase includes N first write time periods set sequentially. The second write phase includes N second write time periods set sequentially.

[0399] The data line is used to provide the nth first control data voltage during the nth first write time period. The data voltage providing circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit of the N pixel circuits during the nth first write time period under the control of the nth data multiplexing control signal, so as to write the nth first control data voltage into the first write control circuit in the nth pixel circuit.

[0400] The first write control circuit in each pixel circuit is used to control the connection or disconnection between the light emission control node and the light emission control terminal according to the first control data voltage received during the first setting phase.

[0401] The data line is used to provide the nth second control data voltage during the nth second write time period. The data voltage providing circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits during the nth second write time period under the control of the nth data multiplexing control signal, so as to write the nth second control data voltage into the second write control circuit in the nth pixel circuit.

[0402] The second write control circuit in each pixel circuit is used to control the connection or disconnection between the light-emitting control node and the display control terminal according to the second control data voltage received during the second setting phase.

[0403] In at least one embodiment of this disclosure, the display control terminal is used to provide an effective display control signal for at least a portion of the time period between two display cycles.

[0404] In at least one embodiment of this disclosure, the display control terminal is used to provide an effective display control signal during the first setting phase.

[0405] In at least one embodiment of this disclosure, the display control terminal is used to provide an effective display control signal during a first control phase.

[0406] The display device described in this disclosure includes the display panel described above.

[0407] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving method applied to a display panel, the display panel including multiple pixel circuits, each pixel circuit including a data voltage input terminal; the display time of the display panel including multiple display cycles; each display cycle including a reset phase and a data writing phase set sequentially; the driving method comprising: During at least a portion of the time period included in the reset phase, a reset data voltage is provided to the data voltage access terminal; During at least a portion of the time period included in the data writing phase, a corresponding display data voltage is provided to the data voltage access terminal.

2. The driving method as described in claim 1, wherein, During at least a portion of the time period included in the reset phase, the same reset data voltage is provided to the data voltage access terminals of the plurality of pixel circuits.

3. The driving method as described in claim 1, wherein, The display panel includes a data voltage supply module, which includes multiple data voltage supply circuits. Each data voltage supply circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal in one of the N pixel circuits. Under the control of a data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The reset phase includes N reset time periods set sequentially; the driving method includes: During the reset phase, the data line provides the reset data voltage; During the nth reset time period included in the reset phase, the data voltage supply circuit, under the control of the nth data multiplexing control signal, controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal in the nth pixel circuit.

4. The driving method as described in claim 1, wherein, The display panel includes a data voltage supply module, which includes multiple data voltage supply circuits. Each data voltage supply circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal of N pixel circuits. Under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit in the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N; the driving method includes: During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal in the nth pixel circuit.

5. The driving method as described in claim 1, wherein, The display panel includes a data voltage supply module, which includes multiple data voltage supply circuits. Each data voltage supply circuit is electrically connected to N data multiplexing terminals, a data line, and data voltage access terminals of N pixel circuits. Under the control of a data multiplexing control signal provided by the nth data multiplexing terminal, the circuit controls the connection or disconnection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits. N is an integer greater than 1, and n is a positive integer less than or equal to N. The display cycle includes a first multiplexing time period. The data writing phase includes N sequentially set data writing time periods. The first multiplexing time period includes the reset phase and the first data writing time period included in the data writing phase. The driving method includes: During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal of the nth pixel circuit. During the first multiplexing time period, the data voltage providing circuit, under the control of the first data multiplexing control signal provided by the first data multiplexing terminal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits. During the nth data writing time period included in the data writing phase, the data line provides the nth display data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits, and writes the nth display data voltage into the nth pixel circuit.

6. The driving method according to any one of claims 3 to 5, wherein, The pixel circuit includes a data writing circuit, a first writing control circuit, and a second writing control circuit. The data writing circuit is electrically connected to the scanning end and the data voltage access end, respectively, and is used to receive the display data voltage provided by the data voltage access end under the control of the scanning signal provided by the scanning end. The first writing control circuit is electrically connected to the first reset control end, the data voltage access end, the light emission control end, and the light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the light emission control end according to the first control data voltage provided by the data voltage access end under the control of the first reset control signal provided by the first reset control end. The second writing control circuit is connected to the second reset control end, the data voltage access end, the data voltage access end, and the light emission control node, respectively. A voltage input terminal, a display control terminal, and a light-emitting control node are electrically connected, used to control the connection or disconnection between the light-emitting control node and the display control terminal according to the second control data voltage provided by the data voltage input terminal under the control of the second reset control signal provided by the second reset control terminal; the display cycle includes a first control phase and a second control phase set before the reset phase, the first control phase includes a first write phase and a first set phase set sequentially, and the second control phase includes a second write phase and a second set phase set sequentially; the first write phase includes N first write time periods set sequentially, and the second write phase includes N second write time periods set sequentially; the driving method includes: During the nth first write time period, the data line provides the nth first control data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the data line to connect with the data voltage access terminal in the nth pixel circuit among the N pixel circuits, and writes the nth first control data voltage into the first write control circuit of the nth pixel circuit. During the first setting phase, the first write control circuit in each pixel circuit controls the connection or disconnection between the light emission control node and the light emission control terminal according to the first control data voltage received. During the nth second write time period, the data line provides the nth second control data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit of the N pixel circuits, thus writing the nth second control data voltage into the... The second write control circuit in the nth pixel circuit; During the second setting phase, the second write control circuit in each pixel circuit controls the connection or disconnection between the light-emitting control node and the display control terminal according to the received second control data voltage.

7. The driving method as described in claim 6, wherein, Also includes: During at least a portion of the time period between two display cycles, the display control terminal provides a valid display control signal.

8. The driving method as described in claim 6, wherein, Also includes: During the first setting phase, the display control terminal provides a valid display control signal.

9. The driving method as described in claim 6, wherein, Also includes: In the first control phase, the display control terminal provides effective display control signals.

10. A display panel, comprising a plurality of pixel circuits, each pixel circuit including a data voltage input terminal; the display panel further comprising a data voltage supply module; the display time of the display panel comprising a plurality of display cycles; the display cycle comprising a reset phase and a data writing phase configured sequentially. The data voltage providing module is used to provide a reset data voltage to the data voltage access terminal during at least a portion of the time period included in the reset phase, and to provide a corresponding display data voltage to the data voltage access terminal during at least a portion of the time period included in the data writing phase.

11. The display panel as claimed in claim 10, wherein, The data voltage providing module is used to control the reset data voltage provided to the data voltage access terminals of the plurality of pixel circuits to be the same during at least a portion of the time period included in the reset phase.

12. The display panel as claimed in claim 10, wherein, The data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal included in the N pixel circuits, respectively, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; the reset phase includes N reset time periods set sequentially; The data line is used to provide the reset data voltage during the reset phase; The data voltage providing circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit under the control of the nth data multiplexing control signal during the nth reset time period included in the reset phase, and to write the reset data voltage into the data voltage access terminal in the nth pixel circuit.

13. The display panel as claimed in claim 10, wherein, The data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal included in N pixel circuits, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; The data line is used to provide the reset data voltage during the reset phase; The data voltage providing circuit is used during the reset phase to control the connection between the data line and the data voltage access terminal in the nth pixel circuit under the control of the nth data multiplexing control signal, and to write the reset data voltage into the data voltage access terminal in the nth pixel circuit.

14. The display panel as claimed in claim 10, wherein, The data voltage providing module includes multiple data voltage providing circuits; each data voltage providing circuit is electrically connected to N data multiplexing terminals, a data line, and a data voltage access terminal included in N pixel circuits, and is used to control the connection or disconnection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits under the control of the nth data multiplexing control signal provided by the nth data multiplexing terminal; N is an integer greater than 1, and n is a positive integer less than or equal to N; the display cycle includes a first multiplexing time period; the data writing stage includes N data writing time periods set sequentially; the first multiplexing time period includes the reset stage and the first data writing time period included in the data writing stage; the driving method includes: During the reset phase, the data line provides the reset data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal in the nth pixel circuit, and writes the reset data voltage into the data voltage access terminal of the nth pixel circuit. During the first multiplexing time period, the data voltage providing circuit, under the control of the first data multiplexing control signal provided by the first data multiplexing terminal, controls the data line to connect with the data voltage access terminal in the first pixel circuit of the N pixel circuits. During the nth data writing time period included in the data writing phase, the data line provides the nth display data voltage. Under the control of the nth data multiplexing control signal, the data voltage providing circuit controls the connection between the data line and the data voltage access terminal of the nth pixel circuit among the N pixel circuits, and writes the nth display data voltage into the nth pixel circuit.

15. The display panel according to any one of claims 12 to 14, wherein, The pixel circuit includes a data writing circuit, a first writing control circuit, and a second writing control circuit. The data writing circuit is electrically connected to the scanning end and the data voltage access end, respectively, and is used to receive the display data voltage provided by the data voltage access end under the control of the scanning signal provided by the scanning end. The first writing control circuit is electrically connected to the first reset control end, the data voltage access end, the light emission control end, and the light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the light emission control end according to the first control data voltage provided by the data voltage access end under the control of the first reset control signal provided by the first reset control end. The second writing control circuit is electrically connected to the second reset control end, the data voltage access end, the display control end, and the light emission control node, respectively, and is used to control the connection or disconnection between the light emission control node and the display control end according to the second control data voltage provided by the data voltage access end under the control of the second reset control signal provided by the second reset control end. The display cycle includes a first control phase and a second control phase set before the reset phase. The first control phase includes a first write phase and a first set phase set sequentially. The second control phase includes a second write phase and a second set phase set sequentially. The first write phase includes N first write time periods set sequentially. The second write phase includes N second write time periods set sequentially. The data line is used to provide the nth first control data voltage during the nth first write time period. The voltage supply circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits during the nth first write time period, under the control of the nth data multiplexing control signal, and write the nth first control data voltage into the first write control circuit of the nth pixel circuit. The first write control circuit in each pixel circuit is used to control the connection or disconnection between the light emission control node and the light emission control terminal according to the first control data voltage received during the first setting phase. The data line is used to provide the nth second control data voltage during the nth second write time period. The data voltage providing circuit is used to control the connection between the data line and the data voltage access terminal in the nth pixel circuit among the N pixel circuits during the nth second write time period under the control of the nth data multiplexing control signal, so as to write the nth second control data voltage into the second write control circuit in the nth pixel circuit. The second write control circuit in each pixel circuit is used to control the connection or disconnection between the light-emitting control node and the display control terminal according to the second control data voltage received during the second setting phase.

16. The display panel as claimed in claim 15, wherein, The display control terminal is used to provide an effective display control signal for at least a portion of the time period between two display cycles.

17. The display panel as claimed in claim 15, wherein, The display control terminal is used to provide an effective display control signal during the first setting phase.

18. The display panel as claimed in claim 15, wherein, The display control terminal is used to provide effective display control signals during the first control phase.

19. A display device comprising a display panel as claimed in any one of claims 10 to 18.

Images