High-precision reference voltage calibration method and system based on lookup table

Abstract

The application relates to an Internet of Things technology service technical field such as a sensing technology service, and relates to a high-precision reference voltage calibration method and system based on a lookup table, which comprises the following steps: judging whether an original reference voltage value belongs to a target voltage range, if yes, not performing reference voltage calibration, if not, performing reference voltage testing according to a first target gear value, obtaining a first verification reference voltage value, judging whether the first verification reference voltage value belongs to the target voltage range, if yes, performing EFUSE programming according to the first target gear value, obtaining an EFUSE value, if not, calculating a second target gear value by using a gear adjustment step actual value, performing EFUSE programming according to the second target gear value, obtaining the EFUSE value, performing output resistance ratio adjustment according to the EFUSE value, obtaining a target output resistance ratio, and performing high-precision reference voltage calibration according to the target output resistance ratio. The application can solve the problems of low calibration efficiency and high risk in current chip internal reference voltage calibration.

Description

Technical Field

[0001] This invention relates to the field of Internet of Things (IoT) technology services, such as sensor technology services, and in particular to a high-precision reference voltage calibration method and system based on a lookup table. Background Technology

[0002] The internal reference voltage (VREF) is a core parameter ensuring the normal operation of on-chip analog and digital circuits. Especially in chip applications for industrial IoT information sensing and other IoT technology services, the accuracy and consistency of the reference voltage are crucial to the reliability of sensed data and system stability. While traditional bandgap reference voltage sources possess good temperature stability, they are susceptible to manufacturing process variations, leading to significant reference voltage drift between chips from the same batch and different batches. Therefore, calibrating and adjusting the reference voltage during the chip factory testing phase is essential to eliminate inter-chip differences and improve yield.

[0003] EFUSE, as an on-chip one-time programmable (OTP) memory unit, is widely used for the permanent storage of reference voltage calibration data due to its non-volatility and reliability. Existing reference voltage calibration schemes based on EFUSE often employ a binary search or successive approximation method to select the trim_code. For example, the European patent EP2489042B1, entitled "METHOD AND APPARATUS FOR TRIMMING DIE-TO-DIE VARIATION OF AN ON-CHIP GENERATED VOLTAGEREFERENCE," lacks validity verification before storage, and the target trim level is calculated only once before programming, lacking pre-storage validity verification. Furthermore, trim level determination relies on multiple trial calculations and iterative approximations. Since EFUSE programming is irreversible, an incorrect trim level selection will directly cause chip failure, especially for high-reliability chips serving IoT sensing and data processing technologies, further increasing production costs and testing risks. Therefore, current on-chip reference voltage calibration suffers from low calibration efficiency and high risk. Summary of the Invention

[0004] This invention provides a high-precision reference voltage calibration method and system based on a lookup table, the main purpose of which is to solve the problems of low calibration efficiency and high risk in current in-chip reference voltage calibration.

[0005] To achieve the above objectives, the present invention provides a high-precision reference voltage calibration method based on a lookup table, comprising:

[0006] Test the raw reference voltage value using a pre-built default hardware programming file;

[0007] Determine whether the original reference voltage value belongs to the preset target voltage range;

[0008] If the original reference voltage value falls within the target voltage range, then reference voltage calibration is not performed;

[0009] If the original reference voltage value does not fall within the target voltage range, the first target gear value is calculated based on the original reference voltage value, the preset reference voltage target value, and the theoretical value of the gear adjustment step size.

[0010] Based on the first target gear value, a reference voltage test is performed using a pre-built lookup table to obtain the first verification reference voltage value;

[0011] Determine whether the first verification reference voltage value belongs to the target voltage range;

[0012] If the first verification reference voltage value is within the target voltage range, then EFUSE is programmed according to the first target range value to obtain the EFUSE value;

[0013] If the first verification reference voltage value does not fall within the target voltage range, the actual value of the gear adjustment step size is calculated based on the first verification reference voltage value, the original reference voltage value, and the first target gear value.

[0014] The second target gear value is calculated using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size. The EFUSE value is obtained by programming the EFUSE value based on the second target gear value.

[0015] The output resistance ratio is adjusted according to the EFUSE value to obtain the target output resistance ratio, and a high-precision reference voltage calibration is performed based on the target output resistance ratio.

[0016] Optionally, the step of calculating the first target gear value based on the original reference voltage value, the preset reference voltage target value, and the theoretical value of the gear adjustment step size includes:

[0017] Based on the original reference voltage value, the target reference voltage value, and the theoretical value of the gear adjustment step size, the first target gear value is calculated using a pre-constructed first gear formula, wherein the first target gear value is trim_code1, and the first gear formula is as follows:

[0018]

[0019] in, This indicates the first target gear value. This indicates the default gear value. Indicates the target value of the reference voltage. This represents the original reference voltage value. This indicates the theoretical value of the gear adjustment step size.

[0020] Optionally, the step of performing a reference voltage test using a pre-built lookup table based on the first target range value to obtain a first verification reference voltage value includes:

[0021] Based on the first target gear value, the hardware burning file for the first gear is identified using a pre-built lookup table;

[0022] The first target gear value is programmed into the register of the pre-built control module using the first gear hardware programming file, and a reference voltage test is performed to obtain the first verification reference voltage value.

[0023] Optionally, the step of performing EFUSE programming based on the first target gear value to obtain the EFUSE value includes:

[0024] Using a pre-built EFUSE programming file, the first target bit value is programmed into the pre-built EFUSE circuit according to a preset EFUSE programming scheme to obtain the EFUSE value. The EFUSE programming scheme includes a single-bit EFUSE programming scheme and a multi-bit EFUSE programming scheme. The single-bit EFUSE programming scheme includes:

[0025] Identify the bit width of trim_code1 for the first target gear value;

[0026] A single-bit EFUSE programming file is constructed based on the bit width of trim_code1, wherein the number of single-bit EFUSE programming files is equal to the bit width of trim_code1;

[0027] Identify the single trim value of the first target gear position and the single storage location of the single trim value in the EFUSE circuit;

[0028] The single trim bit value is written to the single storage location using the single-bit EFUSE programming file to obtain the EFUSE value;

[0029] The multi-bit EFUSE programming scheme includes:

[0030] A multi-bit EFUSE programming file is constructed based on the first target gear value, wherein the number of the multi-bit EFUSE programming files is: , Indicates the number of bits in trim_code;

[0031] The first target value is programmed into the EFUSE circuit using the multi-bit EFUSE programming file to obtain the EFUSE value.

[0032] Optionally, the step of calculating the actual value of the gear adjustment step size based on the first verification reference voltage value, the original reference voltage value, and the first target gear value includes:

[0033] Based on the first verification reference voltage value, the original reference voltage value, and the first target gear value, the actual value of the gear adjustment step size is calculated using a pre-constructed gear adjustment step size formula, wherein the gear adjustment step size formula is as follows:

[0034]

[0035] in, This indicates the actual value of the gear adjustment step. This represents the first verification reference voltage value.

[0036] Optionally, the step of calculating the second target gear value using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size includes:

[0037] Using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size, the second target gear value is calculated according to the pre-constructed second gear formula, where the second target gear value is trim_code2, and the second gear formula is as follows:

[0038]

[0039] in, This indicates the second target gear value.

[0040] Optionally, the step of adjusting the output resistance ratio based on the EFUSE value to obtain the target output resistance ratio includes:

[0041] A power-off operation is performed on the pre-built chip under test to obtain a reset chip;

[0042] The reset chip is powered on again and the default hardware programming file is loaded. The output resistance ratio of the pre-built Bandgap circuit is adjusted using the EFUSE value to obtain the target output resistance ratio.

[0043] Optionally, the EFUSE value adjusts the output resistance ratio of the Bandgap circuit through a pre-built connection path, wherein the connection path includes a first input path and a second input path, the first input path and the second input path are selected by a pre-built selection circuit, the selection control signal of the selection circuit is output by a register, the first input path is connected to the EFUSE circuit, and the EFUSE circuit has the EFUSE value programmed and fixed.

[0044] The second input path is connected to the register of the control module. The register performs gear value verification through a pre-built hardware programming file. If the preset gear value verification passes, the gear value is programmed and solidified into the EFUSE circuit to obtain the EFUSE value. If the gear value verification fails, the preset updated gear value is written into the hardware programming file and the gear value verification is performed until the updated gear value passes the gear value verification. Then, the updated gear value is programmed and solidified into the EFUSE circuit to obtain the EFUSE value.

[0045] The control module interacts with the EFUSE circuit through a pre-built EFUSE_CTRL circuit. The control module performs read / write operations and scrambling / descrambling control on the EFUSE circuit through the preset JTAG interface and the EFUSE_CTRL circuit.

[0046] Optionally, the process of constructing the lookup table includes:

[0047] Establish the correspondence between the gear value and the hardware flashing file, and construct the lookup table based on the correspondence, wherein the gear value is trim_code. <n>The hardware flashing file is test_VREF_n_trim_code <n>.avc.gz.

[0048] To achieve the above objectives, the present invention also provides a high-precision reference voltage calibration system based on a lookup table, comprising:

[0049] The original reference voltage value determination module is used to test the original reference voltage value using a pre-built default hardware programming file; determine whether the original reference voltage value belongs to a preset target voltage range; if the original reference voltage value belongs to the target voltage range, no reference voltage calibration is performed.

[0050] The first target gear value programming module is used to calculate a first target gear value based on the original reference voltage value, a preset reference voltage target value, and a theoretical value of the gear adjustment step size if the original reference voltage value does not belong to the target voltage range; perform a reference voltage test using a pre-built lookup table based on the first target gear value to obtain a first verification reference voltage value; determine whether the first verification reference voltage value belongs to the target voltage range; and if the first verification reference voltage value belongs to the target voltage range, perform EFUSE programming based on the first target gear value to obtain an EFUSE value.

[0051] The second target gear value programming module is used to calculate the actual value of the gear adjustment step size based on the first verification reference voltage value, the original reference voltage value and the first target gear value if the first verification reference voltage value does not belong to the target voltage range; calculate the second target gear value using the original reference voltage value, the reference voltage target value and the actual value of the gear adjustment step size; and perform EFUSE programming based on the second target gear value to obtain the EFUSE value.

[0052] The output resistance ratio adjustment module is used to adjust the output resistance ratio according to the EFUSE value to obtain the target output resistance ratio, and to perform reference voltage calibration based on the target output resistance ratio.

[0053] To address the problems described in the background art, this invention first uses the original reference voltage value to determine whether reference voltage calibration is needed. Specifically, the original reference voltage value is first tested using the default hardware programming file to determine if it falls within the target voltage range. If the original reference voltage value falls within the target voltage range, reference voltage calibration is not performed. If it does not fall within the target voltage range, a first verification reference voltage value is first performed. First, a first target range value is calculated based on the original reference voltage value, the target reference voltage value, and the theoretical value of the range adjustment step size. Then, based on the first target range value, a reference voltage test is performed using a lookup table to obtain the first verification reference voltage value. At this point, it is determined whether the first verification reference voltage value falls within the target voltage range. If the first verification reference voltage value falls within the target voltage range... If the first target voltage range is not within the target voltage range, then EFUSE is directly programmed based on the first target voltage range value to obtain the EFUSE value. If the first verification reference voltage value does not belong to the target voltage range, it indicates that there is a deviation between the theoretical value of the voltage range adjustment and the actual value of the chip's voltage range adjustment step size. Therefore, it is necessary to first calculate the actual value of the voltage range adjustment step size based on the first verification reference voltage value, the original reference voltage value, and the first target voltage range value. Then, the second target voltage range value is recalculated using the original reference voltage value, the target reference voltage value, and the actual value of the voltage range adjustment step size. Finally, EFUSE is programmed based on the second target voltage range value to obtain the EFUSE value. After obtaining the EFUSE value, the output resistance ratio is adjusted based on the EFUSE value to obtain the target output resistance ratio. Finally, the reference voltage is calibrated based on the target output resistance ratio. Therefore, this invention can solve the problems of low calibration efficiency and high risk in current in-chip reference voltage calibration. Attached Figure Description

[0054] Figure 1 This is a flowchart illustrating a high-precision reference voltage calibration method based on a lookup table, according to an embodiment of the present invention.

[0055] Figure 2 A block diagram of a chip testing system provided in an embodiment of the present invention;

[0056] Figure 3 This is a flowchart of a reference voltage calibration process provided in an embodiment of the present invention;

[0057] Figure 4 This is a flowchart illustrating the calculation of the EFUSE value according to an embodiment of the present invention;

[0058] Figure 5 This is a functional block diagram of a high-precision reference voltage calibration system based on a lookup table provided in an embodiment of the present invention;

[0059] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0060] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0061] Reference Figure 1 The diagram shown is a flowchart illustrating a high-precision reference voltage calibration method based on a lookup table according to an embodiment of the present invention. In this embodiment, the high-precision reference voltage calibration method based on a lookup table includes:

[0062] S1. Test the original reference voltage value using the pre-built default hardware programming file.

[0063] Understandably, the default hardware programming file refers to the hardware programming file pre-configured before the chip leaves the factory, used to put the chip into its original standard operating state. The original reference voltage value refers to the actual reference voltage measurement value output by the bandgap circuit when the chip is in its original factory state without reference voltage calibration, tested using test equipment such as ATE. ATE (Automatic Test Equipment) is a comprehensive test platform integrating computer control, precision measuring instruments, and dedicated test software. In modern integrated circuit production lines, ATE is used to perform high-speed, high-precision functional and performance testing on chips. A typical ATE test platform is not a single device, but a complete mechatronics automated test system.

[0064] S2. Determine whether the original reference voltage value belongs to the preset target voltage range.

[0065] Furthermore, the target voltage range refers to the allowable deviation range of the output voltage value of the Bandgap reference voltage source corresponding to the Bandgap circuit. For example: when the target reference voltage value is The allowable deviation is The target voltage range is [1.198V, 1.202V]. The target reference voltage value refers to the nominal voltage output value of the Bandgap reference voltage source, pre-set during the chip design phase. The Bandgap reference voltage source is one of the most critical modules in analog integrated circuits (e.g., ADCs, DACs, operational amplifiers, etc.). Its core function is to output a stable DC reference voltage regardless of temperature changes or power supply voltage fluctuations. The DC voltage is typically 1.2V or 1.8V, providing a high-precision, high-stability voltage reference for various analog and digital circuits within the chip.

[0066] Understandably, the internal reference voltage of a chip directly determines the reliability of the chip's overall function. As chip integration continues to increase, the requirements of internal analog modules (such as ADCs and PLLs) on power supply voltage are becoming increasingly stringent. Although traditional bandgap reference voltage sources have good temperature stability, they are easily affected by manufacturing process deviations, resulting in significant reference voltage drift between chips of the same batch and between different batches. In order to ensure that the chip functions normally and eliminate performance differences between chips, the reference voltage needs to be calibrated.

[0067] In detail, calibrating the reference voltage addresses the issue of easy deviation in the internal reference voltage source output under different process corners. Through integrated digital control logic, during the chip's factory testing phase, the internal control circuit outputs the internal reference voltage to a dedicated I / O port. Testing equipment (test bench, multimeter, etc.) acquires the actual voltage value, calculates its deviation from the target reference voltage value, and converts the deviation into a corresponding range value. This range value is then programmed into the chip's internal EFUSE circuit using EFUSE. During subsequent normal chip operation, the system reads the EFUSE value stored in the EFUSE circuit and adjusts the output resistance ratio of the bandgap circuit in real time to compensate for inter-chip differences caused by process variations, achieving a high-precision and stable output of the reference voltage. See the chip's test system block diagram. Figure 2 As shown. Large-scale chip screening is typically performed using ATE (Automatic Test Equipment). An EFUSE (Electronic Fuse) is a one-time programmable (OTP) memory cell integrated within the chip. It writes data by burning a specific metal or polysilicon fuse with a high-voltage current. Once the fuse is blown, it is permanently open, and the stored data cannot be erased or rewritten. At the time of chip manufacturing, all EFUSE fuses are in the on state, corresponding to logic 0; after applying high voltage to burn the designated fuse, the corresponding node becomes open, which can be represented as logic 1, thus achieving one-time fixed storage of data.

[0068] If the original reference voltage value is within the target voltage range, then execute S3 and do not perform reference voltage calibration.

[0069] It should be understood that when the original reference voltage value is within the target voltage range, it means that reference voltage calibration is not required, the EFUSE value does not need to be programmed and the output resistance ratio is not needed to be adjusted, and the original output state of the chip meets the design requirements for the reference voltage.

[0070] If the original reference voltage value does not fall within the target voltage range, then execute S4 to calculate the first target gear value based on the original reference voltage value, the preset reference voltage target value, and the theoretical value of the gear adjustment step size.

[0071] Understandably, the theoretical value of the adjustment step size refers to the theoretical change in the Bandgap reference voltage corresponding to a single EFUSE setting, pre-set during the chip circuit design phase. The first target setting value refers to the first EFUSE setting value to be verified during chip reference calibration, derived from theoretical parameters.

[0072] In this embodiment of the invention, calculating the first target gear value based on the original reference voltage value, the preset reference voltage target value, and the theoretical value of the gear adjustment step size includes:

[0073] Based on the original reference voltage value, the target reference voltage value, and the theoretical value of the gear adjustment step size, the first target gear value is calculated using a pre-constructed first gear formula, wherein the first target gear value is trim_code1, and the first gear formula is as follows:

[0074]

[0075] in, This indicates the first target gear value. This indicates the default gear value. Indicates the target value of the reference voltage. This represents the original reference voltage value. This indicates the theoretical value of the gear adjustment step size.

[0076] Furthermore, the default gear value refers to the EFUSE reference starting gear preset during the chip circuit design stage.

[0077] S5. Based on the first target gear value, a reference voltage test is performed using a pre-built lookup table to obtain the first verification reference voltage value.

[0078] Furthermore, the lookup table refers to a table that integrates the EFUSE circuit's range values ​​and hardware programming files according to their corresponding relationships. This lookup table is used to quickly match the hardware programming file corresponding to the range value, enabling rapid range retrieval in the ATE automated calibration process. The reference voltage test refers to the process of using testing equipment such as ATE to measure the reference voltage value output by the Bandgap circuit based on the range value. The first verification reference voltage value refers to the measured verification value of the reference voltage output by the Bandgap circuit after calibration using the first target range value. The lookup table is a software-level data structure that organizes and combines the hardware programming files corresponding to each range value into a dedicated array according to preset rules, facilitating subsequent rapid retrieval and range lookup.

[0079] Understandably, during EFUSE programming, it's first necessary to determine the gear value that meets the target voltage range. Traditionally, this is achieved through actual analysis and calculation or multiple trial programming attempts. While this method fulfills basic functionality, it's cumbersome, time-consuming, inefficient, and difficult to adapt to automated testing processes. To address these issues, this solution integrates the hardware programming files corresponding to all gear values ​​and gear configuration information into a single file based on a calculation formula, forming a generalized lookup table. This lookup table allows for rapid location of the gear value, significantly improving the efficiency of gear value determination, especially in ATE automated testing scenarios. See Table 1, where `trim_code`... <n>This is the actual EFUSE value. The gear values ​​in the lookup table are sorted in ascending order of voltage value.

[0080] Table 1

[0081]

[0082] In this embodiment of the invention, the step of performing a reference voltage test using a pre-built lookup table based on the first target gear value to obtain a first verification reference voltage value includes:

[0083] Based on the first target gear value, the hardware burning file for the first gear is identified using a pre-built lookup table;

[0084] The first target voltage value is programmed into the register of the pre-built control module using the first voltage level hardware programming file, and a reference voltage test is performed to obtain the first verification reference voltage value. The control module is the core control unit managing the chip's data flow, located between the I / O interface and the internal logic. When the hardware programming file is downloaded to the chip, the control module is responsible for data reception, protocol parsing, and timing control, accurately writing the data into the internal storage module, and simultaneously implementing protocol conversion and timing coordination between various interfaces and internal logic.

[0085] Understandably, the first gear position hardware programming file refers to the hardware programming file corresponding to the first target gear position value in the lookup table. The control module refers to the core control unit inside the chip used to receive external instructions, configure register values, and interact with the EFUSE_CTRL circuit. It is responsible for writing the gear position value into the register through the hardware programming file, and for controlling the reading, writing, scrambling, and programming of the EFUSE circuit. The register refers to the temporary storage unit inside the control module.

[0086] In detail, the process of constructing the lookup table includes:

[0087] Establish the correspondence between the gear value and the hardware flashing file, and construct the lookup table based on the correspondence, wherein the gear value is trim_code. <n>The hardware flashing file is test_VREF_n_trim_code <n>.avc.gz.

[0088] S6. Determine whether the first verification reference voltage value belongs to the target voltage range.

[0089] If the first verification reference voltage value is within the target voltage range, then execute S7 to perform EFUSE programming according to the first target range value to obtain the EFUSE value.

[0090] Understandably, EFUSE programming refers to encoding the verified gear value (which can be either a first target gear value or a second target gear value) into binary data recognizable by the EFUSE circuit. This first target gear value is then permanently encoded into the EFUSE circuit using the JTAG interface, control module, and EFUSE_CTRL circuit, through a high-voltage current that fuses the internal EFUSE metal or polysilicon circuitry. The EFUSE circuit refers to a dedicated storage circuit within the chip based on one-time programmable memory technology. It serves as the permanent carrier for the verified gear value and consists of high-voltage-fuseable metal or polysilicon circuitry, storage units, and data read / write paths. The JTAG interface refers to the chip's standard external test interface, acting as a communication bridge between the ATE test equipment, control module, and EFUSE_CTRL circuit. The EFUSE_CTRL circuit refers to a dedicated control logic circuit within the chip that connects the control module and the EFUSE circuit. It acts as a relay and drive unit for data interaction and EFUSE programming between the control module and the EFUSE circuit, performing functions such as reading / writing and scrambling / descrambling on the EFUSE circuit.

[0091] Furthermore, the EFUSE value refers to the one-time programmable calibration data that is permanently embedded in the EFUSE circuit inside the chip after the qualified range value in the chip reference voltage calibration is binary encoded and burned through EFUSE.

[0092] In this embodiment of the invention, the step of performing EFUSE programming based on the first target gear value to obtain the EFUSE value includes:

[0093] Using a pre-built EFUSE programming file, the first target bit value is programmed into the pre-built EFUSE circuit according to a preset EFUSE programming scheme to obtain the EFUSE value. The EFUSE programming scheme includes a single-bit EFUSE programming scheme and a multi-bit EFUSE programming scheme. The single-bit EFUSE programming scheme includes:

[0094] Identify the bit width of trim_code1 for the first target gear value;

[0095] A single-bit EFUSE programming file is constructed based on the bit width of trim_code1, wherein the number of single-bit EFUSE programming files is equal to the bit width of trim_code1;

[0096] Identify the single trim value of the first target gear position and the single storage location of the single trim value in the EFUSE circuit;

[0097] The single trim bit value is written to the single storage location using the single-bit EFUSE programming file to obtain the EFUSE value;

[0098] The multi-bit EFUSE programming scheme includes:

[0099] A multi-bit EFUSE programming file is constructed based on the first target gear value, wherein the number of the multi-bit EFUSE programming files is: , Indicates the number of bits in trim_code;

[0100] The first target value is programmed into the EFUSE circuit using the multi-bit EFUSE programming file to obtain the EFUSE value.

[0101] Furthermore, the EFUSE programming file refers to the dedicated configuration file of the EFUSE circuit during chip reference voltage calibration, where the verified range value is programmed. The verified range value can be either a first target range value or a second target range value. The second target range value refers to the secondary optimized range value derived during chip reference calibration when the first target range value fails verification; this is also the final programming range value.

[0102] In detail, the single-bit EFUSE programming scheme refers to a scheme that performs programming operations on only one unit of memory bit in the EFUSE circuit at a time, requiring the preparation of the same number of single-bit EFUSE programming files according to the bit width of the verified range value. The multi-bit EFUSE programming scheme refers to a scheme that performs programming operations on programming files made according to the verified complete range value, with each multi-bit EFUSE programming file corresponding to one verified range value, and EFUSE programming can be completed in one operation.

[0103] Furthermore, the trim_code1 bit width refers to the number of binary bits in the first target gear value, which is also the total number of programmable fuse bits allocated by the EFUSE circuit for storing the verified gear value. The single-bit EFUSE programming file refers to a dedicated programming configuration file designed for a single fuse bit during EFUSE programming. The single trim bit value refers to the logical value of 0 or 1 corresponding to a single bit in the binary encoding constituting the first target gear value. The single storage location refers to the hardware address or physical storage location of a single independent programmable fuse bit allocated by the EFUSE circuit for storing the binary encoding of the first target gear value.

[0104] It should be explained that the multi-bit EFUSE programming file refers to a dedicated programming configuration file designed based on the complete bit value of the first target bit value or the second target bit value.

[0105] It should be understood that the single-bit EFUSE programming scheme requires multiple programming operations as needed. Although multiple programming operations are required, the single-bit operation is flexible and can be freely combined according to actual needs. The multi-bit EFUSE programming scheme can complete the EFUSE programming of a chip in one operation, which is simple and fast. The specific programming scheme can be determined according to the actual situation.

[0106] In detail, the EFUSE value adjusts the output resistance ratio of the Bandgap circuit through a pre-built connection path, wherein the connection path includes a first input path and a second input path, the first input path and the second input path are selected by a pre-built selection circuit, the selection control signal of the selection circuit is output by a register, the first input path is connected to the EFUSE circuit, and the EFUSE circuit has the EFUSE value programmed and fixed.

[0107] The second input path is connected to the register of the control module. The register performs gear value verification through a pre-built hardware programming file. If the preset gear value verification passes, the gear value is programmed and solidified into the EFUSE circuit to obtain the EFUSE value. If the gear value verification fails, the preset updated gear value is written into the hardware programming file and the gear value verification is performed until the updated gear value passes the gear value verification. Then, the updated gear value is programmed and solidified into the EFUSE circuit to obtain the EFUSE value.

[0108] The control module interacts with the EFUSE circuit through a pre-built EFUSE_CTRL circuit. The control module performs read / write operations and scrambling / descrambling control on the EFUSE circuit through the preset JTAG interface and the EFUSE_CTRL circuit.

[0109] Understandably, the connection path refers to the electrical connection path between the control module, registers, EFUSE circuit, and Bandgap circuit within the chip for transmitting signals or values ​​such as range values, control signals, and voltage signals. The Bandgap circuit refers to the analog circuit within the chip used to generate a high-precision reference voltage that does not change with temperature or power supply voltage. The output resistance ratio adjustment refers to the operation of fine-tuning and calibrating the magnitude of the output reference voltage by changing the resistance ratio of different branches in the internal resistor network of the Bandgap reference voltage source. The first input path refers to the signal transmission path connected to the EFUSE circuit, used to transmit the EFUSE value burned into the EFUSE circuit to the Bandgap circuit to achieve output resistance ratio adjustment of the Bandgap circuit. The second input path refers to the signal transmission path connected to the register of the control module, used to transmit the range value written in the register through a hardware programming file to the Bandgap circuit to complete range value verification and output resistance ratio adjustment. The selection circuit refers to the circuit that selects the first input path or the second input path according to the gating control signal output by the register, so as to input the EFUSE value output by the EFUSE circuit or the range value output by the register to the Bandgap circuit to complete the verification or solidification of the reference voltage.

[0110] In detail, the hardware programming file writes the gear value to be tested into the register of the control module and configures the configuration file for the selected circuit's strobe state. The gear value is written into the register through the configuration file to adjust the output resistance ratio of the Bandgap circuit. The gear value verification refers to the process of inputting the gear value written into the register via the hardware programming file to the Bandgap circuit through the second input path to test and determine whether the output reference voltage belongs to the target voltage range. The gear value update refers to the process of replacing the original gear value with a new gear value calculated based on calibration when the original gear value fails verification, and then re-verifying the new gear value.

[0111] In detail, during the circuit design phase, to meet the requirements of later reference voltage calibration and adjustment, the output voltage divider resistor string of the Bandgap reference voltage source is set as an adjustable structure. The adjustment range value of the voltage divider resistor string adopts a two-input architecture, and the path is selected by a selection circuit. The range value of the first input path comes from the EFUSE circuit, which is used to program and solidify the range value finally determined based on the chip test results. The range value of the second input path comes from the register inside the control module. The range value can be written to the register through a hardware programming file. The selection control signal of the selection circuit is provided by the register, so that the range value can be written to the chip first and verified. After the test confirms that it meets the target voltage range, the range value is then programmed and solidified to the EFUSE circuit, ensuring that the final programmed and solidified EFUSE value is consistent with the target calibration value. In addition, even if the later solidified EFUSE value (i.e., the solidified trim_code) does not meet the requirements, the reference voltage can be adjusted directly by using the range value output by the register by modifying the hardware programming file, bypassing the EFUSE circuit. The reference voltage calibration flowchart can be found in [reference needed]. Figure 3 As shown, VREF represents the reference voltage.

[0112] If the first verification reference voltage value does not fall within the target voltage range, then execute S8 to calculate the actual value of the gear adjustment step based on the first verification reference voltage value, the original reference voltage value, and the first target gear value.

[0113] Understandably, the actual value of the gear adjustment step refers to the true adjustment coefficient of the Bandgap circuit reference voltage as the gear value changes, calculated based on the reference voltage change obtained from actual chip testing and the corresponding gear value change.

[0114] In this embodiment of the invention, the step of calculating the actual value of the gear adjustment step size based on the first verification reference voltage value, the original reference voltage value, and the first target gear value includes:

[0115] Based on the first verification reference voltage value, the original reference voltage value, and the first target gear value, the actual value of the gear adjustment step size is calculated using a pre-constructed gear adjustment step size formula, wherein the gear adjustment step size formula is as follows:

[0116]

[0117] in, This indicates the actual value of the gear adjustment step. This represents the first verification reference voltage value.

[0118] S9. Calculate the second target gear value using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size. Perform EFUSE programming based on the second target gear value to obtain the EFUSE value.

[0119] Understandably, the second target gear value refers to the calibration gear value calculated based on the actual value of the gear adjustment step size, which makes the reference voltage value output by the Bandgap circuit conform to the target voltage range.

[0120] In this embodiment of the invention, the calculation of the second target gear value using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size includes:

[0121] Using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size, the second target gear value is calculated according to the pre-constructed second gear formula, where the second target gear value is trim_code2, and the second gear formula is as follows:

[0122]

[0123] in, This indicates the second target gear value.

[0124] Furthermore, the flowchart for calculating the EFUSE value can be found in [reference needed]. Figure 4 As shown.

[0125] S10. Adjust the output resistance ratio according to the EFUSE value to obtain the target output resistance ratio, and perform reference voltage calibration according to the target output resistance ratio.

[0126] It should be understood that the target output resistance ratio refers to the ideal voltage division ratio that the adjustable voltage divider string inside the Bandgap reference voltage source needs to achieve when the Bandgap reference voltage source outputs a reference voltage within the target voltage range. The reference voltage of the Bandgap reference voltage source is calibrated according to the target output resistance ratio so that its output reference voltage falls within the target voltage range.

[0127] In this embodiment of the invention, adjusting the output resistance ratio based on the EFUSE value to obtain the target output resistance ratio includes:

[0128] A power-off operation is performed on the pre-built chip under test to obtain a reset chip;

[0129] The reset chip is powered on again and the default hardware programming file is loaded. The output resistance ratio of the pre-built Bandgap circuit is adjusted using the EFUSE value to obtain the target output resistance ratio.

[0130] Understandably, the chip under test (DUT) refers to a chip that requires high-precision reference voltage calibration, range value verification, and EFUSE programming; that is, a chip undergoing testing and calibration. The chip reset refers to restoring the internal circuit state, registers, and related configuration parameters of the DUT to their initial power-on state after a power-off operation. The power-off operation refers to cutting off the power supply to the DUT, resetting the chip's internal logic and register states. The power-on reconnection operation refers to reconnecting the chip to operating power after the power-off operation, allowing the chip to start from its initial state, load default configurations, and enter a testable and calibrable state.

[0131] Furthermore, after completing the EFUSE programming, the chip is powered off to allow the calibrated range value to take effect. After the chip is powered on again, the default hardware programming file is loaded. At this time, the range value is provided by the EFUSE circuit. The reference voltage is tested again to confirm that it falls within the target voltage range.

[0132] Explained, this invention directly calculates the required range value based on the reference voltage test results, and quickly matches the corresponding hardware programming file using a lookup table for download and verification. Simultaneously, it calculates the actual range adjustment step size based on measured data. The final range value can be determined in at most two calculations, effectively solving the problem of traditional methods requiring multiple trials, which are time-consuming and resource-intensive. Pre-verification using the hardware programming file avoids reference voltage deviations caused by incorrect range value (trim_code) selection. By constructing a lookup table for the hardware programming files corresponding to each range value and combining it with a calculation method based on test results, it overcomes the inefficiency and multiple attempts required by traditional range selection methods, and avoids the risk of irreversible errors during direct EFUSE programming. It also optimizes the overall testing process, making it easier for ATE equipment to automate through programming, significantly improving calibration efficiency. Compared to existing technologies, this represents a significant improvement.

[0133] To address the problems described in the background art, this invention first uses the original reference voltage value to determine whether reference voltage calibration is needed. Specifically, the original reference voltage value is first tested using the default hardware programming file to determine if it falls within the target voltage range. If the original reference voltage value falls within the target voltage range, reference voltage calibration is not performed. If it does not fall within the target voltage range, a first verification reference voltage value is first performed. First, a first target range value is calculated based on the original reference voltage value, the target reference voltage value, and the theoretical value of the range adjustment step size. Then, based on the first target range value, a reference voltage test is performed using a lookup table to obtain the first verification reference voltage value. At this point, it is determined whether the first verification reference voltage value falls within the target voltage range. If the first verification reference voltage value falls within the target voltage range... If the first target voltage range is not within the target voltage range, then EFUSE is directly programmed based on the first target voltage range value to obtain the EFUSE value. If the first verification reference voltage value does not belong to the target voltage range, it indicates that there is a deviation between the theoretical value of the voltage range adjustment and the actual value of the chip's voltage range adjustment step size. Therefore, it is necessary to first calculate the actual value of the voltage range adjustment step size based on the first verification reference voltage value, the original reference voltage value, and the first target voltage range value. Then, the second target voltage range value is recalculated using the original reference voltage value, the target reference voltage value, and the actual value of the voltage range adjustment step size. Finally, EFUSE is programmed based on the second target voltage range value to obtain the EFUSE value. After obtaining the EFUSE value, the output resistance ratio is adjusted based on the EFUSE value to obtain the target output resistance ratio. Finally, the reference voltage is calibrated based on the target output resistance ratio. Therefore, this invention can solve the problems of low calibration efficiency and high risk in current in-chip reference voltage calibration.

[0134] like Figure 5 The diagram shown is a functional block diagram of a high-precision reference voltage calibration system based on a lookup table provided in an embodiment of the present invention.

[0135] Depending on the functions implemented, the high-precision reference voltage calibration system 100 based on lookup table may include an original reference voltage value judgment module 101, a first target range value writing module 102, a second target range value writing module 103, and an output resistance ratio adjustment module 104.

[0136] The original reference voltage value judgment module 101 is used to test the original reference voltage value using a pre-built default hardware programming file; to determine whether the original reference voltage value belongs to a preset target voltage range; if the original reference voltage value belongs to the target voltage range, then no reference voltage calibration is performed.

[0137] The first target gear value programming module 102 is used to calculate a first target gear value based on the original reference voltage value, a preset reference voltage target value, and a theoretical value of the gear adjustment step size if the original reference voltage value does not belong to the target voltage range; perform a reference voltage test using a pre-built lookup table based on the first target gear value to obtain a first verification reference voltage value; determine whether the first verification reference voltage value belongs to the target voltage range; and if the first verification reference voltage value belongs to the target voltage range, perform EFUSE programming based on the first target gear value to obtain an EFUSE value.

[0138] The second target gear value programming module 103 is used to calculate the actual value of the gear adjustment step size based on the first verification reference voltage value, the original reference voltage value and the first target gear value if the first verification reference voltage value does not belong to the target voltage range; calculate the second target gear value using the original reference voltage value, the reference voltage target value and the actual value of the gear adjustment step size; and perform EFUSE programming based on the second target gear value to obtain the EFUSE value.

[0139] The output resistance ratio adjustment module 104 is used to adjust the output resistance ratio according to the EFUSE value to obtain a target output resistance ratio, and to perform reference voltage calibration according to the target output resistance ratio.

[0140] In detail, the modules in the high-precision reference voltage calibration system 100 based on lookup tables described in this embodiment of the invention employ the same methods as described above. Figure 1 The high-precision reference voltage calibration method based on lookup tables described herein uses the same technical means and can produce the same technical effect, so it will not be repeated here.

[0141] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.< / n> < / n> < / n> < / n> < / n>

Claims

1. A high-precision reference voltage calibration method based on a lookup table, characterized in that, The method includes: Test the raw reference voltage value using a pre-built default hardware programming file; Determine whether the original reference voltage value belongs to the preset target voltage range; If the original reference voltage value falls within the target voltage range, then reference voltage calibration is not performed; If the original reference voltage value does not fall within the target voltage range, the first target gear value is calculated based on the original reference voltage value, the preset reference voltage target value, and the theoretical value of the gear adjustment step size. Based on the first target gear value, a reference voltage test is performed using a pre-built lookup table to obtain the first verification reference voltage value; Determine whether the first verification reference voltage value belongs to the target voltage range; If the first verification reference voltage value is within the target voltage range, then EFUSE is programmed according to the first target range value to obtain the EFUSE value; If the first verification reference voltage value does not fall within the target voltage range, the actual value of the gear adjustment step size is calculated based on the first verification reference voltage value, the original reference voltage value, and the first target gear value. The second target gear value is calculated using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size. The EFUSE value is obtained by programming the EFUSE value based on the second target gear value. The output resistance ratio is adjusted according to the EFUSE value to obtain the target output resistance ratio, and a high-precision reference voltage calibration is performed based on the target output resistance ratio.

2. The high-precision reference voltage calibration method based on a lookup table as described in claim 1, characterized in that, The calculation of the first target gear value based on the original reference voltage value, the preset reference voltage target value, and the theoretical value of the gear adjustment step size includes: Based on the original reference voltage value, the target reference voltage value, and the theoretical value of the gear adjustment step size, the first target gear value is calculated using a pre-constructed first gear formula, wherein the first target gear value is trim_code1, and the first gear formula is as follows: in, This indicates the first target gear value. This indicates the default gear value. Indicates the target value of the reference voltage. This represents the original reference voltage value. This indicates the theoretical value of the gear adjustment step size.

3. The high-precision reference voltage calibration method based on a lookup table as described in claim 2, characterized in that, The step of performing a reference voltage test using a pre-built lookup table based on the first target gear value to obtain a first verification reference voltage value includes: Based on the first target gear value, the hardware burning file for the first gear is identified using a pre-built lookup table; The first target gear value is programmed into the register of the pre-built control module using the first gear hardware programming file, and a reference voltage test is performed to obtain the first verification reference voltage value.

4. The high-precision reference voltage calibration method based on a lookup table as described in claim 3, characterized in that, The step of writing EFUSE based on the first target gear value to obtain the EFUSE value includes: Using a pre-built EFUSE programming file, the first target bit value is programmed into the pre-built EFUSE circuit according to a preset EFUSE programming scheme to obtain the EFUSE value. The EFUSE programming scheme includes a single-bit EFUSE programming scheme and a multi-bit EFUSE programming scheme. The single-bit EFUSE programming scheme includes: Identify the bit width of trim_code1 for the first target gear value; A single-bit EFUSE programming file is constructed based on the bit width of trim_code1, wherein the number of single-bit EFUSE programming files is equal to the bit width of trim_code1; Identify the single trim value of the first target gear position and the single storage location of the single trim value in the EFUSE circuit; The single trim bit value is written to the single storage location using the single-bit EFUSE programming file to obtain the EFUSE value; The multi-bit EFUSE programming scheme includes: A multi-bit EFUSE programming file is constructed based on the first target gear value, wherein the number of the multi-bit EFUSE programming files is: , Indicates the number of bits in trim_code; The first target value is programmed into the EFUSE circuit using the multi-bit EFUSE programming file to obtain the EFUSE value.

5. The high-precision reference voltage calibration method based on a lookup table as described in claim 4, characterized in that, The step of calculating the actual value of the gear adjustment step size based on the first verification reference voltage value, the original reference voltage value, and the first target gear value includes: Based on the first verification reference voltage value, the original reference voltage value, and the first target gear value, the actual value of the gear adjustment step size is calculated using a pre-constructed gear adjustment step size formula, wherein the gear adjustment step size formula is as follows: in, This indicates the actual value of the gear adjustment step. This represents the first verification reference voltage value.

6. The high-precision reference voltage calibration method based on a lookup table as described in claim 5, characterized in that, The calculation of the second target gear value using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size includes: Using the original reference voltage value, the target reference voltage value, and the actual value of the gear adjustment step size, the second target gear value is calculated according to the pre-constructed second gear formula, where the second target gear value is trim_code2, and the second gear formula is as follows: in, This indicates the second target gear value.

7. The high-precision reference voltage calibration method based on a lookup table as described in claim 6, characterized in that, The step of adjusting the output resistance ratio based on the EFUSE value to obtain the target output resistance ratio includes: A power-off operation is performed on the pre-built chip under test to obtain a reset chip; The reset chip is powered on again and the default hardware programming file is loaded. The output resistance ratio of the pre-built Bandgap circuit is adjusted using the EFUSE value to obtain the target output resistance ratio.

8. The high-precision reference voltage calibration method based on a lookup table as described in claim 7, characterized in that, The EFUSE value adjusts the output resistance ratio of the Bandgap circuit through a pre-built connection path, wherein the connection path includes a first input path and a second input path. The first input path and the second input path are selected by a pre-built selection circuit. The selection control signal of the selection circuit is output by a register. The first input path is connected to the EFUSE circuit. The EFUSE circuit has the EFUSE value programmed and fixed. The second input path is connected to the register of the control module. The register performs gear value verification through a pre-built hardware programming file. If the preset gear value verification passes, the gear value is programmed and solidified into the EFUSE circuit to obtain the EFUSE value. If the gear value verification fails, the preset updated gear value is written into the hardware programming file and the gear value verification is performed until the updated gear value passes the gear value verification. Then, the updated gear value is programmed and solidified into the EFUSE circuit to obtain the EFUSE value. The control module interacts with the EFUSE circuit through a pre-built EFUSE_CTRL circuit. The control module performs read / write operations and scrambling / descrambling control on the EFUSE circuit through the preset JTAG interface and the EFUSE_CTRL circuit.

9. The high-precision reference voltage calibration method based on a lookup table as described in claim 8, characterized in that, The process of constructing the lookup table includes: Establish the correspondence between the gear value and the hardware flashing file, and construct the lookup table based on the correspondence, wherein the gear value is trim_code. <n>The hardware flashing file is test_VREF_n_trim_code <n> .avc.gz.< / n> < / n> 10. A high-precision reference voltage calibration system based on a lookup table, characterized in that, The system includes: The original reference voltage value determination module is used to test the original reference voltage value using a pre-built default hardware programming file; determine whether the original reference voltage value belongs to a preset target voltage range; if the original reference voltage value belongs to the target voltage range, no reference voltage calibration is performed. The first target gear value programming module is used to calculate a first target gear value based on the original reference voltage value, a preset reference voltage target value, and a theoretical value of the gear adjustment step size if the original reference voltage value does not belong to the target voltage range; perform a reference voltage test using a pre-built lookup table based on the first target gear value to obtain a first verification reference voltage value; determine whether the first verification reference voltage value belongs to the target voltage range; and if the first verification reference voltage value belongs to the target voltage range, perform EFUSE programming based on the first target gear value to obtain an EFUSE value. The second target gear value programming module is used to calculate the actual value of the gear adjustment step size based on the first verification reference voltage value, the original reference voltage value and the first target gear value if the first verification reference voltage value does not belong to the target voltage range; calculate the second target gear value using the original reference voltage value, the reference voltage target value and the actual value of the gear adjustment step size; and perform EFUSE programming based on the second target gear value to obtain the EFUSE value. The output resistance ratio adjustment module is used to adjust the output resistance ratio according to the EFUSE value to obtain the target output resistance ratio, and to perform reference voltage calibration based on the target output resistance ratio.

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