Satellite digital component on-orbit flight verification system and method

Abstract

The invention provides a satellite digital component on-orbit flight verification system and method.The satellite digital component on-orbit flight verification system comprises a digital component verification mother board and a digital circuit test daughter board, the digital component verification mother board comprises a power module, a main control module, an acquisition module, a storage module and a communication module, and the power module supplies power to the mother board and the daughter board; the acquisition module collects attribute information of a tested component, the main control module performs logic control and data processing, the storage module stores test data, and the communication module realizes communication; the digital circuit test daughter board comprises a test component module and a processor module and is used for testing on-orbit operation conditions of digital components and preprocessing data. Connection and data interaction between the mother board and the daughter board are achieved through the connector and the communication protocol, the verification method covers the whole process from power-on initialization to data acquisition, processing, transmission and analysis evaluation, and the performance and reliability of satellite digital components in on-orbit flight can be effectively verified.

Description

Technical Field

[0001] This invention relates to the field of digital component reliability testing technology, specifically to an on-orbit flight verification system and method for satellite digital components. Background Technology

[0002] With the rapid development of aerospace technology, satellite systems are playing an increasingly important role in fields such as communication, navigation, and remote sensing, and the requirements for the reliability and performance of digital components are becoming increasingly stringent. However, ground-based testing environments cannot fully simulate the extreme conditions of space, including complex conditions such as high vacuum, strong radiation, microgravity, and huge temperature variations. This can lead to performance degradation or even failure of many components that pass ground testing in actual space missions, thereby affecting the normal operation of the entire satellite system.

[0003] Traditional methods for verifying satellite digital components mainly rely on simulation tests in ground laboratories, but this approach has many limitations. On the one hand, ground simulation equipment struggles to accurately reproduce the combined effects of the space environment, especially the long-term cumulative radiation damage and the impact of microgravity on its physical properties, leading to discrepancies between test results and actual on-orbit performance. On the other hand, ground tests typically only provide discrete, short-term performance evaluations of components, failing to monitor their stability and reliability trends in real time during long-duration space missions.

[0004] Currently, although some on-orbit verification systems exist, they suffer from limited functionality and poor versatility. For example, some systems can only perform limited functional tests on specific types of digital components, failing to meet the diverse verification needs of various types of components. Other systems lack sufficient data processing capabilities, unable to efficiently collect, store, and analyze massive amounts of on-orbit test data, making it difficult to quickly and accurately locate potential fault points, thus affecting the comprehensive and accurate evaluation of component performance.

[0005] Patent application CN113299337A discloses an on-orbit flight verification device and method for electronic components. The device includes a main control unit (FPGA), a module under test (DUT), a power supply module, an AD voltage acquisition module, and a CAN communication module. The DUT, connected to the main control unit (FPGA), includes at least one of the following: RRAM chip, SRAM chip, NAND chip, SDRAM chip, MRAM chip, and the DUT chip, with at least one of each type. The DUT chip has BRAM memory. Using the FPGA as the main control unit, the device performs simultaneous on-orbit functional testing on one or more of the following devices (RRAM, NAND FLASH, FPGA, SDRAM, and multiple SRAM devices) used on satellite boards, verifying single-event upset (SEE) and latch-up resistance capabilities. The status information of the mounted devices is transmitted to the main control unit via CAN communication. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide an on-orbit flight verification system and method for satellite digital components.

[0007] The satellite digital component on-orbit flight verification system provided by the present invention includes a digital component verification motherboard, connectors, and a digital circuit test daughterboard; The digital component verification motherboard is connected to the digital circuit test daughterboard via the connector; The digital component verification motherboard includes a power module, a main control module, a data acquisition module, a storage module, and a communication module. The power module is connected to the digital component verification motherboard and the digital circuit test daughterboard, and is used to supply power. The main control module is connected to the acquisition module and the communication module, and is used for logic control and data reading; The acquisition module is connected to the connector and the main control module and is used to acquire the attribute information of the digital component under test. The storage module is connected to the main control module and is used to store test data; The communication module is connected to the main control module and is used to communicate with the spacecraft computer; The spacecraft computer is connected to the communication module and is used to remotely control the verification device; The digital circuit test sub-board includes a test component module and a processor module; The test component module is connected to the processor module and is used to test the on-orbit operation of digital components; The processor module is connected to the connector and the test component module and is used to preprocess the on-orbit operating data.

[0008] Preferably, the power module includes a verification motherboard power supply unit and a test daughterboard power supply unit; The power supply unit of the verification motherboard is connected to the digital component verification motherboard and is used to supply power to the verification motherboard. The power supply unit for the test sub-board is connected to the digital circuit test sub-board and is used to supply power to the test sub-board.

[0009] Preferably, the acquisition module consists of an analog-to-digital converter chip, multiple analog signal input channels, a signal conditioning circuit, a microcontroller, a power management circuit, and a communication interface; The multiple analog signal input channels are connected to the signal conditioning circuit and are used to input analog signals; The signal conditioning circuit is connected to the analog-to-digital converter chip and is used to amplify and filter the analog signal; The analog-to-digital converter chip is connected to the microcontroller and is used to perform A / D conversion under the control of the microcontroller; The microcontroller is connected to the analog-to-digital converter chip and the main control module, and is used to receive digital output and package data. The power management circuit is connected to the analog-to-digital converter chip, multiple analog signal input channels, signal conditioning circuit, microcontroller, and communication interface to provide power. The communication interface is connected to the microcontroller and the main control module for data transmission. For digital signals, they are directly acquired through FPGA logic; for analog signals, they are converted by an ADC and then processed by a microcontroller.

[0010] Preferably, the main control module includes multiple compatible LVDS, SPI, I2C, and JTAG digital interfaces, and has EDAC functionality.

[0011] Preferably, the storage module uses a PostgreSQL relational database as its storage core; Create a main table to store basic information about digital components, including the digital component ID, model, batch number, and production date; Create data sub-tables for different test projects. The sub-tables contain test timestamp, test parameters, results and status fields, and are related to the main table through foreign keys. Data retrieval methods include querying by component ID or model, querying by test item type, and querying by test pass / fail results; It provides a standard SQL query interface and supports combined condition queries.

[0012] Preferably, the communication module is equipped with dual RS422 / RS485 bus interfaces, supporting both RS422 and RS485 communication protocols.

[0013] Preferably, the connector is provided with 30 pairs of LVDS interfaces for connecting the digital component verification motherboard and the digital circuit test daughterboard.

[0014] The verification method for the satellite digital component on-orbit flight verification system provided by the present invention includes the following steps: Step S1: Reset the platform after power-on and initialize each module; Step S2: A clock signal is provided by an external crystal oscillator and input to the main control module FPGA; Step S3: Connect the digital component verification motherboard and the digital circuit test daughterboard; Step S4: Collect the attribute information of the digital component under test; Step S5: Conduct on-orbit flight tests of the digital components under test; Step S6: Under sequential logic, the FPGA main control module performs data acquisition, quantization, framing, and data comparison and analysis on the digital components under test. Step S7: The on-orbit flight data of the digital component under test is buffered by the main control module FPGA. Step S8: Transmit to the spaceborne computer via a standard transmission line; Step S9: Analyze the results and evaluate the performance using the Star Service computer software.

[0015] Preferably, step S6 includes: The main control module FPGA first acquires the output signal of the digital component under test, and then converts the digital signal by ADC or reads it directly. The collected raw data is then quantized, including normalization, anti-interference filtering, and dynamic range adjustment, and converted into standardized digital quantities. Next, the data is framed and encapsulated according to a preset frame format, which includes a synchronization header, timestamp, data type, payload, and CRC checksum. Finally, the real-time data is compared and analyzed with the pre-stored standard parameter library. The performance evaluation is completed by using dynamic threshold judgment and a three-level diagnostic strategy, and the result data with status flags is generated for subsequent processing. The three-level diagnostic strategy includes parameter checking, time series analysis and pattern recognition.

[0016] Preferably, step S9 includes: After the on-orbit flight verification is completed, key performance parameters, including timing characteristics, power consumption fluctuations and error rate, are extracted and analyzed in multiple dimensions based on the preset evaluation model. Compile all test data, error logs, and analysis results displayed by the spacecraft computer to form a verification report; The verification report includes the test results of the basic performance parameters of the digital components under test, the stability performance under different operating modes, the failure mode and failure analysis, and the evaluation and improvement suggestions for the overall verification process.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The system integrates a high-precision acquisition module and a multi-functional main control module, which can collect on-orbit operation data of digital components in all directions, and accurately evaluate the operation status through in-depth processing and analysis to ensure the stable operation of the satellite system in orbit; (2) Relational databases are used to store data, supporting multi-dimensional queries and complex condition combination queries, enabling efficient storage, fast reading and flexible retrieval of test data, meeting the multi-dimensional test data management needs of satellite digital components and improving the efficiency of verification work; (3) It adopts a motherboard-child board separation method, reserves multiple digital interfaces, and is compatible with a variety of satellite digital components; (4) FPGA enables automation and efficiency of data acquisition, quantization, framing, comparison analysis and caching operations. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A structural diagram of an on-orbit flight verification system for satellite digital components; Figure 2 Flowchart of the on-orbit flight verification steps for satellite digital components; Figure 3 This is a pinout diagram of the DAC08. Detailed Implementation

[0019] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0020] Example like Figure 1 As shown, the present invention provides an on-orbit flight verification system for satellite digital components, including a digital component verification motherboard and a digital circuit test daughterboard.

[0021] The digital component verification motherboard includes a power module, a main control module, a data acquisition module, a storage module, and a communication module. The power supply module is used to supply power to the digital component verification motherboard and the digital component test daughterboard. The power supply module includes a verification motherboard power supply unit and a test daughterboard power supply unit. The verification motherboard power supply unit supplies power to the verification motherboard; the test daughterboard power supply unit supplies power to the test daughterboard.

[0022] The acquisition module connects to the connector and the main control module to acquire attribute information of the digital components under test. The acquisition module mainly consists of a high-precision analog-to-digital converter chip, multiple analog signal input channels, signal conditioning circuit, microcontroller (MCU), and related power management circuits and communication interfaces.

[0023] Inside the acquisition module, multiple analog signal input channels are first connected to a signal conditioning circuit to complete amplification and filtering. The conditioned analog signals are then sent to the input terminal of the analog-to-digital converter chip. Under the management of the microcontroller's clock and control lines, the analog-to-digital converter chip performs high-speed A / D conversion, and its digital output is returned to the microcontroller via the data bus. The microcontroller also packages the digital signals directly sent from the FPGA and sends them to the main control module through the communication interface. The power management circuit provides the necessary power at all levels for all the above components and communication interfaces.

[0024] Multiple analog signal input channels are used to receive various analog signals generated during the testing of different satellite digital components. The signal conditioning circuit amplifies and filters the input signals to ensure that they meet the input requirements of the analog-to-digital converter (ADC). Under the control of the MCU, the ADC performs fast and synchronous A / D conversion on the signals of each channel according to the set sampling rate, accurately converting the analog signals into digital signals. The MCU collects the converted data and sends it to the main control module.

[0025] The main control module is connected to the acquisition module and the communication module. The main control module FPGA adopts a multi-compatible digital interface for implementing complex logic control and data reading from the acquisition module. The main control module includes multi-compatible LVDS, SPI, I2C, and JTAG digital interfaces and has EDAC functionality.

[0026] The communication module connects to the main control module and features dual RS422 / RS485 bus interfaces, supporting both RS422 and RS485 communication protocols. It is used for communication between the digital component verification motherboard and the spaceborne computer.

[0027] The storage module is connected to the main control module and is used to store test data of digital components. The storage module uses a PostgreSQL relational database as its storage core, creating a main table to store basic information about the digital components, including their ID, model, batch number, and production date. Corresponding sub-tables are created for different test items, containing test timestamps, test parameters, results, and status fields, and are linked to the main table via foreign keys. Data retrieval methods include querying by component ID or model to obtain all test data for that component; querying by test item type to filter all records under a specific test item; and querying by test pass / fail results to quickly locate problematic components. Simultaneously, the module provides a standard SQL query interface, supporting complex conditional queries to ensure efficient data storage and flexible retrieval, meeting the multi-dimensional test data management needs of satellite digital components.

[0028] The satellite computer is used to remotely control the satellite digital component board-level verification device to verify the components under test.

[0029] The digital component test sub-board includes a test component module and a processor module; The test component module is connected to the processor module and is used to test the on-orbit operation of digital components; The processor module connects to the connector and test component module for preprocessing data from on-orbit operation of digital components.

[0030] Furthermore, the connector is equipped with 30 pairs of LVDS interfaces for connecting the digital component verification motherboard and the digital circuit test daughterboard.

[0031] like Figure 2 As shown, the specific steps of a method for on-orbit flight verification of satellite digital components are as follows: Step S1: After power-on, the platform completes a reset and each module initializes; Step S2: An external crystal oscillator provides a clock signal, which is input to the FPGA; Step S3: Connect the digital component verification motherboard and the digital circuit test daughterboard; Step S4: Collect the attribute information of the digital component under test; Step S5: Conduct on-orbit flight tests of the digital components under test; Step S6: Under sequential logic, the FPGA performs data acquisition, quantization, framing, and data comparison analysis on the digital components under test. Step S7: The FPGA control completes the buffering of the on-orbit flight data of the digital component under test; Step S8: Transmit to the spaceborne computer via a standard transmission line; Step S9: Analyze the results and evaluate the performance using the Star Service computer software.

[0032] Step S6 includes: The main control module FPGA first acquires the output signal of the digital component under test, and converts it by ADC (if it is an analog signal) or directly reads the digital signal; then it quantizes the acquired raw data, including normalization, anti-interference filtering and dynamic range adjustment, and converts it into a standardized digital quantity; then it encapsulates the data frame according to the preset frame format (including synchronization header, timestamp, data type, payload and CRC check); finally, it compares and analyzes the real-time data with the pre-stored standard parameter library, and completes the performance evaluation by using dynamic threshold judgment and a three-level diagnostic strategy (parameter check, timing analysis and pattern recognition), and generates result data with status flags for subsequent processing.

[0033] Step S9 includes the following specific process for analyzing results and evaluating performance using on-board computer software: After the on-orbit flight verification is completed, key performance parameters (such as timing characteristics, power consumption fluctuations, error rates, etc.) are extracted, and multi-dimensional analysis is performed based on a preset evaluation model. All test data, error records, and analysis results displayed by the on-board computer are then compiled to form a detailed verification report. The verification report should include the test results of the basic performance parameters of the digital components under test, their stability performance under different operating modes, failure modes and failure analysis, and an evaluation of the overall verification process and suggestions for improvement. This provides a comprehensive and accurate basis and reference for the on-orbit application of the digital components under test.

[0034] The process of constructing the pre-defined evaluation model is as follows: 1. Model Input Feature Determination: From historical on-orbit test data and ground simulation test data, the following key performance parameters are extracted as model input features: Timing characteristics parameters include signal setup time, hold time, and clock jitter.

[0035] Power consumption fluctuation parameters include static power consumption, dynamic power consumption, and their standard deviation over a specific period.

[0036] Error rate parameters: including bit error rate and frame error rate.

[0037] Environmental parameters: including device operating temperature and radiation dose received.

[0038] 2. Model Output Definition: The model outputs a comprehensive health status score and a failure risk level for the component. The health status score is a continuous value, ranging from [0,1], where 1 represents optimal condition and 0 represents complete failure. The failure risk level is a discrete classification, such as "low risk," "medium risk," and "high risk."

[0039] 3. Model Structure Selection: An ensemble learning model based on machine learning is adopted as the core structure for evaluating the model, specifically a Random Forest model or a Gradient Boosting Decision Tree model. This model consists of multiple decision tree base learners, and the final result is output through voting or weighted averaging.

[0040] The training process for the pre-defined evaluation model is as follows: 1. Training data preparation: Collect historical datasets containing the input features and corresponding labeled "health status" and "fault risk"; 2. Model training process: Divide the dataset into a training set and a validation set according to a preset ratio (e.g., 7:3); On the training set, the model is iteratively trained using the gradient boosting algorithm. In each iteration, a new decision tree is built to fit the negative gradient (i.e., residual) of the current model, thereby gradually reducing the prediction error.

[0041] The objective function of the model Includes loss function and regularization term Specifically:

[0042] in, It is the target value corresponding to the feature vector. It is the model's prediction for the i-th sample. It is the total number of samples. It is the total number of decision trees. This represents the k-th tree. Used to control the complexity of the model to prevent overfitting.

[0043] 3. Model Validation and Optimization: Evaluate the model's performance during training on the validation set, monitoring metrics such as mean squared error; Adjust the model hyperparameters, including the maximum depth of the trees, the learning rate, and the number of trees, through cross-validation; Select the model parameter combination that performs best on the validation set to complete the model training and optimization.

[0044] The verification object in this embodiment is the 32K×16bit digital-to-analog converter DAC08, such as... Figure 3 The diagram shown is a pinout of the DAC08. The specific on-orbit flight verification process for the DAC08 is as follows: Power on the test motherboard sequentially, supplying power to core components such as the DAC08 and FPGA according to the predetermined power-on sequence, and monitoring whether the power supply voltage is stably output within the specified range. Wait for the FPGA to complete its self-test and initialization, including the startup and configuration of its internal memory and PLL module. Use a spaceborne computer to burn the pre-written FPGA program code for controlling the DAC1234 test into the FPGA's internal Flash memory module. The program should include the DAC1234's read / write control logic, data generation and processing module, and communication interface control module. After burning, reset the FPGA to ensure it correctly loads and runs the newly burned program. Inside the FPGA, the data generation module generates a specific 16-bit digital signal sequence as the input data for the DAC1234. Based on the electrical characteristics of the DAC08, set the write timing control signals. When both the DAC1234's enable signal (CE) and write enable signal (WE) are low, the generated data is sequentially written to each memory cell of the DAC1234, completing the write operation across the entire address range of 0x0000 to 0x7FFF. After the write operation is completed, the control signals are switched to put the DAC1234 into read mode, with CE and OE active low and WE high. The FPGA reads the previously written memory cell data from the DAC1234 one by one according to the set read timing. Internally, the FPGA performs an initial comparison between the read data and the previously written original data. If a discrepancy is found, the error address and related data information are immediately recorded, and an error alarm mechanism is triggered. Simultaneously, a secondary verification is performed by rereading the data at that address to determine whether it is an intermittent error or an inherent device problem. Data that passes the initial comparison is stored in the FPGA's internal FIFO memory module for buffering and organization, preparing for subsequent batch transmission to the motherboard and the spaceborne computer for further analysis. During the data storage process, the FPGA can perform some simple preprocessing. The FPGA controls the USB 2.0 module to send data to the spaceborne computer via the USB interface. A CRC check error control mechanism is used during data transmission. After receiving the data, the spaceborne computer runs the data display software to show the output analog signal characteristics of the DAC1234 in the form of waveform graphs and data tables. A detailed comparison and analysis is then performed with the theoretical expected values ​​to further verify whether the DAC1234's performance indicators meet the design requirements. After each full-address range data read / write and transmission, to avoid affecting subsequent tests, the FPGA controls the DAC08 to erase the data stored internally, restoring all memory cells to their initial state. This entire verification process, from data generation to data erasure, is repeated 10 times to simulate data read / write operations during long-term on-orbit operation. The number and types of errors occurring during the verification process are statistically analyzed to evaluate the reliability and stability of the DAC08.

[0045] After the on-orbit flight verification is completed, all test data, error records, and analysis results displayed by the onboard computer will be collected and organized to form a detailed verification report. The verification report should include the test results of the basic performance parameters of DAC1234, its stability performance under different operating modes, failure mode and failure analysis, as well as an evaluation of the overall verification process and improvement suggestions, providing a comprehensive and accurate basis and reference for the on-orbit application of DAC08.

[0046] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A satellite digital component on-orbit flight verification system, characterized in that, This includes a digital component verification motherboard, connectors, and digital circuit test sub-boards; The digital component verification motherboard is connected to the digital circuit test daughterboard via the connector; The digital component verification motherboard includes a power module, a main control module, a data acquisition module, a storage module, and a communication module. The power module is connected to the digital component verification motherboard and the digital circuit test daughterboard, and is used to supply power. The main control module is connected to the acquisition module and the communication module, and is used for logic control and data reading; The acquisition module is connected to the connector and the main control module and is used to acquire the attribute information of the digital component under test. The storage module is connected to the main control module and is used to store test data; The communication module is connected to the main control module and is used to communicate with the spacecraft computer; The spacecraft computer is connected to the communication module and is used to remotely control the verification device; The digital circuit test sub-board includes a test component module and a processor module; The test component module is connected to the processor module and is used to test the on-orbit operation of digital components; The processor module is connected to the connector and the test component module and is used to preprocess the on-orbit operating data.

2. The satellite digital component on-orbit flight verification system according to claim 1, characterized in that, The power module includes a verification motherboard power supply unit and a test daughterboard power supply unit; The power supply unit of the verification motherboard is connected to the digital component verification motherboard and is used to supply power to the verification motherboard. The power supply unit for the test sub-board is connected to the digital circuit test sub-board and is used to supply power to the test sub-board.

3. The satellite digital component on-orbit flight verification system according to claim 1, characterized in that, The acquisition module consists of an analog-to-digital converter chip, multiple analog signal input channels, a signal conditioning circuit, a microcontroller, a power management circuit, and a communication interface; The multiple analog signal input channels are connected to the signal conditioning circuit and are used to input analog signals; The signal conditioning circuit is connected to the analog-to-digital converter chip and is used to amplify and filter the analog signal; The analog-to-digital converter chip is connected to the microcontroller and is used to perform A / D conversion under the control of the microcontroller; The microcontroller is connected to the analog-to-digital converter chip and the main control module, and is used to receive digital output and package data. The power management circuit is connected to the analog-to-digital converter chip, multiple analog signal input channels, signal conditioning circuit, microcontroller, and communication interface to provide power. The communication interface is connected to the microcontroller and the main control module for data transmission. For digital signals, they are directly acquired through FPGA logic; for analog signals, they are converted by an ADC and then processed by a microcontroller.

4. The satellite digital component on-orbit flight verification system according to claim 1, characterized in that, The main control module includes multiple compatible LVDS, SPI, I2C, and JTAG digital interfaces, and also has EDAC functionality.

5. The satellite digital component on-orbit flight verification system according to claim 1, characterized in that, The storage module uses PostgreSQL relational database as its storage core; Create a main table to store basic information about digital components, including the digital component ID, model, batch number, and production date; Create data sub-tables for different test projects. The sub-tables contain test timestamp, test parameters, results and status fields, and are related to the main table through foreign keys. Data retrieval methods include querying by component ID or model, querying by test item type, and querying by test pass / fail results; It provides a standard SQL query interface and supports combined condition queries.

6. The satellite digital component on-orbit flight verification system according to claim 1, characterized in that, The communication module is equipped with dual RS422 / RS485 bus interfaces, supporting both RS422 and RS485 communication protocols.

7. The satellite digital component on-orbit flight verification system according to claim 1, characterized in that, The connector is equipped with 30 pairs of LVDS interfaces for connecting the digital component verification motherboard and the digital circuit test daughterboard.

8. A verification method for a satellite digital component on-orbit flight verification system based on any one of claims 1 to 7, characterized in that, Includes the following steps: Step S1: Reset the platform after power-on and initialize each module; Step S2: A clock signal is provided by an external crystal oscillator and input to the main control module FPGA; Step S3: Connect the digital component verification motherboard and the digital circuit test daughterboard; Step S4: Collect the attribute information of the digital component under test; Step S5: Conduct on-orbit flight tests of the digital components under test; Step S6: Under sequential logic, the FPGA main control module performs data acquisition, quantization, framing, and data comparison and analysis on the digital components under test. Step S7: The on-orbit flight data of the digital component under test is buffered by the main control module FPGA. Step S8: Transmit to the spaceborne computer via a standard transmission line; Step S9: Analyze the results and evaluate the performance using the Star Service computer software.

9. The method for on-orbit flight verification of satellite digital components according to claim 8, characterized in that, Step S6 includes: The main control module FPGA first acquires the output signal of the digital component under test, and then converts the digital signal by ADC or reads it directly. The collected raw data is then quantized, including normalization, anti-interference filtering, and dynamic range adjustment, and converted into standardized digital quantities. Next, the data is framed and encapsulated according to a preset frame format, which includes a synchronization header, timestamp, data type, payload, and CRC checksum. Finally, the real-time data is compared and analyzed with the pre-stored standard parameter library. The performance evaluation is completed by using dynamic threshold judgment and a three-level diagnostic strategy, and the result data with status flags is generated for subsequent processing. The three-level diagnostic strategy includes parameter checking, time series analysis and pattern recognition.

10. The method for on-orbit flight verification of satellite digital components according to claim 8, characterized in that, Step S9 includes: After the on-orbit flight verification is completed, key performance parameters, including timing characteristics, power consumption fluctuations and error rate, are extracted and analyzed in multiple dimensions based on the preset evaluation model. Compile all test data, error logs, and analysis results displayed by the spacecraft computer to form a verification report; The verification report includes the test results of the basic performance parameters of the digital components under test, the stability performance under different operating modes, the failure mode and failure analysis, and the evaluation and improvement suggestions for the overall verification process.

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