Method for evaluating and testing design loss of PCB (Printed Circuit Board) product

Abstract

The invention belongs to the technical field of PCB design optimization, and particularly discloses a PCB product design loss evaluation test method, which comprises the following steps: based on a design file and an electrical specification, constructing an ideal model in electromagnetic simulation software, performing simulation, and obtaining a reference insertion loss curve of a target frequency band, the method comprises the following steps: mapping a surface roughness parameter according to a copper foil model in a manufacturing process, calculating to obtain a first additional loss curve, scanning a wiring structure to identify a risk turning structure, calculating a second additional loss curve of the risk turning structure in a target frequency band, synthesizing the three curves to obtain a total loss prediction curve, and comparing the total loss prediction curve with a preset loss tolerance upper limit. Judging whether the loss performance of the PCB product meets the design requirement or not; according to the method, the ideal transmission loss, the process introduction loss and the design defect loss are systematically integrated, accurate prediction of the high-frequency loss performance of the PCB product in the design stage is realized, and a reliable basis is provided for early design decision and performance margin analysis.

Description

Technical Field

[0001] This invention belongs to the field of PCB design optimization technology and relates to a method for evaluating and testing PCB product design losses. Background Technology

[0002] With the rapid development of technologies such as 5G mobile communication and high-speed data centers, electronic systems are increasingly demanding higher signal transmission rates and integrity. As the core physical carrier for signal and power transmission, the insertion loss characteristics of high-frequency interconnect links on printed circuit boards (PCBs) have become a key factor restricting overall system performance, effective bandwidth, and transmission distance. Even slight deviations in insertion loss can lead to signal distortion, increased bit error rate, and even system malfunctions. Therefore, accurately predicting the loss performance of the final PCB product during the design phase is crucial for ensuring design success, shortening the development cycle, and controlling development costs.

[0003] Currently, the conventional method in the industry for assessing the impact of PCB design on signal loss mainly relies on fabricating physical test boards and conducting actual measurements. For example, Chinese invention patent CN119044735A discloses a scheme for an extended test board. This scheme constructs several discrete loss conditions by setting differential transmission lines with different physical characteristics (such as different lengths and line widths) on the test board, and then tests the quality of electrical signals under these preset loss conditions, providing a reference for subsequent PCB design.

[0004] However, such existing technologies based on physical templates have the following obvious limitations:

[0005] First, this method can only be implemented after the PCB design is completed and a physical prototype is manufactured, resulting in a long evaluation cycle and high costs. It cannot provide real-time feedback in the early stages of design and during rapid iteration, which seriously affects R&D efficiency. At the same time, this method can only provide test results under a limited number of pre-defined discrete loss states, and cannot predict the continuous loss curve of a specific design across its entire target operating frequency band. Therefore, it is difficult to comprehensively evaluate the performance margin of the design across the entire frequency band.

[0006] Second, the total loss measured by this method is the result of the combined effects of multiple factors, such as board characteristics, manufacturing processes (e.g., copper foil roughness), and design structure (e.g., wiring geometry). It cannot effectively separate and quantify these losses from different sources. When the test results are unsatisfactory, designers find it difficult to quickly determine whether the main cause of the excessive loss is due to material selection, process capabilities, or specific wiring design defects. This leads to an unclear direction for optimization, forcing them to rely on experience for trial and error, which is inefficient.

[0007] Therefore, there is an urgent need for an evaluation method that can be implemented in the design phase, does not rely on physical prototypes, and can continuously predict losses and effectively separate and quantify different influencing factors to solve the above-mentioned technical problems. Summary of the Invention

[0008] In view of this, in order to solve the problems mentioned in the background technology, a test method for evaluating the design loss of PCB products is proposed.

[0009] The objective of this invention can be achieved through the following technical solution: This invention provides a PCB product design loss assessment test method, comprising:

[0010] S1. Based on the original design documents of the PCB product and the target operating frequency band and key signal paths determined in the electrical design specifications, construct an ideal model of the PCB product in electromagnetic simulation software and perform simulation to obtain the reference insertion loss curve of the PCB product in the target operating frequency band.

[0011] S2. Based on the copper foil type indicated by the PCB manufacturing process data, map and obtain the corresponding surface roughness parameters, and calculate the first additional loss curve in the target operating frequency band based on the surface roughness parameters.

[0012] S3. Scan the wiring structure of the PCB product, identify all bends, extract the structural feature parameters of each bend, compare the structural feature parameters with the risk judgment threshold to identify and mark the risk bends, and calculate the second additional loss curve for the risk bends in the target operating frequency band.

[0013] S4. Combine the reference insertion loss curve, the first additional loss curve and the second additional loss curve to generate a total loss prediction curve. By comparing the total loss prediction curve with the preset loss tolerance upper limit, determine whether the loss performance of the PCB product meets the design requirements.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention constructs an ideal model in electromagnetic simulation software based on the original design file of PCB products and performs simulation to obtain a reference insertion loss curve, so as to obtain an ideal performance benchmark without relying on a physical template in the design stage, shortening the performance evaluation cycle and thus improving the efficiency of design iteration and optimization.

[0015] (2) The present invention obtains surface roughness parameters and calculates the first additional loss curve by mapping the copper foil model indicated by the PCB manufacturing process data. By quantifying the process characteristics of the copper foil into calculable loss components, the simulation prediction is elevated from an ideal model to a process-aware level, thereby improving the accuracy of loss prediction in the high-frequency band.

[0016] (3) This invention identifies the turning structure by scanning the wiring structure, extracts its structural feature parameters and compares them with the risk judgment threshold to mark the risk structure, and then calculates the second additional loss curve, realizing the quantitative assessment of the loss introduced by wiring defects, and changing the traditional mode of qualitative inspection that relies on manual experience.

[0017] (4) The present invention synthesizes the reference insertion loss curve, the first additional loss curve and the second additional loss curve to generate a total loss prediction curve, systematically integrating ideal transmission loss, process-induced loss and design defect loss, and realizes performance prediction in the design stage, providing a reliable quantitative basis for early design decisions and performance margin analysis.

[0018] (5) This invention compares the generated total loss prediction curve with the loss tolerance upper limit curve to determine whether the loss performance of the PCB product meets the design requirements. It transforms the performance acceptance from complicated data processing after actual measurement to efficient automatic analysis, ensuring the objectivity and consistency of the evaluation results. At the same time, it can quickly locate the frequency bands with excessive performance, thereby improving the efficiency of the design verification process. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram showing the connections between the steps of the method of the present invention.

[0021] Figure 2 This is a schematic diagram showing the connection of the risk turning structure identification and marking steps of the present invention.

[0022] Figure 3 This is a schematic diagram showing the connection steps for calculating the second additional loss curve in this invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This invention achieves accurate prediction and risk assessment of high-frequency losses in PCB products during the design phase through systematic decomposition and quantitative synthesis. Specifically, the method first establishes a performance benchmark for an ideal transmission line; then, it quantifies manufacturing process characteristics (i.e., copper foil surface roughness) as an independent loss increment; next, it quantifies deviations from geometric rules in the routing design as another independent loss increment; finally, it synthesizes these three factors into a total loss and compares it with the design tolerance, thereby completing performance assessment and risk identification before physical manufacturing. This solves the pain points of existing technologies, such as reliance on physical prototypes, delayed assessment, and difficulty in attribution, and realizes the pre-design verification stage.

[0025] Please see Figure 1 As shown, the PCB product design loss assessment test method provided by the present invention includes the following steps S1 to S4.

[0026] S1. Obtain a baseline insertion loss curve. This aims to establish a baseline for the loss performance of the PCB design under ideal conditions, providing a comparative basis for subsequent evaluation of additional losses introduced by process and design defects. Specifically, this includes the following steps:

[0027] S1-1. Constructing the Ideal Model: Based on the original design documents of the PCB product, reconstruct its three-dimensional geometric model in electromagnetic simulation software. The three-dimensional geometric model includes the PCB's layer stack-up structure, all transmission line paths, and via structures. In this model, conductor surfaces are defined as ideal smooth surfaces, and the geometric contours of all wiring bends are defined as ideal contours without manufacturing deviations, thereby constructing the ideal model.

[0028] To isolate the effects of manufacturing process deviations and design rule deviations, an ideal reference state must first be defined. In this model, the surface of the conductor (such as copper foil) is defined as an ideal smooth surface (i.e., ignoring all surface roughness), and the geometric profiles of all wiring bends (such as corners and curved traces) are defined as ideal profiles without manufacturing deviations, that is, ideal geometric shapes that perfectly conform to the design drawings. The model constructed in this way is called the ideal model, and its simulation results characterize the theoretically optimal transmission performance under the current stack-up and ideal geometry.

[0029] S1-2. Determine Critical Signal Paths and Configure Ports: From all transmission line paths in the ideal model, determine the critical signal paths requiring loss assessment according to the electrical design specifications. The electrical design specifications define the critical signal paths in at least one of the following ways:

[0030] (1) The protocol specifies the physical routing of high-speed differential pairs or single-ended signals required by specific industry standard protocols;

[0031] (2) Design constraint-specified paths are marked as critical networks with strict timing, loss, or impedance control requirements in the constraint management system of electronic design automation tools;

[0032] (3) Topological critical path is the signal path that is identified in the system interconnection architecture as the one with the longest link, the most fan-out, or the most complex topology, and thus is expected to have the greatest loss.

[0033] For the critical signal path, wave port excitations are set at its electrical start and end ports to define the input and output interfaces of the simulation signal.

[0034] S1-3. Perform simulation and extract curves: According to the electrical design specifications, set the target operating frequency band to the frequency sweep range of the simulation software, perform frequency domain electromagnetic field solving, and extract the insertion loss component between the starting port and the ending port. Construct the reference insertion loss curve with frequency as the abscissa and the amplitude of the insertion loss component as the ordinate. This curve represents the ideal loss performance under the current design, ignoring process and micro-design defects.

[0035] S2. Calculate the first additional loss curve, which includes the following steps:

[0036] S2-1. Obtaining surface roughness parameters: Based on the PCB manufacturing process data, determine the copper foil type used in the PCB product; according to the predefined copper foil type-surface roughness parameter mapping relationship, determine the surface roughness calculation model type corresponding to the copper foil type; based on the determined model type, obtain the model parameter set matching the copper foil type from the preset parameter database as the surface roughness parameter.

[0037] The copper foil model-surface roughness parameter mapping relationship is a database or knowledge base used to associate commercial copper foil models with high-frequency loss calculation model types and their parameter sets; the preset parameter database stores the surface roughness calculation model types and their complete model parameter sets associated with each copper foil model.

[0038] Furthermore, the mapping relationship between copper foil type and surface roughness parameters, and the parameter set in the preset parameter database, can be established through the following calibration method: For each copper foil type to be used, a standardized test structure (such as a microstrip line or stripline with a specific linewidth and length) is prepared, and the actual insertion loss curve is obtained by measuring it using a vector network analyzer. Subsequently, an ideal model of the corresponding test structure is established in electromagnetic simulation software, and a specific surface roughness model (such as the Huray model) is selected. The model parameters (such as snowball radius and density) are iteratively adjusted through optimization algorithms so that the total loss curve obtained by simulation and the measured curve achieve the best fit within the target frequency band. The model type and parameter combination that are successfully fitted are confirmed as an effective characterization of the copper foil type and stored in the database. By accumulating calibration data from different manufacturers and different models, the mapping relationship and parameter database can be constructed and continuously enriched. Those skilled in the art can establish a corresponding database for the materials used based on this disclosed calibration method, thereby realizing the present invention.

[0039] S2-2. Calculate additional loss values ​​and generate curves: Based on the surface roughness calculation model type and the surface roughness parameters, call the corresponding surface roughness loss calculation formula; take the target operating frequency band as input, and calculate the additional loss values ​​at each frequency point within the target operating frequency band using the calculation formula; then, generate the first additional loss curve with frequency as the abscissa and the additional loss value as the ordinate. This curve reflects the additional signal attenuation brought about by the selected specific copper foil and its surface treatment process throughout the entire operating frequency band.

[0040] Optionally, as a specific implementation, based on the surface roughness calculation model type (e.g., Huray snowball model) and its corresponding model parameter set determined in step S2-2, the surface roughness loss calculation formula corresponding to the model type is called.

[0041] The target operating frequency band is discretized into a series of discrete frequency points. ,in For each frequency point The model parameter set and Substituting the values ​​into the loss calculation formula of the Huray model, the additional loss value caused by surface roughness at this frequency point is calculated.

[0042] Optionally, as a specific calculation implementation method, when the surface roughness calculation model is the Huray snowball model, the model parameter set includes snowball radius R, snowball surface density N, geometric factor k, etc. The calculation of the additional loss value can be based on the following principle:

[0043] First, calculate the characteristic length scale Δ related to the snowball geometry, for example, based on the relation... The calculation is performed, where k is a geometric factor; typical values ​​range from 1.5 to 3.0. The values ​​are contained within the model parameter set obtained from the preset parameter database.

[0044] Secondly, calculate skin depth. , ,in The permeability of free space, Let be the electrical conductivity of copper. Then, the additional conductor loss coefficient introduced by surface roughness can be calculated using the following incremental resistivity formula:

[0045] ;

[0046] There is a definite conversion relationship between the additional loss value and the additional conductor loss coefficient, which can be derived through known transmission line theory models in this field, and will not be elaborated on here.

[0047] After obtaining all discrete frequency points and their corresponding additional loss values, data points are determined in a coordinate system with frequency as the x-axis and additional loss value as the y-axis. The data points are then connected using linear interpolation or curve fitting to generate a continuous first additional loss curve within the target operating frequency band.

[0048] Please see Figures 2-3 As shown, S3, calculate the second additional loss curve, which specifically includes the following steps:

[0049] S3-1. Identify and mark risky turning structures.

[0050] A topology network scan is performed on the wiring structure of the PCB product to locate the connection points of line segments where the extension direction changes in all signal line paths, and these are identified as turning structures. For each identified turning structure, its structural feature parameters are extracted, including at least the turning angle, the inner turning radius, and the line width.

[0051] From the electrical design rules, obtain the risk assessment threshold corresponding to each of the structural characteristic parameters. Compare the structural characteristic parameter of each turning structure with its corresponding risk assessment threshold; if any structural characteristic parameter does not meet its risk assessment threshold, then the turning structure is marked as a risky turning structure.

[0052] S3-2. Calculate the loss contribution value of each risk turning structure.

[0053] For each marked risky turning structure, calculate its loss contribution value at each frequency point within the target operating frequency band. The calculated loss contribution value includes:

[0054] (1) For each structural feature parameter that does not meet the threshold requirement, calculate its deviation value. The deviation value characterizes the severity of the parameter value deviating from the safe design range.

[0055] (2) Based on the type of the turning structure, query the preset unit deviation loss coefficient relationship to obtain the unit deviation loss coefficient corresponding to each frequency point. The unit deviation loss coefficient represents the additional loss caused by a specific parameter of this type of turning structure at each frequency point under a unit deviation degree.

[0056] (3) For each frequency point, multiply the unit deviation loss coefficient of all non-compliance items of the risk turning structure by its corresponding deviation value, and sum the products to obtain the loss contribution value of the risk turning structure at that frequency point.

[0057] S3-3, Generate the second additional loss curve.

[0058] The loss contribution values ​​of all risky turning structures at the same frequency point are summed to obtain the second additional loss value at each frequency point within the target operating frequency band. Based on all frequency points and their second additional loss values, a second additional loss curve is generated with frequency as the x-axis and the second additional loss value as the y-axis. This curve quantifies the cumulative loss impact of all non-ideal geometric structures in the design on the entire signal path.

[0059] Optionally, the deviation value is calculated in the following manner:

[0060] First, the risk assessment direction of each structural characteristic parameter is determined according to the electrical design rules. The risk assessment direction is used to indicate whether there is a risk if the parameter value is too small or too large.

[0061] If the risk assessment value is too small and the structural feature parameter is less than its risk assessment threshold, then the deviation value = (risk assessment threshold - structural feature parameter) / risk assessment threshold; otherwise, the deviation value is 0.

[0062] If the risk assessment value is too large and the structural characteristic parameter is greater than its risk assessment threshold, then the deviation value = (structural characteristic parameter - risk assessment threshold) / risk assessment threshold; otherwise, the deviation value is 0.

[0063] Furthermore, in one specific embodiment, based on a pre-established parametric model library, the unit deviation loss coefficient for each structural characteristic parameter at different frequencies for different turning types can be pre-determined through electromagnetic simulation and linear fitting, and stored as the preset unit deviation loss coefficient relationship for querying.

[0064] One specific method involves creating parametric models of various typical turning structures (right angle, oblique angle, circular arc, etc.) in electromagnetic simulation software; setting key characteristic parameters (such as inner radius) as variables and scanning within a certain range near their risk threshold; performing full-wave simulation within the target operating frequency band to obtain the insertion loss under different parameter values; calculating the difference between the insertion loss and the loss under ideal parameters to obtain the additional loss, and then linearly fitting this to the deviation value of the corresponding parameter. The slope of the fitted line is the unit deviation loss coefficient at that frequency point. By traversing all turning types, all key parameters, and all frequency points, a complete coefficient relationship library can be constructed. This method is a conventional simulation and data processing technique that can be implemented by those skilled in the art.

[0065] S4. Synthesize the total loss prediction curve and determine the performance.

[0066] S4-1. Total Loss Prediction Curve. In high-frequency PCB interconnect analysis, when the frequency is not extremely high enough to produce a strong nonlinear coupling effect, the components such as conductor loss, dielectric loss, and reflection / radiation loss caused by geometric discontinuities have good additivity and independence within a certain frequency band. Therefore, it is reasonable and effective to use the algebraic superposition method for synthesis.

[0067] The reference insertion loss curve, the first additional loss curve, and the second additional loss curve are obtained. At each frequency point within the target operating frequency band, the corresponding reference insertion loss value, the first additional loss value, and the second additional loss value are algebraically superimposed (arithmetic summation) to obtain the total loss prediction value for that frequency point. Based on all frequency points and their total loss prediction values, the total loss prediction curve is generated. This curve represents the complete prediction of the insertion loss performance of the final PCB product within the actual operating frequency band using the method of this invention.

[0068] S4-2. Determine whether the loss performance meets the design requirements.

[0069] Based on the electrical design rules, the maximum allowable insertion loss value of the PCB product at each frequency point within the target operating frequency band is obtained, and a loss tolerance upper limit curve is constructed accordingly.

[0070] Compare the total loss prediction curve with the loss tolerance upper limit curve:

[0071] If all points of the total loss prediction curve within the target operating frequency band are located below the upper limit curve of the loss tolerance, then the loss performance of the PCB product is determined to meet the design requirements.

[0072] If the total loss prediction curve is located above or intersects the loss tolerance upper limit curve in any sub-interval of the target operating frequency band, the loss performance of the PCB product is determined to be non-compliant with the design requirements, and the specific frequency range and the amount of overperformance are recorded.

[0073] This invention constructs a complete PCB loss assessment process implemented during the design phase through the aforementioned steps S1 to S4. By systematically integrating ideal model simulation, process characteristic quantification, and design rule deviation quantification, it provides quantitative basis and verification methods for PCB product design decisions.

[0074] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0075] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0076] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0078] Finally, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for evaluating design loss in PCB products, characterized in that: include: Based on the target operating frequency band and key signal paths determined in the original design documents and electrical design specifications of the PCB product, an ideal model of the PCB product is constructed and simulated to obtain the reference insertion loss curve of the PCB product in the target operating frequency band. Based on the copper foil type indicated by the PCB manufacturing process data, the corresponding surface roughness parameters are mapped and obtained. Based on the surface roughness parameters, the first additional loss curve in the target operating frequency band is calculated. Scan the wiring structure of the PCB product, identify all bends, extract the structural feature parameters of each bend, compare the structural feature parameters with the risk judgment threshold, identify and mark risky bends, and calculate the second additional loss curve under the target operating frequency band. The baseline insertion loss curve, the first additional loss curve, and the second additional loss curve are combined to generate a total loss prediction curve. By comparing the total loss prediction curve with the preset loss tolerance upper limit, it is determined whether the loss performance of the PCB product meets the design requirements.

2. The PCB product design loss assessment test method according to claim 1, characterized in that: The specific steps of step S1 include: Based on the original design documents of the PCB product, reconstruct the three-dimensional geometric model of the PCB product in electromagnetic simulation software; In the three-dimensional geometric model, the conductor surface is defined as an ideal smooth surface, and the geometric contours of all wiring bends are defined as ideal contours without manufacturing deviations, thereby constructing an ideal model; From all transmission line paths in the ideal model, the critical signal path is determined according to the electrical design specifications. For the critical signal path, wave port excitation is set at its start port and end port. According to the electrical design specifications, the target operating frequency band is set as the frequency sweep range of the simulation software, and frequency domain electromagnetic field solution is performed to extract the insertion loss component between the start port and the end port. A baseline insertion loss curve is constructed with frequency on the x-axis and the amplitude of the insertion loss component on the y-axis.

3. The PCB product design loss assessment test method according to claim 1, characterized in that: The acquisition of the surface roughness parameters includes: Based on the PCB manufacturing process data, the copper foil type used in the PCB product is extracted and determined; Based on the predefined copper foil type-surface roughness parameter mapping relationship, determine the corresponding surface roughness calculation model type for the copper foil type; Based on the determined surface roughness calculation model type, a set of model parameters matching the copper foil model is obtained from the preset parameter database, and the set of model parameters is used as the surface roughness parameters.

4. The PCB product design loss assessment test method according to claim 3, characterized in that: The calculation of the first additional loss curve within the target operating frequency band includes: Based on the surface roughness calculation model type and surface roughness parameters, the corresponding surface roughness loss calculation formula is called. Using the target operating frequency band as the input variable range, the additional loss value at each frequency point within the target operating frequency band is calculated using the surface roughness loss calculation formula. Sort and associate each frequency point and its corresponding additional loss value in order of frequency from low to high; The first additional loss curve is generated by plotting frequency on the x-axis and additional loss value on the y-axis.

5. The PCB product design loss assessment test method according to claim 1, characterized in that: The identification and marking of risky turning structures includes: A topology network scan is performed on the wiring structure of the PCB product to locate the connection points of line segments in all signal line paths where the extension direction changes, and these are identified as turning structures. For each identified turning structure, its structural feature parameters are extracted. The structural feature parameters include at least the turning angle, the inner turning radius, and the line width. Risk assessment thresholds for each structural characteristic parameter are obtained from electrical design rules; The structural feature parameters are compared with the corresponding risk assessment thresholds. If any of the structural feature parameters does not meet the corresponding risk assessment threshold, the turning structure is marked as a risky turning structure, and its position, non-compliance item, and specific parameter value are recorded.

6. The PCB product design loss assessment test method according to claim 1, characterized in that: The calculation of the second additional loss curve under the target operating frequency band includes: For each risk-prone turning structure, based on its structural characteristic parameters, calculate its loss contribution value at each frequency point within the target operating frequency band; The loss contribution values ​​of all risk-turning structures at the same frequency point are combined to obtain the second additional loss value at each frequency point. Based on all frequency points and their second additional loss values, a second additional loss curve is generated for the target operating frequency band.

7. The PCB product design loss assessment test method according to claim 6, characterized in that: The calculation of the loss contribution value includes: Calculate the deviation of each structural feature parameter from the corresponding risk assessment threshold; Based on the type of the turning structure, query the preset unit deviation loss coefficient relationship to obtain the unit deviation loss coefficient corresponding to each frequency point; The loss contribution value at each frequency point within the target operating frequency band is obtained by multiplying the unit deviation loss coefficient corresponding to each frequency point with the deviation value of the corresponding parameter and summing the products.

8. The PCB product design loss assessment test method according to claim 7, characterized in that: The calculation of the deviation value includes: For each structural feature parameter, the risk assessment direction is determined according to the electrical design rules of PCB products; When the risk determination direction is too small, if the structural feature parameter is less than its risk determination threshold, the difference between the risk determination threshold and the structural feature parameter is calculated, and the ratio of the difference to the risk determination threshold is used as the deviation value; otherwise, 0 is used as the deviation value. When the risk determination direction is too large, if the structural feature parameter is greater than its risk determination threshold, the difference between the structural feature parameter and the risk determination threshold is calculated, and the ratio of the difference to the risk determination threshold is used as the deviation value; otherwise, 0 is used as the deviation value.

9. The PCB product design loss assessment test method according to claim 1, characterized in that: The generated total loss prediction curve includes: Obtain the baseline insertion loss curve, the first additional loss curve, and the second additional loss curve; At each frequency point within the target operating frequency band, the reference insertion loss value, the first additional loss value, and the second additional loss value are algebraically superimposed. Based on the superposition results at all frequency points, a total loss prediction curve is generated.

10. The PCB product design loss assessment test method according to claim 1, characterized in that: The determination of whether the loss performance of the PCB product meets the design requirements includes: The maximum allowable insertion loss value of the PCB product at each frequency point in the target operating frequency band is obtained from the electrical design rules, and the upper limit curve of the loss tolerance is constructed accordingly. The total loss prediction curve and the loss tolerance upper limit curve are plotted in the same coordinate system for comparison and analysis. If all points of the total loss prediction curve within the target operating frequency band are located below the upper limit curve of the loss tolerance, then the loss performance of the PCB product is determined to meet the design requirements. If the total loss prediction curve is above or intersects the loss tolerance upper limit curve in any sub-interval of the target operating frequency band, the loss performance of the PCB product is determined to be non-compliant with the design requirements, and the frequency range and the amount of excess are recorded.

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