Write line circuit, floating data line circuit and method thereof

Abstract

A write line circuit includes a supply node configured to carry a supply voltage level; a reference node configured to carry a reference voltage level; a first input node configured to receive a first data signal; a second input node configured to receive a second data signal; a third input node configured to receive a control signal; and an output node. The write line circuit is configured to output one of the supply voltage level or the reference voltage level on the output node or float the output node in response to the first data signal, the second data signal, and the control signal. The embodiment of the invention also provides a floating data line circuit and a method thereof.

Description

[0001] This application is a divisional application, with its parent application having application number 201910451961.7, application date of May 28, 2019, and invention title "Write Line Circuit, Floating Data Line Circuit and Method Thereof". Technical Field

[0002] The embodiments of the present invention generally relate to the field of semiconductor technology, and more specifically, to write line circuits, floating data line circuits, and methods thereof. Background Technology

[0003] Memory arrays typically comprise memory cells arranged in multiple columns and rows, where multiple columns correspond to bit positions and multiple rows correspond to word positions. In this configuration, during read and write operations, multiple memory cells associated with a given word are activated at the row position corresponding to that word via one or more word lines, and data is transferred to and from multiple memory cells at the column positions corresponding to multiple bits of the given word via one or more data lines.

[0004] Input-output (I / O) circuitry is used to transfer data during read and write operations, and sometimes this I / O circuitry is shared across multiple columns within a segment of the array, where each column can be selected via switching circuitry. In some cases, one or more bits in a word are masked by the I / O circuitry, allowing data to be written to a subset of the memory cells associated with the word during a write operation. Summary of the Invention

[0005] According to one aspect of the present invention, a write line circuit is provided, comprising: a power node configured to carry a power supply voltage level; a reference node configured to carry a reference voltage level; a first input node configured to receive a first data signal; a second input node configured to receive a second data signal; a third input node configured to receive a control signal; and an output node, wherein the write line circuit is configured to perform any one of the following in response to the first data signal, the second data signal, and the control signal: outputting one of the power supply voltage level or the reference voltage level at the output node, or floating the output node.

[0006] According to another aspect of the present invention, a circuit for a floating data line is provided, comprising: a write driver coupled to a segment of a memory cell array, the write driver being configured to receive a first data signal at a first input node and generate a write line signal on the data line in response to the first data signal; and an interrupt circuit coupled between the write driver and a power node, the power node being configured to carry a power supply voltage level, wherein the interrupt circuit is configured to receive a second data signal at a second input node and disconnect the write driver from the power node in response to the second data signal.

[0007] According to another aspect of the present invention, a method for floating a data line is provided, the method comprising: receiving a first data signal at a first input node of a drive circuit coupled to the data line, a power node, and a reference node; receiving a second data signal at a second input node of the drive circuit; and disconnecting the data line from the power node and the reference node using the drive circuit in response to the first data signal and the second data signal. Attached Figure Description

[0008] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components can be arbitrarily increased or decreased.

[0009] Figure 1 This is a schematic diagram of a storage circuit according to some embodiments.

[0010] Figure 2 This is a schematic diagram of a drive circuit according to some embodiments.

[0011] Figure 3 This is a schematic diagram of a drive circuit according to some embodiments.

[0012] Figure 4 This is a schematic diagram of a pre-charge circuit according to some embodiments.

[0013] Figure 5 This is a diagram of storage circuit operation parameters according to some embodiments.

[0014] Figure 6 This is a flowchart of a method for floating data lines according to some embodiments. Detailed Implementation

[0015] The following disclosure provides several different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the invention. Other components, values, operations, materials, arrangements, etc., are also contemplated. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are formed in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relation terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another element(s) as shown in the figure. In addition to the orientations shown in the figure, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein shall be interpreted accordingly.

[0017] In various embodiments, the write line circuitry of the memory circuitry includes: a power supply and a reference node carrying power supply and reference voltage levels; first, second, and third input nodes receiving first and second data signals and a control signal; and an output node. In response to the first and second data signals and the control signal, the write line circuitry outputs either a power supply or a reference voltage level at the output node, or floats the output node.

[0018] Therefore, the write line circuitry can drive the data lines to logic high and low states during write operations; float the data lines during masked write operations; and in some embodiments, precharge the data lines to logic high states between write operations. Compared to methods that cannot float the data lines during masked write operations, the write line circuitry reduces the current in the selected memory cells and associated bit lines and data lines, thereby improving circuit reliability and energy efficiency. By precharging the data lines between write operations, the write line circuitry prevents the data lines from discharging to a reference voltage level, thus avoiding potential increases in current flow and write time.

[0019] Figure 1This is a schematic diagram of a storage circuit 100 according to some embodiments. The storage circuit 100 includes segments 110U and 110D, wherein each segment is electrically coupled to write lines WLB and WLT. Write line circuit 120B is electrically coupled to write line WLB, and write line circuit 120T is electrically coupled to write line WLT.

[0020] Two or more circuit elements are considered to be electrically coupled based on a direct electrical connection or an electrical connection that includes one or more additional circuit elements and is thus controllable, for example, made of a transistor or other switching device as a resistor or open circuit.

[0021] Storage circuitry 100 is a subset of a storage macro (not shown) that includes one or more additional components, such as at least one segment (not shown) other than segments 110U and 110D and / or at least one write line circuit (not shown) other than write line circuits 120B and 120T. In various embodiments, storage circuitry does not include one or more of segments 110U, 110D, write line circuit 120B, write line circuit 120T, write line WLB, or write line WLT.

[0022] Each of segments 110U and 110D is a segment of a memory array storing a macro and includes selection circuitry 112 electrically coupled to multiple N complementary bit line pairs BL[0..N] / BLB[0..N]. Each bit line pair BL[n] / BLB[n] is electrically coupled to a bit line precharger 114 and a plurality of memory cells 116. In various embodiments, at least one of segments 100U or 110D includes multiple individual bit lines, such as BL[0..N] or BLB[0..N], instead of multiple bit line pairs BL[0..N] / BLB[0..N].

[0023] The write lines WLB and WLT of segments 110B and 110D, as well as the bit line pair BL[0..N] / BLB[0..N], are data lines, wherein the data lines include conductive elements capable of transferring voltage levels to multiple memory cells and / or transferring voltage levels from multiple memory cells 116.

[0024] In some embodiments, each of segments 110U and 110D includes four bit line pairs. In various embodiments, one or both of segments 110U or 110D include fewer or more than four bit line pairs.

[0025] In such Figure 1 In the illustrated embodiment, segment 110U is oriented upwards relative to write line circuits 120B and 120T, and segment 110D is oriented downwards relative to write line circuits 120B and 120T. In various embodiments, segments 110U and 110D have, except... Figure 1Directions other than those shown.

[0026] In response to a selection signal (not shown) having a state corresponding to the selection of bit line pair BL[n] / BLB[n], selection circuit 112 is configured to selectively couple write line WLT to bit line BL[n] and write line WLB to bit line BLB[n]. In some embodiments, selection circuit 112 includes a multiplexer.

[0027] Bit line precharger 114 includes circuitry configured to charge the bit line pair to a power supply voltage level in response to a precharge enable signal. Section 110U is configured such that bit line precharger 114 receives a precharge enable signal BLEQB_UP on an enable line (unlabeled), and section 110D is configured such that bit line precharger 114 receives a precharge enable signal BLEQB_DN on an enable line (unlabeled).

[0028] Each plurality of storage cells 116 is arranged as a column of a storage array. In various embodiments, a column of storage cells 116 includes a plurality of storage cells 116 ranging from 128 to 1024, less than 128 or more than 1024 storage cells.

[0029] A plurality of memory cells 116 include electronic, electromechanical, electromagnetic, or other devices (not individually labeled) configured to store bit data represented by logical states. The logical states of the memory cells 116 can be programmed during write operations and detected during read operations.

[0030] In some embodiments, the logic state corresponds to the voltage level of the charge stored in a given memory cell. In some embodiments, the logic high state corresponds to the power supply voltage level of the memory circuit 100, and the logic low state corresponds to the reference voltage level of the memory circuit 100. In some embodiments, the logic state corresponds to the physical characteristics of the components of a given memory cell, such as resistance or magnetic orientation.

[0031] In some embodiments, the plurality of memory cells 116 include static random access memory (SRAM) cells. In various embodiments, the SRAM cells include five-transistor (5T) SRAM cells, six-transistor (6T) SRAM cells, eight-transistor (8T) SRAM cells, nine-transistor (9T) SRAM cells, or SRAM cells having other numbers of transistors. In some embodiments, the plurality of memory cells 116 include dynamic random access memory (DRAM) cells or other types of memory cells capable of storing bit data.

[0032] exist Figure 1Multiple word lines, represented by example word line WL[x], intersect with bit line pairs BL[0..N] / BLB[0..N]. Memory circuitry 100 is thus configured such that a given word line (e.g., word line WL[x]) is communicatively coupled to one memory cell 116 in each column of memory cells 116 of a given segment in segment 110U or 110D.

[0033] Two or more circuit elements are considered to be communicatively coupled based on direct or indirect signal connections, wherein the indirect signal connection includes one or more logic devices, such as inverters or logic gates, between the two or more circuit elements. In some embodiments, the signal communication between the two or more communicatively coupled circuit elements can be modified by one or more logic devices, such as by inversion or conditional modification.

[0034] In operation, the memory cell 116 located at the position corresponding to the bit line pair BL[n] / BLB[n] and the word line WL[x], responds to the word line signal (not marked) on the word line WL[x], and is electrically coupled to one or both of the write lines WLT or WLB through the bit line pair BL[n] / BLB[n]. In response to the selection signal having a state corresponding to the selection of the bit line pair BL[n] / BLB[n], it is electrically coupled to one or both of the write lines WLT or WLB through the corresponding selection circuit 112.

[0035] Each of the write-line circuits 120B and 120T includes a drive circuit 122 and a pre-charge circuit 124. The drive circuit 122 is electrically coupled between a power node VDD, a reference node VSS, and an output node OUT, the power node being configured to carry the power supply voltage level of the storage circuit 100, and the reference node being configured to carry the reference voltage level of the storage circuit 100. The pre-charge circuit 124 is electrically coupled between the power node VDD and the output node OUT.

[0036] In various embodiments, the memory circuitry 100 is part of a larger system, such as a system-on-a-chip, and the power supply voltage level of the memory circuitry 100 corresponds to the system's operating voltage level or to a memory-specific operating voltage level. In various embodiments, the memory circuitry 100 is part of a larger system, and the reference voltage level of the memory circuitry 100 corresponds to the system's reference voltage level or to a memory-specific reference voltage level. In some embodiments, the reference node VSS is a ground voltage node with a ground voltage level.

[0037] The drive circuit 122 is communicatively coupled to the input nodes D1 and D2 and electrically coupled to the output node OUT, and the precharge circuit 124 is communicatively coupled to the input nodes C1 and C2.

[0038] In such Figure 1In the illustrated embodiment, the write line circuit 120B is configured to receive a data signal GDT at input node D1, a data signal GDB at input node D2, a precharge enable signal BLEQB_DN at input node C1, and a precharge enable signal BLEQB_UP at input node C2, and to output a write line signal WB at an output node OUT electrically coupled to the write line WLB.

[0039] In such Figure 1 In the illustrated embodiment, the write line circuit 120T is configured to receive a data signal GDB at input node D1, a data signal GDT at input node D2, a precharge enable signal BLEQB_DN at input node C1, and a precharge enable signal BLEQB_UP at input node C2, and output a write line signal WT at an output node OUT electrically coupled to the write line WLT.

[0040] Given that the drive circuit 122 is configured to respond to the logic state of the data signals received at input nodes D1 and D2, output either a power supply voltage level or a reference voltage level at output node OUT, or float output node OUT by having a high output impedance at output node OUT.

[0041] The driving circuit 122 is configured to output a write line signal having either a power supply voltage level or a reference voltage level at the output node OUT in response to a logic state of a data signal received at the input node D1. In various embodiments, the driving circuit 122 is configured to output a write line signal having a power supply voltage level in response to one of a low or high logic state at the input node D1, and to output a write line signal having a reference voltage level in response to the other of a low or high logic state at the input node D1.

[0042] In some embodiments, the drive circuit 122 includes an inverter, as shown in the following reference. Figure 2 and Figure 3 The transistors N1 and P1 are discussed and are thus configured to output a write line signal with a power supply voltage level in response to a low logic state at input node D1, and to output a write line signal with a reference voltage level in response to a high logic state at input node D1.

[0043] In such Figure 1 In the illustrated embodiment, the write line circuit 120B includes a driver circuit 122 configured to receive a data signal GDT at an input node D1 and is thus configured to output a write line signal WB having either a power supply voltage level or a reference voltage level to the write line WLB in response to the logic state of the data signal GDT.

[0044] In such Figure 1 In the illustrated embodiment, the write line circuit 120T includes a driver circuit 122 configured to receive a data signal GDB at an input node D1 and is thus configured to output a write line signal WT having either a power supply voltage level or a reference voltage level to the write line WLT in response to the logic state of the data signal GDB.

[0045] The driving circuit 122 is configured to float the output node OUT or output a write line signal having one of a power supply voltage level or a reference voltage level in response to the logic state of the data signals received at input nodes D1 and D2. In various embodiments, the driving circuit 122 is configured to float the output node OUT in response to one or more combinations of low or high logic states at input node D1 and low or high logic states at input node D2, and to output a write line signal having one of a power supply voltage level or a reference voltage level in response to one or more other combinations of low or high logic states at input node D1 and low or high logic states at input node D2.

[0046] In such Figure 1 In the illustrated embodiment, during operation, the drive circuit 122 is configured to float the output node OUT in response to a low logic state at each of the input nodes D1 and D2, output a write line signal with a power supply voltage level in response to a low logic state at input node D1 and a high logic state at input node D2, and output a write line signal with a reference voltage level in response to a high logic state at input node D1 and a low or high logic state at input node D2.

[0047] In various embodiments, the drive circuit 122 is configured to include one or more switching devices electrically coupled to the output node OUT. Figure 1 (Not shown in the diagram) and has a high output impedance at the output node OUT. The switching device includes one or more electronic or electromechanical structures capable of establishing and disconnecting an electrical connection between two or more terminals in response to a voltage level representing a logic state received at one or more control terminals. In various embodiments, the switching device includes one or more of transistors, transmission gates, or other devices suitable for controlling the electrical connection.

[0048] In various embodiments, the transistor includes one or a combination of field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FinFETs), n-type transistors, p-type transistors, vertical-gate transistors, bipolar transistors, or other types of transistors.

[0049] In some embodiments, the drive circuit 122 includes one or more switching devices, for example, as referenced below. Figure 2 The transistor P2 under discussion is configured to selectively disconnect the drive circuit 122 from the power supply node VDD in response to a data signal received at the input node D2, and thus be able to have a high output impedance at the output node OUT at least in part.

[0050] In some embodiments, the drive circuit 122 includes one or more switching devices, for example, as referenced below. Figure 2 and Figure 3 The transistor N1 under discussion is configured to selectively disconnect the drive circuit 122 from the reference node VSS in response to a data signal received at the input node D1, and thus is at least partially able to have a high output impedance at the output node OUT.

[0051] In some embodiments, the drive circuit 122 includes one or more switching devices, for example, as referenced below. Figure 3 The transistor P3 under discussion is configured to selectively disconnect the drive circuit 122 from the output node OUT in response to data signals received at input nodes D1 and D2, and thus be able to have a high output impedance at the output node OUT at least in part.

[0052] In various embodiments, the drive circuit 122 includes one or more logic gates, for example, as referenced below. Figure 3 The illustrated XOR gate NOR1 is configured to receive data signals at one or both input nodes D1 or D2 and generate one or more switching signals capable of controlling one or more switching devices, thereby configuring the drive circuit 122 to have a high output impedance at at least partially the output node OUT. In various embodiments, the drive circuit 122 includes one or more of an inverter, an OR gate, a NOR gate, an XOR gate, an AND gate, a NAND gate, or other logic gates suitable for the applied logic scheme.

[0053] In such Figure 1 In the illustrated embodiment, the write line circuit 120B includes a driver circuit 122 configured to receive data signals GDT and GDB at corresponding input nodes D1 and D2, and thus configured to float the write line WLB or output a write line signal WB having either a power supply voltage level or a reference voltage level to the write line WLB in response to the logic state of the data signals GDT and GDB.

[0054] In such Figure 1In the illustrated embodiment, the write line circuit 120T includes a drive circuit 122 configured to receive data signals GDB and GDT at corresponding input nodes D1 and D2, and thus configured to float the write line WLT or output a write line signal WT having either a power supply voltage level or a reference voltage level to the write line WLT in response to the logic state of the data signals GDB and GDT.

[0055] Given that the precharge circuit 124 is configured to, in response to the logic state of the enable signals received at input nodes C1 and C2, output a power supply voltage level at output node OUT or float output node OUT by having a high output impedance at output node OUT. In operation, the precharge circuit 124 that floats the relevant output node OUT allows the relevant drive circuit 122 to control output node OUT, and the given drive circuit 122 that floats the relevant output node OUT allows the relevant precharge circuit 124 to control output node OUT.

[0056] Through including, for example Figure 1 The drive circuit 122 and precharge circuit 124 shown, and write line circuits 120B and 120T are configured to output a write line signal with one of the power supply voltage level or the reference voltage level at the output node OUT in response to a combination of data signals received at input nodes D1 and D2 and enable signals received at input nodes C1 and C2, or to float the output node OUT.

[0057] In various embodiments, the precharge circuit 124 is configured to output a power supply voltage level in response to one or more combinations of a low or high logic state at input node C1 and a low or high logic state at input node C2, and to float output node OUT in response to one or more other combinations of a low or high logic state at input node C1 and a low or high logic state at input node C2.

[0058] In some embodiments, one or both of the write line circuits 120B and 120T do not include one of the input nodes C1 or C2, and the precharge circuit 124 is configured to output a power supply voltage level or float the output node OUT in response to a low or high logic state at a single input node C1 or C2. In some embodiments, in addition to input nodes C1 and C2, one or both of the write line circuits 120B and 120T also include one or more input nodes (not shown), and the precharge circuit 124 is configured to output a power supply voltage level or float the output node OUT in response to a combination of low or high logic states at some or all of the input nodes.

[0059] In some embodiments, one or both of the write line circuits 120B or 120T do not include the precharge circuit 124, and one or both of the write line circuits 120B or 120T are configured to output a write line signal having one of the power supply voltage level or the reference voltage level at the output node OUT or to float the output node OUT only in response to the data signals received at the input nodes D1 and D2.

[0060] In some embodiments, the pre-charge circuit 124 includes switching devices, for example, as shown below. Figure 4 The transistor P4 under discussion is configured to selectively disconnect the output node OUT from the power supply node VDD in response to an enable signal received at the input node C1, and thus is at least partially able to have a high output impedance at the output node OUT.

[0061] In some embodiments, the pre-charge circuit 124 includes switching devices, for example, as shown below. Figure 4 The transistor P5 under discussion is configured to selectively disconnect the output node OUT from the power supply node VDD in response to an enable signal received at the input node C2, and thus is at least partially able to have a high output impedance at the output node OUT.

[0062] In some embodiments, the pre-charge circuit 124 includes a single switching device, for example, as shown below. Figure 4 One of the transistors P4 and P5 under discussion is configured to selectively disconnect the output node OUT from the power supply node VDD in response to enable signals received at both input nodes C1 and C2, and thus be able to have a high output impedance at the output node OUT at least in part. In some embodiments, the precharge circuit 124 includes one or more logic circuits (not shown) configured to control the switching devices in response to enable signals received at both input nodes C1 and C2.

[0063] In such Figure 1 In the illustrated embodiment, each write line circuit 120B and 120T includes a precharge circuit 124 configured to receive an enable signal BLEQB_DN at input node C1 and an enable signal BLEQB_UP at input node C2. Thus, write line circuit 120B is configured to output a power supply voltage level to write line WLB or float write line WLB in response to the logic states of the enable signals BLEQB_DN and BLEQB_UP, and write line circuit 120T is thereby configured to output a power supply voltage level to write line WLT or float write line WLT in response to the logic states of the enable signals BLEQB_DN and BLEQB_UP.

[0064] The storage circuit 100 is configured such that, between write operations, enable signals BLEQB_DN and BLEQB_UP are received at corresponding input nodes C1 and C2 having logic states, wherein the logic states cause the precharge circuit 124 to output a power supply voltage level to the output node OUT; and during write operations, enable signals BLEQB_DN and BLEQB_UP are available at corresponding input nodes C1 and C2 having logic states that cause the precharge circuit 124 to float the output node OUT.

[0065] Between write operations, the precharge circuit 124 outputs a power supply voltage level to the output node OUT, enabling the write line circuit 120B to maintain the write line WLB at the power supply voltage level, and enabling the write line circuit 120T to maintain the write line WLT at the power supply voltage level. During the write operation, the precharge circuit 124 floats the output node OUT, enabling the write line WLB to be controlled by the drive circuit 122 of the write line circuit 120B, and enabling the write line WLT to be controlled by the drive circuit 122 of the write line circuit 120T.

[0066] During a write operation, data bits in the selected position line pair BL[n] / BLB[n] of either segment 110U or 110D are written to memory cell 116, and memory circuit 100 is configured such that data signals GDT and GDB are received as a complementary pair. During the write operation in which data signals GDT and GDB are received as a complementary pair, based on the configuration discussed above, write line circuit 120B outputs a write line signal WB having one of the power supply voltage level or reference voltage level to write line WLB, and write line circuit 120T outputs a write line signal WT having the other of the power supply voltage level or reference voltage level to write line WLT.

[0067] During a write operation, where the selected bit line corresponding to either segment 110U or 110D of memory cell 116 masks the data bits in BL[n] / BLB[n], the memory circuit 100 is configured to receive each of the data signals GDT and GDB with a low logic state. During a write operation receiving the data signals GDT and GDB with a low logic state, based on the above configuration, the write line circuit 120B floats the write line WLB, and the write line circuit 120T floats the write line WLT.

[0068] In some embodiments, during a write operation, where the data bits in the selected bit line pair BL[n] / BLB[n] corresponding to either segment 110U or 110D of memory cell 116 are masked, memory circuit 100 is configured to receive each of data signals GDT and GDB having a high logic state, and based on the above configuration, write line circuit 120B floats write line WLB, and write line circuit 120T floats write line WLT.

[0069] As described above, in some embodiments, the memory circuit 100 is configured such that during a write operation, the selected memory cell 116 is electrically coupled to the corresponding bit line pair BL[n] / BLB[n] in response to a word line signal on the corresponding word line WL[x], and the bit line pair BL[n] / BLB[n] is electrically coupled to each write line WLT and WLB via the selection circuit 112.

[0070] In the case that the data bits are not masked during a write operation, the write line circuits 120B and 120T output corresponding write line signals WB and WT with power supply and reference voltage levels as complementary pairs, so that the data bits are written to the selected memory cell 116.

[0071] When data bits are masked during a write operation, write line circuits 120B and 120T float the corresponding write lines WLB and WLT, so that the selected memory cell 116 can be electrically coupled to the corresponding floating bit lines BLB[n] and BL[n].

[0072] Compared to methods where selected memory cells are electrically coupled to non-floating bit lines during write operations of masked data bits, such as bit lines being held at or near the power supply voltage level during write operations of masked data bits, the configuration of memory circuit 100 reduces the current in the selected cells and associated bit lines and write lines, thereby improving circuit reliability and energy efficiency.

[0073] The storage circuit 100 is configured to maintain the write lines WLB and WLT at the power supply voltage level between write operations, further realizing the benefits discussed above, thereby preventing one or both of the write lines WLB or WLT from discharging through leakage current to a voltage level at or near the reference voltage level, in which case the memory cell might be unintentionally programmed during a masked write operation.

[0074] Figure 2 This is a schematic diagram of a drive circuit 200 according to some embodiments. The drive circuit 200 can be used as a reference above. Figure 1 The driving circuit 122 is discussed. The driving circuit 200 includes PMOS transistors P1 and P2 and an NMOS transistor N1 that are series-coupled between the power supply node VDD and the reference node VSS.

[0075] Transistors N1 and P1 are configured as inverters, also known as write drivers 210, wherein the source of transistor N1 is electrically coupled to the reference node VSS, and the drain of transistor N1 is electrically coupled to the drain of transistor P1, and the gate of transistor N1 is communicatively coupled to the gate of transistor P1. The source of transistor P1 is electrically coupled to the drain of transistor P2, and the source of transistor P2 is electrically coupled to the power node VDD.

[0076] The gates of transistors N1 and P1 are communicatively coupled to the input node D1, and the drains of transistors N1 and P1 are electrically coupled to the output node OUT. Inverter INV1 is coupled between the input node D2 and the gate of transistor P2, wherein its input (unlabeled) is communicatively coupled to the input node D1, and its output (unlabeled) is communicatively coupled to the gate of transistor P2.

[0077] During operation, the gates of transistors N1 and P1 receive a low logic state of input node D1, causing transistor N1 to turn off and disconnect output node OUT from reference node VSS, while transistor P1 turns on and electrically couples output node OUT to the drain of transistor P2. Conversely, the gates of transistors N1 and P1 receive a high logic state of input node D1, causing transistor N1 to turn on and electrically couple output node OUT to reference node VSS, while transistor P1 turns off and disconnects output node OUT from the drain of transistor P2.

[0078] During operation, the low logic state of input node D2 is inverted by inverter INV1 to a high logic state at the gate of transistor P2, thereby turning off transistor P2 and disconnecting the source of transistor P1 from the power supply node VDD. Conversely, the high logic state of input node D2 is inverted by inverter INV1 to a low logic state at the gate of transistor P2, thereby turning on transistor P2 and electrically coupling the source of transistor P1 to the power supply node VDD.

[0079] Inverter INV1 and transistor P2 are also referred to as interrupt circuit 220. In some embodiments, drive circuit 200 includes interrupt circuit 220 without inverter INV1, and wherein transistor P2 is an NMOS transistor. In these embodiments, during operation, a low logic state of input node D2 turns off transistor P2, and a high logic state of input node D2 turns on transistor P2.

[0080] In operation, by turning off transistors N1 and P2, the low logic states at input nodes D1 and D2 disconnect the output node OUT from both the reference node VSS and the power supply node VDD, thereby floating the output node OUT by having high impedance at the output node OUT.

[0081] During operation, by turning off transistor N1 and turning on transistors P1 and P2, the low logic state at input node D1 and the high logic state at input node D2 disconnect the output node OUT from the reference node VSS and electrically couple the output node OUT to the power supply node VDD, thereby outputting the power supply voltage level at the output node OUT.

[0082] During operation, by turning on transistor N1 and turning off transistors P1 and P2, the high logic state at input node D1 and the low logic state at input node D2 electrically couple the output node OUT to the reference node VSS and disconnect the output node OUT from the power supply node VDD, thereby outputting the reference voltage level at the output node OUT.

[0083] During operation, by turning on transistors N1 and P2 and turning off transistor P1, the high logic state at input node D1 and the high logic state at input node D2 electrically couple the output node OUT to the reference node VSS and disconnect the output node OUT from the power supply node VDD, thereby outputting the reference voltage level at the output node OUT.

[0084] With the configuration discussed above, the drive circuit 200 can achieve the above-mentioned functions regarding the storage circuit 100 and... Figure 1 Benefits of the discussion.

[0085] Figure 3 This is a schematic diagram of a drive circuit 300 according to some embodiments. The drive circuit 300 can be used as a reference above. Figure 1 The driving circuit 122 is discussed.

[0086] The drive circuit 300 includes a write driver 210, which includes the components described above. Figure 2 The transistors N1 and P1 are discussed, but not the inverter INV1 or transistor P2 of the interrupt circuit 220. In addition to the write driver 210, the drive circuit 300 also includes node INT, XOR gate NOR1 and PMOS transistor P3.

[0087] The write driver 210 includes transistors N1 and P1 connected in series and electrically coupled between a power node VDD and a reference node VSS, wherein the source of transistor N1 is electrically coupled to the reference node VSS and the source of transistor P1 is electrically coupled to the power node VDD.

[0088] The drains of transistors N1 and P1 are electrically coupled to node INT, and transistor P3 is coupled between node INT and output node OUT. One of the sources or drains of transistor P3 is electrically coupled to node INT, and the other of the sources or drains of transistor P3 is electrically coupled to output node OUT. The gate of transistor P3 is communicatively coupled to the output (unlabeled) of XOR gate NOR1.

[0089] In addition to the output, the XOR gate NOR1 also includes two inputs (unlabeled). The first input is communicatively coupled to input node D1, and the second input is communicatively coupled to input node D2.

[0090] During operation, the gates of transistors N1 and P1 receive a low logic state of input node D1, thereby turning off transistor N1 and disconnecting node INT from the reference node VSS, and turning on transistor P1 to electrically couple the output node OUT to the power supply node VDD. Conversely, the gates of transistors N1 and P1 receive a high logic state of input node D1, thereby turning on transistor N1 and electrically coupling node INT to the reference node VSS, and turning off transistor P1 to disconnect node INT from the power supply node VDD.

[0091] During operation, the logic state received at input node D1 is received at the first input of the XOR gate NOR1, and the logic state received at input node D2 is received at the second input of the XOR gate NOR1.

[0092] In operation, for each of the low and high logic states of input node D1, the high logic state of input node D2 received at the second input of XOR gate NOR1 causes the output of XOR gate NOR1 and thus the gate of transistor P3 to be in a low logic state. In response to the low logic state at the gate of transistor P3, transistor P3 is turned on, thereby electrically coupling node INT to output node OUT.

[0093] In operation, the low logic state of input node D2 received at the second input of XOR gate NOR1 causes the output of XOR gate NOR1 and thus the gate of transistor P3 to have a logic state based on the logic state at input node D1.

[0094] In this scenario, the low logic state of input node D1 received at the first input of the XOR gate NOR1 causes the output of the XOR gate NOR1 to be connected to the gate of transistor P3, thereby turning off transistor P3 and disconnecting node INT from the output node OUT. Conversely, the high logic state of input node D1 received at the first input of the XOR gate NOR1 causes the output of the XOR gate NOR1 to be connected to the gate of transistor P3, thereby turning on transistor P3 and electrically coupling node INT to the output node OUT.

[0095] During operation, the low logic states at input nodes D1 and D2 disconnect the output node OUT from node INT through cutoff transistors N1 and P3, and thus disconnect it from both the reference node VSS and the power supply node VDD. This allows the output node OUT to float by having high impedance at the output node OUT.

[0096] During operation, the low logic state at input node D1 and the high logic state at input node D2 disconnect the output node OUT from the reference node VSS by cutting off transistor N1 and turning on transistors P1 and P3, and then electrically couple the output node OUT to the power supply node VDD via node INT, thereby outputting the power supply voltage level at the output node OUT.

[0097] During operation, the high logic state at input node D1 and the low logic state at input node D2, through the conduction of transistors N1 and P3 and the cutoff of transistor P1, electrically couple the output node OUT to the reference node VSS via node INT, and disconnect the output node OUT from the power supply node VDD, thereby outputting the reference voltage level at the output node OUT.

[0098] During operation, the high logic states at input node D1 and input node D2, through the conduction of transistors N1 and P3 and the cutoff of transistor P1, electrically couple the output node OUT to the reference node VSS via node INT, and disconnect the output node OUT from the power supply node VDD, thereby outputting the reference voltage level at the output node OUT.

[0099] With the configuration discussed above, the drive circuit 300 can achieve the above-mentioned functions regarding the storage circuit 100 and... Figure 1 Benefits of the discussion.

[0100] Figure 4 This is a schematic diagram of a pre-charge circuit 400 according to some embodiments. The pre-charge circuit 400 can be used as a reference above. Figure 1 The pre-charge circuit 124 is discussed.

[0101] The precharge circuit 400 includes PMOS transistors P4 and P5, which are series-coupled between the power node VDD and the output node OUT. The drain of transistor P4 is electrically coupled to the output node OUT, the source of transistor P4 is electrically coupled to the drain of transistor P5, and the source of transistor P5 is electrically coupled to the power node VDD. The gate of transistor P4 is communicatively coupled to the input node C1, and the gate of transistor P5 is communicatively coupled to the input node C2.

[0102] During operation, the gate of transistor P4 receives a low logic state from input node C1, thereby turning on transistor P4 and electrically coupling output node OUT to the drain of transistor P5. Conversely, the gate of transistor P4 receives a high logic state from input node C1, thereby turning off transistor P4 and disconnecting output node OUT from the drain of transistor P5, thus disconnecting it from the power supply node VDD.

[0103] During operation, the gate of transistor P5 receives a low logic state from input node C2, thereby turning on transistor P5 and electrically coupling the source of transistor P4 to power node VDD. The gate of transistor P5 receives a high logic state from input node C2, thereby turning off transistor P5 and disconnecting the source of transistor P4 from power node VDD, thus disconnecting the output node OUT from the power node.

[0104] The precharge circuit 400 is thus configured such that, during operation, a high logic state at either input node C1 or C2 disconnects the output node OUT from the power supply node VDD, and a low logic state at both input nodes C1 and C2 electrically couples the output node OUT to the power supply node VDD.

[0105] With the configuration discussed above, the pre-charge circuit 400 can achieve the above-mentioned functions regarding the storage circuit 100 and... Figure 1 Benefits of the discussion.

[0106] Figure 5 This is a diagram of storage circuit operation parameters according to some embodiments. Figure 5 The data signals GDT and GDB, enable signals BLEQB_UP and BLEQB_DN, and write line signals WB and WT are described (as shown above). Figure 1 Each of the above examples, along with two bit line voltages BL and BLB, are non-limiting examples. Bit line voltages BL and BLB represent the above-mentioned... Figure 1 Non-limiting examples of voltage levels on one of the multiple bit line pairs BL[n] / BLB[n] discussed.

[0107] The interval from time t1 to time t2 represents a first write operation, in which data bits are written to the selected memory cell 116 in segment 110U corresponding to bit line pair BL[n] / BLB[n]. The interval from time t3 to time t4 represents a second write operation, in which the selected memory cell 116 is masked. For clarity, the timing and control of various signals during the write operation are based on one or more signals not shown, such as a clock signal or a mask enable signal.

[0108] Before time t1, each of the data signals GDT and GDB is in a low logic state. At time t1, the first write operation begins, and the data signal GDT transitions from a low logic state to a high logic state, while the data signal GDB remains in a low logic state; the different logic states represent data bits. In a complementary write operation (not shown), the complementary data bit is represented by the data signal GDB, which transitions from a low logic state to a high logic state, while the data signal GDT remains in a low logic state.

[0109] At time t2, the first write operation ends, the data signal GDT changes from a logic high state back to a logic low state, and the data signal GDB remains in a logic low state.

[0110] From time t3 to time t4, each of the data signals GDT and GDB remains in a logic low state to correspond to the selected memory cell 116 that is masked in the second write operation.

[0111] From time t1 to time t2, the enable signal BLEQB_UP transitions from a logic low state to a logic high state and then returns to a logic low state, corresponding to the memory cell 116 selected in the first write operation in segment 110U. The enable signal BLEQB_DN remains in a logic low state because memory cell 116 in segment 110D was not selected in the first write operation.

[0112] From time t3 to time t4, the enable signal BLEQB_UP changes from a logic low state to a logic high state and then returns to a logic low state, corresponding to the memory cell 116 selected in the second write operation in segment 110U, while the enable signal BLEQB_DN remains in a logic low state because the memory cell 116 in segment 110D was not selected in the second write operation.

[0113] In such Figure 5 In the non-limiting example shown, the enable signal BLEQB_UP or BLEQB_DN with a logic low state corresponds to the bit line precharger 114 being activated to charge the corresponding bit line pair BL[n] / BLB[n] to the power supply voltage level. The enable signal BLEQB_UP or BLEQB_DN with a logic high state corresponds to the bit line precharger 114 being deactivated.

[0114] Therefore, during the first and second write operations, the bit line precharger 114 corresponding to the selected memory cell 116 is either deactivated based on the enable signal BLEQB_UP switching to a logic high state, or activated otherwise to charge the bit line pair BL[n] / BLB[n] corresponding to the selected memory cell 116 to the power supply voltage level. Thus, each of the bit line voltages BL and BLB is charged to a logic high state before time t1, from time t2 to time t3, and after time t4.

[0115] In such Figure 5 In the non-limiting example shown, the enable signals BLEQB_UP and BLEQB_DN, both in a logic low state, correspond to the given precharge circuit 124 outputting a power supply voltage level to the corresponding output node. The enable signals BLEQB_UP and BLEQB_DN, both in a logic high state, correspond to the given precharge circuit 124 floating the corresponding output node.

[0116] Therefore, the precharge circuit 124 of the write line circuits 120T and 120B floats the corresponding write lines WLT and WLB during the first and second write operations, and outputs the power supply voltage level to each write line WLT and WLB before time t1, from time t2 to time t3, and after time t4.

[0117] During the first and second write operations, based on the selection of memory cell 116, the bit line pair BL[n] / BLB[n] is electrically coupled to the corresponding write lines WLT and WLB. Because the bit line precharger 114 corresponding to the selected memory cell 116 is deactivated, and the write line circuits 120T and 120B float their respective write lines WLT and WLB, the write line signals WT and WB correspond to the respective bit line voltages BL and BLB during the first and second write operations.

[0118] During the first write operation, from time t1 to time t2, the write line signal WB and the bit line voltage BLB switch from logic high to logic low and back to logic high in response to receiving the data signal GDT in the high logic state and the data signal GDB in the low logic state, thereby corresponding to the drive circuit 122 in the write line circuit 120B outputting the reference voltage level to the write line WLB.

[0119] During the first write operation, from time t1 to time t2, the write line signal WT and the bit line voltage BL remain in the logic high state in response to the received low logic state data signal GDB and high logic state data signal GDT, thereby corresponding to the drive circuit 122 in the write line circuit 120T outputting the power supply voltage level to the write line WLT.

[0120] During the second write operation, from time t3 to time t4, because the bit line precharger 114 corresponding to the selected memory cell 116 is deactivated, and each of the write lines WLT and WLB is floating relative to the write line circuits 120T and 120B, the write line signals WT and WB and the bit line voltages BL and BLB are controlled by the logic state stored in the selected memory cell 116 during the first write operation.

[0121] Because the write line signal WT and the bit line voltage BL are stored in the selected memory cell 116 during the first write operation, the selected memory cell 116 keeps the write line signal WT and the bit line voltage BL in the logic high state during the second write operation.

[0122] Because the write line signal WB and the bit line voltage BLB store a logic low state in the selected memory cell 116 during the first write operation, the selected memory cell 116 shifts the write line signal WB and the bit line voltage BLB to a logic low state during the second write operation. This shifting of the write line signal WB and the bit line voltage BLB to a logic low state by the selected memory cell is also known as a virtual read operation.

[0123] The rate at which each of the write line signal WB and bit line voltage BLB moves toward a logic low state is based on the current drive capability of the selected memory cell 116, and the distributed parasitic resistance and capacitance values ​​of the write line WLB, bit line voltage BLB, and selection circuit 112 corresponding to the selected memory cell 116.

[0124] In such Figure 5 In the illustrated embodiment, since the bit line BLB[n] is between the corresponding selected memory cell 116 and the write line WLB, the distributed parasitic resistance and capacitance values ​​cause the selected memory cell 116 to move the bit line voltage BLB toward the logic low state faster than the write line WLB.

[0125] Figure 6 This is a flowchart of a method 600 for floating a data line according to one or more embodiments. Method 600 can be used in storage circuitry, for example, as referenced above. Figure 1 The storage circuit 100 is discussed.

[0126] Figure 6 The order of operations of method 600 described herein is for illustrative purposes only; the operations of method 600 can be performed in a different order. Figure 6 The sequence of execution is shown. In some embodiments, in Figure 6 Before, between, during, and / or after the operations described in the text, the execution of other operations is subject to the following conditions. Figure 6 Operations other than those described herein. In some embodiments, the operations of method 600 are a subset of the operations of methods for operating the storage circuitry.

[0127] At operation 610, in some embodiments, a pre-charge circuit is used to couple the data line to a power node. The power node carries a power supply voltage level, and coupling the data line to the power node causes the data line to have a power supply voltage level.

[0128] In some embodiments, at least one power node is one of a plurality of power nodes, a data line is one of a plurality of data lines, or a pre-charge circuit is one of a plurality of pre-charge circuits, and coupling the data line to the power node includes at least one of the following: coupling more than one of the plurality of data lines to more than one of the plurality of power nodes, or using more than one of the plurality of pre-charge circuits for coupling.

[0129] The precharge circuit couples the data lines to the power node in response to one or more logic states of a control signal or a plurality of control signals. In various embodiments, at least one of the control signals or a plurality of control signals is an enable signal, and the bit line precharger of the storage circuit responds to the enable signal by precharging the bit line pairs associated with the precharge circuit. In some embodiments, the control signal is a signal separate from the enable signal and based on one or more enable signals.

[0130] In some embodiments, one or more control signals change a logic state in response to the completion of a write operation on one or more memory cells associated with a precharge circuit. In some embodiments, the write operation includes writing data bits to each of the one or more memory cells and masking the writing of data bits to each of the one or more other memory cells.

[0131] In some embodiments, coupling the data line to the power node includes using precharge circuitry 124 to couple the write line WLB or WLT to the power node VDD, wherein each is referenced above. Figure 1 Let's have a discussion.

[0132] In some embodiments, coupling the data line to the power node includes using a switching device. In some embodiments, coupling the data line to the power node includes using the method described above. Figure 4 One or both of transistors P4 or P5 in the pre-charge circuit 400.

[0133] At operation 620, in some embodiments, a pre-charge circuit is used to disconnect the data line from the power node. For each of the above embodiments, disconnecting the data line from the power node is performed by the reverse of operation 610, which includes a pre-charge circuit with a high output impedance to the reference data line.

[0134] The precharge circuit disconnects the data line from the power node in response to one or more logic states of one or more control signals, wherein the one or more logic states are different from the one or more logic states that cause the precharge circuit to couple the data line to the power node. In some embodiments, one or more control signals change the logic state in response to the commencement of a write operation on one or more memory cells associated with the precharge circuit. In some embodiments, the write operation includes writing data bits to each of the one or more memory cells and masking the writing of data bits to each of the one or more other memory cells.

[0135] The data line is disconnected from the power node so that it can be done simultaneously with operations 630, 640 as described below and, in some embodiments, operation 660, using a pre-charge circuit to disconnect the data line from the power node.

[0136] At operation 630, a first data signal is received at a first input node of the driver circuit coupled to the data line, power node, and reference node, and a second data signal is received at a second input node of the driver circuit. The first and second data signals are generated by the storage circuit and have logic states corresponding to a write operation, in which writing data bits to the storage cell associated with the driver circuit is masked.

[0137] In various embodiments, during a masked write operation, the storage circuit generates first and second data signals, wherein each data signal has a logic low state, each data signal has a logic high state, the first data signal has a logic low state and the second data signal has a logic high state, or the first data signal has a logic high state and the second data signal has a logic low state.

[0138] In some embodiments, as referenced above Figure 1 As described in circuit 100, receiving the first and second data signals includes receiving the first and second data signals at the respective input nodes D1 and D2 of the write line circuit 120B or 120T.

[0139] In some embodiments, as referenced above Figure 2 As described in the driving circuit 200, receiving the first and second data signals includes receiving the first data signal using a write driver 210 and receiving the second data signal using an interrupt circuit 220. In some embodiments, as referenced above... Figure 3 The driving circuit 300 described above, receiving the first and second data signals includes receiving the first data signal using a write driver 210 and an XOR gate NOR1, and receiving the second data signal using an XOR gate NOR1.

[0140] At operation 640, in response to the first data signal and the second data signal, the drive circuitry is used to disconnect the data lines from the power supply node and the reference node. Disconnecting the data lines from the power supply node and the reference node includes a drive circuitry with a high output impedance for the reference data lines.

[0141] In response to first and second data signals having logic states corresponding to a write operation, the drive circuit disconnects the data line from the power node and the reference node, in which the writing of data bits to the memory cell associated with the drive circuit is masked.

[0142] In some embodiments, as referenced above Figure 1 As described in the storage circuit 100, disconnecting the data line from the power node and the reference node includes using write line circuit 120B or 120T to disconnect the write line WLB or WLT from the power node VDD and the reference node VSS.

[0143] In some embodiments, using a driver circuit to disconnect the data line from the power node includes disconnecting the data line from the power node in response to a second data signal. In some embodiments, as referenced above Figure 2 As described in the drive circuit 200, disconnecting the data line from the power node using the drive circuit includes disconnecting the write driver 210 from the power node VDD using the interrupt circuit 220.

[0144] In some embodiments, disconnecting the data line from the reference node using a driving circuit includes a driving circuit responsive to a first data signal. In some embodiments, as referenced above... Figure 1 and Figure 2 As described in drive circuits 200 and 300, disconnecting the data line from the reference node using the drive circuit includes turning off transistor N1 in response to a first data signal received at input node D1.

[0145] In some embodiments, disconnecting the data line from the power node using a driver circuit includes disconnecting the data line from the power node in response to first and second data signals. In some embodiments, as referenced above Figure 3 As described in the drive circuit 300, disconnecting the data line from the power node using the drive circuit includes disconnecting the output node OUT from the write driver 210 using an XOR gate NOR1 and a transistor P3.

[0146] At operation 650, in some embodiments, operation 610 is repeated, and a pre-charge circuit is used to couple the data line to the power node.

[0147] At operation 660, in some embodiments, the driving circuitry is configured to output a write line signal having either a power supply voltage level or a reference voltage level on the data line. Outputting a write line signal having a power supply voltage level includes outputting a power supply voltage level carried on an output power node, and outputting a write line signal having a reference voltage level includes outputting a reference voltage level carried on an output reference node.

[0148] A write line signal with one of a power supply voltage level or a reference voltage level is output on the data line in response to first and second data signals having a logic state corresponding to a write operation in which data bits are written to an unmasked memory cell associated with the drive circuit.

[0149] In various embodiments, during an unmasked write operation, the storage circuit generates first and second data signals, wherein each data signal has a logic low state, each data signal has a logic high state, the first data signal has a logic low state and the second data signal has a logic high state, or the first data signal has a logic high state and the second data signal has a logic low state.

[0150] In various embodiments, one of the power supply voltage level or reference voltage level is output on the data line after operation 650 and / or before operation 610.

[0151] By performing some or all of the operations of method 600, the data line is floated during the masked write operation, thereby obtaining the above reference. Figure 1 The benefits described in the storage circuit 100.

[0152] In some embodiments, a write line circuit includes a power node, a reference node, a first input node, a second input node, a third input node, and an output node. The power node is configured to carry a power supply voltage level, the reference node is configured to carry a reference voltage level, the first input node is configured to receive a first data signal, the second input node is configured to receive a second data signal, and the third input node is configured to receive a control signal. The write line circuit is configured to output either the power supply voltage level or the reference voltage level at the output node, or to float the output node, in response to the first data signal, the second data signal, and the third data signal. In some embodiments, when the first data signal and the second data signal have the same logic state, the write line circuit is configured to float the output node, and when the first data signal and the second data signal have different logic states, the write line circuit is configured to output either the power supply voltage level or the reference voltage level at the output node. In some embodiments, the same logic state is a low logic state. In some embodiments, the write line circuitry further includes an inverter responsive to the first data signal and a switching device coupled to the inverter, the write line circuitry being configured to float the output node by turning on the switching device in response to the second data signal. In some embodiments, the switching device is coupled between the inverter and the power node. In some embodiments, the switching device is coupled between the inverter and the output node. In some embodiments, the write line circuitry further includes a first switching device coupled between the power node and the output node, the first switching device being configured to couple the output node to the power node in response to the control signal. In some embodiments, the control signal is a first control signal among a plurality of control signals, the write line circuitry further includes a fourth input node configured to receive a second control signal among the plurality of control signals and a second switching device connected in series with the first switching device, the second switching device being configured to couple the output node to the power node in response to the second control signal among the plurality of control signals. In some embodiments, the write line circuitry is part of a storage macro, the storage macro including a storage segment configured to receive a precharge signal, and the control signal being based on the precharge signal.

[0153] In an embodiment, when the first data signal and the second data signal have the same logic state, the write line circuit is configured to float the output node, and when the first data signal and the second data signal have different logic states, the write line circuit is configured to output one of the power supply voltage level or the reference voltage level at the output node.

[0154] In this embodiment, the same logical state is a low logical state.

[0155] In one embodiment, the write line circuit further includes: an inverter responsive to the first data signal; and a switching device coupled to the inverter, and the write line circuit is configured to float the output node by disconnecting the switching device in response to the second data signal.

[0156] In one embodiment, the switching device is coupled between the inverter and the power supply node.

[0157] In one embodiment, the switching device is coupled between the inverter and the output node.

[0158] In one embodiment, the write line circuit further includes a first switching device coupled between the power node and the output node, the first switching device being configured to couple the output node to the power node in response to the control signal.

[0159] In one embodiment, the control signal is a first control signal among a plurality of control signals, and the write line circuit further includes: a fourth input node configured to receive a second control signal among the plurality of control signals; and a second switching device connected in series with the first switching device, the second switching device being configured to couple the output node to the power node in response to the second control signal among the plurality of control signals.

[0160] In one embodiment, the write line circuit is part of a storage macro, the storage macro including a storage segment configured to receive a precharge signal, and the control signal being based on the precharge signal.

[0161] In some embodiments, a circuit includes a write driver coupled to a segment of a memory cell array and an interrupt circuit coupled between the write driver and a power node configured to carry a power supply voltage level. The write driver is configured to receive a first data signal at a first input node and generate a write line signal on a data line in response to the first data signal. The interrupt circuit is configured to receive a second data signal at a second input node and disconnect the write driver from the power node in response to the second data signal. In some embodiments, the write driver is configured to float the data line when the write driver is disconnected from the power node and the first data signal has a first logic state. In some embodiments, the write driver is configured to generate the write line signal having a low logic state when the write driver is disconnected from the power node and the first data signal has a high logic state. In some embodiments, the circuit further includes a pre-charge circuit coupled between the data line and the power node, the pre-charge circuit being configured to charge the data line to the power supply voltage level in response to a control signal. In some embodiments, the precharge circuit includes a first PMOS transistor connected in series with a second PMOS transistor, the gate of the first PMOS transistor being configured to receive the control signal corresponding to a segment of the memory cell array, and the gate of the second PMOS transistor being configured to receive another control signal corresponding to another segment of the memory cell array. In some embodiments, the write driver includes an inverter. In some embodiments, the interrupt circuit includes a PMOS transistor.

[0162] In one embodiment, the write driver is configured to float the data line when the write driver is disconnected from the power node and the first data signal has a first logic state.

[0163] In one embodiment, the write driver is configured to generate the write line signal with a low logic state when the write driver is disconnected from the power node and the first data signal has a high logic state.

[0164] In one embodiment, the circuit further includes a pre-charge circuit coupled between the data line and the power node, the pre-charge circuit being configured to charge the data line to the power supply voltage level in response to a control signal.

[0165] In one embodiment, the pre-charge circuit includes a first PMOS transistor and a second PMOS transistor connected in series; the gate of the first PMOS transistor is configured to receive the control signal corresponding to a segment of the memory cell array, and the gate of the second PMOS transistor is configured to receive another control signal corresponding to another segment of the memory cell array.

[0166] In one embodiment, the write driver includes an inverter.

[0167] In one embodiment, the interrupt circuit includes a PMOS transistor.

[0168] In some embodiments, a method for floating a data line includes: receiving a first data signal at a first input node of a driver circuit coupled to the data line, a power node, and a reference node; receiving a second data signal at a second input node of the driver circuit; and using the driver circuit to disconnect the data line from the power node and the reference node in response to the first data signal and the second data signal. In some embodiments, receiving the first data signal at the first input node includes receiving the first data signal with a write driver, receiving the second data signal at the second input node includes receiving the second data signal with an interrupt circuit coupled between the write driver and the power node, and disconnecting the data line from the power node using the driver circuit includes disconnecting the write driver from the power node. In some embodiments, disconnecting the data line from the reference node is in response to the first data signal having a first logic state, and disconnecting the write driver from the power node is in response to the second data signal having the first logic state. In some embodiments, the method further includes coupling the data line to the power node using a pre-charging circuit before disconnecting the data line from the power node and the reference node using the driving circuit; and disconnecting the data line from the power node while simultaneously disconnecting the data line from the power node and the reference node using the driving circuit.

[0169] In one embodiment, receiving a first data signal at a first input node includes receiving the first data signal using a write driver; receiving a second data signal at a second input node includes receiving the second data signal using an interrupt circuit coupled between the write driver and the power node; and disconnecting the data line from the power node using the drive circuit includes disconnecting the write driver from the power node.

[0170] In one embodiment, the data line is disconnected from the reference node in response to the first data signal having a first logic state, and the write driver is disconnected from the power node in response to the second data signal having the first logic state.

[0171] In an embodiment, the method further includes using a pre-charge circuit to: couple the data line to the power node before disconnecting the data line from the power node and the reference node using the drive circuit; and disconnect the data line from the power node while simultaneously disconnecting the data line from the power node and the reference node using the drive circuit.

[0172] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments described in this invention. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways within this invention without departing from the spirit and scope of this disclosure.

Claims

1. A write line circuit, comprising: The power node is configured to carry the power supply voltage level; The reference node is configured to carry a reference voltage level; The first input node is configured to receive the first data signal; The second input node is configured to receive the second data signal; The third input node is configured to receive control signals; as well as Output node, coupled to the data line. The write line circuit is configured to perform any one of the following in response to the first data signal, the second data signal, and the control signal: Between write operations, the power supply voltage level is output to the output node, and the data line is held at the power supply voltage level, or During a write operation, the output node is floated, and a write line signal having one of the power supply voltage level or the reference voltage level is output to the data line.

2. The write line circuit according to claim 1, wherein, When the first data signal and the second data signal have the same logic state, the write line circuit is configured to float the output node, and When the first data signal and the second data signal have different logic states, the write line circuit is configured to output one of the power supply voltage level or the reference voltage level at the output node.

3. The write line circuit according to claim 1, wherein, The write line circuit also includes: Inverter, responding to the first data signal; and A switching device, coupled to the inverter, and The write line circuit is configured to float the output node by disconnecting the switching device in response to the second data signal.

4. The write line circuit according to claim 3, wherein, The switching device is coupled between the inverter and the power supply node.

5. The write line circuit according to claim 3, wherein, The switching device is coupled between the inverter and the output node.

6. The write line circuit according to claim 1, wherein, The write line circuit also includes a first switching device coupled between the power node and the output node, the first switching device being configured to couple the output node to the power node in response to the control signal.

7. The write line circuit according to claim 6, wherein, The control signal is the first control signal among a plurality of control signals, and the write line circuit further includes: The fourth input node is configured to receive the second control signal from the plurality of control signals; and A second switching device, connected in series with the first switching device, is configured to couple the output node to the power node in response to a second control signal among the plurality of control signals.

8. The write line circuit according to claim 1, wherein, The write line circuit is part of a storage macro, which includes storage segments configured to receive precharge signals, and The control signal is based on the precharge signal.

9. A circuit for a floating data line, comprising a driving circuit and a pre-charge circuit, wherein the driving circuit includes a write driver and an interrupt circuit: The write driver is coupled to a segment of the memory cell array and to an output node and a reference node. The write driver is configured to receive a first data signal at a first input node and generate a write line signal on a data line in response to the first data signal. The data line is coupled to the output node. The interrupt circuit is coupled between the write driver and the power node, the power node being configured to carry a power supply voltage level, and the reference node being configured to carry a reference voltage level. The pre-charge circuit is coupled to the output node and the power node. The interrupt circuit is configured to receive a second data signal at the second input node and, in response to the second data signal, disconnect the write driver from the power node. The pre-charge circuit is configured to charge the data line to the power supply voltage level between write operations and to float the output node during write operations. The drive circuit is configured to output a write line signal having one of the power supply voltage level or the reference voltage level to the data line during a write operation.

10. A method for floating a data cable, the method comprising: The first data signal is received at the first input node of the drive circuit coupled to the data line, power node and reference node; The second data signal is received at the second input node of the driving circuit. In response to the first data signal and the second data signal, the driving circuit is used to disconnect the data line from the power node and the reference node; Between write operations, the power supply voltage level of the power node is output to the output node coupled to the data line, and the data line is positioned at the power supply voltage level; as well as During a write operation, the output node is floated, and a write line signal having one of the power supply voltage level or the reference voltage level of the reference node is output to the data line.

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