Image sensor supporting multiple resolutions and method of operating same

Abstract

The invention provides an image sensor supporting multiple resolutions and an operation method thereof, the image sensor comprises a plurality of pixel units arranged in an array, and each pixel unit at least comprises a first pixel part, a second pixel part and a resolution regulation and control part; the first pixel part is connected with the second pixel part through the resolution regulation and control part, the first pixel part and the second pixel part are subjected to pixel merging through the resolution regulation and control part, and resolution regulation and control are achieved. According to the invention, the problem that the expected noise performance cannot be achieved when the pixels with different resolutions are merged in the signal processing stage is solved.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to an image sensor that supports multiple resolutions and its operating method. Background Technology

[0002] As image sensor pixel sizes shrink, current image sensors can support various pixel densities. For example, an image sensor with an upper limit of 200MP can support 50MP / 12.5MP image output. By utilizing variations in pixel density, a single sensor can support different lenses. Based on these requirements, it is desirable for image sensors to exhibit consistent noise performance across all resolutions. However, current technologies that perform pixel merging at different resolutions during signal processing fail to achieve this. Therefore, reducing related noise is a pressing technical problem that those skilled in the art urgently need to solve.

[0003] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an image sensor that supports multiple resolutions and its operation method, so as to solve the problem that the existing technology cannot achieve the expected noise performance when performing pixel merging at different resolutions during the signal processing stage.

[0005] To achieve the above and other related objectives, the present invention provides an image sensor supporting multiple resolutions, comprising:

[0006] A plurality of pixel units arranged in an array, each pixel unit comprising at least a first pixel portion, a second pixel portion, and a resolution adjustment portion, wherein:

[0007] The first pixel portion is connected to the second pixel portion via the resolution control portion, and the first pixel portion and the second pixel portion are merged by the resolution control portion to achieve resolution control.

[0008] Optionally, the first pixel portion includes a first photosensitive module, a first reset module, a first readout module, a first capacitance adjustment module, and a first floating diffusion node; the second pixel portion includes a second photosensitive module, a second reset module, a second readout module, a second capacitance adjustment module, and a second floating diffusion node. Each photosensitive module is connected to its corresponding floating diffusion node to convert an optical signal into a corresponding charge signal. Each reset module is connected to its corresponding floating diffusion node to reset at least the corresponding floating diffusion node. Each readout module is connected to its corresponding floating diffusion node to read out at least the corresponding charge signal. Each capacitance adjustment module is coupled to its corresponding floating diffusion node to adjust the storage capacity of its corresponding pixel portion. The resolution adjustment unit is connected between the first capacitance adjustment module and the second capacitance adjustment module.

[0009] Optionally, the first and second capacitance adjustment modules are gain conversion modules, connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel by switching different conversion gains; or, the first and second capacitance adjustment modules are charge overflow modules, connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel by receiving the charge signal overflowing from the corresponding photosensitive module.

[0010] Optionally, when the first and second tolerance modules are gain conversion modules: the resolution control unit includes at least one first switch, the control terminal of the first switch receives a first control signal, the first end of the first switch is connected to the connection node between the first tolerance module and the first reset module or connected to the end of the first tolerance module away from the first floating diffusion node, the second end of the first switch is connected to the connection node between the second tolerance module and the second reset module or connected to the end of the second tolerance module away from the second floating diffusion node; and / or, at least one reset module in each pixel unit connected to the same resolution control unit is retained, and the others are omitted.

[0011] Optionally, when the number of the first switching transistors is greater than one, the first switching transistors are connected in series.

[0012] Optionally, when the first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules: the first pixel part further includes a first charge overflow module, and the second pixel part further includes a second charge overflow module, wherein the corresponding charge overflow module is connected to the corresponding floating diffusion node and is used to receive the corresponding charge signal overflowing from the corresponding photosensitive module.

[0013] Optionally, when the first and second capacitance adjustment modules are charge overflow modules:

[0014] The resolution control unit includes a shared overflow capacitor. A first end of the shared overflow capacitor is connected to the connection node between the first capacitance adjustment module and the first reset module, and to the connection node between the second capacitance adjustment module and the second reset module; or, it is connected to the end of the first capacitance adjustment module away from the first floating diffusion node and the end of the second capacitance adjustment module away from the second floating diffusion node. The second end of the shared overflow capacitor is connected to a first potential. Alternatively, the resolution control unit includes a first overflow capacitor, a second overflow capacitor, and at least one second switching transistor. A first end of the first overflow capacitor is connected to the connection node between the first capacitance adjustment module and the first reset module, or to the end of the first capacitance adjustment module away from the first floating diffusion node. The second end of the first overflow capacitor is connected to a second potential. A first end of the second overflow capacitor is connected to the connection node between the second capacitance adjustment module and the second reset module, or to the end of the second capacitance adjustment module away from the second floating diffusion node. The second end of the second overflow capacitor is connected to a third potential. The control terminal of the second switching transistor receives a second control signal. A first end of the second switching transistor is connected to the first end of the first overflow capacitor, and a second end of the second switching transistor is connected to the first end of the second overflow capacitor.

[0015] And / or, at least one reset module in each pixel unit connected to the same resolution control unit shall be retained, and the others shall be omitted.

[0016] Optionally, the resolution control unit further includes a fast reset transistor, the control terminal of which receives a fast reset control signal, the first terminal of which is connected to a power supply potential, and the second terminal of which is connected to the second terminal of a corresponding overflow capacitor.

[0017] Optionally, the first pixel unit further includes a first gain conversion module, and the second pixel unit further includes a second gain conversion module. When the first tolerance module and the second tolerance module are connected between the corresponding reset module and the corresponding floating diffusion node, the corresponding gain conversion module is connected to the corresponding floating diffusion node. When the first tolerance module and the second tolerance module are connected to the corresponding floating diffusion node, the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, for switching different conversion gains.

[0018] Optionally, when the corresponding gain conversion module is connected to the corresponding floating diffusion node, both the first gain conversion module and the second gain conversion module include a gain transistor and a gain capacitor. The control terminal of the gain transistor receives a gain control signal, the first terminal of the gain transistor is connected to the corresponding floating diffusion node, and the second terminal of the gain transistor is connected to a fourth potential via the gain capacitor. In the at least two pixel units in the same column, the second terminals of the gain transistors in each of the first pixel units are connected to each other, and the second terminals of the gain transistors in each of the second pixel units are connected to each other.

[0019] When the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, both the first gain conversion module and the second gain conversion module include a gain transistor. The control terminal of the gain transistor receives a gain control signal. The first terminal of the gain transistor is connected to the corresponding reset module, and the second terminal of the gain transistor is connected to the corresponding floating diffusion node. In at least two pixel units in the same column, the first terminals of the gain transistors in each of the first pixel units are connected to each other, and the first terminals of the gain transistors in each of the second pixel units are connected to each other.

[0020] The present invention also provides an operation method for an image sensor supporting multiple resolutions as described in any one of the above claims, comprising:

[0021] In the pixel merging mode, the resolution control unit merges the first pixel portion and the second pixel portion, so that the first pixel portion and the second pixel portion work together to obtain the pixel signal.

[0022] Optionally, it also includes: a pixel-independent mode, in which the connection between the first pixel portion and the second pixel portion is cut off by the resolution control unit, so that the first pixel portion and the second pixel portion can operate independently to acquire pixel signals respectively.

[0023] Optionally, the process of acquiring pixel signals includes a reset stage, an exposure stage, and a quantization readout stage, wherein the quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and quantization readout of pixel signals under charge overflow.

[0024] Optionally, when in the pixel merging mode;

[0025] If pixel merging is performed under low conversion gain, the specific readout method includes: merging the first pixel portion and the second pixel portion through the resolution control unit, and performing correlation double sampling after merging the first potential well charge signal and the second potential well charge signal;

[0026] If pixel merging is performed under charge overflow, the specific readout method includes: performing pixel merging on the first pixel part and the second pixel part through the resolution control unit, and performing non-true correlation double sampling after merging the first overflow charge signal and the second overflow charge signal;

[0027] When in the pixel-independent mode, the specific readout methods include:

[0028] At low conversion gain, the first potential well charge signal and the second potential well charge signal are respectively subjected to correlation double sampling;

[0029] At high conversion gain, the first potential well charge signal and the second potential well charge signal are respectively subjected to correlation double sampling;

[0030] Under charge overflow, non-true correlation double sampling is performed on the first overflow charge signal and the second overflow charge signal respectively.

[0031] As described above, the multi-resolution image sensor and its operating method of the present invention can reduce the correlation noise of the signal by combining the signal of the charge domain within the pixel, so that the image sensor has approximately the same noise performance at each resolution, which is beneficial to improving image quality. Attached Figure Description

[0032] Figure 1 The diagram shown is a structural schematic of a pixel unit in Embodiment 1 of the present invention.

[0033] Figure 2 This is a schematic diagram of another structure of the pixel unit in Embodiment 1 of the present invention.

[0034] Figure 3 This is a schematic diagram of another structure of the pixel unit in Embodiment 1 of the present invention.

[0035] Figure 4 This is a schematic diagram of another structure of the pixel unit in Embodiment 1 of the present invention.

[0036] Figure 5 The diagram shown is a structural schematic of a pixel unit in Embodiment 2 of the present invention.

[0037] Figure 6 This is a schematic diagram of another structure of the pixel unit in Embodiment 2 of the present invention.

[0038] Figure 7 This is a schematic diagram of another structure of the pixel unit in Embodiment 2 of the present invention.

[0039] Figure 8 This is a schematic diagram of another structure of the pixel unit in Embodiment 2 of the present invention.

[0040] Figure 9 This is a schematic diagram showing the structure of multiple pixel units in the same column sharing nodes in Embodiment 2 of the present invention.

[0041] Figure 10 The diagram shown is a structural schematic of a pixel unit in Embodiment 3 of the present invention.

[0042] Figure 11 This is a schematic diagram of another structure of the pixel unit in Embodiment 3 of the present invention.

[0043] Figure 12 This is a schematic diagram of another structure of the pixel unit in Embodiment 3 of the present invention.

[0044] Figure 13 This is a schematic diagram of another structure of the pixel unit in Embodiment 3 of the present invention.

[0045] Figure 14 This is a schematic diagram showing the structure of multiple pixel units in the same column sharing nodes in Embodiment 3 of the present invention.

[0046] Component designation explanation

[0047] 100 pixel unit

[0048] 110 First pixel section

[0049] 111 First photosensitive module

[0050] 112 First Reset Module

[0051] 113 First Readout Module

[0052] 114 First Capacity Adjustment Module

[0053] 115 First Charge Overflow Module

[0054] 116 First Gain Conversion Module

[0055] 120 Second pixel section

[0056] 121 Second photosensitive module

[0057] 122 Second Reset Module

[0058] 123 Second Readout Module

[0059] 124 Second Capacity Adjustment Module

[0060] 125 Second charge overflow module

[0061] 126 Second Gain Conversion Module

[0062] 130 Resolution Control Department Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. The term "coupling" mentioned in this application can refer to a direct connection or a connection via other transistors, which can be understood according to the specific solution, as is known to those skilled in the art.

[0064] Please see Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] Example 1

[0066] like Figures 1-4 As shown, this embodiment provides an image sensor that supports multiple resolutions, including a plurality of pixel units 100 arranged in an array; wherein, the pixel unit 100 includes at least a first pixel portion 110, a second pixel portion 120 and a resolution adjustment portion 130.

[0067] The first pixel unit 110 is connected to the second pixel unit 120 via the resolution control unit 130. The first pixel unit 110 and the second pixel unit 120 are merged through the resolution control unit 130 to achieve resolution control. In this embodiment, pixel merging is performed in the charge domain, which helps to reduce noise performance at various resolutions and improve image quality at various resolutions. It should be noted that the pixel unit 100 may also include multiple pixel units, such as a third pixel unit, a fourth pixel unit, etc., and the number of them is set according to needs. When there are multiple pixel units, the pixel units are connected through the resolution control unit 130 to perform signal merging.

[0068] As an example, the first pixel unit 110 includes a first photosensitive module 111, a first reset module 112, a first readout module 113, a first tolerance module 114, and a first floating diffusion node FD1, such as Figure 1As shown. Wherein: a first photosensitive module 111 is connected to a first floating diffusion node FD1, used to convert an optical signal into a first charge signal; a first reset module 112 is connected to the first floating diffusion node FD1, used to reset at least the first floating diffusion node FD1; a first readout module 113 is connected to the first floating diffusion node FD1, used to read out at least the first charge signal; a first tolerance module 114 is coupled to the first floating diffusion node FD1, for example, the first tolerance module 114 is connected between the first reset module 112 and the first floating diffusion node FD1, or the first tolerance module 114 is connected to the first floating diffusion node FD1. In this case, both the first tolerance module 114 and the first reset module 112 are each connected to the first floating diffusion node FD1. The first tolerance module 114 is used to adjust the storage capacity of the first pixel unit 110. In a specific example, the first tolerance module 114 is a gain conversion module, which adjusts the storage capacity of the first pixel unit 110 by switching different conversion gains (e.g., low conversion gain and high conversion gain). Furthermore, the first pixel unit 110 also includes a first charge overflow module 115, connected to the first floating diffusion node FD1, for receiving a first charge signal (i.e., a first overflow charge signal) overflowing from the first photosensitive module 111, such as... Figures 2-4 As shown; at this time, the first charge signal includes a first potential well charge signal and a first overflow charge signal, wherein the first potential well charge signal is stored in the first photosensitive module 111 and the first overflow charge signal is stored in the first charge overflow module 115.

[0069] The second pixel unit 120 includes a second photosensitive module 121, a second reset module 122, a second readout module 123, a second tolerance module 124, and a second floating diffusion node FD2, such as Figure 1As shown. Wherein: the second photosensitive module 121 is connected to the second floating diffusion node FD2, used to convert the light signal into a second charge signal; the second reset module 122 is connected to the second floating diffusion node FD2, used to reset at least the second floating diffusion node FD2; the second readout module 123 is connected to the second floating diffusion node FD2, used to read out at least the second charge signal; the second tolerance module 124 is coupled to the second floating diffusion node FD2, for example, the second tolerance module 124 is connected between the second reset module 122 and the second floating diffusion node FD2, or the second tolerance module 124 is connected to the second floating diffusion node FD2. In this case, both the second tolerance module 124 and the second reset module 122 are each connected to the second floating diffusion node FD2. The second tolerance module 124 is used to adjust the storage capacity of the second pixel unit 120. In a specific example, the second tolerance module 124 is a gain conversion module, which adjusts the storage capacity of the second pixel unit 120 by switching different conversion gains (e.g., low conversion gain and high conversion gain). Furthermore, the second pixel unit 120 also includes a second charge overflow module 125, connected to the second floating diffusion node FD2, for receiving a second charge signal (i.e., a second overflow charge signal) overflowing from the second photosensitive module 121, such as... Figures 2-4 As shown; at this time, the second charge signal includes a second potential well charge signal and a second overflow charge signal, wherein the second potential well charge signal is stored in the second photosensitive module 121 and the second overflow charge signal is stored in the second charge overflow module 125.

[0070] Specifically, the first photosensitive module 111 and the second photosensitive module 121 have the same circuit structure, including at least one transmission transistor and at least one photosensitive element. In one optional embodiment, they include eight transmission transistors M11 to M18 and eight photosensitive elements PD1 to PD8. Of course, including other numbers of transmission transistors and photosensitive elements is also feasible. Each transmission transistor corresponds one-to-one with a photosensitive element. The control terminal of the transmission transistor receives a corresponding transmission control signal. The first terminal of the transmission transistor is connected to a corresponding floating diffusion node, and the second terminal of the transmission transistor is connected to a reference potential (e.g., reference ground) via the photosensitive element. Figures 1-4 As shown. In practical applications, the resolution of the image sensor is adjusted by changing the number of photosensitive elements involved in the calculation.

[0071] The first reset module 112 and the second reset module 122 have the same circuit structure, including a reset transistor M2; wherein, the control terminal of the reset transistor M2 receives the reset control signal RST, the first terminal of the reset transistor M2 is connected to the power supply potential, and the second terminal of the reset transistor M2 is connected to the corresponding floating diffusion node, such as... Figures 1-4 As shown.

[0072] The first readout module 113 and the second readout module 123 have the same circuit structure, including a source follower transistor M3 and a select transistor M4; wherein, the control terminal of the source follower transistor M3 is connected to the corresponding floating diffusion node, the first terminal of the source follower transistor M3 is connected to the power supply potential, the second terminal of the source follower transistor M3 is connected to the first terminal of the select transistor M4, the control terminal of the select transistor M4 receives the select control signal SEL, and the second terminal of the select transistor M4 is connected to the column line, such as... Figures 1-4 As shown.

[0073] The first capacitance adjustment module 114 and the second capacitance adjustment module 124 have the same circuit structure, including a gain transistor M5. When the corresponding capacitance adjustment module is connected between the corresponding reset module and the corresponding floating diffusion node, the control terminal of the gain transistor M5 receives a gain control signal DCG. The first terminal of the gain transistor M5 is connected to the corresponding reset module, and the second terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, as shown below. Figures 1-3 As shown. When the corresponding capacitance adjustment module is connected to the corresponding floating diffusion node, the control terminal of the gain transistor M5 receives the gain control signal DCG. The first terminal of the gain transistor M5 is connected to the resolution adjustment unit 130, and the second terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, as shown. Figure 4 As shown.

[0074] The first charge overflow module 115 and the second charge overflow module 125 have the same circuit structure, including an overflow transistor M6 and an overflow capacitor Cof; wherein, the control terminal of the overflow transistor M6 receives an overflow control signal OF, the first terminal of the overflow transistor M6 is connected to a corresponding floating diffusion node, and the second terminal of the overflow transistor M6 is connected to a fifth potential (e.g., a variable potential) via the overflow capacitor Cof. Figures 2-4 As shown, of course, in other implementations, the first charge overflow module 115 and the second charge overflow module 125 may not exist, such as... Figure 1 As shown.

[0075] In the above example, each pixel unit connected to the same resolution control unit 130 includes its own reset module. For example, the first pixel unit 110 includes a first reset module 112, and the second pixel unit 120 includes a second reset module 122. In practical applications, each pixel unit connected to the same resolution control unit 130 may not all include its own reset module, as long as at least one reset module is guaranteed. In this case, at least one reset module is retained in each pixel unit connected to the same resolution control unit 130, and the other reset modules are omitted. For example, the reset module of either the first pixel unit 110 or the second pixel unit 120 is retained, and the reset module of the other is omitted.

[0076] The resolution control unit 130 is connected between the first tolerance module 114 and the second tolerance module 124. For example, it is connected between the connection node of the first tolerance module 114 and the first reset module 112 and the connection node of the second tolerance module 124 and the second reset module 122, or it is connected between the end of the first tolerance module 114 away from the first floating diffusion point FD1 and the end of the second tolerance module 124 away from the second floating diffusion point FD2. Specifically, the resolution control unit 130 includes at least one first switching transistor M7; in one embodiment, the control terminal of the first switching transistor M7 receives a first control signal CTL1, the first end of the first switching transistor M7 is connected to the connection node of the first tolerance module 114 and the first reset module 112, and the second end of the first switching transistor M7 is connected to the connection node of the second tolerance module 124 and the second reset module 122, such as... Figures 1-3 As shown; in another embodiment, the control terminal of the first switch M7 receives the first control signal CTL1, the first terminal of the first switch M7 is connected to the end of the first capacitance module 114 away from the first floating diffusion node FD1, and the second terminal of the first switch M7 is connected to the end of the second capacitance module 124 away from the second floating diffusion node FD2, as shown. Figure 4 As shown. In this embodiment, when the gain transistor M5 is turned on, the first switch M7 can be turned on to perform pixel merging on the first pixel unit 110 and the second pixel unit 120. That is, the first pixel unit 110 and the second pixel unit 120 perform pixel merging by sharing a single LCG (low conversion gain) node through the resolution control unit 130. Of course, by turning off the first switch M7, the first pixel unit 110 and the second pixel unit 120 can also work independently.

[0077] In practical applications, when the number of first switching transistors M7 is greater than one, the first switching transistors M7 are connected in series, such as... Figure 3 As shown; at this time, the first control signal CTL1 received by the control terminal of each first switch transistor M7 is usually partially the same and partially different. Thus, when the first pixel unit 110 and the second pixel unit 120 work independently, by controlling the on and off states of each first switch transistor M7, the storage capacity of the first pixel unit 110 and the second pixel unit 120 can be adjusted when the gain transistor M5 is turned on, thereby obtaining more conversion gain.

[0078] It should be noted that, in one embodiment of the pixel unit 100 of this embodiment, each transistor is an NMOS transistor. In this case, the control terminal is the gate terminal, the first terminal is the drain terminal, the second terminal is the source terminal, and the photosensitive element is a photodiode. Of course, in other embodiments, it is also feasible for each transistor to be a PMOS transistor, and it is also feasible for the photosensitive element to be a grating or a photoconductor.

[0079] In addition, the image sensor of this embodiment includes not only the circuit structure described above, but also an optical structure, wherein the optical structure is located on the upper or lower surface of the circuit structure; in a specific example, the optical structure includes a plurality of color filter units, each color filter unit corresponding to each pixel unit 100, and allows visible light of a specific color to pass through, for example, allowing red light, filtered light or blue light to pass through in order to form a Bayer color array.

[0080] Accordingly, this embodiment also provides an operation method for an image sensor that supports multiple resolutions, including at least a pixel merging mode and further including a pixel independent mode; wherein the image sensor is implemented using the structure described above.

[0081] In the pixel merging mode, the resolution control unit 130 merges the first pixel unit 110 and the second pixel unit 120. During this mode, the first switch M7 in the resolution control unit 130 is turned on, causing the first pixel unit 110 and the second pixel unit 120 to work together to acquire pixel signals. The pixel merging mode includes a reset stage, an exposure stage, and a quantization readout stage. This mode includes at least one step of merging and reading out the first pixel unit 110 and the second pixel unit 120 through the resolution control unit 130 to obtain image information in the merged mode. Of course, it is understood that the operation of this mode may also include a process of separately reading out the signals from the first pixel unit 110 and the second pixel unit 120.

[0082] During the reset phase, the first photosensitive module 111, the first floating diffusion node FD1, and the first capacitance module 114 are reset via the first reset module 112, and the second photosensitive module 121, the second floating diffusion node FD2, and the second capacitance module 124 are reset via the second reset module 122. Furthermore, the first charge overflow module 115 is reset via the first reset module 112, and the second charge overflow module 125 is reset via the second reset module 122.

[0083] For example, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121, the gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124, and the overflow transistor M6 in the first charge overflow module 115 and the second charge overflow module 125 are turned on, and the reset transistor M2 in the first reset module 112 and the second reset module 122 is turned on, so as to clear the charge of the first photosensitive module 111, the first floating diffusion node FD1, the first capacitance adjustment module 114, the first charge overflow module 115, the second photosensitive module 121, the second floating diffusion node FD2, the second capacitance adjustment module 124 and the second charge overflow module 125; then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121, the gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124, and the reset transistor M2 in the first reset module 112 and the second reset module 122 are turned off.

[0084] During the exposure stage, the first potential well charge signal is stored by the first photosensitive module 111, and the second potential well charge signal is stored by the second photosensitive module 121; furthermore, the first overflow charge signal is stored by the first charge overflow module 115, and the second overflow charge signal is stored by the second charge overflow module 125.

[0085] For example, when the amount of charge sensed by the first photosensitive module 111 has not reached the overflow state, the first charge signal only includes the first potential well charge signal, and the first overflow charge signal is zero. At this time, the first potential well charge signal is stored in the first photosensitive module 111, and no first overflow charge signal is stored in the first charge overflow module 115. When the amount of charge sensed by the first photosensitive module 111 reaches the overflow state, the first charge signal includes the first potential well charge signal and the first overflow charge signal. At this time, the first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first charge overflow module 115. After that, the overflow transistor M6 in the first charge overflow module 115 is turned off. Similarly, when the charge sensed by the second photosensitive module 121 has not reached the overflow state, the second charge signal only includes the second potential well charge signal, and the second overflow charge signal is zero. At this time, the second potential well charge signal is stored in the second photosensitive module 121, and no second overflow charge signal is stored in the second charge overflow module 125. When the charge sensed by the second photosensitive module 121 reaches the overflow state, the second charge signal includes the second potential well charge signal and the second overflow charge signal. At this time, the second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second charge overflow module 125. Then, the overflow transistor M6 in the second charge overflow module 125 is turned off. It should be noted that at the end of the reset phase, the overflow transistor M6 in the first charge overflow module 115 and the second charge overflow module 125 is not turned off, so as to facilitate charge overflow during the exposure phase.

[0086] The quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and further includes quantization readout of pixel signals under charge overflow.

[0087] In the low conversion gain scenario, the resolution control unit 130 merges the first pixel unit 110 and the second pixel unit 120, and performs correlation double sampling after merging the first potential well charge signal and the second potential well charge signal. It should be noted that the low gain in this application refers to the low gain corresponding to a larger capacitance relative to the floating diffusion node, and the specific low gain value can be determined based on actual operation. In the high conversion gain scenario, the first potential well charge signal and the second potential well charge signal are respectively subjected to correlation double sampling. In the case of charge overflow, the resolution control unit 130 merges the first pixel unit 110 and the second pixel unit 120, and performs non-true correlation double sampling after merging the first overflow charge signal and the second overflow charge signal, or performs non-true correlation double sampling for the first overflow charge signal and the second overflow charge signal respectively. In the case of charge overflow, the merged readout or independent readout can be controlled by the resolution control unit.

[0088] The following is a specific operating method:

[0089] The gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment increase module 124 is turned on. Since the first switch transistor M7 in the resolution adjustment unit 130 is turned on, the first pixel unit 110 and the second pixel unit 120 enter a low conversion gain and achieve pixel merging. Then, the selection transistor M4 in the first readout module 113 or the second readout module 123 is turned on and then turned off. Under the low conversion gain, the first potential well reset signal and the second potential well reset signal are merged and quantized for readout.

[0090] Subsequently, the gain transistor M5 in the first capacitance modulation module 114 and the second capacitance modulation module 124 is turned off, causing the first pixel portion 110 and the second pixel portion 120 to enter high conversion gain and temporarily cutting off pixel merging. The selection transistor M4 in the first readout module 113 and the second readout module 123 is turned on, and the first potential well reset signal and the second potential well reset signal are quantized and read out respectively under high conversion gain. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are turned on and then turned off. The first potential well charge signal and the second potential well charge signal are quantized and read out respectively under high conversion gain through the first readout module 113 and the second readout module 123, thereby realizing the respective correlation double sampling of the first potential well charge signal and the second potential well charge signal under high conversion gain. After completion, the selection transistor M4 in the first readout module 113 and the second readout module 123 is turned off.

[0091] Subsequently, the gain transistor M5 in the first capacitance modulation module 114 and the second capacitance modulation module 124 is turned on again, causing the first pixel part 110 and the second pixel part 120 to enter a low conversion gain and re-implement pixel merging. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are turned on and then turned off. The selection transistor M4 in the first readout module 113 or the second readout module 123 is turned on. Under low conversion gain, the first potential well charge signal and the second potential well charge signal are merged and quantized for readout, thereby realizing correlation double sampling after merging the first potential well charge signal and the second potential well charge signal under low conversion gain.

[0092] Finally, the overflow transistor M6 in the first charge overflow module 115 and the second charge overflow module 125 is turned on, and the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are turned on and then turned off. The first overflow charge signal and the second overflow charge signal are combined and quantized for reading through the first readout module 113 or the second readout module 123. Then, the reset transistor M2 in the first reset module 112 and the second reset module 122 is turned on and then turned off to reset the first charge overflow module 115 and the second charge overflow module 125. The first overflow reset signal and the second overflow reset signal are combined and quantized for reading through the first readout module 113 or the second readout module 123, thereby realizing a non-true correlation double sampling after the first overflow charge signal and the second overflow charge signal are combined under charge overflow.

[0093] It should be noted that in pixel merging mode, the first switch M7 in the resolution control unit 130 is always in the on state. Of course, it is also feasible for the first switch M7 to be in the off state during the reset and exposure stages and only in the on state during the quantization readout stage. In addition, the selection transistor M4 in the first readout module 113 and the second readout module 123 can also be controlled differently, as long as the relevant signals are read out normally.

[0094] In the pixel-independent mode, the connection between the first pixel unit 110 and the second pixel unit 120 is severed by the resolution control unit 130. At this time, the first switch M7 in the resolution control unit 130 is turned off, allowing the first pixel unit 110 and the second pixel unit 120 to operate independently and acquire pixel signals respectively. The pixel-independent mode includes a reset stage, an exposure stage, and a quantization readout stage. In this mode, turning off at least one first switch M7 enables signal readout between pixel units, obtaining high-resolution pixel information. Of course, if multiple first switches M7 exist, other non-turned-off first switches M7 corresponding to each pixel unit can be used to adjust their gain, which can help optimize the gain mode.

[0095] Specifically, the quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and further includes quantization readout of pixel signals under charge overflow. Specifically, under low conversion gain, the first potential well charge signal and the second potential well charge signal are subjected to correlation double sampling respectively; under high conversion gain, the first potential well charge signal and the second potential well charge signal are subjected to correlation double sampling respectively; under charge overflow, the first overflow charge signal and the second overflow charge signal are subjected to non-true correlation double sampling respectively.

[0096] It should be noted that when the first pixel unit 110 and the second pixel unit 120 operate independently, their control is the same; and, in the pixel independent mode, the on / off control of each transistor in the first pixel unit 110 and the second pixel unit 120 at each stage is roughly the same as the on / off control of each transistor in the first pixel unit 110 and the second pixel unit 120 at each stage in the pixel merging mode, so it will not be described again here.

[0097] Example 2

[0098] like Figures 5 to 8 As shown, this embodiment provides an image sensor that supports multiple resolutions. The difference from Embodiment 1 is that the first tolerance module 114 in the first pixel unit 110 and the second tolerance module 124 in the second pixel unit 120 are changed from gain conversion modules to charge overflow modules. The first pixel unit 110 also includes a first gain conversion module 116, and the second pixel unit 120 also includes a second gain conversion module 126. Furthermore, the circuit structure of the resolution control unit 130 is different.

[0099] The first pixel unit 110 includes a first photosensitive module 111, a first reset module 112, a first readout module 113, a first tolerance module 114, and a first floating diffusion node FD1. The first tolerance module 114 is a charge overflow module connected between the first reset module 112 and the first floating diffusion node FD1. It adjusts the storage capacity of the first pixel unit 110 by receiving a first charge signal overflowing from the first photosensitive module 111. The first charge signal includes a first potential well charge signal and a first overflow charge signal. The first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first tolerance module 114. Furthermore, the first pixel unit 110 also includes a first gain conversion module 116 connected to the first floating diffusion node FD1, used to switch between different conversion gains (e.g., low conversion gain and high conversion gain).

[0100] The second pixel unit 120 includes a second photosensitive module 121, a second reset module 122, a second readout module 123, a second tolerance module 124, and a second floating diffusion node FD2. The second tolerance module 124 is a charge overflow module connected between the second reset module 122 and the second floating diffusion node FD2. It adjusts the storage capacity of the second pixel unit 120 by receiving a second charge signal overflowing from the second photosensitive module 121. The second charge signal includes a second potential well charge signal and a second overflow charge signal. The second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second tolerance module 124. Furthermore, the second pixel unit 120 also includes a second gain conversion module 126 connected to the second floating diffusion node FD2, used to switch between different conversion gains (e.g., low conversion gain and high conversion gain).

[0101] Specifically, the first capacitance adjustment module 114 and the second capacitance adjustment module 124 have the same circuit structure, including an overflow transistor M6; wherein, the control terminal of the overflow transistor M6 receives an overflow control signal OF, the first terminal of the overflow transistor M6 is connected to the corresponding reset module, and the second terminal of the overflow transistor M6 is connected to the corresponding floating diffusion node.

[0102] The first gain conversion module 116 and the second gain conversion module 126 have the same circuit structure, including a gain transistor M5 and a gain capacitor Cdcg; wherein, the control terminal of the gain transistor M5 receives the gain control signal DCG, the first terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, and the second terminal of the gain transistor M5 is connected to the fourth potential V4 (e.g., a variable potential) via the gain capacitor Cdcg.

[0103] Furthermore, the first photosensitive module 111, the first reset module 112, and the first readout module 113 in the first pixel unit 110, and the second photosensitive module 121, the second reset module 122, and the second readout module 123 in the second pixel unit 120 are the same as in Embodiment 1, and will not be described again here.

[0104] In the above example, each pixel unit connected to the same resolution control unit 130 includes its own reset module. For example, the first pixel unit 110 includes a first reset module 112, and the second pixel unit 120 includes a second reset module 122. In practical applications, each pixel unit connected to the same resolution control unit 130 may not all include its own reset module, as long as at least one reset module is guaranteed. In this case, at least one reset module is retained in each pixel unit connected to the same resolution control unit 130, and the other reset modules are omitted. For example, the reset module of either the first pixel unit 110 or the second pixel unit 120 is retained, and the reset module of the other is omitted.

[0105] The resolution control unit 130 is connected between the first capacitance adjustment module 114 and the second capacitance adjustment module 124, and has the following different circuit structures.

[0106] In one implementation, such as Figure 5As shown, the resolution control unit 130 includes a shared overflow capacitor Cof; wherein, the first end of the shared overflow capacitor Cof is connected to the connection node between the first capacitance adjustment module 114 and the first reset module 112 and the connection node between the second capacitance adjustment module 124 and the second reset module 122, and the second end of the shared overflow capacitor Cof is connected to a first potential V1 (e.g., a variable potential). In this embodiment, when the overflow transistor M6 is turned on, pixel merging of the first pixel part 110 and the second pixel part 120 can be realized based on the shared overflow capacitor Cof, that is, the first pixel part 110 and the second pixel part 120 are merged by the resolution control unit 130 in a manner that shares a single overflow capacitor node.

[0107] In another implementation, such as Figure 6 As shown, the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2, and at least one second switch M8; wherein, the first end of the first overflow capacitor Cof1 is connected to the connection node of the first capacitance adjustment module 114 and the first reset module 112, the second end of the first overflow capacitor Cof1 is connected to the second potential V2 (e.g., a variable potential), the first end of the second overflow capacitor Cof2 is connected to the connection node of the second capacitance adjustment module 124 and the second reset module 122, the second end of the second overflow capacitor Cof2 is connected to the third potential V3 (e.g., a variable potential), the control terminal of the second switch M8 receives the second control signal CTL2, the first end of the second switch M8 is connected to the first end of the first overflow capacitor Cof1, and the second end of the second switch M8 is connected to the first end of the second overflow capacitor Cof2. In this embodiment, when the overflow transistor M6 is turned on, the first pixel unit 110 and the second pixel unit 120 can be merged by controlling the second switch M8 to turn on. Of course, the first pixel unit 110 and the second pixel unit 120 can also work independently by controlling the second switch M8 to turn off. Through the design of the second switch M8, the first pixel unit 110 and the second pixel unit 120 can be configured with different overflow capacitors.

[0108] In practical applications, the number of second switching transistors M8 can be one or more than one; when the number of second switching transistors M8 is greater than one, the second switching transistors M8 are connected in series, see [reference needed]. Figure 2 The connection method of the first switching transistor M7; at this time, the second control signal CTL2 received by the control terminal of each second switching transistor M8 is usually partially the same and partially different. Thus, when the first pixel unit 110 and the second pixel unit 120 work independently, by controlling the conduction and turn-off status of each second switching transistor M8, the storage capacity of the first pixel unit 110 and the second pixel unit 120 can be adjusted when the overflow transistor M6 is turned on, thereby obtaining more conversion gain.

[0109] Furthermore, such as Figure 7 As shown, the resolution control unit 130 also includes a fast reset transistor M9. When the resolution control unit 130 includes a shared overflow capacitor Cof, the control terminal of the fast reset transistor M9 receives a fast reset control signal OF_RST. The first terminal of the fast reset transistor M9 is connected to the power supply potential VDD, and the second terminal of the fast reset transistor M9 is connected to the second terminal of the shared overflow capacitor Cof. In this case, the second terminal of the shared overflow capacitor Cof is no longer connected to the first potential V1. When the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2, and at least one second switching transistor M8, the control terminal of the fast reset transistor M9 receives a fast reset control signal OF_RST. The first terminal of the fast reset transistor M9 is connected to the power supply potential VDD, and the second terminal of the fast reset transistor M9 is connected to the second terminals of the first overflow capacitor Cof1 and the second terminals of the second overflow capacitor Cof2. In this case, the second terminal of the first overflow capacitor Cof1 is no longer connected to the second potential V2, and the second terminal of the second overflow capacitor Cof2 is no longer connected to the third potential V3. Through the design of the fast reset transistor M9, fast reset can be achieved by controlling the fast reset transistor M9 to conduct when resetting the corresponding overflow capacitor. Alternatively, when the fast reset transistor M9 is present, the first reset module 112 or the second reset module 122 can be omitted, such as... Figure 8 The example shown is an example where the second reset module 122 is omitted.

[0110] Optionally, such as Figure 9 As shown, for the image sensor of this embodiment, in at least two pixel units 100 in the same column, the second terminals of each gain transistor M5 in each first pixel part 110 are connected to each other, and the second terminals of each gain transistor M5 in each second pixel part 120 are connected to each other. In this way, each pixel unit 100 can realize the sharing of gain capacitors. For example, the low gain terminals of two pixel parts in adjacent rows are shared, and the gain node of the required row can be borrowed during readout.

[0111] Accordingly, this embodiment also provides an operation method for an image sensor that supports multiple resolutions, including at least a pixel merging mode; wherein, if the image sensor adopts Figure 5 , Figure 7 or Figure 8 The structure shown only includes pixel merging mode in its operation method; if the image sensor uses... Figure 6 Given the structure shown, the operation method can include not only pixel merging mode but also pixel independent mode.

[0112] For the pixel merging mode: the resolution control unit 130 merges the first pixel unit 110 and the second pixel unit 120, so that the first pixel unit 110 and the second pixel unit 120 work together to obtain pixel signals; wherein, the pixel merging mode includes a reset stage, an exposure stage, and a quantization readout stage. In this mode, at least one step is included in which the resolution control unit 130 merges and reads out the first pixel unit 110 and the second pixel unit 120 to obtain image information in the merging mode. Of course, it can be understood that the operation of this mode may also include a process of reading out the signals in the first pixel unit 110 and the second pixel unit 120 separately. It should be noted that the reset stage and exposure stage of the pixel merging mode in this embodiment are the same as the reset stage and exposure stage of the pixel merging mode in Embodiment 1, and will not be described again here. Only the quantization readout stage will be described.

[0113] The quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and quantization readout of pixel signals under charge overflow. Specifically, under low conversion gain, the first and second potential well charge signals are subjected to correlation double sampling respectively; under high conversion gain, the first and second potential well charge signals are subjected to correlation double sampling respectively; under charge overflow, the resolution control unit performs pixel merging on the first and second pixel portions, and the first overflow charge signal and the second overflow charge signal are merged and then subjected to non-true correlation double sampling.

[0114] For example, the gain transistor M5 in the first gain conversion module 116 and the second gain conversion module 126 is turned on, so that the first pixel part 110 and the second pixel part 120 enter a low conversion gain. Then, the selection transistor M4 in the first readout module 113 and the second readout module 123 is turned on, and the first potential well reset signal and the second potential well reset signal are quantized and read out respectively under the low conversion gain.

[0115] Subsequently, the gain transistor M5 in the first gain conversion module 116 and the second gain conversion module 126 is turned off, causing the first pixel 110 and the second pixel 120 to enter a high conversion gain. The first potential well reset signal and the second potential well reset signal are quantized and read out respectively by the first readout module 113 and the second readout module 123 under the high conversion gain. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are turned on and then turned off. The first potential well charge signal and the second potential well charge signal are quantized and read out respectively by the first readout module 113 and the second readout module 123 under the high conversion gain, thereby realizing the respective correlation double sampling of the first potential well charge signal and the second potential well charge signal under the high conversion gain.

[0116] Subsequently, the gain transistor M5 in the first gain conversion module 116 and the second gain conversion module 126 is turned on again, causing the first pixel 110 and the second pixel 120 to enter a low conversion gain. The transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are turned on and then turned off, so that the first potential well charge signal and the second potential well charge signal can be quantized and read out by the first readout module 113 and the second readout module 123 under low conversion gain, thereby realizing the correlation double sampling of the first potential well charge signal and the second potential well charge signal under low conversion gain. After completion, the selection transistor M4 in the first readout module 113 and the second readout module 123 is turned off.

[0117] Finally, the overflow transistor M6 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124 is turned on, enabling pixel merging of the first pixel portion 110 and the second pixel portion 120. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are turned on and then turned off. The selection transistor M4 in the first readout module 113 or the second readout module 123 is turned on, and the first overflow charge signal and the second overflow charge signal are merged and quantized for readout. Then, the reset transistor M2 in the first reset module 112 and the second reset module 122 is turned on and then turned off, resetting the first capacitance adjustment module 114 and the second capacitance adjustment module 124. The first overflow reset signal and the second overflow reset signal are merged and quantized for readout through the first readout module 113 or the second readout module 123, thereby realizing non-true correlated double sampling after merging the first overflow charge signal and the second overflow charge signal under charge overflow.

[0118] It should be noted that in pixel merging mode, for Figure 5 , Figure 7 or Figure 8 The structure shown only requires the overflow transistor M6 to be turned on, while for Figure 6 The structure shown requires the second switch M8 to always be in the on state. Of course, it is also feasible for the second switch M8 to be in the off state during the reset and exposure stages and only in the on state during the quantization readout stage. In addition, the selection transistor M4 in the first readout module 113 and the second readout module 123 can also be controlled differently, as long as the relevant signals are read out normally.

[0119] For the pixel-independent mode: the connection between the first pixel unit 110 and the second pixel unit 120 is disconnected by the resolution control unit 130. At this time, the second switch M8 in the resolution control unit 130 is turned off, allowing the first pixel unit 110 and the second pixel unit 120 to operate independently to acquire pixel signals respectively. The pixel-independent mode includes a reset stage, an exposure stage, and a quantization readout stage. In this mode, turning off at least one second switch M8 enables signal readout between pixel units, obtaining high-resolution pixel information. Of course, if multiple second switches M8 exist, the gain of each pixel unit can be adjusted by utilizing other non-turned-off second switches M8 corresponding to it, which can help optimize the gain mode.

[0120] Specifically, the quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and quantization readout of pixel signals under charge overflow. Specifically, under low conversion gain, correlation double sampling is performed on the first and second potential well charge signals respectively; under high conversion gain, correlation double sampling is performed on the first and second potential well charge signals respectively; under charge overflow, non-true correlation double sampling is performed on the first and second overflow charge signals respectively.

[0121] It should be noted that when the first pixel unit 110 and the second pixel unit 120 operate independently, their control is the same; and, in the pixel independent mode, the on / off control of each transistor in the first pixel unit 110 and the second pixel unit 120 at each stage is roughly the same as the on / off control of each transistor in the first pixel unit 110 and the second pixel unit 120 at each stage in the pixel merging mode, so it will not be described again here.

[0122] Example 3

[0123] like Figures 10 to 13 As shown, this embodiment provides an image sensor that supports multiple resolutions. The difference from Embodiment 1 is that the first tolerance module 114 in the first pixel unit 110 and the second tolerance module 124 in the second pixel unit 120 are changed from gain conversion modules to charge overflow modules. The first pixel unit 110 also includes a first gain conversion module 116, and the second pixel unit 120 also includes a second gain conversion module 126. Furthermore, the circuit structure of the resolution control unit 130 is different.

[0124] The first pixel unit 110 includes a first photosensitive module 111, a first reset module 112, a first readout module 113, a first tolerance module 114, and a first floating diffusion node FD1. The first tolerance module 114 is a charge overflow module connected to the first floating diffusion node FD1. It adjusts the storage capacity of the first pixel unit 110 by receiving a first charge signal overflowing from the first photosensitive module 111. The first charge signal includes a first potential well charge signal and a first overflow charge signal. The first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first tolerance module 114. Further, the first pixel unit 110 also includes a first gain conversion module 116 connected between the first reset module 112 and the first floating diffusion node FD1, or connected to the first floating diffusion node FD1, for switching different conversion gains (e.g., low conversion gain and high conversion gain).

[0125] The second pixel unit 120 includes a second photosensitive module 121, a second reset module 122, a second readout module 123, a second tolerance module 124, and a second floating diffusion node FD2. The second tolerance module 124 is a charge overflow module connected to the second floating diffusion node FD2. It adjusts the storage capacity of the second pixel unit 120 by receiving a second charge signal overflowing from the second photosensitive module 121. The second charge signal includes a second potential well charge signal and a second overflow charge signal. The second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second tolerance module 124. Furthermore, the second pixel unit 120 also includes a second gain conversion module 126 connected between the second reset module 122 and the second floating diffusion node FD2, or connected to the second floating diffusion node FD2, for switching different conversion gains (e.g., low conversion gain and high conversion gain).

[0126] Specifically, the first capacitance adjustment module 114 and the second capacitance adjustment module 124 have the same circuit structure, including an overflow transistor M6; wherein, the control terminal of the overflow transistor M6 receives an overflow control signal OF, the first terminal of the overflow transistor M6 is connected to the corresponding floating diffusion node, and the second terminal of the overflow transistor M6 is connected to the resolution adjustment unit 130, as shown below. Figures 10-13 As shown.

[0127] The first gain conversion module 116 and the second gain conversion module 126 have the same circuit structure; when the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, it includes a gain transistor M5. The control terminal of the gain transistor M5 receives a gain control signal DCG. The first terminal of the gain transistor M5 is connected to the corresponding reset module, and the second terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, such as... Figures 10-12As shown; when the corresponding gain conversion module is connected to the corresponding floating diffusion node, it includes a gain transistor M5 and a gain capacitor Cdcg. The control terminal of the gain transistor M5 receives a gain control signal. The first terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, and the second terminal of the gain transistor M5 is connected to a fourth potential via the gain capacitor Cdcg, as shown. Figure 13 As shown.

[0128] Furthermore, the first photosensitive module 111, the first reset module 112, and the first readout module 113 in the first pixel unit 110, and the second photosensitive module 121, the second reset module 122, and the second readout module 123 in the second pixel unit 120 are the same as in Embodiment 1, and will not be described again here.

[0129] In the above example, each pixel unit connected to the same resolution control unit 130 includes its own reset module. For example, the first pixel unit 110 includes a first reset module 112, and the second pixel unit 120 includes a second reset module 122. In practical applications, each pixel unit connected to the same resolution control unit 130 may not all include its own reset module, as long as at least one reset module is guaranteed. In this case, at least one reset module is retained in each pixel unit connected to the same resolution control unit 130, and the other reset modules are omitted. For example, the reset module of either the first pixel unit 110 or the second pixel unit 120 is retained, and the reset module of the other is omitted.

[0130] The resolution control unit 130 is connected between the first capacitance adjustment module 114 and the second capacitance adjustment module 124, and has the following different circuit structures.

[0131] In one implementation, such as Figure 10 As shown, the resolution control unit 130 includes a shared overflow capacitor Cof; wherein, the first end of the shared overflow capacitor Cof is connected to the end of the first capacitance adjustment module 114 away from the first floating diffusion node FD1, and is connected to the end of the second capacitance adjustment module 124 away from the second floating diffusion node FD2, and the second end of the shared overflow capacitor Cof is connected to a first potential V1 (e.g., a variable potential). In this embodiment, when the overflow transistor M6 is turned on, pixel merging of the first pixel part 110 and the second pixel part 120 can be realized based on the shared overflow capacitor Cof, that is, the first pixel part 110 and the second pixel part 120 are pixel merged by the resolution control unit 130 in a manner that shares a single overflow capacitor node.

[0132] In another implementation, such as Figure 11As shown, the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2, and at least one second switch M8; wherein, the first end of the first overflow capacitor Cof1 is connected to the end of the first capacitance adjustment module 114 away from the first floating diffusion node FD1, the second end of the first overflow capacitor Cof1 is connected to a second potential V2 (e.g., a variable potential), the first end of the second overflow capacitor Cof2 is connected to the end of the second capacitance adjustment module 124 away from the second floating diffusion node FD2, the second end of the second overflow capacitor Cof2 is connected to a third potential V3 (e.g., a variable potential), the control terminal of the second switch M8 receives a second control signal CTL2, the first end of the second switch M8 is connected to the first end of the first overflow capacitor Cof1, and the second end of the second switch M8 is connected to the first end of the second overflow capacitor Cof2. In this embodiment, when the overflow transistor M6 is turned on, the first pixel unit 110 and the second pixel unit 120 can be merged by controlling the second switch M8 to turn on. Of course, the first pixel unit 110 and the second pixel unit 120 can also work independently by controlling the second switch M8 to turn off. Through the design of the second switch M8, the first pixel unit 110 and the second pixel unit 120 can be configured with different overflow capacitors.

[0133] In practical applications, the number of second switching transistors M8 can be one or more than one; when the number of second switching transistors M8 is greater than one, the second switching transistors M8 are connected in series, see [reference needed]. Figure 2 The connection method of the first switching transistor M7; at this time, the second control signal CTL2 received by the control terminal of each second switching transistor M8 is usually partially the same and partially different. Thus, when the first pixel unit 110 and the second pixel unit 120 work independently, by controlling the conduction and turn-off status of each second switching transistor M8, the storage capacity of the first pixel unit 110 and the second pixel unit 120 can be adjusted when the overflow transistor M6 is turned on, thereby obtaining more conversion gain.

[0134] Furthermore, such as Figure 12As shown, the resolution control unit 130 also includes a fast reset transistor M9. When the resolution control unit 130 includes a shared overflow capacitor Cof, the control terminal of the fast reset transistor M9 receives a fast reset control signal OF_RST. The first terminal of the fast reset transistor M9 is connected to the power supply potential VDD, and the second terminal of the fast reset transistor M9 is connected to the second terminal of the shared overflow capacitor Cof. In this case, the second terminal of the shared overflow capacitor Cof is no longer connected to the first potential V1. When the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2, and at least one second switching transistor M8, the control terminal of the fast reset transistor M9 receives a fast reset control signal OF_RST. The first terminal of the fast reset transistor M9 is connected to the power supply potential VDD, and the second terminal of the fast reset transistor M9 is connected to the second terminals of the first overflow capacitor Cof1 and the second terminals of the second overflow capacitor Cof2. In this case, the second terminal of the first overflow capacitor Cof1 is no longer connected to the second potential V2, and the second terminal of the second overflow capacitor Cof2 is no longer connected to the third potential V3. Through the design of the fast reset transistor M9, fast reset can be achieved by controlling the fast reset transistor M9 to conduct when resetting the corresponding overflow capacitor. Alternatively, when a fast reset transistor M9 is present, the first reset module 112 or the second reset module 122 can be omitted.

[0135] Optionally, for the image sensor of this embodiment: when the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, in at least two pixel units 100 in the same column, the first terminals of each gain transistor M5 in each first pixel portion 110 are connected to each other, and the first terminals of each gain transistor M5 in each second pixel portion 120 are connected to each other. In this way, each pixel unit 100 can achieve gain capacitance sharing, such as... Figure 14 As shown. When the corresponding gain conversion module is connected to the corresponding floating diffusion node, in at least two pixel units 100 in the same column, the second terminals of each gain transistor M5 in each first pixel part 110 are connected to each other, and the second terminals of each gain transistor M5 in each second pixel part 120 are connected to each other, so that each pixel unit 100 can achieve gain capacitor sharing.

[0136] Accordingly, this embodiment also provides an operation method for an image sensor that supports multiple resolutions, including at least a pixel merging mode; wherein, if the image sensor adopts Figure 10 , Figure 12 or Figure 13 The structure shown only includes pixel merging mode in its operation method; if the image sensor uses... Figure 11 The structure shown allows for the operation method to include both pixel merging and pixel independence modes. It should be noted that the pixel merging and pixel independence modes in this embodiment are the same as in Embodiment 2, and will not be described again here.

[0137] It should be noted that the pixel merging mode and pixel independent mode provided by this invention can be selected according to actual needs, such as considering resolution requirements. Different operating modes may include different information under merged signals and independent signals. The actual readout data is not contradictory in different modes. In practical applications, the corresponding signals can be read out according to the circuit structure as needed. When both merged and independent modes need to be read out, the reset stage and exposure stage can be shared. Different modes are read out only in the readout stage. Image information at different resolutions can be obtained in a single frame. Based on the design of this invention, readout at different resolutions can be achieved, which can reduce noise and noise differences at different resolutions and improve the quality of the final acquired image.

[0138] In summary, the multi-resolution image sensor and its operating method of the present invention, through signal merging operations within the charge domain of pixels, can reduce correlated noise of the signals, enabling the image sensor to exhibit approximately the same noise performance at various resolutions, thus improving image quality. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0139] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor supporting multiple resolutions, characterized in that, include: A plurality of pixel units arranged in an array, each pixel unit comprising at least a first pixel portion, a second pixel portion, and a resolution adjustment portion, wherein: The first pixel portion is connected to the second pixel portion via the resolution control portion, and the first pixel portion and the second pixel portion are merged by the resolution control portion to achieve resolution control.

2. The multi-resolution image sensor according to claim 1, characterized in that, The first pixel unit includes a first photosensitive module, a first reset module, a first readout module, a first capacitance adjustment module, and a first floating diffusion node. The second pixel unit includes a second photosensitive module, a second reset module, a second readout module, a second capacitance adjustment module, and a second floating diffusion node. Each photosensitive module is connected to a corresponding floating diffusion node to convert light signals into corresponding charge signals. Each reset module is connected to a corresponding floating diffusion node to reset at least the corresponding floating diffusion node. Each readout module is connected to a corresponding floating diffusion node to read out at least the corresponding charge signals. Each capacitance adjustment module is coupled to a corresponding floating diffusion node to adjust the storage capacity of the corresponding pixel unit. The resolution adjustment unit is connected between the first capacitance adjustment module and the second capacitance adjustment module.

3. The multi-resolution image sensor according to claim 2, characterized in that, The first and second capacitance adjustment modules are gain conversion modules, connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel by switching different conversion gains; or, the first and second capacitance adjustment modules are charge overflow modules, connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel by receiving the charge signal overflowing from the corresponding photosensitive module.

4. The multi-resolution image sensor according to claim 3, characterized in that, When the first and second tolerance modules are gain conversion modules: the resolution control unit includes at least one first switch transistor, the control terminal of the first switch transistor receives a first control signal, the first end of the first switch transistor is connected to the connection node between the first tolerance module and the first reset module or connected to the end of the first tolerance module away from the first floating diffusion node, the second end of the first switch transistor is connected to the connection node between the second tolerance module and the second reset module or connected to the end of the second tolerance module away from the second floating diffusion node; and / or, at least one reset module in each pixel unit connected to the same resolution control unit is retained, and the others are omitted.

5. The multi-resolution image sensor according to claim 4, characterized in that, When the number of the first switching transistors is greater than one, the first switching transistors are connected in series.

6. The multi-resolution image sensor according to claim 3, characterized in that, When the first tolerance module and the second tolerance module are gain conversion modules: the first pixel part further includes a first charge overflow module, and the second pixel part further includes a second charge overflow module, wherein the corresponding charge overflow module is connected to the corresponding floating diffusion node and is used to receive the corresponding charge signal overflowing from the corresponding photosensitive module.

7. The multi-resolution image sensor according to claim 3, characterized in that, When the first and second capacitance adjustment modules are charge overflow modules: The resolution control unit includes a shared overflow capacitor. A first end of the shared overflow capacitor is connected to the connection node between the first capacitance adjustment module and the first reset module, and to the connection node between the second capacitance adjustment module and the second reset module; or, it is connected to the end of the first capacitance adjustment module away from the first floating diffusion node and the end of the second capacitance adjustment module away from the second floating diffusion node. The second end of the shared overflow capacitor is connected to a first potential. Alternatively, the resolution control unit includes a first overflow capacitor, a second overflow capacitor, and at least one second switching transistor. A first end of the first overflow capacitor is connected to the connection node between the first capacitance adjustment module and the first reset module, or to the end of the first capacitance adjustment module away from the first floating diffusion node. The second end of the first overflow capacitor is connected to a second potential. A first end of the second overflow capacitor is connected to the connection node between the second capacitance adjustment module and the second reset module, or to the end of the second capacitance adjustment module away from the second floating diffusion node. The second end of the second overflow capacitor is connected to a third potential. The control terminal of the second switching transistor receives a second control signal. A first end of the second switching transistor is connected to the first end of the first overflow capacitor, and a second end of the second switching transistor is connected to the first end of the second overflow capacitor. And / or, at least one reset module in each pixel unit connected to the same resolution control unit shall be retained, and the others shall be omitted.

8. The multi-resolution image sensor according to claim 7, characterized in that, The resolution control unit also includes a fast reset transistor. The control terminal of the fast reset transistor receives a fast reset control signal. The first terminal of the fast reset transistor is connected to the power supply potential, and the second terminal of the fast reset transistor is connected to the second terminal of the corresponding overflow capacitor.

9. The multi-resolution image sensor according to claim 7, characterized in that, The first pixel unit further includes a first gain conversion module, and the second pixel unit further includes a second gain conversion module. When the first tolerance module and the second tolerance module are connected between the corresponding reset module and the corresponding floating diffusion node, the corresponding gain conversion module is connected to the corresponding floating diffusion node. When the first tolerance module and the second tolerance module are connected to the corresponding floating diffusion node, the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, for switching different conversion gains.

10. The multi-resolution image sensor according to claim 9, characterized in that, When the corresponding gain conversion module is connected to the corresponding floating diffusion node, both the first gain conversion module and the second gain conversion module include a gain transistor and a gain capacitor. The control terminal of the gain transistor receives a gain control signal, the first terminal of the gain transistor is connected to the corresponding floating diffusion node, and the second terminal of the gain transistor is connected to a fourth potential via the gain capacitor. In at least two pixel units in the same column, the second terminals of the gain transistors in each of the first pixel units are connected to each other, and the second terminals of the gain transistors in each of the second pixel units are connected to each other. When the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, both the first gain conversion module and the second gain conversion module include a gain transistor. The control terminal of the gain transistor receives a gain control signal. The first terminal of the gain transistor is connected to the corresponding reset module, and the second terminal of the gain transistor is connected to the corresponding floating diffusion node. In at least two pixel units in the same column, the first terminals of the gain transistors in each of the first pixel units are connected to each other, and the first terminals of the gain transistors in each of the second pixel units are connected to each other.

11. An operation method for an image sensor supporting multiple resolutions as described in any one of claims 1 to 10, characterized in that, include: In the pixel merging mode, the resolution control unit merges the first pixel portion and the second pixel portion, so that the first pixel portion and the second pixel portion work together to obtain the pixel signal.

12. The operation method of the image sensor supporting multiple resolutions according to claim 11, characterized in that, Also includes: In the pixel-independent mode, the resolution control unit disconnects the connection between the first pixel unit and the second pixel unit, allowing the first pixel unit and the second pixel unit to operate independently to acquire pixel signals respectively.

13. The method of operating a multi-resolution image sensor according to claim 11 or 12, characterized in that, The process of acquiring pixel signals includes a reset stage, an exposure stage, and a quantization readout stage. The quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and quantization readout of pixel signals under charge overflow.

14. The operation method of the image sensor supporting multiple resolutions according to claim 13, characterized in that, When in the pixel merging mode; If pixel merging is performed under low conversion gain, the specific readout method includes: merging the first pixel portion and the second pixel portion through the resolution control unit, and performing correlation double sampling after merging the first potential well charge signal and the second potential well charge signal; If pixel merging is performed under charge overflow, the specific readout method includes: performing pixel merging on the first pixel part and the second pixel part through the resolution control unit, and performing non-true correlation double sampling after merging the first overflow charge signal and the second overflow charge signal; When in the pixel-independent mode, the specific readout methods include: At low conversion gain, the first potential well charge signal and the second potential well charge signal are respectively subjected to correlation double sampling; At high conversion gain, the first potential well charge signal and the second potential well charge signal are respectively subjected to correlation double sampling; Under charge overflow, non-true correlation double sampling is performed on the first overflow charge signal and the second overflow charge signal respectively.

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