Semiconductor structure and forming method thereof

Abstract

A semiconductor structure according to the present disclosure includes a first active region and a second active region, a first gate structure disposed over the first active region, a second gate structure disposed over the second active region, and a gate isolation feature sandwiched between a sidewall of the first gate structure and a sidewall of the second gate structure. The gate isolation feature includes: a first dielectric layer bordering a sidewall of the first gate structure and a sidewall of the second gate structure; a diffusion barrier liner bordering the first dielectric layer; and a second dielectric layer interfacing with the diffusion barrier liner. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner. The embodiment of the invention also provides a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. FinFETs and gate-all-around (GAA) transistors are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a semiconductor material “fin” extending from the substrate). GAA transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because their gate structure surrounds the channel region, GAA transistors can also be called gate-around transistors (SGT) or multi-bridge channel (MBC) transistors. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistors alternative names, such as nanosheet transistors or nanowire transistors.

[0004] As the semiconductor industry further advances to sub-10 nanometer (nm) technology nodes in pursuit of higher device density, higher performance, and lower cost, challenges in manufacturing and design have given rise to stacked device structure configurations, such as complementary field-effect transistors (CFETs), where n-type multi-gate transistors and p-type multi-gate transistors are stacked vertically on top of each other. While existing CFET structures and manufacturing processes are generally sufficient to meet their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] Some embodiments of this disclosure provide a semiconductor structure including: a first active region and a second active region; a first gate structure disposed above the first active region; a second gate structure disposed above the second active region; and a gate isolation member sandwiched between the sidewalls of the first gate structure and the sidewalls of the second gate structure. The gate isolation member includes: a first dielectric layer at the junction of the sidewalls of the first and second gate structures; a diffusion barrier pad at the junction of the first dielectric layer; and a second dielectric layer at the junction of the diffusion barrier pad. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier pad. The composition of the first dielectric layer is different from the composition of the second dielectric layer.

[0006] Other embodiments of this disclosure provide a semiconductor structure comprising: a substrate having a memory device region and a logic device region; a first gate structure and a second gate structure located above the memory device region; a third gate structure and a fourth gate structure located above the logic device region; a first gate isolation member sandwiched between the first gate structure and the second gate structure; and a second gate isolation member sandwiched between the third gate structure and the fourth gate structure, wherein the composition of the first gate isolation member is different from the composition of the second gate isolation member.

[0007] Another embodiment of this disclosure provides a method for forming a semiconductor structure, the method comprising: providing a precursor structure, the precursor structure comprising: a substrate including a first device region and a second device region; a first bottom gate structure located above the first device region; a first top gate structure located above the first bottom gate structure; a first hard mask layer located above the first top gate structure; a second bottom gate structure located above the second device region; a second top gate structure located above the second bottom gate structure; and a second hard mask layer located above the second top gate structure; forming a first trench, the first trench passing through the first hard mask layer, the first top gate structure, and the first bottom gate structure; and forming a second trench, the second trench passing through the second hard mask layer and the second top gate structure. The method comprises: constructing a first device region and a second bottom gate structure; depositing a first dielectric layer over the first device region and the second device region to fill the first trench and the second trench; forming a patterned mask over the first device region and the second device region, wherein a portion of the first dielectric layer over the second trench is exposed through an opening in the patterned mask; etching the first dielectric layer in the second trench to form an inner trench; removing the patterned mask; depositing a second dielectric layer over the inner trench; and after depositing the second dielectric layer, planarizing the precursor structure to expose the top surfaces of the first top gate structure and the second top gate structure, and forming a first gate dicing member in the first trench and a second gate dicing member in the second trench, wherein the composition of the first dielectric layer is different from the composition of the second dielectric layer. Attached Figure Description

[0008] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 The layout of the top device layer of an exemplary 6-transistor (6T) static random access memory (SRAM) cell implemented using a CFET architecture according to one or more aspects of this disclosure is shown.

[0010] Figure 2 The layout of the bottom device layer of an exemplary 6T SRAM cell implemented with a CFET architecture according to one or more aspects of this disclosure is shown.

[0011] Figure 3 The layout of the top device layer of a logic standard cell implemented using a CFET architecture according to one or more aspects of this disclosure is shown.

[0012] Figure 4 The layout of the bottom device layer of a logic standard cell implemented using a CFET architecture according to one or more aspects of this disclosure is shown.

[0013] Figure 5 The following are shown as one or more aspects of this disclosure. Figure 1 , Figure 2 , Figure 3 or Figure 4 A partial cross-sectional view of line A-A' in the diagram.

[0014] Figure 6 The following are shown as one or more aspects of this disclosure. Figure 1 , Figure 2 , Figure 3 or Figure 4 A partial cross-sectional view of line B-B' in the diagram.

[0015] Figure 7 The following are shown as one or more aspects of this disclosure. Figure 1 , Figure 2 , Figure 3 or Figure 4 A partial cross-sectional view of line C-C' in the diagram.

[0016] Figure 8 A flowchart illustrating a method for forming a gate isolation component in a CFET structure according to one or more aspects of this disclosure is shown.

[0017] Figures 9 to 15 This demonstrates the experience of one or more aspects of this disclosure. Figure 8 Partial cross-sectional views of the precursors for each manufacturing process in the method.

[0018] Figure 16 This is a schematic diagram illustrating the oxygen barrier advantage of a gate isolation component according to one or more aspects of this disclosure.

[0019] Figure 17 This is a schematic diagram illustrating the threshold voltage advantage of a gate isolation component according to one or more aspects of this disclosure.

[0020] Figure 18 A flowchart is shown of a method for forming different gate isolation components in different device regions according to one or more aspects of this disclosure.

[0021] Figures 19 to 26 This demonstrates the experience of one or more aspects of this disclosure. Figure 18 Partial cross-sectional views of the precursors for each manufacturing process in the method. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to cover values ​​within a reasonable range, taking into account the inherent variations during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with that value, the numerical value or range covers a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer with a thickness of "about 5 nm" could cover a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%.

[0025] A stacked multi-gate device (CFET) refers to a semiconductor device comprising a bottom CFET and a top CFET stacked on top of the bottom CFET. When the bottom and top CFETs have different conductivity types, the CFET can be called a complementary field-effect transistor (CFET). The CFET can be a FinFET or a GAA transistor. Depending on the design, the gate structures of the top and second CFETs can be electrically coupled together or insulated from each other. During the fabrication of a CFET over a substrate, a gate stack spanning multiple active regions can be formed, and a gate dicing process can be performed to divide the gate stack into segments via gate isolation components. Because each gate isolation component is positioned between two gate segments, the industry has consistently strived to reduce or minimize the effective dielectric constant of the gate isolation components. The goal of these efforts is to reduce parasitic capacitance between gate segments and increase device speed.

[0026] Reducing the dielectric constant of the gate isolation component does not come without its drawbacks. Low-k dielectric materials in the gate isolation component tend to contain oxygen and can become oxygen sources during the gate oxidation process. When the metal in the gate structure oxidizes, the device's threshold voltage may deviate from its design value. Logic devices are less sensitive to threshold voltage decay as long as they can still switch with adequate response time. However, this is not the case for memory devices, such as static random access memory (SRAM) devices. When the oxidation of components in the gate structure is uneven at different locations in an SRAM array, the minimum supply voltage (V) on the SRAM array will deviate significantly. min The oxygen content may rise, and some SRAM cells may stop functioning properly. At least for memory devices, it is necessary to suppress oxygen diffusion from the gate isolation components.

[0027] This disclosure provides several methods for forming gate isolation components to reduce gate oxidation of devices in memory structures. According to one embodiment, a gate isolation trench is formed in the gate structure of a CFET structure in both a logic device region and a memory device region. A nitrogen-containing layer is deposited in the gate isolation trench. A pad is deposited over the nitrogen-containing layer. An oxygen-containing dielectric layer is deposited over the pad. A planarization process is performed to form a gate isolation component in the gate isolation trench. The pad helps reduce or control oxygen diffusion into the gate structure. According to another embodiment, a first gate isolation trench is formed in the gate structure of a CFET structure in the logic device region, and a second gate isolation trench is formed in the gate structure of a CFET structure in the memory device region. A nitrogen-containing dielectric layer is deposited to fill the first and second gate isolation trenches. In the case of covering the memory device region, an inner trench is formed in the nitrogen-containing dielectric layer in the first gate isolation trench. An oxygen-containing dielectric layer is then deposited in the inner trench. A planarization process is then performed to form a first gate isolation component in the logic device region and a second gate isolation component in the memory device region. The first gate isolation component is configured to provide fast switching speeds for the logic device, and the second gate isolation component is configured to minimize oxygen diffusion into the gate structure of the memory device.

[0028] Gate isolation components can be implemented in the CFET structure of logic devices and memory devices. Figure 1 and Figure 2 The layout of a 6-transistor (6T) static random access memory (SRAM) cell 10 with a CFET architecture is shown. Figure 1 The layout of the top device layer of SRAM cell 10 is shown, and Figure 2 The layout of the bottom device layer of SRAM cell 10 is shown. (Reference) Figure 1 In the top device layer, the SRAM cell 10 includes a first top active region 12T and a second top active region 14T extending longitudinally parallel along the Y direction. (As will be...) Figure 5 and Figure 6As shown in the partial cross-sectional view, both the first top active region 12T and the second top active region 14T include multiple channel structures or nanostructures that also extend longitudinally along the Y direction. A first top gate structure 16T is bonded to the first top active region 12T to form a first pull-down transistor (PD1). A second top gate structure 18T is bonded to the second top active region 14T to form a second transmission gate transistor (PG2). A third top gate structure 20T is bonded to the first top active region 12T to form the first transmission gate transistor (PG1). A fourth top gate structure 22T is bonded to the second top active region 14T to form the second pull-down transistor (PD2). The first top gate structure 16T and the second top gate structure 18T extend longitudinally along the X direction and are aligned along the X direction. The third top gate structure 20T and the fourth top gate structure 22T extend longitudinally along the X direction and are aligned along the X direction. The first gate isolation component 30 extends longitudinally along the Y direction and is disposed between the first top gate structure 16T and the second top gate structure 18T, and between the third top gate structure 20T and the fourth top gate structure 22T. The drains of the first pull-down transistor (PD1) and the second pull-down transistor (PD2) are coupled to ground voltage (Vss) via the first contact via 40 and the second contact via 42. The second gate isolation component 32 disconnects the first top gate structure 16T. The third gate isolation component 34 disconnects the fourth top gate structure 22T.

[0029] refer to Figure 2 In the bottom device layer, the SRAM cell 10 includes a first bottom active region 12B and a second bottom active region 14B extending longitudinally parallel along the Y direction. (As will be...) Figure 5 and Figure 6 As shown in the partial cross-sectional view, each of the first bottom active region 12B and the second bottom active region 14B includes a plurality of channel structures or nanostructures that also extend longitudinally along the Y direction. The first bottom gate structure 16B is bonded to the first bottom active region 12B to form a first pull-up transistor (PU1).

[0030] The second bottom gate structure 18B is coupled to the second bottom active region 14B and is electrically floated.

[0031] The third bottom gate structure 20B is bonded to the first bottom active region 12B and is electrically floating. The fourth bottom gate structure 22B is bonded to the second bottom active region 14B to form the second pull-up transistor (PU2). The first bottom gate structure 16B and the second bottom gate structure 18B extend longitudinally in the X direction and are aligned in the X direction. The third bottom gate structure 20B and the fourth bottom gate structure 22B extend longitudinally in the X direction and are aligned in the X direction. The first gate isolation member 30 extends longitudinally in the Y direction and is disposed between the first bottom gate structure 16B and the second bottom gate structure 18B, and between the third bottom gate structure 20B and the fourth bottom gate structure 22B. The source of the first pull-up transistor (PU1) and the source of the second pull-up transistor (PU2) are coupled to the power supply voltage (Vdd) via the third contact via 44 and the fourth contact via 46. The second gate isolation member 32 disconnects the first bottom gate structure 16B. The third gate isolation member 34 disconnects the fourth bottom gate structure 22B. As can be seen, the first gate isolation component 30, the second gate isolation component 32 and the third gate isolation component 34 extend through the top device layer and the bottom device layer.

[0032] Figure 3 and Figure 4 The layout of a logic standard cell 50 with a CFET architecture is shown. Figure 3 The layout of the top device layer of the logic standard cell 50 is shown. (See diagram.) Figure 3 As shown, in the top device layer, the logic standard cell 50 includes a first top active region 12T and a second top active region 14T extending longitudinally parallel along the Y direction. (As will be...) Figure 5 and Figure 6As shown in the partial cross-sectional view, each of the first top active region 12T and the second top active region 14T includes a plurality of channel structures or nanostructures that also extend longitudinally along the Y direction. A first top gate structure 16T is bonded to the first top active region 12T. A second top gate structure 18T is bonded to the second top active region 14T. A third top gate structure 20T is bonded to the first top active region 12T. A fourth top gate structure 22T is bonded to the second top active region 14T. The first top gate structure 16T and the second top gate structure 18T extend longitudinally along the X direction and are aligned along the X direction. The third top gate structure 20T and the fourth top gate structure 22T extend longitudinally along the X direction and are aligned along the X direction. A first gate isolation member 30 extends longitudinally along the Y direction and is disposed between the first top gate structure 16T and the second top gate structure 18T, and between the third top gate structure 20T and the fourth top gate structure 22T. A fourth gate isolation member 36 cuts off the first top gate structure 16T and the third top gate structure 20T. The fifth gate isolation component 38 cuts off the second top gate structure 18T and the fourth top gate structure 22T.

[0033] like Figure 4 As shown, in the bottom device layer, the logic standard cell 50 includes a first bottom active region 12B and a second bottom active region 14B extending longitudinally parallel along the Y direction. (As will be...) Figure 5 and Figure 6 As shown in the partial cross-sectional view, each of the first bottom active region 12B and the second bottom active region 14B includes a plurality of channel structures or nanostructures that also extend longitudinally along the Y direction. A first bottom gate structure 16B is bonded to the first bottom active region 12B. A second bottom gate structure 18B is bonded to the second bottom active region 14B. A third bottom gate structure 20B is bonded to the first bottom active region 12B. A fourth bottom gate structure 22B is bonded to the second bottom active region 12B. The first bottom gate structure 16B and the second bottom gate structure 18B extend longitudinally along the X direction and are aligned along the X direction. The third bottom gate structure 20B and the fourth bottom gate structure 22B extend longitudinally along the X direction and are aligned along the X direction. A first gate isolation member 30 extends longitudinally along the Y direction and is disposed between the first bottom gate structure 16B and the second bottom gate structure 18B, and between the third bottom gate structure 20B and the fourth bottom gate structure 22B. A fourth gate isolation member 36 cuts off the first bottom gate structure 16B and the third bottom gate structure 20B. The fifth gate isolation component 38 cuts off the second bottom gate structure 18B and the fourth bottom gate structure 22B.

[0034] It can be seen that SRAM cell 10 and logic standard cell 50 share similarities in the first gate isolation component 30, the first top active region 12T, the second top active region 14T, the first bottom active region 12B, the second bottom active region 14B, the first top gate structure 16T, the second top gate structure 18T, the third top gate structure 20T, the fourth top gate structure 22T, the first bottom gate structure 16B, the second bottom gate structure 18B, the third bottom gate structure 20B, and the fourth bottom gate structure 22B. Figure 5 , Figure 6 and Figure 7 Partial cross-sectional views of line A-A' along the X direction, line B-B' along the X direction, and line C-C' along the Y direction are shown.

[0035] Figure 5 It shows along Figure 1 , Figure 2 , Figure 3 or Figure 4 A partial cross-sectional view along centerline A-A'. A first bottom active region 12B includes first bottom channel structures 106B stacked on top of each other above the base fin 104. A first top active region 12T includes first top channel structures 106T stacked on top of each other above the first bottom channel structures 106B. A first bottom gate structure 16B surrounds each first bottom channel structure 106B. A first top gate structure 16T surrounds each first top channel structure 106T. A second top gate structure 18T surrounds each second top channel structure 108T. A second bottom gate structure 18B surrounds each second bottom channel structure 108B. The base fin 104 is patterned from a substrate 102, which is omitted in subsequent figures for simplicity. An isolation member 103 is deposited above the substrate 102 and extends between the sidewalls of the base fin 104. A first gate isolation member 30 extends between a first bottom gate structure 16B and a second bottom gate structure 18B, and between a first top gate structure 16T and a second top gate structure 18T. In some embodiments, the first gate isolation member 30 extends partially into the isolation member 103 and between the base fins 104. An insulating layer 128 is disposed between the first bottom channel structure 106B and the first top channel structure 106T. In some embodiments, the insulating layer 128 is vertically sandwiched between two intermediate semiconductor layers 106M. In some embodiments, the first bottom gate structure 16B and the second bottom gate structure 18B are p-type gate structures and include a p-type work function metal (p-WFM) layer, and the first top gate structure 16T and the second top gate structure 18T are n-type gate structures and include an n-type work function metal (n-WFM) layer.

[0036] Figure 6 It shows along Figure 1 , Figure 2 , Figure 3 or Figure 4 A partial cross-sectional view of the centerline B-B'. The sidewall of the first bottom channel structure 106B contacts the first bottom source / drain component 150B. The sidewall of the second bottom channel structure 108B contacts the second bottom source / drain component 160B. The sidewall of the first top channel structure 106T contacts the first top source / drain component 150T. The sidewall of the second top channel structure 108B contacts the second top source / drain component 160T. A bottom contact etch stop layer (CESL) 152B is disposed above the surfaces of the isolation component 103, the first bottom source / drain component 150B, and the second bottom source / drain component 160B. A bottom interlayer dielectric (ILD) layer 154B is disposed above the bottom CESL 152B. A top CESL 152T is disposed above the surfaces of the first top source / drain component 150T and the second top source / drain component 160T. The top ILD layer 154T is positioned above the top CESL 152T.

[0037] Figure 7 It shows along Figure 1 , Figure 2 , Figure 3 or Figure 4 A partial cross-sectional view of the centerline C-C'. (See attached image.) Figure 7 As shown, a first bottom channel structure 106B is sandwiched between two first bottom source / drain components 150B; a first top channel structure 106T is sandwiched between two first top source / drain components 150T. Similarly, although not explicitly shown in any cross-sectional view, a second bottom channel structure 108B is sandwiched between two second bottom source / drain components 160B; a second top channel structure 108T is sandwiched between two second top source / drain components 160T.

[0038] The methods described below, such as Figure 8 Method 200 and Figure 18 Method 400 includes forming different gate isolation components to replace Figures 1 to 6 The operation of the first gate isolation member 30 shown. That is, Figures 1 to 7 Details of the structure surrounding the gate isolation component formed using method 200 or method 400 are provided.

[0039] Figure 8 and Figure 18This is a flowchart illustrating methods 200 and 400 for forming gate isolation components of a CFET structure in a logic device region and a memory device region according to various aspects of this disclosure. Methods 200 and 400 are merely examples and are not intended to limit this disclosure to what is expressly shown in methods 200 and 400. Additional steps may be provided before, during, and after methods 200 and 400, and for additional embodiments of the method, the described additional steps may be replaced, eliminated, or moved. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 9 to 15 Description method 200, Figures 9 to 15 This is a partial cross-sectional view of the precursor structure 100 at different manufacturing stages according to an embodiment of method 200. The following is in conjunction with... Figures 19 to 26 Description method 400, Figures 19 to 26 This is a partial cross-sectional view of the precursor structure 100 at different manufacturing stages according to an embodiment of method 400. Because the precursor structure 100 will be manufactured into a semiconductor device 100 after the manufacturing process is completed, the precursor structure 100 may be referred to as the semiconductor device 100, depending on the context. Furthermore, throughout this application and in various embodiments, unless otherwise stated, similar reference numerals denote similar components having similar structures and compositions. Depending on the context, the source / drain region may refer individually or collectively to the source or drain.

[0040] Method 200 forms gate isolation components of the same type in both the logic device region and the memory device region.

[0041] refer to Figure 8 and Figure 9 Method 200 includes block 202, at which a hard mask layer 170 is formed over the precursor structure 100. The precursor structure 100 includes a substrate 102 (shown in dashed lines and omitted in subsequent figures), base fins 104 formed from the substrate 102, isolation members 103 located above the substrate 102 and disposed between the base fins 104, a first bottom channel structure 106B, a second bottom channel structure 108B, a first top channel structure 106T, a second top channel structure 108T, a bottom gate structure 80 surrounding the first bottom channel structure 106B and the second bottom channel structure 108B, and a top gate structure 90 surrounding the first top channel structure 106T and the second top channel structure 108T.

[0042] In one embodiment, substrate 102 may be a silicon (Si) substrate. In other embodiments, substrate 102 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 102 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Base fin 104 is formed from substrate 102 and may share the same composition as substrate 102. In one embodiment, base fin 104 may include silicon (Si). Isolation component 103 may also be referred to as shallow trench isolation (STI) component 103. The isolation component 103 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0043] The first bottom channel structure 106B, the second bottom channel structure 108B, the first top channel structure 106T, and the second top channel structure 108T are formed from a stack of epitaxial layers formed on a substrate 102. In an exemplary process, the stack of epitaxial layers includes a plurality of silicon layers interleaved with a plurality of silicon-germanium layers. After patterning the stack to form a fin structure, a dummy gate stack is formed over the fin structure. After forming source / drain components, the dummy gate stack is selectively removed, and the plurality of silicon-germanium layers are selectively removed to release the first bottom channel structure 106B, the second bottom channel structure 108B, the first top channel structure 106T, and the second top channel structure 108T. In some embodiments, the first bottom channel structure 106B, the second bottom channel structure 108B, the first top channel structure 106T, and the second top channel structure 108T may include silicon (Si). A bottom gate structure 80 is deposited to surround each of the first bottom channel structure 106B and the second bottom channel structure 108B. A top gate structure 90 is deposited to surround each of the first top channel structure 106T and the second top channel structure 108T. The precursor structure 100 also includes two intermediate semiconductor layers 108M. An insulating layer 128 is vertically disposed between the two intermediate semiconductor layers 108M. The insulating layer 128 may include silicon oxide, silicon nitride, or silicon carbonitride to separate the bottom channel structure from the top channel structure.

[0044] The bottom gate structure 80 includes an interface layer bordering the first bottom channel structure 106B and the second bottom channel structure 108B, a gate dielectric layer 114 above the interface layer, and a bottom gate electrode above the gate dielectric layer 114. In some embodiments, the interface layer may include silicon oxide or hafnium silicate. The gate dielectric layer 114 is formed of a high-k dielectric material. As used and described herein, high-k dielectric materials include dielectric materials having a high dielectric constant, for example, a dielectric constant greater than that of thermally heated silicon oxide (~3.9). In one embodiment, the gate dielectric layer 114 may include hafnium oxide. Optionally, the gate dielectric layer 114 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In the illustrated embodiment, the bottom gate structure 80 is a p-type gate structure, and the bottom gate electrode includes at least one p-type work function metal layer. In some examples, the p-type work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), or platinum (Pt).

[0045] The top gate structure 90 includes an interface layer bordering the first top channel structure 106T and the second top channel structure 108T, a gate dielectric layer 114 above the interface layer, and a top gate electrode above the gate dielectric layer 114. In the illustrated embodiment, the top gate structure 90 is an n-type gate structure, and the top gate electrode includes at least one n-type work function metal layer. In some examples, the n-type work function metal layer may include titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or silicon nitride tantalum (TaSiN). When the n-type work function metal layer includes aluminum, it becomes more susceptible to oxidation due to oxygen diffusion from adjacent structures, such as gate isolation components.

[0046] At frame 202, above the precursor 100, such as above the top surface of the top gate structure 90, a hard mask layer 170 is deposited. The hard mask layer 170 can be a single layer or multiple layers. In the illustrated embodiment, the hard mask layer 170 includes a first layer 172, a second layer 173 above the first layer 172, and a third layer 174 above the second layer 173. In some embodiments, the first layer 172 and the third layer 174 may share the same composition, while the second layer 173 may have a different composition than the first layer 172 or the third layer 174. To prevent oxygen diffusion into the top gate structure 90, the first layer 172, the second layer 173, and the third layer 174 are oxygen-free. In some embodiments, the first layer 172 and the third layer 174 comprise silicon nitride or silicon carbonitride, and the second layer comprises silicon. In one embodiment, the first layer 172 and the third layer 174 comprise silicon nitride, and the second layer comprises silicon. In some implementations, chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used to deposit the hard mask layer 170.

[0047] refer to Figure 8 , Figure 10 and Figure 11 Method 200 includes block 204, where a gate isolation trench 184 passes through a top gate structure 90 and a bottom gate structure 80. Operations at block 204 may include forming a first patterned photoresist layer 180 (e.g., ...). Figure 10 (as shown), and using the first patterned photoresist layer 180 as an etching mask to etch the precursor structure 100 (as shown). Figure 11 (As shown). Reference Figure 10 A first photoresist layer 180 is deposited over a hard mask layer 170 using spin coating. At frame 204, the first photoresist layer 180 is patterned by undergoing soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The first patterned photoresist layer 180 includes mask openings 182. Etching processes such as dry etching (e.g., RIE etching), wet etching, or combinations thereof are performed to etch the hard mask layer 170, the top gate structure 90, the bottom gate structure 80, and the isolation component 103. Reference Figure 11 The etching performed at frame 204 can form a gate isolation trench 184, which extends vertically through the hard mask layer 170, dividing the top gate structure 90 into a first top gate structure 120 and a second top gate structure 122, and dividing the bottom gate structure 80 into a first bottom gate structure 110 and a second bottom gate structure 112. Figure 11 In some embodiments shown, to ensure complete cutoff of the bottom gate structure 80, the gate isolation trench 184 extends at least partially into the isolation member 103. For example... Figure 11 As shown, the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 120 and the second top gate structure 122, the sidewalls of the first bottom gate structure 110 and the second bottom gate structure 112, the sidewalls of the isolation member 103, and the top surface of the isolation member 103 are all exposed in the gate isolation trench 184. After the gate isolation trench 184 is formed, any remaining first patterned photoresist layer 180 is removed from the precursor structure 100. In some examples, the gate isolation trench 184 may also be referred to as a gate dicing trench.

[0048] refer to Figure 8 and Figure 12 Method 200 includes block 206, at which an oxygen-free dielectric layer 142 is deposited over a gate isolation trench 184. In some embodiments, the oxygen-free dielectric layer 142 may comprise silicon nitride, and the oxygen-free dielectric layer 142 may be deposited using CVD or ALD. Figure 12 As shown, the deposited oxygen-free dielectric layer 142 can be conformally deposited over the gate isolation trench 184 to intersect with the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 120 and the second top gate structure 122, the sidewalls of the first bottom gate structure 110 and the second bottom gate structure 112, the sidewalls of the isolation member 103, and the top surface of the isolation member 103. The oxygen-free dielectric layer 142 can have a first thickness (T1) between about 3 nm and about 4 nm.

[0049] refer to Figure 8 and Figure 13Method 200 includes block 208, at which an oxygen barrier layer 144 is deposited over a gate isolation trench 184. The oxygen barrier layer 144 can use more than one mechanism to “block” oxygen diffusion. For example, the oxygen barrier layer 144 can be a sacrificial layer to consume and trap oxygen when it is oxidized itself. In this example, the oxygen barrier layer 144 can include amorphous silicon, silicon carbonitride, or amorphous carbon. As another example, the oxygen barrier layer 144 can be a dense oxygen barrier that reduces or restricts oxygen diffusion. In this example, the oxygen barrier layer 144 can include a polymer, such as polyimide. In one embodiment, the oxygen barrier layer 144 can include amorphous silicon. The oxygen barrier layer 144 can be referred to as a pad and has a second thickness T2 less than a first thickness T1. In some examples, the second thickness T2 can be between about 1 nm and about 1.5 nm. The ratio of the second thickness T2 to the first thickness T1 can be between about 1:4 and about 1:2. The oxygen barrier layer 144 can be deposited using ALD or plasma-enhanced ALD (PEALD). Although not explicitly shown in the figures, the oxygen barrier layer 144 can be multilayered. In one example, the oxygen barrier layer 144 may include a silicon sublayer intersecting with the oxygen-free dielectric layer 142 and a silicon carbonitride sublayer intersecting with the oxygen-containing dielectric layer to be deposited. It should be noted that the additional layer interface created by introducing the oxygen barrier layer 144 also helps to slow down oxygen diffusion. For example, without the oxygen barrier layer 144, the oxygen-free dielectric layer 142 directly intersects with the oxygen-containing dielectric layer 146 (described below). With the oxygen barrier layer 144 introduced, the oxygen-free dielectric layer 142 intersects with the oxygen barrier layer 144, and the oxygen barrier layer 144 intersects with the oxygen-containing dielectric layer 146. The additional interface creates a barrier for oxygen diffusion from the oxygen-containing dielectric layer 146.

[0050] refer to Figure 8 and Figure 14 Method 200 includes block 210, at which an oxygen-containing dielectric layer 146 is deposited over an oxygen barrier layer 144. In some embodiments, the oxygen-containing dielectric layer 146 may comprise silicon oxide, and the oxygen-containing dielectric layer 146 may be deposited using flowable CVD (FCVD), spin coating, CVD, or ALD. Figure 14 As shown, at frame 210, the oxygen-containing dielectric layer 146 not only completely fills the gate isolation trench 184, but also includes a certain thickness above the top surface of the oxygen barrier layer 144.

[0051] refer to Figure 8 and Figure 15Method 200 includes block 212, where a planarization process 300 is performed to expose top gate structures 120 and 122. The planarization process 300 may include a chemical mechanical polishing (CMP) process. At block 212, the planarization process 300 is performed to remove excess portions of the oxygen-free dielectric layer 142, the oxygen barrier layer 144, and the oxygen-containing layer 146 to expose the top surfaces of the first top gate structure 120 and the second top gate structure 122. At this stage, the gate isolation component 140 is substantially formed. Figure 15 As shown, the gate isolation component 140 includes an oxygen-free dielectric layer 142 that intersects with the gate structure (including a first top gate structure 120, a second top gate structure 122, a first bottom gate structure 110, and a second bottom gate structure 112). The gate isolation component 140 also includes an oxygen barrier layer 144 for protecting the oxygen-free dielectric layer 142 from oxygen diffusion from the innermost oxygen-containing dielectric layer 146.

[0052] refer to Figure 8 Method 200 includes block 214, where further processes are performed. Such further processes may include forming a mid-process online (MEOL) component and forming a back-process online (BEOL) component. The MEOL component may include a front-side source / drain contact, a gate contact via, a back-side source / drain contact via, and a back-side gate contact via. The BEOL component may include a front-side interconnect structure and a back-side interconnect structure. The front-side interconnect structure includes multiple dielectric layers and multiple metal layers disposed within the multiple dielectric layers. In some embodiments, the front-side interconnect structure includes about 8 to about 20 metal layers. The back-side interconnect structure includes multiple dielectric layers and multiple metal layers disposed within the multiple dielectric layers. In some embodiments, the back-side interconnect structure includes about 2 to about 10 metal layers.

[0053] Simulations and experiments have demonstrated the advantages of oxygen barrier layer 144 in blocking oxygen. (First, refer to...) Figure 16 , Figure 16 The relationship between oxygen concentration and gate isolation member distance was plotted for embodiments with and without oxygen barrier layer 144. Figure 16 The graph shows that the oxygen concentration distribution tends to decrease away from the gate isolation component 140. This demonstrates that the oxygen barrier layer 144 slows down oxygen diffusion into the gate structure and towards the channel. Figure 17 The included graphs show that the implementation of the oxygen barrier layer 144 reduces the threshold voltage variation by approximately 8% to approximately 10%. As mentioned above, the non-uniform oxidation of the gate structure (especially an n-type gate structure including aluminum (Al)) reduces the minimum supply voltage (V) on the SRAM array. minThe voltage may rise, and some SRAM cells may not function properly. When an oxygen barrier layer 144 is implemented in the SRAM structure, the oxygen barrier layer 144 reduces the voltage threshold change by decreasing the Vthreshold. min Changes or increases.

[0054] Method 400 forms different types of gate isolation components in the logic device region and the memory device region.

[0055] refer to Figure 18 and Figure 19 Method 400 includes a frame 402, at which a hard mask 170 is formed over a first device region 1000 and a second device region 2000 of the precursor structure 100. Figure 19 The precursor structure 100 shown is similar to Figure 9 The precursor structure 100 is shown. For simplicity, details are omitted. Figure 19 Detailed description of the precursor structure 100. The precursor structure 100 includes a first device region 1000 and a second device region 2000. In some embodiments, the first device region 1000 includes... Figure 1 and Figure 2 The SRAM cell 10 shown includes a memory device region, and the second device region 2000 includes... Figure 3 and Figure 4 The logic device region of the logic standard unit 50 shown. It should be noted that the method 200 described above does not refer to different device regions because the operations performed on different device regions are similar, not because the aforementioned precursor 100 does not include multiple device regions.

[0056] The precursor structure 100 includes a substrate 102 (shown in dashed lines and omitted in subsequent figures) located in both the first device region 1000 and the second device region 2000, a base fin 104 formed from the substrate 102, an isolation member 103 located above the substrate 102 and disposed between the base fins 104, a first bottom channel structure 106B, a second bottom channel structure 108B, a first top channel structure 106T, and a second top channel structure 108T. For ease of description, the different arrangements of the gate structures in the two device regions, and the reference numerals for the top gate structure and the bottom gate structure in the two device regions are used interchangeably with those used in the previous description. Figure 9 The differences are as described. (Reference) Figure 19Above the first device region 1000, there is a bottom gate structure 1080 surrounding the first bottom channel structure 106B and the second bottom channel structure 108B, and a top gate structure 1090 surrounding the first top channel structure 106T and the second top channel structure 108T. Above the second device region 2000, there is a bottom gate structure 2080 surrounding the first bottom channel structure 106B and the second bottom channel structure 108B, and a top gate structure 2090 surrounding the first top channel structure 106T and the second top channel structure 108T.

[0057] At frame 402, a hard mask layer 170 is deposited over the first device region 1000 and the second device region 2000 (e.g., above the top surfaces of the top gate structure 1090 and the top gate structure 2090). The hard mask layer 170 may be a single layer or multiple layers. In the illustrated embodiment, the hard mask layer 170 includes a first layer 172, a second layer 173 above the first layer 172, and a third layer 174 above the second layer 173. In some embodiments, the first layer 172 and the third layer 174 may share the same composition, while the second layer 173 may have a different composition than the first layer 172 or the third layer 174. To prevent oxygen diffusion into the top gate structure 90, the first layer 172, the second layer 173, and the third layer 174 are oxygen-free. In some embodiments, the first layer 172 and the third layer 174 comprise silicon nitride or silicon carbonitride, and the second layer comprises silicon. In one embodiment, the first layer 172 and the third layer 174 comprise silicon nitride, and the second layer comprises silicon. In some implementations, chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used to deposit the hard mask layer 170.

[0058] refer to Figure 18 , Figure 20 and Figure 21 Method 400 includes block 404, where a first gate isolation trench 184-1 is formed in a first device region 1000, and a second gate isolation trench 184-2 is formed in a second device region 2000. The operation at block 404 may include forming a first patterned photoresist layer 180 (e.g., ...). Figure 20 (as shown), and using the first patterned photoresist layer 180 as an etching mask to etch the precursor structure 100 (as shown). Figure 21 (As shown). Reference Figure 20A first photoresist layer 180 is deposited over a hard mask layer 170 using spin coating. At frame 404, the first photoresist layer 180 is patterned by undergoing soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The first patterned photoresist layer 180 includes a first mask opening 182-1 over a first device region 1000 and a second mask opening 182-2 over a second device region 2000. Etching processes such as dry etching (e.g., RIE etching), wet etching, or combinations thereof are performed to etch the hard mask layer 170, top gate structures 1090 and 2090, bottom gate structures 1080 and 2080, and isolation member 103. Reference Figure 21 The etching performed at frame 404 can form a first gate isolation trench 184-1 in the first device region 1000. This first gate isolation trench 184-1 extends vertically through the hard mask layer 170, dividing the top gate structure 1090 into a first top gate structure 1020 and a second top gate structure 1022, and dividing the bottom gate structure 1080 into a first bottom gate structure 1010 and a second bottom gate structure 1012. The etching performed at frame 404 can also form a second gate isolation trench 184-2 in the second device region 2000. This second gate isolation trench 184-2 extends vertically through the hard mask layer 170, dividing the top gate structure 2090 into a first top gate structure 2020 and a second top gate structure 2022, and dividing the bottom gate structure 2080 into a first bottom gate structure 2010 and a second bottom gate structure 2012. Figure 21 In some embodiments shown, to ensure complete cutoff of the bottom gate structure 1080 or 2080, gate isolation trenches 184-1 and 184-2 extend at least partially into the isolation member 103. Figure 21As shown, the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 1020 and the second top gate structure 1022, the sidewalls of the first bottom gate structure 1010 and the second bottom gate structure 1012, the sidewalls of the isolation member 103, and the top surface of the isolation member 103 are all exposed in the first gate isolation trench 184-1. In the second device region 2000, the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 2020 and the second top gate structure 2022, the sidewalls of the first bottom gate structure 2010 and the second bottom gate structure 2012, the sidewalls of the isolation member 103, and the top surface of the isolation member 103 are all exposed in the second gate isolation trench 184-2. After forming the first gate isolation trench 184-1 and the second gate isolation trench 184-2, any remaining first patterned photoresist layer 180 is removed from the precursor structure 100. In some examples, the first gate isolation trench 184-1 and the second gate isolation trench 184-2 may also be referred to as the first gate cleaving trench 184-1 and the second gate cleaving trench 184-2.

[0059] refer to Figure 18 and Figure 22 Method 400 includes block 406, at which an oxygen-free dielectric layer 142 is deposited over a first gate isolation trench 184-1 and a second gate isolation trench 184-2. In some embodiments, the oxygen-free dielectric layer 142 may comprise silicon nitride, and the oxygen-free dielectric layer 142 may be deposited using CVD or ALD. Figure 22 As shown, the deposited oxygen-free dielectric layer 142 can be deposited over the first gate isolation trench 184-1 and the second gate isolation trench 184-2. In the illustrated embodiment, the oxygen-free dielectric layer 142 completely fills the first gate isolation trench 184-1 in the first device region 1000 and the second gate isolation trench 184-2 in the second device region 2000. In some examples, the oxygen-free dielectric layer 142 deposited at frame 406 covers the top surface of the hard mask layer 170.

[0060] refer to Figure 18 and Figure 23 Method 400 includes block 408, where a first device region 1000 and a second device region 2000 are planarized in planarization process 320 to thin the oxygen-free dielectric layer 142. To form a smooth and planar top surface for subsequent operations, block 408 planarizes the precursor structure 100 to reduce the thickness of the oxygen-free dielectric layer 142 above the top surface of the hard mask layer 170. In some examples, planarization process 300 includes a chemical mechanical polishing (CMP) process.

[0061] refer to Figure 18 and Figure 24Method 400 includes block 410, where an internal trench 192 extends through an oxygen-free dielectric layer 142 in a second gate isolation trench 184-2. Operations at block 410 may include forming a second patterned photoresist layer 190 and using the second patterned photoresist layer 190 as an etch mask to etch the precursor structure 100. Reference Figure 24 A second photoresist layer 190 is deposited over a hard mask layer 170 using spin coating. At frame 410, the second photoresist layer 190 is patterned by undergoing soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The second patterned photoresist layer 190 includes a mask opening located directly above a second gate isolation trench 184-2 filled with an oxygen-free dielectric layer 142. An etching process, such as dry etching (e.g., RIE etching), wet etching, or combinations thereof, is performed to etch the oxygen-free dielectric layer 142 in the second gate isolation trench 184-2. Reference Figure 24 The etching at frame 410 can form an internal trench 192 that extends vertically through the oxygen-free dielectric layer 142 in the second gate isolation trench 184-2. For example... Figure 24 As shown, the internal trench 192 is spaced apart from the sidewalls of the first top gate structure 2020 and the second top gate structure 2022, the sidewalls of the first bottom gate structure 2010 and the second bottom gate structure 2012, and the isolation member 103 by an oxygen-free dielectric layer. Figure 24 In some embodiments shown, the bottom surface of the internal trench 192 may extend below the top surface of the isolation member 103. After the internal trench 192 is formed, any remaining second patterned photoresist layer 190 is removed from the precursor structure 100.

[0062] refer to Figure 18 and Figure 25 Method 400 includes a block 412, at which an oxygen-containing dielectric layer 146 is deposited over an internal trench 192. In some embodiments, the oxygen-containing dielectric layer 146 may comprise silicon oxide, and the oxygen-containing dielectric layer 146 may be deposited using flowable CVD (FCVD), spin coating, CVD, or ALD. Figure 25 As shown, at frame 412, the oxygen-containing dielectric layer 146 not only completely fills the internal trench 192 in the second device region 2000, but is also deposited above the top surface of the oxygen-free dielectric layer 142 in the first device region 1000.

[0063] refer to Figure 18 and Figure 26Method 400 includes block 414, where a planarization process 340 is performed to expose top gate structures 120 and 122. The planarization process 340 may include a chemical mechanical polishing (CMP) process and is used to remove excess oxygen-free dielectric layer 142 and oxygen-containing dielectric 146 above the top surfaces of the first top gate structure 1020 and the second top gate structure 1022 in the first device region 1000, and above the top surfaces of the first top gate structure 2020 and the second top gate structure 2022 in the second device region 2000. At this time, a first type gate isolation component 1400 is formed in the first device region 1000, and a second type gate isolation component 1402 is formed in the second device region 2000. The first type gate isolation component 1400 is formed entirely of the oxygen-free dielectric layer 142 and helps reduce oxygen diffusion into the gate structure it contacts. The first type gate isolation component 1400 is suitable for applications where device performance degradation is primarily caused by oxygen diffusion. The second type gate isolation component 1402 includes both an oxygen-free dielectric layer 142 and an oxygen-containing dielectric layer 146. The second type gate isolation component 1402 tends to have a smaller dielectric constant and is suitable for logic devices that require fast switching and low parasitic capacitance.

[0064] refer to Figure 18 Method 400 includes block 416, where further processes are performed. Such further processes may include forming a mid-process online (MEOL) component and forming a back-process online (BEOL) component. The MEOL component may include a front-side source / drain contact, a gate contact via, a back-side source / drain contact via, and a back-side gate contact via. The BEOL component may include a front-side interconnect structure and a back-side interconnect structure. The front-side interconnect structure includes multiple dielectric layers and multiple metal layers disposed within the multiple dielectric layers. In some embodiments, the front-side interconnect structure includes about 8 to about 20 metal layers. The back-side interconnect structure includes multiple dielectric layers and multiple metal layers disposed within the multiple dielectric layers. In some embodiments, the back-side interconnect structure includes about 2 to about 10 metal layers.

[0065] In one exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes a first active region and a second active region, a first gate structure disposed over the first active region, a second gate structure disposed over the second active region, and a gate isolation member sandwiched between sidewalls of the first and second gate structures. The gate isolation member includes a first dielectric layer bordering the sidewalls of the first and second gate structures, a diffusion barrier pad bordering the first dielectric layer, and a second dielectric layer bordering the diffusion barrier pad. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier pad, and the composition of the first dielectric layer differs from the composition of the second dielectric layer.

[0066] In some embodiments, the diffusion barrier pad comprises amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer. In some embodiments, a first active region comprises a first plurality of nanostructures, a second active region comprises a second plurality of nanostructures, a first gate structure surrounds each of the first plurality of nanostructures, and a second gate structure surrounds each of the second plurality of nanostructures. In some embodiments, the semiconductor structure further comprises a third active region above the first active region, a fourth active region above the second active region, a third gate structure disposed above the third active region, and a fourth gate structure disposed above the fourth active region. A gate isolation member is also sandwiched between the sidewalls of the third gate structure and the sidewalls of the fourth gate structure. In some embodiments, the third gate structure is disposed above the first gate structure, and the fourth gate structure is disposed above the second gate structure. In some embodiments, the first gate structure and the second gate structure comprise p-type work function layers, and the third gate structure and the fourth gate structure comprise n-type work function layers. In some embodiments, the n-type work function layer comprises titanium aluminum. In some embodiments, the diffusion barrier pad comprises a first thickness, and the first dielectric layer comprises a second thickness greater than the first thickness. In some embodiments, the ratio of the first thickness to the second thickness is between about 1:4 and about 1:2. In some embodiments, the first thickness is between about 1 nm and about 1.5 nm, and the second thickness is between about 3 nm and about 4 nm.

[0067] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate having a memory device region and a logic device region; a first gate structure and a second gate structure located above the memory device region; a third gate structure and a fourth gate structure located above the logic device region; a first gate isolation member sandwiched between the first gate structure and the second gate structure; and a second gate isolation member sandwiched between the third gate structure and the fourth gate structure. The composition of the first gate isolation member differs from the composition of the second gate isolation member.

[0068] In some embodiments, the first gate isolation member comprises silicon nitride, and the second gate isolation member comprises: an outer layer that intersects with the sidewalls of the third gate structure and the fourth gate structure; and an inner layer that is spaced apart from the sidewalls of the third gate structure and the fourth gate structure by the outer layer. The composition of the outer layer differs from that of the inner layer. In some embodiments, the dielectric constant of the outer layer is greater than that of the inner layer. In some embodiments, the outer layer comprises silicon nitride, and the inner layer comprises silicon oxide. In some embodiments, the semiconductor structure further comprises: a first top gate structure located above the first gate structure; a second top gate structure located above the second gate structure; a third top gate structure located above the third gate structure; and a fourth top gate structure located above the fourth gate structure. The first gate isolation member extends between the first top gate structure and the second top gate structure, and the second gate isolation member extends between the third top gate structure and the fourth top gate structure. In some embodiments, the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure comprise a p-type work function metal layer, and the first top gate structure, the second top gate structure, the third top gate structure, and the fourth top gate structure comprise an n-type work function metal layer.

[0069] In another exemplary aspect, this disclosure relates to a method. The method includes: providing a precursor structure comprising: a substrate including a first device region and a second device region; a first bottom gate structure over the first device region; a first top gate structure over the first bottom gate structure; a first hard mask layer over the first top gate structure; a second bottom gate structure over the second device region; a second top gate structure over the second bottom gate structure; and a second hard mask layer over the second top gate structure; forming a first trench through the first hard mask layer, the first top gate structure, and the first bottom gate structure; and forming a second trench through the second hard mask layer and the second top gate structure. The system comprises a gate structure and a second bottom gate structure; depositing a first dielectric layer over a first device region and a second device region to fill a first trench and a second trench; forming a patterned mask over the first device region and the second device region, wherein a portion of the first dielectric layer over the second trench is exposed through an opening in the patterned mask; etching the first dielectric layer in the second trench to form an inner trench; removing the patterned mask; depositing a second dielectric layer over the inner trench; and after depositing the second dielectric layer, planarizing a precursor structure to expose the top surfaces of a first top gate structure and a second top gate structure, and forming a first gate dicing feature in the first trench and a second gate dicing feature in the second trench. The composition of the first dielectric layer differs from the composition of the second dielectric layer.

[0070] In some embodiments, the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises silicon oxide. In some embodiments, the first bottom gate structure and the second bottom gate structure comprise p-type work function metal layers, and the first top gate structure and the second top gate structure comprise n-type work function metal layers. In some embodiments, a first gate dicing member is disposed between a first stack of nanostructures and a second stack of nanostructures, the first gate dicing member dividing the first bottom gate structure into a first gate segment and a second gate segment, the first gate segment surrounding each of the first stack of nanostructures, and the second gate segment surrounding each of the second stack of nanostructures.

[0071] Some embodiments of this application provide a semiconductor structure including: a first active region and a second active region; a first gate structure disposed above the first active region; a second gate structure disposed above the second active region; and a gate isolation member sandwiched between the sidewalls of the first gate structure and the sidewalls of the second gate structure. The gate isolation member includes: a first dielectric layer bordering the sidewalls of the first and second gate structures; a diffusion barrier pad bordering the first dielectric layer; and a second dielectric layer bordering the diffusion barrier pad. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier pad. The composition of the first dielectric layer is different from the composition of the second dielectric layer. In some embodiments, the diffusion barrier pad includes amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer. In some embodiments, the first active region includes a first plurality of nanostructures, and the second active region includes a second plurality of nanostructures. The first gate structure surrounds each of the first plurality of nanostructures, and the second gate structure surrounds each of the second plurality of nanostructures. In some embodiments, the semiconductor structure further includes: a third active region located above the first active region; a fourth active region located above the second active region; a third gate structure disposed above the third active region; and a fourth gate structure disposed above the fourth active region, wherein a gate isolation member is also sandwiched between the sidewalls of the third gate structure and the sidewalls of the fourth gate structure. In some embodiments, the third gate structure is disposed above the first gate structure, and wherein the fourth gate structure is disposed above the second gate structure. In some embodiments, the first gate structure and the second gate structure include a p-type work function layer, wherein the third gate structure and the fourth gate structure include an n-type work function layer. In some embodiments, the n-type work function layer includes titanium aluminum. In some embodiments, the diffusion barrier pad includes a first thickness, wherein the first dielectric layer includes a second thickness greater than the first thickness. In some embodiments, the ratio of the first thickness to the second thickness is between about 1:4 and about 1:2. In some embodiments, the first thickness is between about 1 nm and about 1.5 nm, wherein the second thickness is between about 3 nm and about 4 nm.

[0072] Other embodiments of this application provide a semiconductor structure comprising: a substrate having a memory device region and a logic device region; a first gate structure and a second gate structure located above the memory device region; a third gate structure and a fourth gate structure located above the logic device region; a first gate isolation member sandwiched between the first gate structure and the second gate structure; and a second gate isolation member sandwiched between the third gate structure and the fourth gate structure, wherein the composition of the first gate isolation member is different from the composition of the second gate isolation member. In some embodiments, the first gate isolation member comprises silicon nitride, wherein the second gate isolation member comprises: an outer layer bordering the sidewalls of the third gate structure and the fourth gate structure; and an inner layer spaced apart from the sidewalls of the third gate structure and the fourth gate structure by the outer layer, wherein the composition of the outer layer is different from the composition of the inner layer. In some embodiments, the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer. In some embodiments, the outer layer comprises silicon nitride, and the inner layer comprises silicon oxide. In some embodiments, the semiconductor structure further includes: a first top gate structure located above the first gate structure; a second top gate structure located above the second gate structure; a third top gate structure located above the third gate structure; and a fourth top gate structure located above the fourth gate structure, wherein a first gate isolation member extends between the first top gate structure and the second top gate structure, and wherein the second gate isolation member extends between the third top gate structure and the fourth top gate structure. In some embodiments, the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure include a p-type work function metal layer, wherein the first top gate structure, the second top gate structure, the third top gate structure, and the fourth top gate structure include an n-type work function metal layer.

[0073] Some other embodiments of this application provide a method for forming a semiconductor structure, the method comprising: providing a precursor structure, the precursor structure comprising: a substrate including a first device region and a second device region; a first bottom gate structure located above the first device region; a first top gate structure located above the first bottom gate structure; a first hard mask layer located above the first top gate structure; a second bottom gate structure located above the second device region; a second top gate structure located above the second bottom gate structure; and a second hard mask layer located above the second top gate structure; forming a first trench, the first trench passing through the first hard mask layer, the first top gate structure, and the first bottom gate structure; and forming a second trench, the second trench passing through the second hard mask layer and the second top gate structure. The system comprises a first device region and a second bottom gate structure; depositing a first dielectric layer over a first device region and a second device region to fill a first trench and a second trench; forming a patterned mask over the first device region and the second device region, wherein a portion of the first dielectric layer over the second trench is exposed through an opening in the patterned mask; etching the first dielectric layer in the second trench to form an inner trench; removing the patterned mask; depositing a second dielectric layer over the inner trench; and after depositing the second dielectric layer, planarizing a precursor structure to expose the top surfaces of a first top gate structure and a second top gate structure, and forming a first gate dicing feature in the first trench and a second gate dicing feature in the second trench, wherein the composition of the first dielectric layer is different from the composition of the second dielectric layer. In some embodiments, the first dielectric layer comprises silicon nitride, wherein the second dielectric layer comprises silicon oxide. In some embodiments, the first bottom gate structure and the second bottom gate structure comprise p-type work function metal layers; wherein the first top gate structure and the second top gate structure comprise n-type work function metal layers. In some embodiments, a first gate dicing member is disposed between a first stack of nanostructures and a second stack of nanostructures; wherein the first gate dicing member divides a first bottom gate structure into a first gate segment and a second gate segment; wherein the first gate segment surrounds each of the first stack of nanostructures; wherein the second gate segment surrounds each of the second stack of nanostructures.

[0074] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other operations and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: First active region and second active region; A first gate structure is disposed above the first active region; A second gate structure is disposed above the second active region; as well as A gate isolation component is sandwiched between the sidewall of the first gate structure and the sidewall of the second gate structure. The gate isolation component includes: The first dielectric layer intersects with the sidewalls of the first gate structure and the sidewalls of the second gate structure. The diffusion barrier pad, at the interface with the first dielectric layer, and The second dielectric layer intersects with the diffusion barrier pad. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier pad. The composition of the first dielectric layer is different from that of the second dielectric layer.

2. The semiconductor structure according to claim 1, wherein, The diffusion barrier liner includes amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer.

3. The semiconductor structure according to claim 1, in, The first active region includes a first plurality of nanostructures. The second active region includes a second plurality of nanostructures. The first gate structure surrounds each of the first plurality of nanostructures. The second gate structure surrounds each of the second plurality of nanostructures.

4. The semiconductor structure according to claim 1, further comprising: The third active region is located above the first active region; The fourth active region is located above the second active region; A third gate structure is disposed above the third active region; as well as A fourth gate structure is disposed above the fourth active region. The gate isolation component is also sandwiched between the sidewall of the third gate structure and the sidewall of the fourth gate structure.

5. The semiconductor structure according to claim 4, in, The third gate structure is disposed above the first gate structure, and the fourth gate structure is disposed above the second gate structure.

6. The semiconductor structure according to claim 5, in, The first gate structure and the second gate structure include a p-type work function layer. The third gate structure and the fourth gate structure include an n-type work function layer.

7. The semiconductor structure according to claim 6, wherein, The n-type work function layer comprises titanium aluminum.

8. The semiconductor structure according to claim 1, in, The diffusion barrier liner includes a first thickness. The first dielectric layer has a second thickness greater than the first thickness.

9. A semiconductor structure, comprising: The substrate has a memory device region and a logic device region; The first gate structure and the second gate structure are located above the memory device region; The third gate structure and the fourth gate structure are located above the logic device region; A first gate isolation component is sandwiched between the first gate structure and the second gate structure; and The second gate isolation component is sandwiched between the third gate structure and the fourth gate structure. The composition of the first gate isolation component is different from that of the second gate isolation component.

10. A method for forming a semiconductor structure, comprising: A precursor structure is provided, the precursor structure comprising: The substrate includes a first device region and a second device region. The first bottom gate structure is located above the first device region. The first top gate structure is located above the first bottom gate structure. A first hard mask layer is located above the first top gate structure. The second bottom gate structure is located above the second device region. The second top gate structure is located above the second bottom gate structure, and The second hard mask layer is located above the second top gate structure. A first trench is formed, which passes through the first hard mask layer, the first top gate structure, and the first bottom gate structure; A second trench is formed, which passes through the second hard mask layer, the second top gate structure, and the second bottom gate structure; A first dielectric layer is deposited over the first device region and the second device region to fill the first trench and the second trench; A patterned mask is formed over the first device region and the second device region, and a portion of the first dielectric layer over the second trench is exposed through an opening in the patterned mask; Etch the first dielectric layer in the second trench to form an internal trench; Remove the patterned mask; A second dielectric layer is deposited above the internal trench; and After depositing the second dielectric layer, the precursor structure is planarized to expose the top surfaces of the first top gate structure and the second top gate structure, and a first gate dicing feature is formed in the first trench, and a second gate dicing feature is formed in the second trench. The composition of the first dielectric layer is different from that of the second dielectric layer.

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